1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMCallingConv.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMPerfectShuffle.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalValue.h"
40 #include "llvm/IR/IRBuilder.h"
41 #include "llvm/IR/Instruction.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/Type.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 #define DEBUG_TYPE "arm-isel"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
58 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
61 EnableARMLongCalls("arm-long-calls", cl::Hidden,
62 cl::desc("Generate calls via indirect call instructions"),
66 ARMInterworking("arm-interworking", cl::Hidden,
67 cl::desc("Enable / disable ARM interworking (for debugging only)"),
71 class ARMCCState : public CCState {
73 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
74 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
76 : CCState(CC, isVarArg, MF, locs, C) {
77 assert(((PC == Call) || (PC == Prologue)) &&
78 "ARMCCState users must specify whether their context is call"
79 "or prologue generation.");
85 // The APCS parameter registers.
86 static const MCPhysReg GPRArgRegs[] = {
87 ARM::R0, ARM::R1, ARM::R2, ARM::R3
90 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
91 MVT PromotedBitwiseVT) {
92 if (VT != PromotedLdStVT) {
93 setOperationAction(ISD::LOAD, VT, Promote);
94 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
96 setOperationAction(ISD::STORE, VT, Promote);
97 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
100 MVT ElemTy = VT.getVectorElementType();
101 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
102 setOperationAction(ISD::SETCC, VT, Custom);
103 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
104 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
105 if (ElemTy == MVT::i32) {
106 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
107 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
108 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
109 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
111 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
112 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
113 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
114 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
116 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
117 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
118 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
119 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
120 setOperationAction(ISD::SELECT, VT, Expand);
121 setOperationAction(ISD::SELECT_CC, VT, Expand);
122 setOperationAction(ISD::VSELECT, VT, Expand);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
124 if (VT.isInteger()) {
125 setOperationAction(ISD::SHL, VT, Custom);
126 setOperationAction(ISD::SRA, VT, Custom);
127 setOperationAction(ISD::SRL, VT, Custom);
130 // Promote all bit-wise operations.
131 if (VT.isInteger() && VT != PromotedBitwiseVT) {
132 setOperationAction(ISD::AND, VT, Promote);
133 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
134 setOperationAction(ISD::OR, VT, Promote);
135 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
136 setOperationAction(ISD::XOR, VT, Promote);
137 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
140 // Neon does not support vector divide/remainder operations.
141 setOperationAction(ISD::SDIV, VT, Expand);
142 setOperationAction(ISD::UDIV, VT, Expand);
143 setOperationAction(ISD::FDIV, VT, Expand);
144 setOperationAction(ISD::SREM, VT, Expand);
145 setOperationAction(ISD::UREM, VT, Expand);
146 setOperationAction(ISD::FREM, VT, Expand);
149 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
150 addRegisterClass(VT, &ARM::DPRRegClass);
151 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
154 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
155 addRegisterClass(VT, &ARM::DPairRegClass);
156 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
159 ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM)
160 : TargetLowering(TM) {
161 Subtarget = &TM.getSubtarget<ARMSubtarget>();
162 RegInfo = TM.getSubtargetImpl()->getRegisterInfo();
163 Itins = TM.getSubtargetImpl()->getInstrItineraryData();
165 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
167 if (Subtarget->isTargetMachO()) {
168 // Uses VFP for Thumb libfuncs if available.
169 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
170 Subtarget->hasARMOps() && !TM.Options.UseSoftFloat) {
171 // Single-precision floating-point arithmetic.
172 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
173 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
174 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
175 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
177 // Double-precision floating-point arithmetic.
178 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
179 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
180 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
181 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
183 // Single-precision comparisons.
184 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
185 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
186 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
187 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
188 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
189 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
190 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
191 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
193 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
194 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
195 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
196 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
202 // Double-precision comparisons.
203 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
204 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
205 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
206 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
207 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
208 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
209 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
210 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
212 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
218 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
219 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
221 // Floating-point to integer conversions.
222 // i64 conversions are done via library routines even when generating VFP
223 // instructions, so use the same ones.
224 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
225 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
226 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
227 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
229 // Conversions between floating types.
230 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
231 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
233 // Integer to floating-point conversions.
234 // i64 conversions are done via library routines even when generating VFP
235 // instructions, so use the same ones.
236 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
237 // e.g., __floatunsidf vs. __floatunssidfvfp.
238 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
239 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
240 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
241 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
245 // These libcalls are not available in 32-bit.
246 setLibcallName(RTLIB::SHL_I128, nullptr);
247 setLibcallName(RTLIB::SRL_I128, nullptr);
248 setLibcallName(RTLIB::SRA_I128, nullptr);
250 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() &&
251 !Subtarget->isTargetWindows()) {
252 static const struct {
253 const RTLIB::Libcall Op;
254 const char * const Name;
255 const CallingConv::ID CC;
256 const ISD::CondCode Cond;
258 // Double-precision floating-point arithmetic helper functions
259 // RTABI chapter 4.1.2, Table 2
260 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
261 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
262 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
263 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
265 // Double-precision floating-point comparison helper functions
266 // RTABI chapter 4.1.2, Table 3
267 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
268 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
269 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
270 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
271 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
272 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
273 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
274 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
276 // Single-precision floating-point arithmetic helper functions
277 // RTABI chapter 4.1.2, Table 4
278 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
279 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
280 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
281 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
283 // Single-precision floating-point comparison helper functions
284 // RTABI chapter 4.1.2, Table 5
285 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
286 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
287 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
288 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
289 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
290 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
291 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
292 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
294 // Floating-point to integer conversions.
295 // RTABI chapter 4.1.2, Table 6
296 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
297 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
298 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
299 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
300 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
301 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
302 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
303 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
305 // Conversions between floating types.
306 // RTABI chapter 4.1.2, Table 7
307 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
308 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
309 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
311 // Integer to floating-point conversions.
312 // RTABI chapter 4.1.2, Table 8
313 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
314 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
315 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
316 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
317 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
318 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
319 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
320 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
322 // Long long helper functions
323 // RTABI chapter 4.2, Table 9
324 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
325 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
326 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
327 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
329 // Integer division functions
330 // RTABI chapter 4.3.1
331 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
332 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
333 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
334 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
335 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
336 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
337 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
338 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
341 // RTABI chapter 4.3.4
342 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
343 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
344 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
347 for (const auto &LC : LibraryCalls) {
348 setLibcallName(LC.Op, LC.Name);
349 setLibcallCallingConv(LC.Op, LC.CC);
350 if (LC.Cond != ISD::SETCC_INVALID)
351 setCmpLibcallCC(LC.Op, LC.Cond);
355 if (Subtarget->isTargetWindows()) {
356 static const struct {
357 const RTLIB::Libcall Op;
358 const char * const Name;
359 const CallingConv::ID CC;
361 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
362 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
363 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
364 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
365 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
366 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
367 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
368 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
371 for (const auto &LC : LibraryCalls) {
372 setLibcallName(LC.Op, LC.Name);
373 setLibcallCallingConv(LC.Op, LC.CC);
377 // Use divmod compiler-rt calls for iOS 5.0 and later.
378 if (Subtarget->getTargetTriple().isiOS() &&
379 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
380 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
381 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
384 // The half <-> float conversion functions are always soft-float, but are
385 // needed for some targets which use a hard-float calling convention by
387 if (Subtarget->isAAPCS_ABI()) {
388 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
393 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
394 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
397 if (Subtarget->isThumb1Only())
398 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
400 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
401 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
402 !Subtarget->isThumb1Only()) {
403 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
404 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
407 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
408 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
409 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
410 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
411 setTruncStoreAction((MVT::SimpleValueType)VT,
412 (MVT::SimpleValueType)InnerVT, Expand);
413 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
414 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
415 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
417 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
418 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
419 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
420 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
422 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
425 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
426 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
428 if (Subtarget->hasNEON()) {
429 addDRTypeForNEON(MVT::v2f32);
430 addDRTypeForNEON(MVT::v8i8);
431 addDRTypeForNEON(MVT::v4i16);
432 addDRTypeForNEON(MVT::v2i32);
433 addDRTypeForNEON(MVT::v1i64);
435 addQRTypeForNEON(MVT::v4f32);
436 addQRTypeForNEON(MVT::v2f64);
437 addQRTypeForNEON(MVT::v16i8);
438 addQRTypeForNEON(MVT::v8i16);
439 addQRTypeForNEON(MVT::v4i32);
440 addQRTypeForNEON(MVT::v2i64);
442 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
443 // neither Neon nor VFP support any arithmetic operations on it.
444 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
445 // supported for v4f32.
446 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
447 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
448 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
449 // FIXME: Code duplication: FDIV and FREM are expanded always, see
450 // ARMTargetLowering::addTypeForNEON method for details.
451 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
452 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
453 // FIXME: Create unittest.
454 // In another words, find a way when "copysign" appears in DAG with vector
456 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
457 // FIXME: Code duplication: SETCC has custom operation action, see
458 // ARMTargetLowering::addTypeForNEON method for details.
459 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
460 // FIXME: Create unittest for FNEG and for FABS.
461 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
462 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
463 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
464 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
465 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
466 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
467 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
468 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
469 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
470 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
471 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
472 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
473 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
474 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
475 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
476 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
477 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
478 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
479 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
481 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
482 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
483 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
484 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
485 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
486 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
487 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
488 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
489 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
490 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
491 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
492 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
493 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
494 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
495 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
497 // Mark v2f32 intrinsics.
498 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
499 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
500 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
501 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
502 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
503 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
504 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
505 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
506 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
507 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
508 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
509 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
510 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
511 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
512 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
514 // Neon does not support some operations on v1i64 and v2i64 types.
515 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
516 // Custom handling for some quad-vector types to detect VMULL.
517 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
518 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
519 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
520 // Custom handling for some vector types to avoid expensive expansions
521 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
522 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
523 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
524 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
525 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
526 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
527 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
528 // a destination type that is wider than the source, and nor does
529 // it have a FP_TO_[SU]INT instruction with a narrower destination than
531 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
532 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
533 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
534 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
536 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
537 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
539 // NEON does not have single instruction CTPOP for vectors with element
540 // types wider than 8-bits. However, custom lowering can leverage the
541 // v8i8/v16i8 vcnt instruction.
542 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
543 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
544 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
545 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
547 // NEON only has FMA instructions as of VFP4.
548 if (!Subtarget->hasVFP4()) {
549 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
550 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
553 setTargetDAGCombine(ISD::INTRINSIC_VOID);
554 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
555 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
556 setTargetDAGCombine(ISD::SHL);
557 setTargetDAGCombine(ISD::SRL);
558 setTargetDAGCombine(ISD::SRA);
559 setTargetDAGCombine(ISD::SIGN_EXTEND);
560 setTargetDAGCombine(ISD::ZERO_EXTEND);
561 setTargetDAGCombine(ISD::ANY_EXTEND);
562 setTargetDAGCombine(ISD::SELECT_CC);
563 setTargetDAGCombine(ISD::BUILD_VECTOR);
564 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
565 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
566 setTargetDAGCombine(ISD::STORE);
567 setTargetDAGCombine(ISD::FP_TO_SINT);
568 setTargetDAGCombine(ISD::FP_TO_UINT);
569 setTargetDAGCombine(ISD::FDIV);
571 // It is legal to extload from v4i8 to v4i16 or v4i32.
572 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
573 MVT::v4i16, MVT::v2i16,
575 for (unsigned i = 0; i < 6; ++i) {
576 setLoadExtAction(ISD::EXTLOAD, Tys[i], Legal);
577 setLoadExtAction(ISD::ZEXTLOAD, Tys[i], Legal);
578 setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal);
582 // ARM and Thumb2 support UMLAL/SMLAL.
583 if (!Subtarget->isThumb1Only())
584 setTargetDAGCombine(ISD::ADDC);
586 if (Subtarget->isFPOnlySP()) {
587 // When targetting a floating-point unit with only single-precision
588 // operations, f64 is legal for the few double-precision instructions which
589 // are present However, no double-precision operations other than moves,
590 // loads and stores are provided by the hardware.
591 setOperationAction(ISD::FADD, MVT::f64, Expand);
592 setOperationAction(ISD::FSUB, MVT::f64, Expand);
593 setOperationAction(ISD::FMUL, MVT::f64, Expand);
594 setOperationAction(ISD::FMA, MVT::f64, Expand);
595 setOperationAction(ISD::FDIV, MVT::f64, Expand);
596 setOperationAction(ISD::FREM, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
599 setOperationAction(ISD::FNEG, MVT::f64, Expand);
600 setOperationAction(ISD::FABS, MVT::f64, Expand);
601 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
602 setOperationAction(ISD::FSIN, MVT::f64, Expand);
603 setOperationAction(ISD::FCOS, MVT::f64, Expand);
604 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
605 setOperationAction(ISD::FPOW, MVT::f64, Expand);
606 setOperationAction(ISD::FLOG, MVT::f64, Expand);
607 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
608 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
609 setOperationAction(ISD::FEXP, MVT::f64, Expand);
610 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
611 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
612 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
613 setOperationAction(ISD::FRINT, MVT::f64, Expand);
614 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
615 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
616 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
617 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
620 computeRegisterProperties();
622 // ARM does not have floating-point extending loads.
623 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
624 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
626 // ... or truncating stores
627 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
628 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
629 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
631 // ARM does not have i1 sign extending load.
632 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
634 // ARM supports all 4 flavors of integer indexed load / store.
635 if (!Subtarget->isThumb1Only()) {
636 for (unsigned im = (unsigned)ISD::PRE_INC;
637 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
638 setIndexedLoadAction(im, MVT::i1, Legal);
639 setIndexedLoadAction(im, MVT::i8, Legal);
640 setIndexedLoadAction(im, MVT::i16, Legal);
641 setIndexedLoadAction(im, MVT::i32, Legal);
642 setIndexedStoreAction(im, MVT::i1, Legal);
643 setIndexedStoreAction(im, MVT::i8, Legal);
644 setIndexedStoreAction(im, MVT::i16, Legal);
645 setIndexedStoreAction(im, MVT::i32, Legal);
649 setOperationAction(ISD::SADDO, MVT::i32, Custom);
650 setOperationAction(ISD::UADDO, MVT::i32, Custom);
651 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
652 setOperationAction(ISD::USUBO, MVT::i32, Custom);
654 // i64 operation support.
655 setOperationAction(ISD::MUL, MVT::i64, Expand);
656 setOperationAction(ISD::MULHU, MVT::i32, Expand);
657 if (Subtarget->isThumb1Only()) {
658 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
659 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
661 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
662 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
663 setOperationAction(ISD::MULHS, MVT::i32, Expand);
665 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
666 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
667 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
668 setOperationAction(ISD::SRL, MVT::i64, Custom);
669 setOperationAction(ISD::SRA, MVT::i64, Custom);
671 if (!Subtarget->isThumb1Only()) {
672 // FIXME: We should do this for Thumb1 as well.
673 setOperationAction(ISD::ADDC, MVT::i32, Custom);
674 setOperationAction(ISD::ADDE, MVT::i32, Custom);
675 setOperationAction(ISD::SUBC, MVT::i32, Custom);
676 setOperationAction(ISD::SUBE, MVT::i32, Custom);
679 // ARM does not have ROTL.
680 setOperationAction(ISD::ROTL, MVT::i32, Expand);
681 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
682 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
683 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
684 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
686 // These just redirect to CTTZ and CTLZ on ARM.
687 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
688 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
690 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
692 // Only ARMv6 has BSWAP.
693 if (!Subtarget->hasV6Ops())
694 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
696 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
697 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
698 // These are expanded into libcalls if the cpu doesn't have HW divider.
699 setOperationAction(ISD::SDIV, MVT::i32, Expand);
700 setOperationAction(ISD::UDIV, MVT::i32, Expand);
703 // FIXME: Also set divmod for SREM on EABI
704 setOperationAction(ISD::SREM, MVT::i32, Expand);
705 setOperationAction(ISD::UREM, MVT::i32, Expand);
706 // Register based DivRem for AEABI (RTABI 4.2)
707 if (Subtarget->isTargetAEABI()) {
708 setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
709 setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
710 setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
711 setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
712 setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
713 setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
714 setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
715 setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
717 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
718 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
719 setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
720 setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
721 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
722 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
723 setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
724 setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
726 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
727 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
729 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
730 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
733 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
734 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
735 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
736 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
737 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
739 setOperationAction(ISD::TRAP, MVT::Other, Legal);
741 // Use the default implementation.
742 setOperationAction(ISD::VASTART, MVT::Other, Custom);
743 setOperationAction(ISD::VAARG, MVT::Other, Expand);
744 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
745 setOperationAction(ISD::VAEND, MVT::Other, Expand);
746 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
747 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
749 if (!Subtarget->isTargetMachO()) {
750 // Non-MachO platforms may return values in these registers via the
751 // personality function.
752 setExceptionPointerRegister(ARM::R0);
753 setExceptionSelectorRegister(ARM::R1);
756 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
757 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
759 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
761 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
762 // the default expansion. If we are targeting a single threaded system,
763 // then set them all for expand so we can lower them later into their
765 if (TM.Options.ThreadModel == ThreadModel::Single)
766 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
767 else if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
768 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
769 // to ldrex/strex loops already.
770 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
772 // On v8, we have particularly efficient implementations of atomic fences
773 // if they can be combined with nearby atomic loads and stores.
774 if (!Subtarget->hasV8Ops()) {
775 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
776 setInsertFencesForAtomic(true);
779 // If there's anything we can use as a barrier, go through custom lowering
781 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
782 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
784 // Set them all for expansion, which will force libcalls.
785 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
786 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
787 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
788 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
789 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
790 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
791 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
792 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
793 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
794 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
795 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
796 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
797 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
798 // Unordered/Monotonic case.
799 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
800 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
803 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
805 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
806 if (!Subtarget->hasV6Ops()) {
807 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
808 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
810 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
812 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
813 !Subtarget->isThumb1Only()) {
814 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
815 // iff target supports vfp2.
816 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
817 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
820 // We want to custom lower some of our intrinsics.
821 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
822 if (Subtarget->isTargetDarwin()) {
823 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
824 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
825 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
828 setOperationAction(ISD::SETCC, MVT::i32, Expand);
829 setOperationAction(ISD::SETCC, MVT::f32, Expand);
830 setOperationAction(ISD::SETCC, MVT::f64, Expand);
831 setOperationAction(ISD::SELECT, MVT::i32, Custom);
832 setOperationAction(ISD::SELECT, MVT::f32, Custom);
833 setOperationAction(ISD::SELECT, MVT::f64, Custom);
834 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
835 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
836 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
838 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
839 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
840 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
841 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
842 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
844 // We don't support sin/cos/fmod/copysign/pow
845 setOperationAction(ISD::FSIN, MVT::f64, Expand);
846 setOperationAction(ISD::FSIN, MVT::f32, Expand);
847 setOperationAction(ISD::FCOS, MVT::f32, Expand);
848 setOperationAction(ISD::FCOS, MVT::f64, Expand);
849 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
850 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
851 setOperationAction(ISD::FREM, MVT::f64, Expand);
852 setOperationAction(ISD::FREM, MVT::f32, Expand);
853 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
854 !Subtarget->isThumb1Only()) {
855 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
856 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
858 setOperationAction(ISD::FPOW, MVT::f64, Expand);
859 setOperationAction(ISD::FPOW, MVT::f32, Expand);
861 if (!Subtarget->hasVFP4()) {
862 setOperationAction(ISD::FMA, MVT::f64, Expand);
863 setOperationAction(ISD::FMA, MVT::f32, Expand);
866 // Various VFP goodness
867 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
868 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
869 if (Subtarget->hasVFP2()) {
870 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
871 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
872 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
873 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
876 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
877 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
878 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
879 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
882 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
883 if (!Subtarget->hasFP16()) {
884 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
885 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
889 // Combine sin / cos into one node or libcall if possible.
890 if (Subtarget->hasSinCos()) {
891 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
892 setLibcallName(RTLIB::SINCOS_F64, "sincos");
893 if (Subtarget->getTargetTriple().isiOS()) {
894 // For iOS, we don't want to the normal expansion of a libcall to
895 // sincos. We want to issue a libcall to __sincos_stret.
896 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
897 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
901 // FP-ARMv8 implements a lot of rounding-like FP operations.
902 if (Subtarget->hasFPARMv8()) {
903 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
904 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
905 setOperationAction(ISD::FROUND, MVT::f32, Legal);
906 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
907 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
908 setOperationAction(ISD::FRINT, MVT::f32, Legal);
909 if (!Subtarget->isFPOnlySP()) {
910 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
911 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
912 setOperationAction(ISD::FROUND, MVT::f64, Legal);
913 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
914 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
915 setOperationAction(ISD::FRINT, MVT::f64, Legal);
918 // We have target-specific dag combine patterns for the following nodes:
919 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
920 setTargetDAGCombine(ISD::ADD);
921 setTargetDAGCombine(ISD::SUB);
922 setTargetDAGCombine(ISD::MUL);
923 setTargetDAGCombine(ISD::AND);
924 setTargetDAGCombine(ISD::OR);
925 setTargetDAGCombine(ISD::XOR);
927 if (Subtarget->hasV6Ops())
928 setTargetDAGCombine(ISD::SRL);
930 setStackPointerRegisterToSaveRestore(ARM::SP);
932 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
933 !Subtarget->hasVFP2())
934 setSchedulingPreference(Sched::RegPressure);
936 setSchedulingPreference(Sched::Hybrid);
938 //// temporary - rewrite interface to use type
939 MaxStoresPerMemset = 8;
940 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
941 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
942 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
943 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
944 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
946 // On ARM arguments smaller than 4 bytes are extended, so all arguments
947 // are at least 4 bytes aligned.
948 setMinStackArgumentAlignment(4);
950 // Prefer likely predicted branches to selects on out-of-order cores.
951 PredictableSelectIsExpensive = Subtarget->isLikeA9();
953 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
956 // FIXME: It might make sense to define the representative register class as the
957 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
958 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
959 // SPR's representative would be DPR_VFP2. This should work well if register
960 // pressure tracking were modified such that a register use would increment the
961 // pressure of the register class's representative and all of it's super
962 // classes' representatives transitively. We have not implemented this because
963 // of the difficulty prior to coalescing of modeling operand register classes
964 // due to the common occurrence of cross class copies and subregister insertions
966 std::pair<const TargetRegisterClass*, uint8_t>
967 ARMTargetLowering::findRepresentativeClass(MVT VT) const{
968 const TargetRegisterClass *RRC = nullptr;
970 switch (VT.SimpleTy) {
972 return TargetLowering::findRepresentativeClass(VT);
973 // Use DPR as representative register class for all floating point
974 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
975 // the cost is 1 for both f32 and f64.
976 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
977 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
978 RRC = &ARM::DPRRegClass;
979 // When NEON is used for SP, only half of the register file is available
980 // because operations that define both SP and DP results will be constrained
981 // to the VFP2 class (D0-D15). We currently model this constraint prior to
982 // coalescing by double-counting the SP regs. See the FIXME above.
983 if (Subtarget->useNEONForSinglePrecisionFP())
986 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
987 case MVT::v4f32: case MVT::v2f64:
988 RRC = &ARM::DPRRegClass;
992 RRC = &ARM::DPRRegClass;
996 RRC = &ARM::DPRRegClass;
1000 return std::make_pair(RRC, Cost);
1003 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1005 default: return nullptr;
1006 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1007 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1008 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1009 case ARMISD::CALL: return "ARMISD::CALL";
1010 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1011 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1012 case ARMISD::tCALL: return "ARMISD::tCALL";
1013 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1014 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1015 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1016 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1017 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1018 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1019 case ARMISD::CMP: return "ARMISD::CMP";
1020 case ARMISD::CMN: return "ARMISD::CMN";
1021 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1022 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1023 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1024 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1025 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1027 case ARMISD::CMOV: return "ARMISD::CMOV";
1029 case ARMISD::RBIT: return "ARMISD::RBIT";
1031 case ARMISD::FTOSI: return "ARMISD::FTOSI";
1032 case ARMISD::FTOUI: return "ARMISD::FTOUI";
1033 case ARMISD::SITOF: return "ARMISD::SITOF";
1034 case ARMISD::UITOF: return "ARMISD::UITOF";
1036 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1037 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1038 case ARMISD::RRX: return "ARMISD::RRX";
1040 case ARMISD::ADDC: return "ARMISD::ADDC";
1041 case ARMISD::ADDE: return "ARMISD::ADDE";
1042 case ARMISD::SUBC: return "ARMISD::SUBC";
1043 case ARMISD::SUBE: return "ARMISD::SUBE";
1045 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1046 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1048 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1049 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
1051 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1053 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1055 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1057 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1059 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1061 case ARMISD::WIN__CHKSTK: return "ARMISD:::WIN__CHKSTK";
1063 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1064 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1065 case ARMISD::VCGE: return "ARMISD::VCGE";
1066 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1067 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1068 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1069 case ARMISD::VCGT: return "ARMISD::VCGT";
1070 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1071 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1072 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1073 case ARMISD::VTST: return "ARMISD::VTST";
1075 case ARMISD::VSHL: return "ARMISD::VSHL";
1076 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1077 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1078 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1079 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1080 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1081 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1082 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1083 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1084 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1085 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1086 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1087 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1088 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1089 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1090 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1091 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1092 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1093 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1094 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1095 case ARMISD::VDUP: return "ARMISD::VDUP";
1096 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1097 case ARMISD::VEXT: return "ARMISD::VEXT";
1098 case ARMISD::VREV64: return "ARMISD::VREV64";
1099 case ARMISD::VREV32: return "ARMISD::VREV32";
1100 case ARMISD::VREV16: return "ARMISD::VREV16";
1101 case ARMISD::VZIP: return "ARMISD::VZIP";
1102 case ARMISD::VUZP: return "ARMISD::VUZP";
1103 case ARMISD::VTRN: return "ARMISD::VTRN";
1104 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1105 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1106 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1107 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1108 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1109 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1110 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1111 case ARMISD::FMAX: return "ARMISD::FMAX";
1112 case ARMISD::FMIN: return "ARMISD::FMIN";
1113 case ARMISD::VMAXNM: return "ARMISD::VMAX";
1114 case ARMISD::VMINNM: return "ARMISD::VMIN";
1115 case ARMISD::BFI: return "ARMISD::BFI";
1116 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1117 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1118 case ARMISD::VBSL: return "ARMISD::VBSL";
1119 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1120 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1121 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1122 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1123 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1124 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1125 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1126 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1127 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1128 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1129 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1130 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1131 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1132 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1133 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1134 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1135 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1136 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1137 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1138 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1142 EVT ARMTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1143 if (!VT.isVector()) return getPointerTy();
1144 return VT.changeVectorElementTypeToInteger();
1147 /// getRegClassFor - Return the register class that should be used for the
1148 /// specified value type.
1149 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1150 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1151 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1152 // load / store 4 to 8 consecutive D registers.
1153 if (Subtarget->hasNEON()) {
1154 if (VT == MVT::v4i64)
1155 return &ARM::QQPRRegClass;
1156 if (VT == MVT::v8i64)
1157 return &ARM::QQQQPRRegClass;
1159 return TargetLowering::getRegClassFor(VT);
1162 // Create a fast isel object.
1164 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1165 const TargetLibraryInfo *libInfo) const {
1166 return ARM::createFastISel(funcInfo, libInfo);
1169 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
1170 /// be used for loads / stores from the global.
1171 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1172 return (Subtarget->isThumb1Only() ? 127 : 4095);
1175 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1176 unsigned NumVals = N->getNumValues();
1178 return Sched::RegPressure;
1180 for (unsigned i = 0; i != NumVals; ++i) {
1181 EVT VT = N->getValueType(i);
1182 if (VT == MVT::Glue || VT == MVT::Other)
1184 if (VT.isFloatingPoint() || VT.isVector())
1188 if (!N->isMachineOpcode())
1189 return Sched::RegPressure;
1191 // Load are scheduled for latency even if there instruction itinerary
1192 // is not available.
1193 const TargetInstrInfo *TII =
1194 getTargetMachine().getSubtargetImpl()->getInstrInfo();
1195 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1197 if (MCID.getNumDefs() == 0)
1198 return Sched::RegPressure;
1199 if (!Itins->isEmpty() &&
1200 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1203 return Sched::RegPressure;
1206 //===----------------------------------------------------------------------===//
1208 //===----------------------------------------------------------------------===//
1210 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1211 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1213 default: llvm_unreachable("Unknown condition code!");
1214 case ISD::SETNE: return ARMCC::NE;
1215 case ISD::SETEQ: return ARMCC::EQ;
1216 case ISD::SETGT: return ARMCC::GT;
1217 case ISD::SETGE: return ARMCC::GE;
1218 case ISD::SETLT: return ARMCC::LT;
1219 case ISD::SETLE: return ARMCC::LE;
1220 case ISD::SETUGT: return ARMCC::HI;
1221 case ISD::SETUGE: return ARMCC::HS;
1222 case ISD::SETULT: return ARMCC::LO;
1223 case ISD::SETULE: return ARMCC::LS;
1227 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1228 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1229 ARMCC::CondCodes &CondCode2) {
1230 CondCode2 = ARMCC::AL;
1232 default: llvm_unreachable("Unknown FP condition!");
1234 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1236 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1238 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1239 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1240 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1241 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1242 case ISD::SETO: CondCode = ARMCC::VC; break;
1243 case ISD::SETUO: CondCode = ARMCC::VS; break;
1244 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1245 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1246 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1248 case ISD::SETULT: CondCode = ARMCC::LT; break;
1250 case ISD::SETULE: CondCode = ARMCC::LE; break;
1252 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1256 //===----------------------------------------------------------------------===//
1257 // Calling Convention Implementation
1258 //===----------------------------------------------------------------------===//
1260 #include "ARMGenCallingConv.inc"
1262 /// getEffectiveCallingConv - Get the effective calling convention, taking into
1263 /// account presence of floating point hardware and calling convention
1264 /// limitations, such as support for variadic functions.
1266 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1267 bool isVarArg) const {
1270 llvm_unreachable("Unsupported calling convention");
1271 case CallingConv::ARM_AAPCS:
1272 case CallingConv::ARM_APCS:
1273 case CallingConv::GHC:
1275 case CallingConv::ARM_AAPCS_VFP:
1276 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1277 case CallingConv::C:
1278 if (!Subtarget->isAAPCS_ABI())
1279 return CallingConv::ARM_APCS;
1280 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1281 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1283 return CallingConv::ARM_AAPCS_VFP;
1285 return CallingConv::ARM_AAPCS;
1286 case CallingConv::Fast:
1287 if (!Subtarget->isAAPCS_ABI()) {
1288 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1289 return CallingConv::Fast;
1290 return CallingConv::ARM_APCS;
1291 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1292 return CallingConv::ARM_AAPCS_VFP;
1294 return CallingConv::ARM_AAPCS;
1298 /// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1299 /// CallingConvention.
1300 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1302 bool isVarArg) const {
1303 switch (getEffectiveCallingConv(CC, isVarArg)) {
1305 llvm_unreachable("Unsupported calling convention");
1306 case CallingConv::ARM_APCS:
1307 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1308 case CallingConv::ARM_AAPCS:
1309 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1310 case CallingConv::ARM_AAPCS_VFP:
1311 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1312 case CallingConv::Fast:
1313 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1314 case CallingConv::GHC:
1315 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1319 /// LowerCallResult - Lower the result values of a call into the
1320 /// appropriate copies out of appropriate physical registers.
1322 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1323 CallingConv::ID CallConv, bool isVarArg,
1324 const SmallVectorImpl<ISD::InputArg> &Ins,
1325 SDLoc dl, SelectionDAG &DAG,
1326 SmallVectorImpl<SDValue> &InVals,
1327 bool isThisReturn, SDValue ThisVal) const {
1329 // Assign locations to each value returned by this call.
1330 SmallVector<CCValAssign, 16> RVLocs;
1331 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1332 *DAG.getContext(), Call);
1333 CCInfo.AnalyzeCallResult(Ins,
1334 CCAssignFnForNode(CallConv, /* Return*/ true,
1337 // Copy all of the result registers out of their specified physreg.
1338 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1339 CCValAssign VA = RVLocs[i];
1341 // Pass 'this' value directly from the argument to return value, to avoid
1342 // reg unit interference
1343 if (i == 0 && isThisReturn) {
1344 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1345 "unexpected return calling convention register assignment");
1346 InVals.push_back(ThisVal);
1351 if (VA.needsCustom()) {
1352 // Handle f64 or half of a v2f64.
1353 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1355 Chain = Lo.getValue(1);
1356 InFlag = Lo.getValue(2);
1357 VA = RVLocs[++i]; // skip ahead to next loc
1358 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1360 Chain = Hi.getValue(1);
1361 InFlag = Hi.getValue(2);
1362 if (!Subtarget->isLittle())
1364 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1366 if (VA.getLocVT() == MVT::v2f64) {
1367 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1368 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1369 DAG.getConstant(0, MVT::i32));
1371 VA = RVLocs[++i]; // skip ahead to next loc
1372 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1373 Chain = Lo.getValue(1);
1374 InFlag = Lo.getValue(2);
1375 VA = RVLocs[++i]; // skip ahead to next loc
1376 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1377 Chain = Hi.getValue(1);
1378 InFlag = Hi.getValue(2);
1379 if (!Subtarget->isLittle())
1381 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1382 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1383 DAG.getConstant(1, MVT::i32));
1386 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1388 Chain = Val.getValue(1);
1389 InFlag = Val.getValue(2);
1392 switch (VA.getLocInfo()) {
1393 default: llvm_unreachable("Unknown loc info!");
1394 case CCValAssign::Full: break;
1395 case CCValAssign::BCvt:
1396 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1400 InVals.push_back(Val);
1406 /// LowerMemOpCallTo - Store the argument to the stack.
1408 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1409 SDValue StackPtr, SDValue Arg,
1410 SDLoc dl, SelectionDAG &DAG,
1411 const CCValAssign &VA,
1412 ISD::ArgFlagsTy Flags) const {
1413 unsigned LocMemOffset = VA.getLocMemOffset();
1414 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1415 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1416 return DAG.getStore(Chain, dl, Arg, PtrOff,
1417 MachinePointerInfo::getStack(LocMemOffset),
1421 void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
1422 SDValue Chain, SDValue &Arg,
1423 RegsToPassVector &RegsToPass,
1424 CCValAssign &VA, CCValAssign &NextVA,
1426 SmallVectorImpl<SDValue> &MemOpChains,
1427 ISD::ArgFlagsTy Flags) const {
1429 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1430 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1431 unsigned id = Subtarget->isLittle() ? 0 : 1;
1432 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1434 if (NextVA.isRegLoc())
1435 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1437 assert(NextVA.isMemLoc());
1438 if (!StackPtr.getNode())
1439 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1441 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1447 /// LowerCall - Lowering a call into a callseq_start <-
1448 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1451 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1452 SmallVectorImpl<SDValue> &InVals) const {
1453 SelectionDAG &DAG = CLI.DAG;
1455 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1456 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1457 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1458 SDValue Chain = CLI.Chain;
1459 SDValue Callee = CLI.Callee;
1460 bool &isTailCall = CLI.IsTailCall;
1461 CallingConv::ID CallConv = CLI.CallConv;
1462 bool doesNotRet = CLI.DoesNotReturn;
1463 bool isVarArg = CLI.IsVarArg;
1465 MachineFunction &MF = DAG.getMachineFunction();
1466 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1467 bool isThisReturn = false;
1468 bool isSibCall = false;
1470 // Disable tail calls if they're not supported.
1471 if (!Subtarget->supportsTailCall() || MF.getTarget().Options.DisableTailCalls)
1475 // Check if it's really possible to do a tail call.
1476 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1477 isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
1478 Outs, OutVals, Ins, DAG);
1479 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
1480 report_fatal_error("failed to perform tail call elimination on a call "
1481 "site marked musttail");
1482 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1483 // detected sibcalls.
1490 // Analyze operands of the call, assigning locations to each operand.
1491 SmallVector<CCValAssign, 16> ArgLocs;
1492 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1493 *DAG.getContext(), Call);
1494 CCInfo.AnalyzeCallOperands(Outs,
1495 CCAssignFnForNode(CallConv, /* Return*/ false,
1498 // Get a count of how many bytes are to be pushed on the stack.
1499 unsigned NumBytes = CCInfo.getNextStackOffset();
1501 // For tail calls, memory operands are available in our caller's stack.
1505 // Adjust the stack pointer for the new arguments...
1506 // These operations are automatically eliminated by the prolog/epilog pass
1508 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1511 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1513 RegsToPassVector RegsToPass;
1514 SmallVector<SDValue, 8> MemOpChains;
1516 // Walk the register/memloc assignments, inserting copies/loads. In the case
1517 // of tail call optimization, arguments are handled later.
1518 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1520 ++i, ++realArgIdx) {
1521 CCValAssign &VA = ArgLocs[i];
1522 SDValue Arg = OutVals[realArgIdx];
1523 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1524 bool isByVal = Flags.isByVal();
1526 // Promote the value if needed.
1527 switch (VA.getLocInfo()) {
1528 default: llvm_unreachable("Unknown loc info!");
1529 case CCValAssign::Full: break;
1530 case CCValAssign::SExt:
1531 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1533 case CCValAssign::ZExt:
1534 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1536 case CCValAssign::AExt:
1537 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1539 case CCValAssign::BCvt:
1540 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1544 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1545 if (VA.needsCustom()) {
1546 if (VA.getLocVT() == MVT::v2f64) {
1547 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1548 DAG.getConstant(0, MVT::i32));
1549 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1550 DAG.getConstant(1, MVT::i32));
1552 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1553 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1555 VA = ArgLocs[++i]; // skip ahead to next loc
1556 if (VA.isRegLoc()) {
1557 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1558 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1560 assert(VA.isMemLoc());
1562 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1563 dl, DAG, VA, Flags));
1566 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1567 StackPtr, MemOpChains, Flags);
1569 } else if (VA.isRegLoc()) {
1570 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1571 assert(VA.getLocVT() == MVT::i32 &&
1572 "unexpected calling convention register assignment");
1573 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1574 "unexpected use of 'returned'");
1575 isThisReturn = true;
1577 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1578 } else if (isByVal) {
1579 assert(VA.isMemLoc());
1580 unsigned offset = 0;
1582 // True if this byval aggregate will be split between registers
1584 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1585 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1587 if (CurByValIdx < ByValArgsCount) {
1589 unsigned RegBegin, RegEnd;
1590 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1592 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1594 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1595 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1596 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1597 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1598 MachinePointerInfo(),
1599 false, false, false,
1600 DAG.InferPtrAlignment(AddArg));
1601 MemOpChains.push_back(Load.getValue(1));
1602 RegsToPass.push_back(std::make_pair(j, Load));
1605 // If parameter size outsides register area, "offset" value
1606 // helps us to calculate stack slot for remained part properly.
1607 offset = RegEnd - RegBegin;
1609 CCInfo.nextInRegsParam();
1612 if (Flags.getByValSize() > 4*offset) {
1613 unsigned LocMemOffset = VA.getLocMemOffset();
1614 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1615 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1617 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1618 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1619 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1621 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
1623 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1624 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1625 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1628 } else if (!isSibCall) {
1629 assert(VA.isMemLoc());
1631 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1632 dl, DAG, VA, Flags));
1636 if (!MemOpChains.empty())
1637 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1639 // Build a sequence of copy-to-reg nodes chained together with token chain
1640 // and flag operands which copy the outgoing args into the appropriate regs.
1642 // Tail call byval lowering might overwrite argument registers so in case of
1643 // tail call optimization the copies to registers are lowered later.
1645 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1646 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1647 RegsToPass[i].second, InFlag);
1648 InFlag = Chain.getValue(1);
1651 // For tail calls lower the arguments to the 'real' stack slot.
1653 // Force all the incoming stack arguments to be loaded from the stack
1654 // before any new outgoing arguments are stored to the stack, because the
1655 // outgoing stack slots may alias the incoming argument stack slots, and
1656 // the alias isn't otherwise explicit. This is slightly more conservative
1657 // than necessary, because it means that each store effectively depends
1658 // on every argument instead of just those arguments it would clobber.
1660 // Do not flag preceding copytoreg stuff together with the following stuff.
1662 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1663 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1664 RegsToPass[i].second, InFlag);
1665 InFlag = Chain.getValue(1);
1670 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1671 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1672 // node so that legalize doesn't hack it.
1673 bool isDirect = false;
1674 bool isARMFunc = false;
1675 bool isLocalARMFunc = false;
1676 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1678 if (EnableARMLongCalls) {
1679 assert((Subtarget->isTargetWindows() ||
1680 getTargetMachine().getRelocationModel() == Reloc::Static) &&
1681 "long-calls with non-static relocation model!");
1682 // Handle a global address or an external symbol. If it's not one of
1683 // those, the target's already in a register, so we don't need to do
1685 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1686 const GlobalValue *GV = G->getGlobal();
1687 // Create a constant pool entry for the callee address
1688 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1689 ARMConstantPoolValue *CPV =
1690 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1692 // Get the address of the callee into a register
1693 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1694 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1695 Callee = DAG.getLoad(getPointerTy(), dl,
1696 DAG.getEntryNode(), CPAddr,
1697 MachinePointerInfo::getConstantPool(),
1698 false, false, false, 0);
1699 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1700 const char *Sym = S->getSymbol();
1702 // Create a constant pool entry for the callee address
1703 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1704 ARMConstantPoolValue *CPV =
1705 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1706 ARMPCLabelIndex, 0);
1707 // Get the address of the callee into a register
1708 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1709 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1710 Callee = DAG.getLoad(getPointerTy(), dl,
1711 DAG.getEntryNode(), CPAddr,
1712 MachinePointerInfo::getConstantPool(),
1713 false, false, false, 0);
1715 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1716 const GlobalValue *GV = G->getGlobal();
1718 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1719 bool isStub = (isExt && Subtarget->isTargetMachO()) &&
1720 getTargetMachine().getRelocationModel() != Reloc::Static;
1721 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1722 // ARM call to a local ARM function is predicable.
1723 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1724 // tBX takes a register source operand.
1725 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1726 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
1727 Callee = DAG.getNode(ARMISD::WrapperPIC, dl, getPointerTy(),
1728 DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
1729 0, ARMII::MO_NONLAZY));
1730 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
1731 MachinePointerInfo::getGOT(), false, false, true, 0);
1732 } else if (Subtarget->isTargetCOFF()) {
1733 assert(Subtarget->isTargetWindows() &&
1734 "Windows is the only supported COFF target");
1735 unsigned TargetFlags = GV->hasDLLImportStorageClass()
1736 ? ARMII::MO_DLLIMPORT
1737 : ARMII::MO_NO_FLAG;
1738 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), /*Offset=*/0,
1740 if (GV->hasDLLImportStorageClass())
1741 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1742 DAG.getNode(ARMISD::Wrapper, dl, getPointerTy(),
1743 Callee), MachinePointerInfo::getGOT(),
1744 false, false, false, 0);
1746 // On ELF targets for PIC code, direct calls should go through the PLT
1747 unsigned OpFlags = 0;
1748 if (Subtarget->isTargetELF() &&
1749 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1750 OpFlags = ARMII::MO_PLT;
1751 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1753 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1755 bool isStub = Subtarget->isTargetMachO() &&
1756 getTargetMachine().getRelocationModel() != Reloc::Static;
1757 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1758 // tBX takes a register source operand.
1759 const char *Sym = S->getSymbol();
1760 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1761 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1762 ARMConstantPoolValue *CPV =
1763 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1764 ARMPCLabelIndex, 4);
1765 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1766 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1767 Callee = DAG.getLoad(getPointerTy(), dl,
1768 DAG.getEntryNode(), CPAddr,
1769 MachinePointerInfo::getConstantPool(),
1770 false, false, false, 0);
1771 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1772 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1773 getPointerTy(), Callee, PICLabel);
1775 unsigned OpFlags = 0;
1776 // On ELF targets for PIC code, direct calls should go through the PLT
1777 if (Subtarget->isTargetELF() &&
1778 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1779 OpFlags = ARMII::MO_PLT;
1780 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1784 // FIXME: handle tail calls differently.
1786 bool HasMinSizeAttr = MF.getFunction()->getAttributes().hasAttribute(
1787 AttributeSet::FunctionIndex, Attribute::MinSize);
1788 if (Subtarget->isThumb()) {
1789 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1790 CallOpc = ARMISD::CALL_NOLINK;
1792 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1794 if (!isDirect && !Subtarget->hasV5TOps())
1795 CallOpc = ARMISD::CALL_NOLINK;
1796 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1797 // Emit regular call when code size is the priority
1799 // "mov lr, pc; b _foo" to avoid confusing the RSP
1800 CallOpc = ARMISD::CALL_NOLINK;
1802 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1805 std::vector<SDValue> Ops;
1806 Ops.push_back(Chain);
1807 Ops.push_back(Callee);
1809 // Add argument registers to the end of the list so that they are known live
1811 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1812 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1813 RegsToPass[i].second.getValueType()));
1815 // Add a register mask operand representing the call-preserved registers.
1817 const uint32_t *Mask;
1818 const TargetRegisterInfo *TRI =
1819 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
1820 const ARMBaseRegisterInfo *ARI = static_cast<const ARMBaseRegisterInfo*>(TRI);
1822 // For 'this' returns, use the R0-preserving mask if applicable
1823 Mask = ARI->getThisReturnPreservedMask(CallConv);
1825 // Set isThisReturn to false if the calling convention is not one that
1826 // allows 'returned' to be modeled in this way, so LowerCallResult does
1827 // not try to pass 'this' straight through
1828 isThisReturn = false;
1829 Mask = ARI->getCallPreservedMask(CallConv);
1832 Mask = ARI->getCallPreservedMask(CallConv);
1834 assert(Mask && "Missing call preserved mask for calling convention");
1835 Ops.push_back(DAG.getRegisterMask(Mask));
1838 if (InFlag.getNode())
1839 Ops.push_back(InFlag);
1841 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1843 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
1845 // Returns a chain and a flag for retval copy to use.
1846 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
1847 InFlag = Chain.getValue(1);
1849 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1850 DAG.getIntPtrConstant(0, true), InFlag, dl);
1852 InFlag = Chain.getValue(1);
1854 // Handle result values, copying them out of physregs into vregs that we
1856 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1857 InVals, isThisReturn,
1858 isThisReturn ? OutVals[0] : SDValue());
1861 /// HandleByVal - Every parameter *after* a byval parameter is passed
1862 /// on the stack. Remember the next parameter register to allocate,
1863 /// and then confiscate the rest of the parameter registers to insure
1866 ARMTargetLowering::HandleByVal(
1867 CCState *State, unsigned &size, unsigned Align) const {
1868 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1869 assert((State->getCallOrPrologue() == Prologue ||
1870 State->getCallOrPrologue() == Call) &&
1871 "unhandled ParmContext");
1873 if ((ARM::R0 <= reg) && (reg <= ARM::R3)) {
1874 if (Subtarget->isAAPCS_ABI() && Align > 4) {
1875 unsigned AlignInRegs = Align / 4;
1876 unsigned Waste = (ARM::R4 - reg) % AlignInRegs;
1877 for (unsigned i = 0; i < Waste; ++i)
1878 reg = State->AllocateReg(GPRArgRegs, 4);
1881 unsigned excess = 4 * (ARM::R4 - reg);
1883 // Special case when NSAA != SP and parameter size greater than size of
1884 // all remained GPR regs. In that case we can't split parameter, we must
1885 // send it to stack. We also must set NCRN to R4, so waste all
1886 // remained registers.
1887 const unsigned NSAAOffset = State->getNextStackOffset();
1888 if (Subtarget->isAAPCS_ABI() && NSAAOffset != 0 && size > excess) {
1889 while (State->AllocateReg(GPRArgRegs, 4))
1894 // First register for byval parameter is the first register that wasn't
1895 // allocated before this method call, so it would be "reg".
1896 // If parameter is small enough to be saved in range [reg, r4), then
1897 // the end (first after last) register would be reg + param-size-in-regs,
1898 // else parameter would be splitted between registers and stack,
1899 // end register would be r4 in this case.
1900 unsigned ByValRegBegin = reg;
1901 unsigned ByValRegEnd = (size < excess) ? reg + size/4 : (unsigned)ARM::R4;
1902 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
1903 // Note, first register is allocated in the beginning of function already,
1904 // allocate remained amount of registers we need.
1905 for (unsigned i = reg+1; i != ByValRegEnd; ++i)
1906 State->AllocateReg(GPRArgRegs, 4);
1907 // A byval parameter that is split between registers and memory needs its
1908 // size truncated here.
1909 // In the case where the entire structure fits in registers, we set the
1910 // size in memory to zero.
1919 /// MatchingStackOffset - Return true if the given stack call argument is
1920 /// already available in the same position (relatively) of the caller's
1921 /// incoming argument stack.
1923 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1924 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1925 const TargetInstrInfo *TII) {
1926 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1928 if (Arg.getOpcode() == ISD::CopyFromReg) {
1929 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1930 if (!TargetRegisterInfo::isVirtualRegister(VR))
1932 MachineInstr *Def = MRI->getVRegDef(VR);
1935 if (!Flags.isByVal()) {
1936 if (!TII->isLoadFromStackSlot(Def, FI))
1941 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1942 if (Flags.isByVal())
1943 // ByVal argument is passed in as a pointer but it's now being
1944 // dereferenced. e.g.
1945 // define @foo(%struct.X* %A) {
1946 // tail call @bar(%struct.X* byval %A)
1949 SDValue Ptr = Ld->getBasePtr();
1950 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1953 FI = FINode->getIndex();
1957 assert(FI != INT_MAX);
1958 if (!MFI->isFixedObjectIndex(FI))
1960 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1963 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1964 /// for tail call optimization. Targets which want to do tail call
1965 /// optimization should implement this function.
1967 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1968 CallingConv::ID CalleeCC,
1970 bool isCalleeStructRet,
1971 bool isCallerStructRet,
1972 const SmallVectorImpl<ISD::OutputArg> &Outs,
1973 const SmallVectorImpl<SDValue> &OutVals,
1974 const SmallVectorImpl<ISD::InputArg> &Ins,
1975 SelectionDAG& DAG) const {
1976 const Function *CallerF = DAG.getMachineFunction().getFunction();
1977 CallingConv::ID CallerCC = CallerF->getCallingConv();
1978 bool CCMatch = CallerCC == CalleeCC;
1980 // Look for obvious safe cases to perform tail call optimization that do not
1981 // require ABI changes. This is what gcc calls sibcall.
1983 // Do not sibcall optimize vararg calls unless the call site is not passing
1985 if (isVarArg && !Outs.empty())
1988 // Exception-handling functions need a special set of instructions to indicate
1989 // a return to the hardware. Tail-calling another function would probably
1991 if (CallerF->hasFnAttribute("interrupt"))
1994 // Also avoid sibcall optimization if either caller or callee uses struct
1995 // return semantics.
1996 if (isCalleeStructRet || isCallerStructRet)
1999 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
2000 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
2001 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
2002 // support in the assembler and linker to be used. This would need to be
2003 // fixed to fully support tail calls in Thumb1.
2005 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
2006 // LR. This means if we need to reload LR, it takes an extra instructions,
2007 // which outweighs the value of the tail call; but here we don't know yet
2008 // whether LR is going to be used. Probably the right approach is to
2009 // generate the tail call here and turn it back into CALL/RET in
2010 // emitEpilogue if LR is used.
2012 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
2013 // but we need to make sure there are enough registers; the only valid
2014 // registers are the 4 used for parameters. We don't currently do this
2016 if (Subtarget->isThumb1Only())
2019 // Externally-defined functions with weak linkage should not be
2020 // tail-called on ARM when the OS does not support dynamic
2021 // pre-emption of symbols, as the AAELF spec requires normal calls
2022 // to undefined weak functions to be replaced with a NOP or jump to the
2023 // next instruction. The behaviour of branch instructions in this
2024 // situation (as used for tail calls) is implementation-defined, so we
2025 // cannot rely on the linker replacing the tail call with a return.
2026 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2027 const GlobalValue *GV = G->getGlobal();
2028 if (GV->hasExternalWeakLinkage())
2032 // If the calling conventions do not match, then we'd better make sure the
2033 // results are returned in the same way as what the caller expects.
2035 SmallVector<CCValAssign, 16> RVLocs1;
2036 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2037 *DAG.getContext(), Call);
2038 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
2040 SmallVector<CCValAssign, 16> RVLocs2;
2041 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2042 *DAG.getContext(), Call);
2043 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
2045 if (RVLocs1.size() != RVLocs2.size())
2047 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2048 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2050 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2052 if (RVLocs1[i].isRegLoc()) {
2053 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2056 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2062 // If Caller's vararg or byval argument has been split between registers and
2063 // stack, do not perform tail call, since part of the argument is in caller's
2065 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
2066 getInfo<ARMFunctionInfo>();
2067 if (AFI_Caller->getArgRegsSaveSize())
2070 // If the callee takes no arguments then go on to check the results of the
2072 if (!Outs.empty()) {
2073 // Check if stack adjustment is needed. For now, do not do this if any
2074 // argument is passed on the stack.
2075 SmallVector<CCValAssign, 16> ArgLocs;
2076 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2077 *DAG.getContext(), Call);
2078 CCInfo.AnalyzeCallOperands(Outs,
2079 CCAssignFnForNode(CalleeCC, false, isVarArg));
2080 if (CCInfo.getNextStackOffset()) {
2081 MachineFunction &MF = DAG.getMachineFunction();
2083 // Check if the arguments are already laid out in the right way as
2084 // the caller's fixed stack objects.
2085 MachineFrameInfo *MFI = MF.getFrameInfo();
2086 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2087 const TargetInstrInfo *TII =
2088 getTargetMachine().getSubtargetImpl()->getInstrInfo();
2089 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2091 ++i, ++realArgIdx) {
2092 CCValAssign &VA = ArgLocs[i];
2093 EVT RegVT = VA.getLocVT();
2094 SDValue Arg = OutVals[realArgIdx];
2095 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2096 if (VA.getLocInfo() == CCValAssign::Indirect)
2098 if (VA.needsCustom()) {
2099 // f64 and vector types are split into multiple registers or
2100 // register/stack-slot combinations. The types will not match
2101 // the registers; give up on memory f64 refs until we figure
2102 // out what to do about this.
2105 if (!ArgLocs[++i].isRegLoc())
2107 if (RegVT == MVT::v2f64) {
2108 if (!ArgLocs[++i].isRegLoc())
2110 if (!ArgLocs[++i].isRegLoc())
2113 } else if (!VA.isRegLoc()) {
2114 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2126 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2127 MachineFunction &MF, bool isVarArg,
2128 const SmallVectorImpl<ISD::OutputArg> &Outs,
2129 LLVMContext &Context) const {
2130 SmallVector<CCValAssign, 16> RVLocs;
2131 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2132 return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2136 static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2137 SDLoc DL, SelectionDAG &DAG) {
2138 const MachineFunction &MF = DAG.getMachineFunction();
2139 const Function *F = MF.getFunction();
2141 StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
2143 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2144 // version of the "preferred return address". These offsets affect the return
2145 // instruction if this is a return from PL1 without hypervisor extensions.
2146 // IRQ/FIQ: +4 "subs pc, lr, #4"
2147 // SWI: 0 "subs pc, lr, #0"
2148 // ABORT: +4 "subs pc, lr, #4"
2149 // UNDEF: +4/+2 "subs pc, lr, #0"
2150 // UNDEF varies depending on where the exception came from ARM or Thumb
2151 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2154 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2157 else if (IntKind == "SWI" || IntKind == "UNDEF")
2160 report_fatal_error("Unsupported interrupt attribute. If present, value "
2161 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2163 RetOps.insert(RetOps.begin() + 1, DAG.getConstant(LROffset, MVT::i32, false));
2165 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2169 ARMTargetLowering::LowerReturn(SDValue Chain,
2170 CallingConv::ID CallConv, bool isVarArg,
2171 const SmallVectorImpl<ISD::OutputArg> &Outs,
2172 const SmallVectorImpl<SDValue> &OutVals,
2173 SDLoc dl, SelectionDAG &DAG) const {
2175 // CCValAssign - represent the assignment of the return value to a location.
2176 SmallVector<CCValAssign, 16> RVLocs;
2178 // CCState - Info about the registers and stack slots.
2179 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2180 *DAG.getContext(), Call);
2182 // Analyze outgoing return values.
2183 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2187 SmallVector<SDValue, 4> RetOps;
2188 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2189 bool isLittleEndian = Subtarget->isLittle();
2191 MachineFunction &MF = DAG.getMachineFunction();
2192 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2193 AFI->setReturnRegsCount(RVLocs.size());
2195 // Copy the result values into the output registers.
2196 for (unsigned i = 0, realRVLocIdx = 0;
2198 ++i, ++realRVLocIdx) {
2199 CCValAssign &VA = RVLocs[i];
2200 assert(VA.isRegLoc() && "Can only return in registers!");
2202 SDValue Arg = OutVals[realRVLocIdx];
2204 switch (VA.getLocInfo()) {
2205 default: llvm_unreachable("Unknown loc info!");
2206 case CCValAssign::Full: break;
2207 case CCValAssign::BCvt:
2208 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2212 if (VA.needsCustom()) {
2213 if (VA.getLocVT() == MVT::v2f64) {
2214 // Extract the first half and return it in two registers.
2215 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2216 DAG.getConstant(0, MVT::i32));
2217 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2218 DAG.getVTList(MVT::i32, MVT::i32), Half);
2220 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2221 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2223 Flag = Chain.getValue(1);
2224 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2225 VA = RVLocs[++i]; // skip ahead to next loc
2226 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2227 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2229 Flag = Chain.getValue(1);
2230 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2231 VA = RVLocs[++i]; // skip ahead to next loc
2233 // Extract the 2nd half and fall through to handle it as an f64 value.
2234 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2235 DAG.getConstant(1, MVT::i32));
2237 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2239 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2240 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2241 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2242 fmrrd.getValue(isLittleEndian ? 0 : 1),
2244 Flag = Chain.getValue(1);
2245 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2246 VA = RVLocs[++i]; // skip ahead to next loc
2247 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2248 fmrrd.getValue(isLittleEndian ? 1 : 0),
2251 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2253 // Guarantee that all emitted copies are
2254 // stuck together, avoiding something bad.
2255 Flag = Chain.getValue(1);
2256 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2259 // Update chain and glue.
2262 RetOps.push_back(Flag);
2264 // CPUs which aren't M-class use a special sequence to return from
2265 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2266 // though we use "subs pc, lr, #N").
2268 // M-class CPUs actually use a normal return sequence with a special
2269 // (hardware-provided) value in LR, so the normal code path works.
2270 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2271 !Subtarget->isMClass()) {
2272 if (Subtarget->isThumb1Only())
2273 report_fatal_error("interrupt attribute is not supported in Thumb1");
2274 return LowerInterruptReturn(RetOps, dl, DAG);
2277 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2280 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2281 if (N->getNumValues() != 1)
2283 if (!N->hasNUsesOfValue(1, 0))
2286 SDValue TCChain = Chain;
2287 SDNode *Copy = *N->use_begin();
2288 if (Copy->getOpcode() == ISD::CopyToReg) {
2289 // If the copy has a glue operand, we conservatively assume it isn't safe to
2290 // perform a tail call.
2291 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2293 TCChain = Copy->getOperand(0);
2294 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2295 SDNode *VMov = Copy;
2296 // f64 returned in a pair of GPRs.
2297 SmallPtrSet<SDNode*, 2> Copies;
2298 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2300 if (UI->getOpcode() != ISD::CopyToReg)
2304 if (Copies.size() > 2)
2307 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2309 SDValue UseChain = UI->getOperand(0);
2310 if (Copies.count(UseChain.getNode()))
2314 // We are at the top of this chain.
2315 // If the copy has a glue operand, we conservatively assume it
2316 // isn't safe to perform a tail call.
2317 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2323 } else if (Copy->getOpcode() == ISD::BITCAST) {
2324 // f32 returned in a single GPR.
2325 if (!Copy->hasOneUse())
2327 Copy = *Copy->use_begin();
2328 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2330 // If the copy has a glue operand, we conservatively assume it isn't safe to
2331 // perform a tail call.
2332 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2334 TCChain = Copy->getOperand(0);
2339 bool HasRet = false;
2340 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2342 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2343 UI->getOpcode() != ARMISD::INTRET_FLAG)
2355 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2356 if (!Subtarget->supportsTailCall())
2359 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2362 return !Subtarget->isThumb1Only();
2365 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2366 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2367 // one of the above mentioned nodes. It has to be wrapped because otherwise
2368 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2369 // be used to form addressing mode. These wrapped nodes will be selected
2371 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2372 EVT PtrVT = Op.getValueType();
2373 // FIXME there is no actual debug info here
2375 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2377 if (CP->isMachineConstantPoolEntry())
2378 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2379 CP->getAlignment());
2381 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2382 CP->getAlignment());
2383 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2386 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2387 return MachineJumpTableInfo::EK_Inline;
2390 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2391 SelectionDAG &DAG) const {
2392 MachineFunction &MF = DAG.getMachineFunction();
2393 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2394 unsigned ARMPCLabelIndex = 0;
2396 EVT PtrVT = getPointerTy();
2397 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2398 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2400 if (RelocM == Reloc::Static) {
2401 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2403 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2404 ARMPCLabelIndex = AFI->createPICLabelUId();
2405 ARMConstantPoolValue *CPV =
2406 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2407 ARMCP::CPBlockAddress, PCAdj);
2408 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2410 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2411 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2412 MachinePointerInfo::getConstantPool(),
2413 false, false, false, 0);
2414 if (RelocM == Reloc::Static)
2416 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2417 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2420 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2422 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2423 SelectionDAG &DAG) const {
2425 EVT PtrVT = getPointerTy();
2426 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2427 MachineFunction &MF = DAG.getMachineFunction();
2428 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2429 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2430 ARMConstantPoolValue *CPV =
2431 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2432 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2433 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2434 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2435 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2436 MachinePointerInfo::getConstantPool(),
2437 false, false, false, 0);
2438 SDValue Chain = Argument.getValue(1);
2440 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2441 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2443 // call __tls_get_addr.
2446 Entry.Node = Argument;
2447 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2448 Args.push_back(Entry);
2450 // FIXME: is there useful debug info available here?
2451 TargetLowering::CallLoweringInfo CLI(DAG);
2452 CLI.setDebugLoc(dl).setChain(Chain)
2453 .setCallee(CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2454 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args),
2457 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2458 return CallResult.first;
2461 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2462 // "local exec" model.
2464 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2466 TLSModel::Model model) const {
2467 const GlobalValue *GV = GA->getGlobal();
2470 SDValue Chain = DAG.getEntryNode();
2471 EVT PtrVT = getPointerTy();
2472 // Get the Thread Pointer
2473 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2475 if (model == TLSModel::InitialExec) {
2476 MachineFunction &MF = DAG.getMachineFunction();
2477 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2478 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2479 // Initial exec model.
2480 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2481 ARMConstantPoolValue *CPV =
2482 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2483 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2485 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2486 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2487 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2488 MachinePointerInfo::getConstantPool(),
2489 false, false, false, 0);
2490 Chain = Offset.getValue(1);
2492 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2493 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2495 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2496 MachinePointerInfo::getConstantPool(),
2497 false, false, false, 0);
2500 assert(model == TLSModel::LocalExec);
2501 ARMConstantPoolValue *CPV =
2502 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2503 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2504 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2505 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2506 MachinePointerInfo::getConstantPool(),
2507 false, false, false, 0);
2510 // The address of the thread local variable is the add of the thread
2511 // pointer with the offset of the variable.
2512 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2516 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2517 // TODO: implement the "local dynamic" model
2518 assert(Subtarget->isTargetELF() &&
2519 "TLS not implemented for non-ELF targets");
2520 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2522 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2525 case TLSModel::GeneralDynamic:
2526 case TLSModel::LocalDynamic:
2527 return LowerToTLSGeneralDynamicModel(GA, DAG);
2528 case TLSModel::InitialExec:
2529 case TLSModel::LocalExec:
2530 return LowerToTLSExecModels(GA, DAG, model);
2532 llvm_unreachable("bogus TLS model");
2535 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2536 SelectionDAG &DAG) const {
2537 EVT PtrVT = getPointerTy();
2539 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2540 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2541 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2542 ARMConstantPoolValue *CPV =
2543 ARMConstantPoolConstant::Create(GV,
2544 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2545 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2546 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2547 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2549 MachinePointerInfo::getConstantPool(),
2550 false, false, false, 0);
2551 SDValue Chain = Result.getValue(1);
2552 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2553 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2555 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2556 MachinePointerInfo::getGOT(),
2557 false, false, false, 0);
2561 // If we have T2 ops, we can materialize the address directly via movt/movw
2562 // pair. This is always cheaper.
2563 if (Subtarget->useMovt(DAG.getMachineFunction())) {
2565 // FIXME: Once remat is capable of dealing with instructions with register
2566 // operands, expand this into two nodes.
2567 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2568 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2570 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2571 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2572 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2573 MachinePointerInfo::getConstantPool(),
2574 false, false, false, 0);
2578 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2579 SelectionDAG &DAG) const {
2580 EVT PtrVT = getPointerTy();
2582 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2583 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2585 if (Subtarget->useMovt(DAG.getMachineFunction()))
2588 // FIXME: Once remat is capable of dealing with instructions with register
2589 // operands, expand this into multiple nodes
2591 RelocM == Reloc::PIC_ ? ARMISD::WrapperPIC : ARMISD::Wrapper;
2593 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2594 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
2596 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2597 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2598 MachinePointerInfo::getGOT(), false, false, false, 0);
2602 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
2603 SelectionDAG &DAG) const {
2604 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
2605 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&
2606 "Windows on ARM expects to use movw/movt");
2608 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2609 const ARMII::TOF TargetFlags =
2610 (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
2611 EVT PtrVT = getPointerTy();
2617 // FIXME: Once remat is capable of dealing with instructions with register
2618 // operands, expand this into two nodes.
2619 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
2620 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
2622 if (GV->hasDLLImportStorageClass())
2623 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2624 MachinePointerInfo::getGOT(), false, false, false, 0);
2628 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2629 SelectionDAG &DAG) const {
2630 assert(Subtarget->isTargetELF() &&
2631 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2632 MachineFunction &MF = DAG.getMachineFunction();
2633 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2634 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2635 EVT PtrVT = getPointerTy();
2637 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2638 ARMConstantPoolValue *CPV =
2639 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2640 ARMPCLabelIndex, PCAdj);
2641 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2642 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2643 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2644 MachinePointerInfo::getConstantPool(),
2645 false, false, false, 0);
2646 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2647 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2651 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2653 SDValue Val = DAG.getConstant(0, MVT::i32);
2654 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2655 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2656 Op.getOperand(1), Val);
2660 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2662 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2663 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2667 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2668 const ARMSubtarget *Subtarget) const {
2669 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2672 default: return SDValue(); // Don't custom lower most intrinsics.
2673 case Intrinsic::arm_rbit: {
2674 assert(Op.getOperand(1).getValueType() == MVT::i32 &&
2675 "RBIT intrinsic must have i32 type!");
2676 return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(1));
2678 case Intrinsic::arm_thread_pointer: {
2679 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2680 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2682 case Intrinsic::eh_sjlj_lsda: {
2683 MachineFunction &MF = DAG.getMachineFunction();
2684 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2685 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2686 EVT PtrVT = getPointerTy();
2687 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2689 unsigned PCAdj = (RelocM != Reloc::PIC_)
2690 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2691 ARMConstantPoolValue *CPV =
2692 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2693 ARMCP::CPLSDA, PCAdj);
2694 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2695 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2697 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2698 MachinePointerInfo::getConstantPool(),
2699 false, false, false, 0);
2701 if (RelocM == Reloc::PIC_) {
2702 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2703 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2707 case Intrinsic::arm_neon_vmulls:
2708 case Intrinsic::arm_neon_vmullu: {
2709 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2710 ? ARMISD::VMULLs : ARMISD::VMULLu;
2711 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2712 Op.getOperand(1), Op.getOperand(2));
2717 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2718 const ARMSubtarget *Subtarget) {
2719 // FIXME: handle "fence singlethread" more efficiently.
2721 if (!Subtarget->hasDataBarrier()) {
2722 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2723 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2725 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2726 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
2727 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2728 DAG.getConstant(0, MVT::i32));
2731 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
2732 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
2733 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
2734 if (Subtarget->isMClass()) {
2735 // Only a full system barrier exists in the M-class architectures.
2736 Domain = ARM_MB::SY;
2737 } else if (Subtarget->isSwift() && Ord == Release) {
2738 // Swift happens to implement ISHST barriers in a way that's compatible with
2739 // Release semantics but weaker than ISH so we'd be fools not to use
2740 // it. Beware: other processors probably don't!
2741 Domain = ARM_MB::ISHST;
2744 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
2745 DAG.getConstant(Intrinsic::arm_dmb, MVT::i32),
2746 DAG.getConstant(Domain, MVT::i32));
2749 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2750 const ARMSubtarget *Subtarget) {
2751 // ARM pre v5TE and Thumb1 does not have preload instructions.
2752 if (!(Subtarget->isThumb2() ||
2753 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2754 // Just preserve the chain.
2755 return Op.getOperand(0);
2758 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2760 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2761 // ARMv7 with MP extension has PLDW.
2762 return Op.getOperand(0);
2764 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2765 if (Subtarget->isThumb()) {
2767 isRead = ~isRead & 1;
2768 isData = ~isData & 1;
2771 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2772 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2773 DAG.getConstant(isData, MVT::i32));
2776 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2777 MachineFunction &MF = DAG.getMachineFunction();
2778 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2780 // vastart just stores the address of the VarArgsFrameIndex slot into the
2781 // memory location argument.
2783 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2784 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2785 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2786 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2787 MachinePointerInfo(SV), false, false, 0);
2791 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2792 SDValue &Root, SelectionDAG &DAG,
2794 MachineFunction &MF = DAG.getMachineFunction();
2795 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2797 const TargetRegisterClass *RC;
2798 if (AFI->isThumb1OnlyFunction())
2799 RC = &ARM::tGPRRegClass;
2801 RC = &ARM::GPRRegClass;
2803 // Transform the arguments stored in physical registers into virtual ones.
2804 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2805 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2808 if (NextVA.isMemLoc()) {
2809 MachineFrameInfo *MFI = MF.getFrameInfo();
2810 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2812 // Create load node to retrieve arguments from the stack.
2813 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2814 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2815 MachinePointerInfo::getFixedStack(FI),
2816 false, false, false, 0);
2818 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2819 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2821 if (!Subtarget->isLittle())
2822 std::swap (ArgValue, ArgValue2);
2823 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2827 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2828 unsigned InRegsParamRecordIdx,
2830 unsigned &ArgRegsSize,
2831 unsigned &ArgRegsSaveSize)
2834 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2835 unsigned RBegin, REnd;
2836 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2837 NumGPRs = REnd - RBegin;
2839 unsigned int firstUnalloced;
2840 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2841 sizeof(GPRArgRegs) /
2842 sizeof(GPRArgRegs[0]));
2843 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2846 unsigned Align = MF.getTarget()
2848 ->getFrameLowering()
2849 ->getStackAlignment();
2850 ArgRegsSize = NumGPRs * 4;
2852 // If parameter is split between stack and GPRs...
2853 if (NumGPRs && Align > 4 &&
2854 (ArgRegsSize < ArgSize ||
2855 InRegsParamRecordIdx >= CCInfo.getInRegsParamsCount())) {
2856 // Add padding for part of param recovered from GPRs. For example,
2857 // if Align == 8, its last byte must be at address K*8 - 1.
2858 // We need to do it, since remained (stack) part of parameter has
2859 // stack alignment, and we need to "attach" "GPRs head" without gaps
2862 // |---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
2863 // [ [padding] [GPRs head] ] [ Tail passed via stack ....
2865 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2867 OffsetToAlignment(ArgRegsSize + AFI->getArgRegsSaveSize(), Align);
2868 ArgRegsSaveSize = ArgRegsSize + Padding;
2870 // We don't need to extend regs save size for byval parameters if they
2871 // are passed via GPRs only.
2872 ArgRegsSaveSize = ArgRegsSize;
2875 // The remaining GPRs hold either the beginning of variable-argument
2876 // data, or the beginning of an aggregate passed by value (usually
2877 // byval). Either way, we allocate stack slots adjacent to the data
2878 // provided by our caller, and store the unallocated registers there.
2879 // If this is a variadic function, the va_list pointer will begin with
2880 // these values; otherwise, this reassembles a (byval) structure that
2881 // was split between registers and memory.
2882 // Return: The frame index registers were stored into.
2884 ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
2885 SDLoc dl, SDValue &Chain,
2886 const Value *OrigArg,
2887 unsigned InRegsParamRecordIdx,
2888 unsigned OffsetFromOrigArg,
2892 unsigned ByValStoreOffset,
2893 unsigned TotalArgRegsSaveSize) const {
2895 // Currently, two use-cases possible:
2896 // Case #1. Non-var-args function, and we meet first byval parameter.
2897 // Setup first unallocated register as first byval register;
2898 // eat all remained registers
2899 // (these two actions are performed by HandleByVal method).
2900 // Then, here, we initialize stack frame with
2901 // "store-reg" instructions.
2902 // Case #2. Var-args function, that doesn't contain byval parameters.
2903 // The same: eat all remained unallocated registers,
2904 // initialize stack frame.
2906 MachineFunction &MF = DAG.getMachineFunction();
2907 MachineFrameInfo *MFI = MF.getFrameInfo();
2908 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2909 unsigned firstRegToSaveIndex, lastRegToSaveIndex;
2910 unsigned RBegin, REnd;
2911 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2912 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2913 firstRegToSaveIndex = RBegin - ARM::R0;
2914 lastRegToSaveIndex = REnd - ARM::R0;
2916 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2917 (GPRArgRegs, array_lengthof(GPRArgRegs));
2918 lastRegToSaveIndex = 4;
2921 unsigned ArgRegsSize, ArgRegsSaveSize;
2922 computeRegArea(CCInfo, MF, InRegsParamRecordIdx, ArgSize,
2923 ArgRegsSize, ArgRegsSaveSize);
2925 // Store any by-val regs to their spots on the stack so that they may be
2926 // loaded by deferencing the result of formal parameter pointer or va_next.
2927 // Note: once stack area for byval/varargs registers
2928 // was initialized, it can't be initialized again.
2929 if (ArgRegsSaveSize) {
2930 unsigned Padding = ArgRegsSaveSize - ArgRegsSize;
2933 assert(AFI->getStoredByValParamsPadding() == 0 &&
2934 "The only parameter may be padded.");
2935 AFI->setStoredByValParamsPadding(Padding);
2938 int FrameIndex = MFI->CreateFixedObject(ArgRegsSaveSize,
2941 (int64_t)TotalArgRegsSaveSize,
2943 SDValue FIN = DAG.getFrameIndex(FrameIndex, getPointerTy());
2945 MFI->CreateFixedObject(Padding,
2946 ArgOffset + ByValStoreOffset -
2947 (int64_t)ArgRegsSaveSize,
2951 SmallVector<SDValue, 4> MemOps;
2952 for (unsigned i = 0; firstRegToSaveIndex < lastRegToSaveIndex;
2953 ++firstRegToSaveIndex, ++i) {
2954 const TargetRegisterClass *RC;
2955 if (AFI->isThumb1OnlyFunction())
2956 RC = &ARM::tGPRRegClass;
2958 RC = &ARM::GPRRegClass;
2960 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2961 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2963 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2964 MachinePointerInfo(OrigArg, OffsetFromOrigArg + 4*i),
2966 MemOps.push_back(Store);
2967 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2968 DAG.getConstant(4, getPointerTy()));
2971 AFI->setArgRegsSaveSize(ArgRegsSaveSize + AFI->getArgRegsSaveSize());
2973 if (!MemOps.empty())
2974 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2978 // We cannot allocate a zero-byte object for the first variadic argument,
2979 // so just make up a size.
2982 // This will point to the next argument passed via stack.
2983 return MFI->CreateFixedObject(
2984 ArgSize, ArgOffset, !ForceMutable);
2988 // Setup stack frame, the va_list pointer will start from.
2990 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2991 SDLoc dl, SDValue &Chain,
2993 unsigned TotalArgRegsSaveSize,
2994 bool ForceMutable) const {
2995 MachineFunction &MF = DAG.getMachineFunction();
2996 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2998 // Try to store any remaining integer argument regs
2999 // to their spots on the stack so that they may be loaded by deferencing
3000 // the result of va_next.
3001 // If there is no regs to be stored, just point address after last
3002 // argument passed via stack.
3004 StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3005 CCInfo.getInRegsParamsCount(), 0, ArgOffset, 0, ForceMutable,
3006 0, TotalArgRegsSaveSize);
3008 AFI->setVarArgsFrameIndex(FrameIndex);
3012 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
3013 CallingConv::ID CallConv, bool isVarArg,
3014 const SmallVectorImpl<ISD::InputArg>
3016 SDLoc dl, SelectionDAG &DAG,
3017 SmallVectorImpl<SDValue> &InVals)
3019 MachineFunction &MF = DAG.getMachineFunction();
3020 MachineFrameInfo *MFI = MF.getFrameInfo();
3022 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3024 // Assign locations to all of the incoming arguments.
3025 SmallVector<CCValAssign, 16> ArgLocs;
3026 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3027 *DAG.getContext(), Prologue);
3028 CCInfo.AnalyzeFormalArguments(Ins,
3029 CCAssignFnForNode(CallConv, /* Return*/ false,
3032 SmallVector<SDValue, 16> ArgValues;
3033 int lastInsIndex = -1;
3035 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
3036 unsigned CurArgIdx = 0;
3038 // Initially ArgRegsSaveSize is zero.
3039 // Then we increase this value each time we meet byval parameter.
3040 // We also increase this value in case of varargs function.
3041 AFI->setArgRegsSaveSize(0);
3043 unsigned ByValStoreOffset = 0;
3044 unsigned TotalArgRegsSaveSize = 0;
3045 unsigned ArgRegsSaveSizeMaxAlign = 4;
3047 // Calculate the amount of stack space that we need to allocate to store
3048 // byval and variadic arguments that are passed in registers.
3049 // We need to know this before we allocate the first byval or variadic
3050 // argument, as they will be allocated a stack slot below the CFA (Canonical
3051 // Frame Address, the stack pointer at entry to the function).
3052 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3053 CCValAssign &VA = ArgLocs[i];
3054 if (VA.isMemLoc()) {
3055 int index = VA.getValNo();
3056 if (index != lastInsIndex) {
3057 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3058 if (Flags.isByVal()) {
3059 unsigned ExtraArgRegsSize;
3060 unsigned ExtraArgRegsSaveSize;
3061 computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsProcessed(),
3062 Flags.getByValSize(),
3063 ExtraArgRegsSize, ExtraArgRegsSaveSize);
3065 TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
3066 if (Flags.getByValAlign() > ArgRegsSaveSizeMaxAlign)
3067 ArgRegsSaveSizeMaxAlign = Flags.getByValAlign();
3068 CCInfo.nextInRegsParam();
3070 lastInsIndex = index;
3074 CCInfo.rewindByValRegsInfo();
3076 if (isVarArg && MFI->hasVAStart()) {
3077 unsigned ExtraArgRegsSize;
3078 unsigned ExtraArgRegsSaveSize;
3079 computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsCount(), 0,
3080 ExtraArgRegsSize, ExtraArgRegsSaveSize);
3081 TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
3083 // If the arg regs save area contains N-byte aligned values, the
3084 // bottom of it must be at least N-byte aligned.
3085 TotalArgRegsSaveSize = RoundUpToAlignment(TotalArgRegsSaveSize, ArgRegsSaveSizeMaxAlign);
3086 TotalArgRegsSaveSize = std::min(TotalArgRegsSaveSize, 16U);
3088 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3089 CCValAssign &VA = ArgLocs[i];
3090 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
3091 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
3092 // Arguments stored in registers.
3093 if (VA.isRegLoc()) {
3094 EVT RegVT = VA.getLocVT();
3096 if (VA.needsCustom()) {
3097 // f64 and vector types are split up into multiple registers or
3098 // combinations of registers and stack slots.
3099 if (VA.getLocVT() == MVT::v2f64) {
3100 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3102 VA = ArgLocs[++i]; // skip ahead to next loc
3104 if (VA.isMemLoc()) {
3105 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
3106 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3107 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3108 MachinePointerInfo::getFixedStack(FI),
3109 false, false, false, 0);
3111 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3114 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3115 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3116 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
3117 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3118 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
3120 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3123 const TargetRegisterClass *RC;
3125 if (RegVT == MVT::f32)
3126 RC = &ARM::SPRRegClass;
3127 else if (RegVT == MVT::f64)
3128 RC = &ARM::DPRRegClass;
3129 else if (RegVT == MVT::v2f64)
3130 RC = &ARM::QPRRegClass;
3131 else if (RegVT == MVT::i32)
3132 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3133 : &ARM::GPRRegClass;
3135 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3137 // Transform the arguments in physical registers into virtual ones.
3138 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3139 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3142 // If this is an 8 or 16-bit value, it is really passed promoted
3143 // to 32 bits. Insert an assert[sz]ext to capture this, then
3144 // truncate to the right size.
3145 switch (VA.getLocInfo()) {
3146 default: llvm_unreachable("Unknown loc info!");
3147 case CCValAssign::Full: break;
3148 case CCValAssign::BCvt:
3149 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3151 case CCValAssign::SExt:
3152 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3153 DAG.getValueType(VA.getValVT()));
3154 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3156 case CCValAssign::ZExt:
3157 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3158 DAG.getValueType(VA.getValVT()));
3159 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3163 InVals.push_back(ArgValue);
3165 } else { // VA.isRegLoc()
3168 assert(VA.isMemLoc());
3169 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3171 int index = ArgLocs[i].getValNo();
3173 // Some Ins[] entries become multiple ArgLoc[] entries.
3174 // Process them only once.
3175 if (index != lastInsIndex)
3177 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3178 // FIXME: For now, all byval parameter objects are marked mutable.
3179 // This can be changed with more analysis.
3180 // In case of tail call optimization mark all arguments mutable.
3181 // Since they could be overwritten by lowering of arguments in case of
3183 if (Flags.isByVal()) {
3184 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3186 ByValStoreOffset = RoundUpToAlignment(ByValStoreOffset, Flags.getByValAlign());
3187 int FrameIndex = StoreByValRegs(
3188 CCInfo, DAG, dl, Chain, CurOrigArg,
3190 Ins[VA.getValNo()].PartOffset,
3191 VA.getLocMemOffset(),
3192 Flags.getByValSize(),
3193 true /*force mutable frames*/,
3195 TotalArgRegsSaveSize);
3196 ByValStoreOffset += Flags.getByValSize();
3197 ByValStoreOffset = std::min(ByValStoreOffset, 16U);
3198 InVals.push_back(DAG.getFrameIndex(FrameIndex, getPointerTy()));
3199 CCInfo.nextInRegsParam();
3201 unsigned FIOffset = VA.getLocMemOffset();
3202 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3205 // Create load nodes to retrieve arguments from the stack.
3206 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3207 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3208 MachinePointerInfo::getFixedStack(FI),
3209 false, false, false, 0));
3211 lastInsIndex = index;
3217 if (isVarArg && MFI->hasVAStart())
3218 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3219 CCInfo.getNextStackOffset(),
3220 TotalArgRegsSaveSize);
3222 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3227 /// isFloatingPointZero - Return true if this is +0.0.
3228 static bool isFloatingPointZero(SDValue Op) {
3229 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3230 return CFP->getValueAPF().isPosZero();
3231 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3232 // Maybe this has already been legalized into the constant pool?
3233 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3234 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3235 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3236 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3237 return CFP->getValueAPF().isPosZero();
3239 } else if (Op->getOpcode() == ISD::BITCAST &&
3240 Op->getValueType(0) == MVT::f64) {
3241 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3242 // created by LowerConstantFP().
3243 SDValue BitcastOp = Op->getOperand(0);
3244 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM) {
3245 SDValue MoveOp = BitcastOp->getOperand(0);
3246 if (MoveOp->getOpcode() == ISD::TargetConstant &&
3247 cast<ConstantSDNode>(MoveOp)->getZExtValue() == 0) {
3255 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3256 /// the given operands.
3258 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3259 SDValue &ARMcc, SelectionDAG &DAG,
3261 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3262 unsigned C = RHSC->getZExtValue();
3263 if (!isLegalICmpImmediate(C)) {
3264 // Constant does not fit, try adjusting it by one?
3269 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3270 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3271 RHS = DAG.getConstant(C-1, MVT::i32);
3276 if (C != 0 && isLegalICmpImmediate(C-1)) {
3277 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3278 RHS = DAG.getConstant(C-1, MVT::i32);
3283 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3284 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3285 RHS = DAG.getConstant(C+1, MVT::i32);
3290 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3291 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3292 RHS = DAG.getConstant(C+1, MVT::i32);
3299 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3300 ARMISD::NodeType CompareType;
3303 CompareType = ARMISD::CMP;
3308 CompareType = ARMISD::CMPZ;
3311 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3312 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3315 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3317 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
3319 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64);
3321 if (!isFloatingPointZero(RHS))
3322 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3324 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3325 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3328 /// duplicateCmp - Glue values can have only one use, so this function
3329 /// duplicates a comparison node.
3331 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3332 unsigned Opc = Cmp.getOpcode();
3334 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3335 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3337 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3338 Cmp = Cmp.getOperand(0);
3339 Opc = Cmp.getOpcode();
3340 if (Opc == ARMISD::CMPFP)
3341 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3343 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3344 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3346 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3349 std::pair<SDValue, SDValue>
3350 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3351 SDValue &ARMcc) const {
3352 assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3354 SDValue Value, OverflowCmp;
3355 SDValue LHS = Op.getOperand(0);
3356 SDValue RHS = Op.getOperand(1);
3359 // FIXME: We are currently always generating CMPs because we don't support
3360 // generating CMN through the backend. This is not as good as the natural
3361 // CMP case because it causes a register dependency and cannot be folded
3364 switch (Op.getOpcode()) {
3366 llvm_unreachable("Unknown overflow instruction!");
3368 ARMcc = DAG.getConstant(ARMCC::VC, MVT::i32);
3369 Value = DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(), LHS, RHS);
3370 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, Value, LHS);
3373 ARMcc = DAG.getConstant(ARMCC::HS, MVT::i32);
3374 Value = DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(), LHS, RHS);
3375 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, Value, LHS);
3378 ARMcc = DAG.getConstant(ARMCC::VC, MVT::i32);
3379 Value = DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(), LHS, RHS);
3380 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, LHS, RHS);
3383 ARMcc = DAG.getConstant(ARMCC::HS, MVT::i32);
3384 Value = DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(), LHS, RHS);
3385 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, LHS, RHS);
3389 return std::make_pair(Value, OverflowCmp);
3394 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
3395 // Let legalize expand this if it isn't a legal type yet.
3396 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
3399 SDValue Value, OverflowCmp;
3401 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
3402 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3403 // We use 0 and 1 as false and true values.
3404 SDValue TVal = DAG.getConstant(1, MVT::i32);
3405 SDValue FVal = DAG.getConstant(0, MVT::i32);
3406 EVT VT = Op.getValueType();
3408 SDValue Overflow = DAG.getNode(ARMISD::CMOV, SDLoc(Op), VT, TVal, FVal,
3409 ARMcc, CCR, OverflowCmp);
3411 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
3412 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
3416 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3417 SDValue Cond = Op.getOperand(0);
3418 SDValue SelectTrue = Op.getOperand(1);
3419 SDValue SelectFalse = Op.getOperand(2);
3421 unsigned Opc = Cond.getOpcode();
3423 if (Cond.getResNo() == 1 &&
3424 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3425 Opc == ISD::USUBO)) {
3426 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
3429 SDValue Value, OverflowCmp;
3431 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
3432 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3433 EVT VT = Op.getValueType();
3435 return getCMOV(SDLoc(Op), VT, SelectTrue, SelectFalse, ARMcc, CCR,
3441 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3442 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3444 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3445 const ConstantSDNode *CMOVTrue =
3446 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
3447 const ConstantSDNode *CMOVFalse =
3448 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3450 if (CMOVTrue && CMOVFalse) {
3451 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3452 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3456 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3458 False = SelectFalse;
3459 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3464 if (True.getNode() && False.getNode()) {
3465 EVT VT = Op.getValueType();
3466 SDValue ARMcc = Cond.getOperand(2);
3467 SDValue CCR = Cond.getOperand(3);
3468 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
3469 assert(True.getValueType() == VT);
3470 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
3475 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3476 // undefined bits before doing a full-word comparison with zero.
3477 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3478 DAG.getConstant(1, Cond.getValueType()));
3480 return DAG.getSelectCC(dl, Cond,
3481 DAG.getConstant(0, Cond.getValueType()),
3482 SelectTrue, SelectFalse, ISD::SETNE);
3485 static ISD::CondCode getInverseCCForVSEL(ISD::CondCode CC) {
3486 if (CC == ISD::SETNE)
3488 return ISD::getSetCCInverse(CC, true);
3491 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3492 bool &swpCmpOps, bool &swpVselOps) {
3493 // Start by selecting the GE condition code for opcodes that return true for
3495 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3497 CondCode = ARMCC::GE;
3499 // and GT for opcodes that return false for 'equality'.
3500 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3502 CondCode = ARMCC::GT;
3504 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3505 // to swap the compare operands.
3506 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3510 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
3511 // If we have an unordered opcode, we need to swap the operands to the VSEL
3512 // instruction (effectively negating the condition).
3514 // This also has the effect of swapping which one of 'less' or 'greater'
3515 // returns true, so we also swap the compare operands. It also switches
3516 // whether we return true for 'equality', so we compensate by picking the
3517 // opposite condition code to our original choice.
3518 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3519 CC == ISD::SETUGT) {
3520 swpCmpOps = !swpCmpOps;
3521 swpVselOps = !swpVselOps;
3522 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
3525 // 'ordered' is 'anything but unordered', so use the VS condition code and
3526 // swap the VSEL operands.
3527 if (CC == ISD::SETO) {
3528 CondCode = ARMCC::VS;
3532 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3533 // code and swap the VSEL operands.
3534 if (CC == ISD::SETUNE) {
3535 CondCode = ARMCC::EQ;
3540 SDValue ARMTargetLowering::getCMOV(SDLoc dl, EVT VT, SDValue FalseVal,
3541 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
3542 SDValue Cmp, SelectionDAG &DAG) const {
3543 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
3544 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3545 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
3546 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3547 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
3549 SDValue TrueLow = TrueVal.getValue(0);
3550 SDValue TrueHigh = TrueVal.getValue(1);
3551 SDValue FalseLow = FalseVal.getValue(0);
3552 SDValue FalseHigh = FalseVal.getValue(1);
3554 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
3556 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
3557 ARMcc, CCR, duplicateCmp(Cmp, DAG));
3559 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
3561 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3566 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3567 EVT VT = Op.getValueType();
3568 SDValue LHS = Op.getOperand(0);
3569 SDValue RHS = Op.getOperand(1);
3570 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3571 SDValue TrueVal = Op.getOperand(2);
3572 SDValue FalseVal = Op.getOperand(3);
3575 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3576 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3579 // If softenSetCCOperands only returned one value, we should compare it to
3581 if (!RHS.getNode()) {
3582 RHS = DAG.getConstant(0, LHS.getValueType());
3587 if (LHS.getValueType() == MVT::i32) {
3588 // Try to generate VSEL on ARMv8.
3589 // The VSEL instruction can't use all the usual ARM condition
3590 // codes: it only has two bits to select the condition code, so it's
3591 // constrained to use only GE, GT, VS and EQ.
3593 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3594 // swap the operands of the previous compare instruction (effectively
3595 // inverting the compare condition, swapping 'less' and 'greater') and
3596 // sometimes need to swap the operands to the VSEL (which inverts the
3597 // condition in the sense of firing whenever the previous condition didn't)
3598 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3599 TrueVal.getValueType() == MVT::f64)) {
3600 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3601 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3602 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3603 CC = getInverseCCForVSEL(CC);
3604 std::swap(TrueVal, FalseVal);
3609 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3610 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3611 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3614 ARMCC::CondCodes CondCode, CondCode2;
3615 FPCCToARMCC(CC, CondCode, CondCode2);
3617 // Try to generate VSEL on ARMv8.
3618 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3619 TrueVal.getValueType() == MVT::f64)) {
3620 // We can select VMAXNM/VMINNM from a compare followed by a select with the
3621 // same operands, as follows:
3622 // c = fcmp [ogt, olt, ugt, ult] a, b
3624 // We only do this in unsafe-fp-math, because signed zeros and NaNs are
3625 // handled differently than the original code sequence.
3626 if (getTargetMachine().Options.UnsafeFPMath) {
3627 if (LHS == TrueVal && RHS == FalseVal) {
3628 if (CC == ISD::SETOGT || CC == ISD::SETUGT)
3629 return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3630 if (CC == ISD::SETOLT || CC == ISD::SETULT)
3631 return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3632 } else if (LHS == FalseVal && RHS == TrueVal) {
3633 if (CC == ISD::SETOLT || CC == ISD::SETULT)
3634 return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3635 if (CC == ISD::SETOGT || CC == ISD::SETUGT)
3636 return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3640 bool swpCmpOps = false;
3641 bool swpVselOps = false;
3642 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3644 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3645 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3647 std::swap(LHS, RHS);
3649 std::swap(TrueVal, FalseVal);
3653 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3654 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3655 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3656 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3657 if (CondCode2 != ARMCC::AL) {
3658 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
3659 // FIXME: Needs another CMP because flag can have but one use.
3660 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3661 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
3666 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
3667 /// to morph to an integer compare sequence.
3668 static bool canChangeToInt(SDValue Op, bool &SeenZero,
3669 const ARMSubtarget *Subtarget) {
3670 SDNode *N = Op.getNode();
3671 if (!N->hasOneUse())
3672 // Otherwise it requires moving the value from fp to integer registers.
3674 if (!N->getNumValues())
3676 EVT VT = Op.getValueType();
3677 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3678 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3679 // vmrs are very slow, e.g. cortex-a8.
3682 if (isFloatingPointZero(Op)) {
3686 return ISD::isNormalLoad(N);
3689 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3690 if (isFloatingPointZero(Op))
3691 return DAG.getConstant(0, MVT::i32);
3693 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3694 return DAG.getLoad(MVT::i32, SDLoc(Op),
3695 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3696 Ld->isVolatile(), Ld->isNonTemporal(),
3697 Ld->isInvariant(), Ld->getAlignment());
3699 llvm_unreachable("Unknown VFP cmp argument!");
3702 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3703 SDValue &RetVal1, SDValue &RetVal2) {
3704 if (isFloatingPointZero(Op)) {
3705 RetVal1 = DAG.getConstant(0, MVT::i32);
3706 RetVal2 = DAG.getConstant(0, MVT::i32);
3710 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3711 SDValue Ptr = Ld->getBasePtr();
3712 RetVal1 = DAG.getLoad(MVT::i32, SDLoc(Op),
3713 Ld->getChain(), Ptr,
3714 Ld->getPointerInfo(),
3715 Ld->isVolatile(), Ld->isNonTemporal(),
3716 Ld->isInvariant(), Ld->getAlignment());
3718 EVT PtrType = Ptr.getValueType();
3719 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3720 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(Op),
3721 PtrType, Ptr, DAG.getConstant(4, PtrType));
3722 RetVal2 = DAG.getLoad(MVT::i32, SDLoc(Op),
3723 Ld->getChain(), NewPtr,
3724 Ld->getPointerInfo().getWithOffset(4),
3725 Ld->isVolatile(), Ld->isNonTemporal(),
3726 Ld->isInvariant(), NewAlign);
3730 llvm_unreachable("Unknown VFP cmp argument!");
3733 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3734 /// f32 and even f64 comparisons to integer ones.
3736 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3737 SDValue Chain = Op.getOperand(0);
3738 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3739 SDValue LHS = Op.getOperand(2);
3740 SDValue RHS = Op.getOperand(3);
3741 SDValue Dest = Op.getOperand(4);
3744 bool LHSSeenZero = false;
3745 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3746 bool RHSSeenZero = false;
3747 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3748 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3749 // If unsafe fp math optimization is enabled and there are no other uses of
3750 // the CMP operands, and the condition code is EQ or NE, we can optimize it
3751 // to an integer comparison.
3752 if (CC == ISD::SETOEQ)
3754 else if (CC == ISD::SETUNE)
3757 SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
3759 if (LHS.getValueType() == MVT::f32) {
3760 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3761 bitcastf32Toi32(LHS, DAG), Mask);
3762 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3763 bitcastf32Toi32(RHS, DAG), Mask);
3764 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3765 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3766 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3767 Chain, Dest, ARMcc, CCR, Cmp);
3772 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3773 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3774 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3775 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3776 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3777 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3778 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3779 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3780 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
3786 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3787 SDValue Chain = Op.getOperand(0);
3788 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3789 SDValue LHS = Op.getOperand(2);
3790 SDValue RHS = Op.getOperand(3);
3791 SDValue Dest = Op.getOperand(4);
3794 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3795 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3798 // If softenSetCCOperands only returned one value, we should compare it to
3800 if (!RHS.getNode()) {
3801 RHS = DAG.getConstant(0, LHS.getValueType());
3806 if (LHS.getValueType() == MVT::i32) {
3808 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3809 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3810 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3811 Chain, Dest, ARMcc, CCR, Cmp);
3814 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3816 if (getTargetMachine().Options.UnsafeFPMath &&
3817 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3818 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3819 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3820 if (Result.getNode())
3824 ARMCC::CondCodes CondCode, CondCode2;
3825 FPCCToARMCC(CC, CondCode, CondCode2);
3827 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3828 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3829 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3830 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3831 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3832 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3833 if (CondCode2 != ARMCC::AL) {
3834 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3835 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3836 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3841 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3842 SDValue Chain = Op.getOperand(0);
3843 SDValue Table = Op.getOperand(1);
3844 SDValue Index = Op.getOperand(2);
3847 EVT PTy = getPointerTy();
3848 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3849 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3850 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
3851 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3852 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3853 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
3854 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3855 if (Subtarget->isThumb2()) {
3856 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3857 // which does another jump to the destination. This also makes it easier
3858 // to translate it to TBB / TBH later.
3859 // FIXME: This might not work if the function is extremely large.
3860 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3861 Addr, Op.getOperand(2), JTI, UId);
3863 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3864 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3865 MachinePointerInfo::getJumpTable(),
3866 false, false, false, 0);
3867 Chain = Addr.getValue(1);
3868 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3869 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3871 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3872 MachinePointerInfo::getJumpTable(),
3873 false, false, false, 0);
3874 Chain = Addr.getValue(1);
3875 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3879 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3880 EVT VT = Op.getValueType();
3883 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3884 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3886 return DAG.UnrollVectorOp(Op.getNode());
3889 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3890 "Invalid type for custom lowering!");
3891 if (VT != MVT::v4i16)
3892 return DAG.UnrollVectorOp(Op.getNode());
3894 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3895 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3898 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
3899 EVT VT = Op.getValueType();
3901 return LowerVectorFP_TO_INT(Op, DAG);
3903 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
3905 if (Op.getOpcode() == ISD::FP_TO_SINT)
3906 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
3909 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
3911 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3912 /*isSigned*/ false, SDLoc(Op)).first;
3918 switch (Op.getOpcode()) {
3919 default: llvm_unreachable("Invalid opcode!");
3920 case ISD::FP_TO_SINT:
3921 Opc = ARMISD::FTOSI;
3923 case ISD::FP_TO_UINT:
3924 Opc = ARMISD::FTOUI;
3927 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3928 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3931 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3932 EVT VT = Op.getValueType();
3935 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3936 if (VT.getVectorElementType() == MVT::f32)
3938 return DAG.UnrollVectorOp(Op.getNode());
3941 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3942 "Invalid type for custom lowering!");
3943 if (VT != MVT::v4f32)
3944 return DAG.UnrollVectorOp(Op.getNode());
3948 switch (Op.getOpcode()) {
3949 default: llvm_unreachable("Invalid opcode!");
3950 case ISD::SINT_TO_FP:
3951 CastOpc = ISD::SIGN_EXTEND;
3952 Opc = ISD::SINT_TO_FP;
3954 case ISD::UINT_TO_FP:
3955 CastOpc = ISD::ZERO_EXTEND;
3956 Opc = ISD::UINT_TO_FP;
3960 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3961 return DAG.getNode(Opc, dl, VT, Op);
3964 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
3965 EVT VT = Op.getValueType();
3967 return LowerVectorINT_TO_FP(Op, DAG);
3969 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
3971 if (Op.getOpcode() == ISD::SINT_TO_FP)
3972 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
3975 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
3977 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3978 /*isSigned*/ false, SDLoc(Op)).first;
3984 switch (Op.getOpcode()) {
3985 default: llvm_unreachable("Invalid opcode!");
3986 case ISD::SINT_TO_FP:
3987 Opc = ARMISD::SITOF;
3989 case ISD::UINT_TO_FP:
3990 Opc = ARMISD::UITOF;
3994 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3995 return DAG.getNode(Opc, dl, VT, Op);
3998 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3999 // Implement fcopysign with a fabs and a conditional fneg.
4000 SDValue Tmp0 = Op.getOperand(0);
4001 SDValue Tmp1 = Op.getOperand(1);
4003 EVT VT = Op.getValueType();
4004 EVT SrcVT = Tmp1.getValueType();
4005 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
4006 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4007 bool UseNEON = !InGPR && Subtarget->hasNEON();
4010 // Use VBSL to copy the sign bit.
4011 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
4012 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4013 DAG.getTargetConstant(EncodedVal, MVT::i32));
4014 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4016 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4017 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4018 DAG.getConstant(32, MVT::i32));
4019 else /*if (VT == MVT::f32)*/
4020 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4021 if (SrcVT == MVT::f32) {
4022 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4024 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4025 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4026 DAG.getConstant(32, MVT::i32));
4027 } else if (VT == MVT::f32)
4028 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4029 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4030 DAG.getConstant(32, MVT::i32));
4031 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4032 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4034 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4036 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4037 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4038 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4040 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4041 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4042 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4043 if (VT == MVT::f32) {
4044 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4045 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4046 DAG.getConstant(0, MVT::i32));
4048 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4054 // Bitcast operand 1 to i32.
4055 if (SrcVT == MVT::f64)
4056 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4058 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4060 // Or in the signbit with integer operations.
4061 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
4062 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
4063 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
4064 if (VT == MVT::f32) {
4065 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
4066 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4067 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4068 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
4071 // f64: Or the high part with signbit and then combine two parts.
4072 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4074 SDValue Lo = Tmp0.getValue(0);
4075 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
4076 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
4077 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
4080 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
4081 MachineFunction &MF = DAG.getMachineFunction();
4082 MachineFrameInfo *MFI = MF.getFrameInfo();
4083 MFI->setReturnAddressIsTaken(true);
4085 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
4088 EVT VT = Op.getValueType();
4090 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4092 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4093 SDValue Offset = DAG.getConstant(4, MVT::i32);
4094 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
4095 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
4096 MachinePointerInfo(), false, false, false, 0);
4099 // Return LR, which contains the return address. Mark it an implicit live-in.
4100 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4101 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
4104 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
4105 const ARMBaseRegisterInfo &ARI =
4106 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
4107 MachineFunction &MF = DAG.getMachineFunction();
4108 MachineFrameInfo *MFI = MF.getFrameInfo();
4109 MFI->setFrameAddressIsTaken(true);
4111 EVT VT = Op.getValueType();
4112 SDLoc dl(Op); // FIXME probably not meaningful
4113 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4114 unsigned FrameReg = ARI.getFrameRegister(MF);
4115 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
4117 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
4118 MachinePointerInfo(),
4119 false, false, false, 0);
4123 // FIXME? Maybe this could be a TableGen attribute on some registers and
4124 // this table could be generated automatically from RegInfo.
4125 unsigned ARMTargetLowering::getRegisterByName(const char* RegName,
4127 unsigned Reg = StringSwitch<unsigned>(RegName)
4128 .Case("sp", ARM::SP)
4132 report_fatal_error("Invalid register name global variable");
4135 /// ExpandBITCAST - If the target supports VFP, this function is called to
4136 /// expand a bit convert where either the source or destination type is i64 to
4137 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
4138 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
4139 /// vectors), since the legalizer won't know what to do with that.
4140 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
4141 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4143 SDValue Op = N->getOperand(0);
4145 // This function is only supposed to be called for i64 types, either as the
4146 // source or destination of the bit convert.
4147 EVT SrcVT = Op.getValueType();
4148 EVT DstVT = N->getValueType(0);
4149 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
4150 "ExpandBITCAST called for non-i64 type");
4152 // Turn i64->f64 into VMOVDRR.
4153 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
4154 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4155 DAG.getConstant(0, MVT::i32));
4156 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4157 DAG.getConstant(1, MVT::i32));
4158 return DAG.getNode(ISD::BITCAST, dl, DstVT,
4159 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
4162 // Turn f64->i64 into VMOVRRD.
4163 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
4165 if (TLI.isBigEndian() && SrcVT.isVector() &&
4166 SrcVT.getVectorNumElements() > 1)
4167 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4168 DAG.getVTList(MVT::i32, MVT::i32),
4169 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
4171 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4172 DAG.getVTList(MVT::i32, MVT::i32), Op);
4173 // Merge the pieces into a single i64 value.
4174 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
4180 /// getZeroVector - Returns a vector of specified type with all zero elements.
4181 /// Zero vectors are used to represent vector negation and in those cases
4182 /// will be implemented with the NEON VNEG instruction. However, VNEG does
4183 /// not support i64 elements, so sometimes the zero vectors will need to be
4184 /// explicitly constructed. Regardless, use a canonical VMOV to create the
4186 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) {
4187 assert(VT.isVector() && "Expected a vector type");
4188 // The canonical modified immediate encoding of a zero vector is....0!
4189 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
4190 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
4191 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
4192 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4195 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4196 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4197 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
4198 SelectionDAG &DAG) const {
4199 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4200 EVT VT = Op.getValueType();
4201 unsigned VTBits = VT.getSizeInBits();
4203 SDValue ShOpLo = Op.getOperand(0);
4204 SDValue ShOpHi = Op.getOperand(1);
4205 SDValue ShAmt = Op.getOperand(2);
4207 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4209 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4211 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4212 DAG.getConstant(VTBits, MVT::i32), ShAmt);
4213 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4214 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4215 DAG.getConstant(VTBits, MVT::i32));
4216 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4217 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4218 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4220 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4221 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
4223 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4224 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
4227 SDValue Ops[2] = { Lo, Hi };
4228 return DAG.getMergeValues(Ops, dl);
4231 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4232 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4233 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
4234 SelectionDAG &DAG) const {
4235 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4236 EVT VT = Op.getValueType();
4237 unsigned VTBits = VT.getSizeInBits();
4239 SDValue ShOpLo = Op.getOperand(0);
4240 SDValue ShOpHi = Op.getOperand(1);
4241 SDValue ShAmt = Op.getOperand(2);
4244 assert(Op.getOpcode() == ISD::SHL_PARTS);
4245 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4246 DAG.getConstant(VTBits, MVT::i32), ShAmt);
4247 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4248 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4249 DAG.getConstant(VTBits, MVT::i32));
4250 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4251 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4253 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4254 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4255 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
4257 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4258 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
4261 SDValue Ops[2] = { Lo, Hi };
4262 return DAG.getMergeValues(Ops, dl);
4265 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4266 SelectionDAG &DAG) const {
4267 // The rounding mode is in bits 23:22 of the FPSCR.
4268 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
4269 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
4270 // so that the shift + and get folded into a bitfield extract.
4272 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
4273 DAG.getConstant(Intrinsic::arm_get_fpscr,
4275 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
4276 DAG.getConstant(1U << 22, MVT::i32));
4277 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
4278 DAG.getConstant(22, MVT::i32));
4279 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
4280 DAG.getConstant(3, MVT::i32));
4283 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
4284 const ARMSubtarget *ST) {
4285 EVT VT = N->getValueType(0);
4288 if (!ST->hasV6T2Ops())
4291 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
4292 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
4295 /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
4296 /// for each 16-bit element from operand, repeated. The basic idea is to
4297 /// leverage vcnt to get the 8-bit counts, gather and add the results.
4299 /// Trace for v4i16:
4300 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4301 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
4302 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
4303 /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
4304 /// [b0 b1 b2 b3 b4 b5 b6 b7]
4305 /// +[b1 b0 b3 b2 b5 b4 b7 b6]
4306 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
4307 /// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
4308 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
4309 EVT VT = N->getValueType(0);
4312 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
4313 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
4314 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
4315 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
4316 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
4317 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
4320 /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
4321 /// bit-count for each 16-bit element from the operand. We need slightly
4322 /// different sequencing for v4i16 and v8i16 to stay within NEON's available
4323 /// 64/128-bit registers.
4325 /// Trace for v4i16:
4326 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4327 /// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
4328 /// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
4329 /// v4i16:Extracted = [k0 k1 k2 k3 ]
4330 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
4331 EVT VT = N->getValueType(0);
4334 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
4335 if (VT.is64BitVector()) {
4336 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
4337 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
4338 DAG.getIntPtrConstant(0));
4340 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
4341 BitCounts, DAG.getIntPtrConstant(0));
4342 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
4346 /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
4347 /// bit-count for each 32-bit element from the operand. The idea here is
4348 /// to split the vector into 16-bit elements, leverage the 16-bit count
4349 /// routine, and then combine the results.
4351 /// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
4352 /// input = [v0 v1 ] (vi: 32-bit elements)
4353 /// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
4354 /// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
4355 /// vrev: N0 = [k1 k0 k3 k2 ]
4357 /// N1 =+[k1 k0 k3 k2 ]
4359 /// N2 =+[k1 k3 k0 k2 ]
4361 /// Extended =+[k1 k3 k0 k2 ]
4363 /// Extracted=+[k1 k3 ]
4365 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
4366 EVT VT = N->getValueType(0);
4369 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4371 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
4372 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
4373 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4374 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
4375 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4377 if (VT.is64BitVector()) {
4378 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4379 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
4380 DAG.getIntPtrConstant(0));
4382 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
4383 DAG.getIntPtrConstant(0));
4384 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
4388 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
4389 const ARMSubtarget *ST) {
4390 EVT VT = N->getValueType(0);
4392 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
4393 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
4394 VT == MVT::v4i16 || VT == MVT::v8i16) &&
4395 "Unexpected type for custom ctpop lowering");
4397 if (VT.getVectorElementType() == MVT::i32)
4398 return lowerCTPOP32BitElements(N, DAG);
4400 return lowerCTPOP16BitElements(N, DAG);
4403 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
4404 const ARMSubtarget *ST) {
4405 EVT VT = N->getValueType(0);
4411 // Lower vector shifts on NEON to use VSHL.
4412 assert(ST->hasNEON() && "unexpected vector shift");
4414 // Left shifts translate directly to the vshiftu intrinsic.
4415 if (N->getOpcode() == ISD::SHL)
4416 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4417 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
4418 N->getOperand(0), N->getOperand(1));
4420 assert((N->getOpcode() == ISD::SRA ||
4421 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4423 // NEON uses the same intrinsics for both left and right shifts. For
4424 // right shifts, the shift amounts are negative, so negate the vector of
4426 EVT ShiftVT = N->getOperand(1).getValueType();
4427 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
4428 getZeroVector(ShiftVT, DAG, dl),
4430 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
4431 Intrinsic::arm_neon_vshifts :
4432 Intrinsic::arm_neon_vshiftu);
4433 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4434 DAG.getConstant(vshiftInt, MVT::i32),
4435 N->getOperand(0), NegatedCount);
4438 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4439 const ARMSubtarget *ST) {
4440 EVT VT = N->getValueType(0);
4443 // We can get here for a node like i32 = ISD::SHL i32, i64
4447 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
4448 "Unknown shift to lower!");
4450 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4451 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
4452 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
4455 // If we are in thumb mode, we don't have RRX.
4456 if (ST->isThumb1Only()) return SDValue();
4458 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
4459 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4460 DAG.getConstant(0, MVT::i32));
4461 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4462 DAG.getConstant(1, MVT::i32));
4464 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4465 // captures the result into a carry flag.
4466 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
4467 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
4469 // The low part is an ARMISD::RRX operand, which shifts the carry in.
4470 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4472 // Merge the pieces into a single i64 value.
4473 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4476 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4477 SDValue TmpOp0, TmpOp1;
4478 bool Invert = false;
4482 SDValue Op0 = Op.getOperand(0);
4483 SDValue Op1 = Op.getOperand(1);
4484 SDValue CC = Op.getOperand(2);
4485 EVT VT = Op.getValueType();
4486 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4489 if (Op1.getValueType().isFloatingPoint()) {
4490 switch (SetCCOpcode) {
4491 default: llvm_unreachable("Illegal FP comparison");
4493 case ISD::SETNE: Invert = true; // Fallthrough
4495 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4497 case ISD::SETLT: Swap = true; // Fallthrough
4499 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4501 case ISD::SETLE: Swap = true; // Fallthrough
4503 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4504 case ISD::SETUGE: Swap = true; // Fallthrough
4505 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4506 case ISD::SETUGT: Swap = true; // Fallthrough
4507 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4508 case ISD::SETUEQ: Invert = true; // Fallthrough
4510 // Expand this to (OLT | OGT).
4514 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4515 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
4517 case ISD::SETUO: Invert = true; // Fallthrough
4519 // Expand this to (OLT | OGE).
4523 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4524 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
4528 // Integer comparisons.
4529 switch (SetCCOpcode) {
4530 default: llvm_unreachable("Illegal integer comparison");
4531 case ISD::SETNE: Invert = true;
4532 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4533 case ISD::SETLT: Swap = true;
4534 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4535 case ISD::SETLE: Swap = true;
4536 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4537 case ISD::SETULT: Swap = true;
4538 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4539 case ISD::SETULE: Swap = true;
4540 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4543 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
4544 if (Opc == ARMISD::VCEQ) {
4547 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4549 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4552 // Ignore bitconvert.
4553 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
4554 AndOp = AndOp.getOperand(0);
4556 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4558 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
4559 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
4566 std::swap(Op0, Op1);
4568 // If one of the operands is a constant vector zero, attempt to fold the
4569 // comparison to a specialized compare-against-zero form.
4571 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4573 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
4574 if (Opc == ARMISD::VCGE)
4575 Opc = ARMISD::VCLEZ;
4576 else if (Opc == ARMISD::VCGT)
4577 Opc = ARMISD::VCLTZ;
4582 if (SingleOp.getNode()) {
4585 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
4587 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
4589 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
4591 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
4593 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
4595 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4598 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4602 Result = DAG.getNOT(dl, Result, VT);
4607 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
4608 /// valid vector constant for a NEON instruction with a "modified immediate"
4609 /// operand (e.g., VMOV). If so, return the encoded value.
4610 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
4611 unsigned SplatBitSize, SelectionDAG &DAG,
4612 EVT &VT, bool is128Bits, NEONModImmType type) {
4613 unsigned OpCmode, Imm;
4615 // SplatBitSize is set to the smallest size that splats the vector, so a
4616 // zero vector will always have SplatBitSize == 8. However, NEON modified
4617 // immediate instructions others than VMOV do not support the 8-bit encoding
4618 // of a zero vector, and the default encoding of zero is supposed to be the
4623 switch (SplatBitSize) {
4625 if (type != VMOVModImm)
4627 // Any 1-byte value is OK. Op=0, Cmode=1110.
4628 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
4631 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
4635 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
4636 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4637 if ((SplatBits & ~0xff) == 0) {
4638 // Value = 0x00nn: Op=x, Cmode=100x.
4643 if ((SplatBits & ~0xff00) == 0) {
4644 // Value = 0xnn00: Op=x, Cmode=101x.
4646 Imm = SplatBits >> 8;
4652 // NEON's 32-bit VMOV supports splat values where:
4653 // * only one byte is nonzero, or
4654 // * the least significant byte is 0xff and the second byte is nonzero, or
4655 // * the least significant 2 bytes are 0xff and the third is nonzero.
4656 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
4657 if ((SplatBits & ~0xff) == 0) {
4658 // Value = 0x000000nn: Op=x, Cmode=000x.
4663 if ((SplatBits & ~0xff00) == 0) {
4664 // Value = 0x0000nn00: Op=x, Cmode=001x.
4666 Imm = SplatBits >> 8;
4669 if ((SplatBits & ~0xff0000) == 0) {
4670 // Value = 0x00nn0000: Op=x, Cmode=010x.
4672 Imm = SplatBits >> 16;
4675 if ((SplatBits & ~0xff000000) == 0) {
4676 // Value = 0xnn000000: Op=x, Cmode=011x.
4678 Imm = SplatBits >> 24;
4682 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
4683 if (type == OtherModImm) return SDValue();
4685 if ((SplatBits & ~0xffff) == 0 &&
4686 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
4687 // Value = 0x0000nnff: Op=x, Cmode=1100.
4689 Imm = SplatBits >> 8;
4693 if ((SplatBits & ~0xffffff) == 0 &&
4694 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
4695 // Value = 0x00nnffff: Op=x, Cmode=1101.
4697 Imm = SplatBits >> 16;
4701 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
4702 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4703 // VMOV.I32. A (very) minor optimization would be to replicate the value
4704 // and fall through here to test for a valid 64-bit splat. But, then the
4705 // caller would also need to check and handle the change in size.
4709 if (type != VMOVModImm)
4711 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
4712 uint64_t BitMask = 0xff;
4714 unsigned ImmMask = 1;
4716 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
4717 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
4720 } else if ((SplatBits & BitMask) != 0) {
4727 if (DAG.getTargetLoweringInfo().isBigEndian())
4728 // swap higher and lower 32 bit word
4729 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
4731 // Op=1, Cmode=1110.
4733 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4738 llvm_unreachable("unexpected size for isNEONModifiedImm");
4741 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4742 return DAG.getTargetConstant(EncodedVal, MVT::i32);
4745 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4746 const ARMSubtarget *ST) const {
4750 bool IsDouble = Op.getValueType() == MVT::f64;
4751 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4753 // Use the default (constant pool) lowering for double constants when we have
4755 if (IsDouble && Subtarget->isFPOnlySP())
4758 // Try splatting with a VMOV.f32...
4759 APFloat FPVal = CFP->getValueAPF();
4760 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4763 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4764 // We have code in place to select a valid ConstantFP already, no need to
4769 // It's a float and we are trying to use NEON operations where
4770 // possible. Lower it to a splat followed by an extract.
4772 SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
4773 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4775 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4776 DAG.getConstant(0, MVT::i32));
4779 // The rest of our options are NEON only, make sure that's allowed before
4781 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4785 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4787 // It wouldn't really be worth bothering for doubles except for one very
4788 // important value, which does happen to match: 0.0. So make sure we don't do
4790 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
4793 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4794 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4796 if (NewVal != SDValue()) {
4798 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4801 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4803 // It's a float: cast and extract a vector element.
4804 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4806 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4807 DAG.getConstant(0, MVT::i32));
4810 // Finally, try a VMVN.i32
4811 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4813 if (NewVal != SDValue()) {
4815 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4818 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4820 // It's a float: cast and extract a vector element.
4821 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4823 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4824 DAG.getConstant(0, MVT::i32));
4830 // check if an VEXT instruction can handle the shuffle mask when the
4831 // vector sources of the shuffle are the same.
4832 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4833 unsigned NumElts = VT.getVectorNumElements();
4835 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4841 // If this is a VEXT shuffle, the immediate value is the index of the first
4842 // element. The other shuffle indices must be the successive elements after
4844 unsigned ExpectedElt = Imm;
4845 for (unsigned i = 1; i < NumElts; ++i) {
4846 // Increment the expected index. If it wraps around, just follow it
4847 // back to index zero and keep going.
4849 if (ExpectedElt == NumElts)
4852 if (M[i] < 0) continue; // ignore UNDEF indices
4853 if (ExpectedElt != static_cast<unsigned>(M[i]))
4861 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
4862 bool &ReverseVEXT, unsigned &Imm) {
4863 unsigned NumElts = VT.getVectorNumElements();
4864 ReverseVEXT = false;
4866 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4872 // If this is a VEXT shuffle, the immediate value is the index of the first
4873 // element. The other shuffle indices must be the successive elements after
4875 unsigned ExpectedElt = Imm;
4876 for (unsigned i = 1; i < NumElts; ++i) {
4877 // Increment the expected index. If it wraps around, it may still be
4878 // a VEXT but the source vectors must be swapped.
4880 if (ExpectedElt == NumElts * 2) {
4885 if (M[i] < 0) continue; // ignore UNDEF indices
4886 if (ExpectedElt != static_cast<unsigned>(M[i]))
4890 // Adjust the index value if the source operands will be swapped.
4897 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
4898 /// instruction with the specified blocksize. (The order of the elements
4899 /// within each block of the vector is reversed.)
4900 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4901 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
4902 "Only possible block sizes for VREV are: 16, 32, 64");
4904 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4908 unsigned NumElts = VT.getVectorNumElements();
4909 unsigned BlockElts = M[0] + 1;
4910 // If the first shuffle index is UNDEF, be optimistic.
4912 BlockElts = BlockSize / EltSz;
4914 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4917 for (unsigned i = 0; i < NumElts; ++i) {
4918 if (M[i] < 0) continue; // ignore UNDEF indices
4919 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
4926 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
4927 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
4928 // range, then 0 is placed into the resulting vector. So pretty much any mask
4929 // of 8 elements can work here.
4930 return VT == MVT::v8i8 && M.size() == 8;
4933 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4934 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4938 unsigned NumElts = VT.getVectorNumElements();
4939 WhichResult = (M[0] == 0 ? 0 : 1);
4940 for (unsigned i = 0; i < NumElts; i += 2) {
4941 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4942 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
4948 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
4949 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4950 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4951 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4952 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4956 unsigned NumElts = VT.getVectorNumElements();
4957 WhichResult = (M[0] == 0 ? 0 : 1);
4958 for (unsigned i = 0; i < NumElts; i += 2) {
4959 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4960 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
4966 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4967 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4971 unsigned NumElts = VT.getVectorNumElements();
4972 WhichResult = (M[0] == 0 ? 0 : 1);
4973 for (unsigned i = 0; i != NumElts; ++i) {
4974 if (M[i] < 0) continue; // ignore UNDEF indices
4975 if ((unsigned) M[i] != 2 * i + WhichResult)
4979 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4980 if (VT.is64BitVector() && EltSz == 32)
4986 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
4987 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4988 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4989 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4990 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4994 unsigned Half = VT.getVectorNumElements() / 2;
4995 WhichResult = (M[0] == 0 ? 0 : 1);
4996 for (unsigned j = 0; j != 2; ++j) {
4997 unsigned Idx = WhichResult;
4998 for (unsigned i = 0; i != Half; ++i) {
4999 int MIdx = M[i + j * Half];
5000 if (MIdx >= 0 && (unsigned) MIdx != Idx)
5006 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5007 if (VT.is64BitVector() && EltSz == 32)
5013 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5014 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5018 unsigned NumElts = VT.getVectorNumElements();
5019 WhichResult = (M[0] == 0 ? 0 : 1);
5020 unsigned Idx = WhichResult * NumElts / 2;
5021 for (unsigned i = 0; i != NumElts; i += 2) {
5022 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
5023 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
5028 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5029 if (VT.is64BitVector() && EltSz == 32)
5035 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
5036 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5037 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5038 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5039 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5043 unsigned NumElts = VT.getVectorNumElements();
5044 WhichResult = (M[0] == 0 ? 0 : 1);
5045 unsigned Idx = WhichResult * NumElts / 2;
5046 for (unsigned i = 0; i != NumElts; i += 2) {
5047 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
5048 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
5053 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5054 if (VT.is64BitVector() && EltSz == 32)
5060 /// \return true if this is a reverse operation on an vector.
5061 static bool isReverseMask(ArrayRef<int> M, EVT VT) {
5062 unsigned NumElts = VT.getVectorNumElements();
5063 // Make sure the mask has the right size.
5064 if (NumElts != M.size())
5067 // Look for <15, ..., 3, -1, 1, 0>.
5068 for (unsigned i = 0; i != NumElts; ++i)
5069 if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
5075 // If N is an integer constant that can be moved into a register in one
5076 // instruction, return an SDValue of such a constant (will become a MOV
5077 // instruction). Otherwise return null.
5078 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
5079 const ARMSubtarget *ST, SDLoc dl) {
5081 if (!isa<ConstantSDNode>(N))
5083 Val = cast<ConstantSDNode>(N)->getZExtValue();
5085 if (ST->isThumb1Only()) {
5086 if (Val <= 255 || ~Val <= 255)
5087 return DAG.getConstant(Val, MVT::i32);
5089 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
5090 return DAG.getConstant(Val, MVT::i32);
5095 // If this is a case we can't handle, return null and let the default
5096 // expansion code take care of it.
5097 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
5098 const ARMSubtarget *ST) const {
5099 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5101 EVT VT = Op.getValueType();
5103 APInt SplatBits, SplatUndef;
5104 unsigned SplatBitSize;
5106 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5107 if (SplatBitSize <= 64) {
5108 // Check if an immediate VMOV works.
5110 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5111 SplatUndef.getZExtValue(), SplatBitSize,
5112 DAG, VmovVT, VT.is128BitVector(),
5114 if (Val.getNode()) {
5115 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
5116 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5119 // Try an immediate VMVN.
5120 uint64_t NegatedImm = (~SplatBits).getZExtValue();
5121 Val = isNEONModifiedImm(NegatedImm,
5122 SplatUndef.getZExtValue(), SplatBitSize,
5123 DAG, VmovVT, VT.is128BitVector(),
5125 if (Val.getNode()) {
5126 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
5127 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5130 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
5131 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
5132 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
5134 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
5135 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
5141 // Scan through the operands to see if only one value is used.
5143 // As an optimisation, even if more than one value is used it may be more
5144 // profitable to splat with one value then change some lanes.
5146 // Heuristically we decide to do this if the vector has a "dominant" value,
5147 // defined as splatted to more than half of the lanes.
5148 unsigned NumElts = VT.getVectorNumElements();
5149 bool isOnlyLowElement = true;
5150 bool usesOnlyOneValue = true;
5151 bool hasDominantValue = false;
5152 bool isConstant = true;
5154 // Map of the number of times a particular SDValue appears in the
5156 DenseMap<SDValue, unsigned> ValueCounts;
5158 for (unsigned i = 0; i < NumElts; ++i) {
5159 SDValue V = Op.getOperand(i);
5160 if (V.getOpcode() == ISD::UNDEF)
5163 isOnlyLowElement = false;
5164 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5167 ValueCounts.insert(std::make_pair(V, 0));
5168 unsigned &Count = ValueCounts[V];
5170 // Is this value dominant? (takes up more than half of the lanes)
5171 if (++Count > (NumElts / 2)) {
5172 hasDominantValue = true;
5176 if (ValueCounts.size() != 1)
5177 usesOnlyOneValue = false;
5178 if (!Value.getNode() && ValueCounts.size() > 0)
5179 Value = ValueCounts.begin()->first;
5181 if (ValueCounts.size() == 0)
5182 return DAG.getUNDEF(VT);
5184 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
5185 // Keep going if we are hitting this case.
5186 if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
5187 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5189 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5191 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
5192 // i32 and try again.
5193 if (hasDominantValue && EltSize <= 32) {
5197 // If we are VDUPing a value that comes directly from a vector, that will
5198 // cause an unnecessary move to and from a GPR, where instead we could
5199 // just use VDUPLANE. We can only do this if the lane being extracted
5200 // is at a constant index, as the VDUP from lane instructions only have
5201 // constant-index forms.
5202 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5203 isa<ConstantSDNode>(Value->getOperand(1))) {
5204 // We need to create a new undef vector to use for the VDUPLANE if the
5205 // size of the vector from which we get the value is different than the
5206 // size of the vector that we need to create. We will insert the element
5207 // such that the register coalescer will remove unnecessary copies.
5208 if (VT != Value->getOperand(0).getValueType()) {
5209 ConstantSDNode *constIndex;
5210 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
5211 assert(constIndex && "The index is not a constant!");
5212 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
5213 VT.getVectorNumElements();
5214 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5215 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
5216 Value, DAG.getConstant(index, MVT::i32)),
5217 DAG.getConstant(index, MVT::i32));
5219 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5220 Value->getOperand(0), Value->getOperand(1));
5222 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
5224 if (!usesOnlyOneValue) {
5225 // The dominant value was splatted as 'N', but we now have to insert
5226 // all differing elements.
5227 for (unsigned I = 0; I < NumElts; ++I) {
5228 if (Op.getOperand(I) == Value)
5230 SmallVector<SDValue, 3> Ops;
5232 Ops.push_back(Op.getOperand(I));
5233 Ops.push_back(DAG.getConstant(I, MVT::i32));
5234 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
5239 if (VT.getVectorElementType().isFloatingPoint()) {
5240 SmallVector<SDValue, 8> Ops;
5241 for (unsigned i = 0; i < NumElts; ++i)
5242 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
5244 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
5245 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5246 Val = LowerBUILD_VECTOR(Val, DAG, ST);
5248 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5250 if (usesOnlyOneValue) {
5251 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
5252 if (isConstant && Val.getNode())
5253 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
5257 // If all elements are constants and the case above didn't get hit, fall back
5258 // to the default expansion, which will generate a load from the constant
5263 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5265 SDValue shuffle = ReconstructShuffle(Op, DAG);
5266 if (shuffle != SDValue())
5270 // Vectors with 32- or 64-bit elements can be built by directly assigning
5271 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
5272 // will be legalized.
5273 if (EltSize >= 32) {
5274 // Do the expansion with floating-point types, since that is what the VFP
5275 // registers are defined to use, and since i64 is not legal.
5276 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5277 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5278 SmallVector<SDValue, 8> Ops;
5279 for (unsigned i = 0; i < NumElts; ++i)
5280 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
5281 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5282 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5285 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5286 // know the default expansion would otherwise fall back on something even
5287 // worse. For a vector with one or two non-undef values, that's
5288 // scalar_to_vector for the elements followed by a shuffle (provided the
5289 // shuffle is valid for the target) and materialization element by element
5290 // on the stack followed by a load for everything else.
5291 if (!isConstant && !usesOnlyOneValue) {
5292 SDValue Vec = DAG.getUNDEF(VT);
5293 for (unsigned i = 0 ; i < NumElts; ++i) {
5294 SDValue V = Op.getOperand(i);
5295 if (V.getOpcode() == ISD::UNDEF)
5297 SDValue LaneIdx = DAG.getConstant(i, MVT::i32);
5298 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5306 // Gather data to see if the operation can be modelled as a
5307 // shuffle in combination with VEXTs.
5308 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
5309 SelectionDAG &DAG) const {
5311 EVT VT = Op.getValueType();
5312 unsigned NumElts = VT.getVectorNumElements();
5314 SmallVector<SDValue, 2> SourceVecs;
5315 SmallVector<unsigned, 2> MinElts;
5316 SmallVector<unsigned, 2> MaxElts;
5318 for (unsigned i = 0; i < NumElts; ++i) {
5319 SDValue V = Op.getOperand(i);
5320 if (V.getOpcode() == ISD::UNDEF)
5322 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
5323 // A shuffle can only come from building a vector from various
5324 // elements of other vectors.
5326 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
5327 VT.getVectorElementType()) {
5328 // This code doesn't know how to handle shuffles where the vector
5329 // element types do not match (this happens because type legalization
5330 // promotes the return type of EXTRACT_VECTOR_ELT).
5331 // FIXME: It might be appropriate to extend this code to handle
5332 // mismatched types.
5336 // Record this extraction against the appropriate vector if possible...
5337 SDValue SourceVec = V.getOperand(0);
5338 // If the element number isn't a constant, we can't effectively
5339 // analyze what's going on.
5340 if (!isa<ConstantSDNode>(V.getOperand(1)))
5342 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
5343 bool FoundSource = false;
5344 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
5345 if (SourceVecs[j] == SourceVec) {
5346 if (MinElts[j] > EltNo)
5348 if (MaxElts[j] < EltNo)
5355 // Or record a new source if not...
5357 SourceVecs.push_back(SourceVec);
5358 MinElts.push_back(EltNo);
5359 MaxElts.push_back(EltNo);
5363 // Currently only do something sane when at most two source vectors
5365 if (SourceVecs.size() > 2)
5368 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
5369 int VEXTOffsets[2] = {0, 0};
5371 // This loop extracts the usage patterns of the source vectors
5372 // and prepares appropriate SDValues for a shuffle if possible.
5373 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
5374 if (SourceVecs[i].getValueType() == VT) {
5375 // No VEXT necessary
5376 ShuffleSrcs[i] = SourceVecs[i];
5379 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
5380 // It probably isn't worth padding out a smaller vector just to
5381 // break it down again in a shuffle.
5385 // Since only 64-bit and 128-bit vectors are legal on ARM and
5386 // we've eliminated the other cases...
5387 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
5388 "unexpected vector sizes in ReconstructShuffle");
5390 if (MaxElts[i] - MinElts[i] >= NumElts) {
5391 // Span too large for a VEXT to cope
5395 if (MinElts[i] >= NumElts) {
5396 // The extraction can just take the second half
5397 VEXTOffsets[i] = NumElts;
5398 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5400 DAG.getIntPtrConstant(NumElts));
5401 } else if (MaxElts[i] < NumElts) {
5402 // The extraction can just take the first half
5404 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5406 DAG.getIntPtrConstant(0));
5408 // An actual VEXT is needed
5409 VEXTOffsets[i] = MinElts[i];
5410 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5412 DAG.getIntPtrConstant(0));
5413 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5415 DAG.getIntPtrConstant(NumElts));
5416 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
5417 DAG.getConstant(VEXTOffsets[i], MVT::i32));
5421 SmallVector<int, 8> Mask;
5423 for (unsigned i = 0; i < NumElts; ++i) {
5424 SDValue Entry = Op.getOperand(i);
5425 if (Entry.getOpcode() == ISD::UNDEF) {
5430 SDValue ExtractVec = Entry.getOperand(0);
5431 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
5432 .getOperand(1))->getSExtValue();
5433 if (ExtractVec == SourceVecs[0]) {
5434 Mask.push_back(ExtractElt - VEXTOffsets[0]);
5436 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
5440 // Final check before we try to produce nonsense...
5441 if (isShuffleMaskLegal(Mask, VT))
5442 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
5448 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5449 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5450 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5451 /// are assumed to be legal.
5453 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5455 if (VT.getVectorNumElements() == 4 &&
5456 (VT.is128BitVector() || VT.is64BitVector())) {
5457 unsigned PFIndexes[4];
5458 for (unsigned i = 0; i != 4; ++i) {
5462 PFIndexes[i] = M[i];
5465 // Compute the index in the perfect shuffle table.
5466 unsigned PFTableIndex =
5467 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5468 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5469 unsigned Cost = (PFEntry >> 30);
5476 unsigned Imm, WhichResult;
5478 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5479 return (EltSize >= 32 ||
5480 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5481 isVREVMask(M, VT, 64) ||
5482 isVREVMask(M, VT, 32) ||
5483 isVREVMask(M, VT, 16) ||
5484 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5485 isVTBLMask(M, VT) ||
5486 isVTRNMask(M, VT, WhichResult) ||
5487 isVUZPMask(M, VT, WhichResult) ||
5488 isVZIPMask(M, VT, WhichResult) ||
5489 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
5490 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
5491 isVZIP_v_undef_Mask(M, VT, WhichResult) ||
5492 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5495 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5496 /// the specified operations to build the shuffle.
5497 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5498 SDValue RHS, SelectionDAG &DAG,
5500 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5501 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5502 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5505 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5514 OP_VUZPL, // VUZP, left result
5515 OP_VUZPR, // VUZP, right result
5516 OP_VZIPL, // VZIP, left result
5517 OP_VZIPR, // VZIP, right result
5518 OP_VTRNL, // VTRN, left result
5519 OP_VTRNR // VTRN, right result
5522 if (OpNum == OP_COPY) {
5523 if (LHSID == (1*9+2)*9+3) return LHS;
5524 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5528 SDValue OpLHS, OpRHS;
5529 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5530 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5531 EVT VT = OpLHS.getValueType();
5534 default: llvm_unreachable("Unknown shuffle opcode!");
5536 // VREV divides the vector in half and swaps within the half.
5537 if (VT.getVectorElementType() == MVT::i32 ||
5538 VT.getVectorElementType() == MVT::f32)
5539 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
5540 // vrev <4 x i16> -> VREV32
5541 if (VT.getVectorElementType() == MVT::i16)
5542 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
5543 // vrev <4 x i8> -> VREV16
5544 assert(VT.getVectorElementType() == MVT::i8);
5545 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
5550 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5551 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
5555 return DAG.getNode(ARMISD::VEXT, dl, VT,
5557 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
5560 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5561 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
5564 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5565 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
5568 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5569 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
5573 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
5574 ArrayRef<int> ShuffleMask,
5575 SelectionDAG &DAG) {
5576 // Check to see if we can use the VTBL instruction.
5577 SDValue V1 = Op.getOperand(0);
5578 SDValue V2 = Op.getOperand(1);
5581 SmallVector<SDValue, 8> VTBLMask;
5582 for (ArrayRef<int>::iterator
5583 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
5584 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
5586 if (V2.getNode()->getOpcode() == ISD::UNDEF)
5587 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5588 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5590 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5591 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5594 static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
5595 SelectionDAG &DAG) {
5597 SDValue OpLHS = Op.getOperand(0);
5598 EVT VT = OpLHS.getValueType();
5600 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5601 "Expect an v8i16/v16i8 type");
5602 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
5603 // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
5604 // extract the first 8 bytes into the top double word and the last 8 bytes
5605 // into the bottom double word. The v8i16 case is similar.
5606 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5607 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
5608 DAG.getConstant(ExtractNum, MVT::i32));
5611 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
5612 SDValue V1 = Op.getOperand(0);
5613 SDValue V2 = Op.getOperand(1);
5615 EVT VT = Op.getValueType();
5616 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5618 // Convert shuffles that are directly supported on NEON to target-specific
5619 // DAG nodes, instead of keeping them as shuffles and matching them again
5620 // during code selection. This is more efficient and avoids the possibility
5621 // of inconsistencies between legalization and selection.
5622 // FIXME: floating-point vectors should be canonicalized to integer vectors
5623 // of the same time so that they get CSEd properly.
5624 ArrayRef<int> ShuffleMask = SVN->getMask();
5626 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5627 if (EltSize <= 32) {
5628 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
5629 int Lane = SVN->getSplatIndex();
5630 // If this is undef splat, generate it via "just" vdup, if possible.
5631 if (Lane == -1) Lane = 0;
5633 // Test if V1 is a SCALAR_TO_VECTOR.
5634 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5635 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5637 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5638 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
5640 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5641 !isa<ConstantSDNode>(V1.getOperand(0))) {
5642 bool IsScalarToVector = true;
5643 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
5644 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
5645 IsScalarToVector = false;
5648 if (IsScalarToVector)
5649 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5651 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
5652 DAG.getConstant(Lane, MVT::i32));
5657 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
5660 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
5661 DAG.getConstant(Imm, MVT::i32));
5664 if (isVREVMask(ShuffleMask, VT, 64))
5665 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
5666 if (isVREVMask(ShuffleMask, VT, 32))
5667 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
5668 if (isVREVMask(ShuffleMask, VT, 16))
5669 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
5671 if (V2->getOpcode() == ISD::UNDEF &&
5672 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
5673 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
5674 DAG.getConstant(Imm, MVT::i32));
5677 // Check for Neon shuffles that modify both input vectors in place.
5678 // If both results are used, i.e., if there are two shuffles with the same
5679 // source operands and with masks corresponding to both results of one of
5680 // these operations, DAG memoization will ensure that a single node is
5681 // used for both shuffles.
5682 unsigned WhichResult;
5683 if (isVTRNMask(ShuffleMask, VT, WhichResult))
5684 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5685 V1, V2).getValue(WhichResult);
5686 if (isVUZPMask(ShuffleMask, VT, WhichResult))
5687 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5688 V1, V2).getValue(WhichResult);
5689 if (isVZIPMask(ShuffleMask, VT, WhichResult))
5690 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5691 V1, V2).getValue(WhichResult);
5693 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
5694 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5695 V1, V1).getValue(WhichResult);
5696 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5697 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5698 V1, V1).getValue(WhichResult);
5699 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5700 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5701 V1, V1).getValue(WhichResult);
5704 // If the shuffle is not directly supported and it has 4 elements, use
5705 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5706 unsigned NumElts = VT.getVectorNumElements();
5708 unsigned PFIndexes[4];
5709 for (unsigned i = 0; i != 4; ++i) {
5710 if (ShuffleMask[i] < 0)
5713 PFIndexes[i] = ShuffleMask[i];
5716 // Compute the index in the perfect shuffle table.
5717 unsigned PFTableIndex =
5718 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5719 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5720 unsigned Cost = (PFEntry >> 30);
5723 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5726 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
5727 if (EltSize >= 32) {
5728 // Do the expansion with floating-point types, since that is what the VFP
5729 // registers are defined to use, and since i64 is not legal.
5730 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5731 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5732 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
5733 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
5734 SmallVector<SDValue, 8> Ops;
5735 for (unsigned i = 0; i < NumElts; ++i) {
5736 if (ShuffleMask[i] < 0)
5737 Ops.push_back(DAG.getUNDEF(EltVT));
5739 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
5740 ShuffleMask[i] < (int)NumElts ? V1 : V2,
5741 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
5744 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5745 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5748 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
5749 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
5751 if (VT == MVT::v8i8) {
5752 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
5753 if (NewOp.getNode())
5760 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5761 // INSERT_VECTOR_ELT is legal only for immediate indexes.
5762 SDValue Lane = Op.getOperand(2);
5763 if (!isa<ConstantSDNode>(Lane))
5769 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5770 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
5771 SDValue Lane = Op.getOperand(1);
5772 if (!isa<ConstantSDNode>(Lane))
5775 SDValue Vec = Op.getOperand(0);
5776 if (Op.getValueType() == MVT::i32 &&
5777 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
5779 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
5785 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5786 // The only time a CONCAT_VECTORS operation can have legal types is when
5787 // two 64-bit vectors are concatenated to a 128-bit vector.
5788 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
5789 "unexpected CONCAT_VECTORS");
5791 SDValue Val = DAG.getUNDEF(MVT::v2f64);
5792 SDValue Op0 = Op.getOperand(0);
5793 SDValue Op1 = Op.getOperand(1);
5794 if (Op0.getOpcode() != ISD::UNDEF)
5795 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5796 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
5797 DAG.getIntPtrConstant(0));
5798 if (Op1.getOpcode() != ISD::UNDEF)
5799 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5800 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
5801 DAG.getIntPtrConstant(1));
5802 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
5805 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
5806 /// element has been zero/sign-extended, depending on the isSigned parameter,
5807 /// from an integer type half its size.
5808 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
5810 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
5811 EVT VT = N->getValueType(0);
5812 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
5813 SDNode *BVN = N->getOperand(0).getNode();
5814 if (BVN->getValueType(0) != MVT::v4i32 ||
5815 BVN->getOpcode() != ISD::BUILD_VECTOR)
5817 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5818 unsigned HiElt = 1 - LoElt;
5819 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
5820 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
5821 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
5822 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
5823 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
5826 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
5827 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
5830 if (Hi0->isNullValue() && Hi1->isNullValue())
5836 if (N->getOpcode() != ISD::BUILD_VECTOR)
5839 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5840 SDNode *Elt = N->getOperand(i).getNode();
5841 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
5842 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5843 unsigned HalfSize = EltSize / 2;
5845 if (!isIntN(HalfSize, C->getSExtValue()))
5848 if (!isUIntN(HalfSize, C->getZExtValue()))
5859 /// isSignExtended - Check if a node is a vector value that is sign-extended
5860 /// or a constant BUILD_VECTOR with sign-extended elements.
5861 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
5862 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
5864 if (isExtendedBUILD_VECTOR(N, DAG, true))
5869 /// isZeroExtended - Check if a node is a vector value that is zero-extended
5870 /// or a constant BUILD_VECTOR with zero-extended elements.
5871 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
5872 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
5874 if (isExtendedBUILD_VECTOR(N, DAG, false))
5879 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
5880 if (OrigVT.getSizeInBits() >= 64)
5883 assert(OrigVT.isSimple() && "Expecting a simple value type");
5885 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
5886 switch (OrigSimpleTy) {
5887 default: llvm_unreachable("Unexpected Vector Type");
5896 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
5897 /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
5898 /// We insert the required extension here to get the vector to fill a D register.
5899 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
5902 unsigned ExtOpcode) {
5903 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
5904 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
5905 // 64-bits we need to insert a new extension so that it will be 64-bits.
5906 assert(ExtTy.is128BitVector() && "Unexpected extension size");
5907 if (OrigTy.getSizeInBits() >= 64)
5910 // Must extend size to at least 64 bits to be used as an operand for VMULL.
5911 EVT NewVT = getExtensionTo64Bits(OrigTy);
5913 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
5916 /// SkipLoadExtensionForVMULL - return a load of the original vector size that
5917 /// does not do any sign/zero extension. If the original vector is less
5918 /// than 64 bits, an appropriate extension will be added after the load to
5919 /// reach a total size of 64 bits. We have to add the extension separately
5920 /// because ARM does not have a sign/zero extending load for vectors.
5921 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
5922 EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
5924 // The load already has the right type.
5925 if (ExtendedTy == LD->getMemoryVT())
5926 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
5927 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
5928 LD->isNonTemporal(), LD->isInvariant(),
5929 LD->getAlignment());
5931 // We need to create a zextload/sextload. We cannot just create a load
5932 // followed by a zext/zext node because LowerMUL is also run during normal
5933 // operation legalization where we can't create illegal types.
5934 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
5935 LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
5936 LD->getMemoryVT(), LD->isVolatile(), LD->isInvariant(),
5937 LD->isNonTemporal(), LD->getAlignment());
5940 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
5941 /// extending load, or BUILD_VECTOR with extended elements, return the
5942 /// unextended value. The unextended vector should be 64 bits so that it can
5943 /// be used as an operand to a VMULL instruction. If the original vector size
5944 /// before extension is less than 64 bits we add a an extension to resize
5945 /// the vector to 64 bits.
5946 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
5947 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
5948 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
5949 N->getOperand(0)->getValueType(0),
5953 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
5954 return SkipLoadExtensionForVMULL(LD, DAG);
5956 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
5957 // have been legalized as a BITCAST from v4i32.
5958 if (N->getOpcode() == ISD::BITCAST) {
5959 SDNode *BVN = N->getOperand(0).getNode();
5960 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
5961 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
5962 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5963 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
5964 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
5966 // Construct a new BUILD_VECTOR with elements truncated to half the size.
5967 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
5968 EVT VT = N->getValueType(0);
5969 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
5970 unsigned NumElts = VT.getVectorNumElements();
5971 MVT TruncVT = MVT::getIntegerVT(EltSize);
5972 SmallVector<SDValue, 8> Ops;
5973 for (unsigned i = 0; i != NumElts; ++i) {
5974 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
5975 const APInt &CInt = C->getAPIntValue();
5976 // Element types smaller than 32 bits are not legal, so use i32 elements.
5977 // The values are implicitly truncated so sext vs. zext doesn't matter.
5978 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
5980 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
5981 MVT::getVectorVT(TruncVT, NumElts), Ops);
5984 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
5985 unsigned Opcode = N->getOpcode();
5986 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5987 SDNode *N0 = N->getOperand(0).getNode();
5988 SDNode *N1 = N->getOperand(1).getNode();
5989 return N0->hasOneUse() && N1->hasOneUse() &&
5990 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5995 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
5996 unsigned Opcode = N->getOpcode();
5997 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5998 SDNode *N0 = N->getOperand(0).getNode();
5999 SDNode *N1 = N->getOperand(1).getNode();
6000 return N0->hasOneUse() && N1->hasOneUse() &&
6001 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
6006 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
6007 // Multiplications are only custom-lowered for 128-bit vectors so that
6008 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
6009 EVT VT = Op.getValueType();
6010 assert(VT.is128BitVector() && VT.isInteger() &&
6011 "unexpected type for custom-lowering ISD::MUL");
6012 SDNode *N0 = Op.getOperand(0).getNode();
6013 SDNode *N1 = Op.getOperand(1).getNode();
6014 unsigned NewOpc = 0;
6016 bool isN0SExt = isSignExtended(N0, DAG);
6017 bool isN1SExt = isSignExtended(N1, DAG);
6018 if (isN0SExt && isN1SExt)
6019 NewOpc = ARMISD::VMULLs;
6021 bool isN0ZExt = isZeroExtended(N0, DAG);
6022 bool isN1ZExt = isZeroExtended(N1, DAG);
6023 if (isN0ZExt && isN1ZExt)
6024 NewOpc = ARMISD::VMULLu;
6025 else if (isN1SExt || isN1ZExt) {
6026 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
6027 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
6028 if (isN1SExt && isAddSubSExt(N0, DAG)) {
6029 NewOpc = ARMISD::VMULLs;
6031 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
6032 NewOpc = ARMISD::VMULLu;
6034 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
6036 NewOpc = ARMISD::VMULLu;
6042 if (VT == MVT::v2i64)
6043 // Fall through to expand this. It is not legal.
6046 // Other vector multiplications are legal.
6051 // Legalize to a VMULL instruction.
6054 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
6056 Op0 = SkipExtensionForVMULL(N0, DAG);
6057 assert(Op0.getValueType().is64BitVector() &&
6058 Op1.getValueType().is64BitVector() &&
6059 "unexpected types for extended operands to VMULL");
6060 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
6063 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
6064 // isel lowering to take advantage of no-stall back to back vmul + vmla.
6071 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
6072 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
6073 EVT Op1VT = Op1.getValueType();
6074 return DAG.getNode(N0->getOpcode(), DL, VT,
6075 DAG.getNode(NewOpc, DL, VT,
6076 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
6077 DAG.getNode(NewOpc, DL, VT,
6078 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
6082 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) {
6084 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
6085 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
6086 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
6087 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
6088 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
6089 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
6090 // Get reciprocal estimate.
6091 // float4 recip = vrecpeq_f32(yf);
6092 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6093 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
6094 // Because char has a smaller range than uchar, we can actually get away
6095 // without any newton steps. This requires that we use a weird bias
6096 // of 0xb000, however (again, this has been exhaustively tested).
6097 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
6098 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
6099 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
6100 Y = DAG.getConstant(0xb000, MVT::i32);
6101 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
6102 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
6103 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
6104 // Convert back to short.
6105 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
6106 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
6111 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
6113 // Convert to float.
6114 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
6115 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
6116 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
6117 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
6118 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6119 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6121 // Use reciprocal estimate and one refinement step.
6122 // float4 recip = vrecpeq_f32(yf);
6123 // recip *= vrecpsq_f32(yf, recip);
6124 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6125 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
6126 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6127 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
6129 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6130 // Because short has a smaller range than ushort, we can actually get away
6131 // with only a single newton step. This requires that we use a weird bias
6132 // of 89, however (again, this has been exhaustively tested).
6133 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
6134 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6135 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6136 N1 = DAG.getConstant(0x89, MVT::i32);
6137 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6138 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6139 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6140 // Convert back to integer and return.
6141 // return vmovn_s32(vcvt_s32_f32(result));
6142 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6143 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6147 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
6148 EVT VT = Op.getValueType();
6149 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6150 "unexpected type for custom-lowering ISD::SDIV");
6153 SDValue N0 = Op.getOperand(0);
6154 SDValue N1 = Op.getOperand(1);
6157 if (VT == MVT::v8i8) {
6158 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
6159 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
6161 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6162 DAG.getIntPtrConstant(4));
6163 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6164 DAG.getIntPtrConstant(4));
6165 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6166 DAG.getIntPtrConstant(0));
6167 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6168 DAG.getIntPtrConstant(0));
6170 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
6171 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
6173 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6174 N0 = LowerCONCAT_VECTORS(N0, DAG);
6176 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
6179 return LowerSDIV_v4i16(N0, N1, dl, DAG);
6182 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
6183 EVT VT = Op.getValueType();
6184 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6185 "unexpected type for custom-lowering ISD::UDIV");
6188 SDValue N0 = Op.getOperand(0);
6189 SDValue N1 = Op.getOperand(1);
6192 if (VT == MVT::v8i8) {
6193 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
6194 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
6196 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6197 DAG.getIntPtrConstant(4));
6198 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6199 DAG.getIntPtrConstant(4));
6200 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6201 DAG.getIntPtrConstant(0));
6202 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6203 DAG.getIntPtrConstant(0));
6205 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
6206 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
6208 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6209 N0 = LowerCONCAT_VECTORS(N0, DAG);
6211 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
6212 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
6217 // v4i16 sdiv ... Convert to float.
6218 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
6219 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
6220 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
6221 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
6222 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6223 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6225 // Use reciprocal estimate and two refinement steps.
6226 // float4 recip = vrecpeq_f32(yf);
6227 // recip *= vrecpsq_f32(yf, recip);
6228 // recip *= vrecpsq_f32(yf, recip);
6229 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6230 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
6231 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6232 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
6234 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6235 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6236 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
6238 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6239 // Simply multiplying by the reciprocal estimate can leave us a few ulps
6240 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
6241 // and that it will never cause us to return an answer too large).
6242 // float4 result = as_float4(as_int4(xf*recip) + 2);
6243 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6244 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6245 N1 = DAG.getConstant(2, MVT::i32);
6246 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6247 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6248 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6249 // Convert back to integer and return.
6250 // return vmovn_u32(vcvt_s32_f32(result));
6251 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6252 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6256 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
6257 EVT VT = Op.getNode()->getValueType(0);
6258 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
6261 bool ExtraOp = false;
6262 switch (Op.getOpcode()) {
6263 default: llvm_unreachable("Invalid code");
6264 case ISD::ADDC: Opc = ARMISD::ADDC; break;
6265 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
6266 case ISD::SUBC: Opc = ARMISD::SUBC; break;
6267 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
6271 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6273 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6274 Op.getOperand(1), Op.getOperand(2));
6277 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
6278 assert(Subtarget->isTargetDarwin());
6280 // For iOS, we want to call an alternative entry point: __sincos_stret,
6281 // return values are passed via sret.
6283 SDValue Arg = Op.getOperand(0);
6284 EVT ArgVT = Arg.getValueType();
6285 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
6287 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6288 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6290 // Pair of floats / doubles used to pass the result.
6291 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
6293 // Create stack object for sret.
6294 const uint64_t ByteSize = TLI.getDataLayout()->getTypeAllocSize(RetTy);
6295 const unsigned StackAlign = TLI.getDataLayout()->getPrefTypeAlignment(RetTy);
6296 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
6297 SDValue SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
6303 Entry.Ty = RetTy->getPointerTo();
6304 Entry.isSExt = false;
6305 Entry.isZExt = false;
6306 Entry.isSRet = true;
6307 Args.push_back(Entry);
6311 Entry.isSExt = false;
6312 Entry.isZExt = false;
6313 Args.push_back(Entry);
6315 const char *LibcallName = (ArgVT == MVT::f64)
6316 ? "__sincos_stret" : "__sincosf_stret";
6317 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
6319 TargetLowering::CallLoweringInfo CLI(DAG);
6320 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
6321 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), Callee,
6323 .setDiscardResult();
6325 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
6327 SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
6328 MachinePointerInfo(), false, false, false, 0);
6330 // Address of cos field.
6331 SDValue Add = DAG.getNode(ISD::ADD, dl, getPointerTy(), SRet,
6332 DAG.getIntPtrConstant(ArgVT.getStoreSize()));
6333 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
6334 MachinePointerInfo(), false, false, false, 0);
6336 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
6337 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
6338 LoadSin.getValue(0), LoadCos.getValue(0));
6341 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
6342 // Monotonic load/store is legal for all targets
6343 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
6346 // Acquire/Release load/store is not legal for targets without a
6347 // dmb or equivalent available.
6351 static void ReplaceREADCYCLECOUNTER(SDNode *N,
6352 SmallVectorImpl<SDValue> &Results,
6354 const ARMSubtarget *Subtarget) {
6356 SDValue Cycles32, OutChain;
6358 if (Subtarget->hasPerfMon()) {
6359 // Under Power Management extensions, the cycle-count is:
6360 // mrc p15, #0, <Rt>, c9, c13, #0
6361 SDValue Ops[] = { N->getOperand(0), // Chain
6362 DAG.getConstant(Intrinsic::arm_mrc, MVT::i32),
6363 DAG.getConstant(15, MVT::i32),
6364 DAG.getConstant(0, MVT::i32),
6365 DAG.getConstant(9, MVT::i32),
6366 DAG.getConstant(13, MVT::i32),
6367 DAG.getConstant(0, MVT::i32)
6370 Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
6371 DAG.getVTList(MVT::i32, MVT::Other), Ops);
6372 OutChain = Cycles32.getValue(1);
6374 // Intrinsic is defined to return 0 on unsupported platforms. Technically
6375 // there are older ARM CPUs that have implementation-specific ways of
6376 // obtaining this information (FIXME!).
6377 Cycles32 = DAG.getConstant(0, MVT::i32);
6378 OutChain = DAG.getEntryNode();
6382 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
6383 Cycles32, DAG.getConstant(0, MVT::i32));
6384 Results.push_back(Cycles64);
6385 Results.push_back(OutChain);
6388 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6389 switch (Op.getOpcode()) {
6390 default: llvm_unreachable("Don't know how to custom lower this!");
6391 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6392 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6393 case ISD::GlobalAddress:
6394 switch (Subtarget->getTargetTriple().getObjectFormat()) {
6395 default: llvm_unreachable("unknown object format");
6397 return LowerGlobalAddressWindows(Op, DAG);
6399 return LowerGlobalAddressELF(Op, DAG);
6401 return LowerGlobalAddressDarwin(Op, DAG);
6403 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6404 case ISD::SELECT: return LowerSELECT(Op, DAG);
6405 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6406 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
6407 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
6408 case ISD::VASTART: return LowerVASTART(Op, DAG);
6409 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
6410 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
6411 case ISD::SINT_TO_FP:
6412 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6413 case ISD::FP_TO_SINT:
6414 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
6415 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6416 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6417 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6418 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
6419 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
6420 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
6421 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6423 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
6426 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
6427 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
6428 case ISD::SRL_PARTS:
6429 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
6430 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
6431 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
6432 case ISD::SETCC: return LowerVSETCC(Op, DAG);
6433 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
6434 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6435 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6436 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6437 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6438 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
6439 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6440 case ISD::MUL: return LowerMUL(Op, DAG);
6441 case ISD::SDIV: return LowerSDIV(Op, DAG);
6442 case ISD::UDIV: return LowerUDIV(Op, DAG);
6446 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
6451 return LowerXALUO(Op, DAG);
6452 case ISD::ATOMIC_LOAD:
6453 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
6454 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
6456 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
6457 case ISD::DYNAMIC_STACKALLOC:
6458 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
6459 return LowerDYNAMIC_STACKALLOC(Op, DAG);
6460 llvm_unreachable("Don't know how to custom lower this!");
6461 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
6462 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
6466 /// ReplaceNodeResults - Replace the results of node with an illegal result
6467 /// type with new values built out of custom code.
6468 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6469 SmallVectorImpl<SDValue>&Results,
6470 SelectionDAG &DAG) const {
6472 switch (N->getOpcode()) {
6474 llvm_unreachable("Don't know how to custom expand this!");
6476 Res = ExpandBITCAST(N, DAG);
6480 Res = Expand64BitShift(N, DAG, Subtarget);
6482 case ISD::READCYCLECOUNTER:
6483 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
6487 Results.push_back(Res);
6490 //===----------------------------------------------------------------------===//
6491 // ARM Scheduler Hooks
6492 //===----------------------------------------------------------------------===//
6494 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
6495 /// registers the function context.
6496 void ARMTargetLowering::
6497 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
6498 MachineBasicBlock *DispatchBB, int FI) const {
6499 const TargetInstrInfo *TII =
6500 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6501 DebugLoc dl = MI->getDebugLoc();
6502 MachineFunction *MF = MBB->getParent();
6503 MachineRegisterInfo *MRI = &MF->getRegInfo();
6504 MachineConstantPool *MCP = MF->getConstantPool();
6505 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6506 const Function *F = MF->getFunction();
6508 bool isThumb = Subtarget->isThumb();
6509 bool isThumb2 = Subtarget->isThumb2();
6511 unsigned PCLabelId = AFI->createPICLabelUId();
6512 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
6513 ARMConstantPoolValue *CPV =
6514 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6515 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6517 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass
6518 : &ARM::GPRRegClass;
6520 // Grab constant pool and fixed stack memory operands.
6521 MachineMemOperand *CPMMO =
6522 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
6523 MachineMemOperand::MOLoad, 4, 4);
6525 MachineMemOperand *FIMMOSt =
6526 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6527 MachineMemOperand::MOStore, 4, 4);
6529 // Load the address of the dispatch MBB into the jump buffer.
6531 // Incoming value: jbuf
6532 // ldr.n r5, LCPI1_1
6535 // str r5, [$jbuf, #+4] ; &jbuf[1]
6536 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6537 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6538 .addConstantPoolIndex(CPI)
6539 .addMemOperand(CPMMO));
6540 // Set the low bit because of thumb mode.
6541 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6543 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6544 .addReg(NewVReg1, RegState::Kill)
6546 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6547 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6548 .addReg(NewVReg2, RegState::Kill)
6550 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6551 .addReg(NewVReg3, RegState::Kill)
6553 .addImm(36) // &jbuf[1] :: pc
6554 .addMemOperand(FIMMOSt));
6555 } else if (isThumb) {
6556 // Incoming value: jbuf
6557 // ldr.n r1, LCPI1_4
6561 // add r2, $jbuf, #+4 ; &jbuf[1]
6563 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6564 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6565 .addConstantPoolIndex(CPI)
6566 .addMemOperand(CPMMO));
6567 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6568 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6569 .addReg(NewVReg1, RegState::Kill)
6571 // Set the low bit because of thumb mode.
6572 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6573 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6574 .addReg(ARM::CPSR, RegState::Define)
6576 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6577 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6578 .addReg(ARM::CPSR, RegState::Define)
6579 .addReg(NewVReg2, RegState::Kill)
6580 .addReg(NewVReg3, RegState::Kill));
6581 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6582 BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
6584 .addImm(36); // &jbuf[1] :: pc
6585 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6586 .addReg(NewVReg4, RegState::Kill)
6587 .addReg(NewVReg5, RegState::Kill)
6589 .addMemOperand(FIMMOSt));
6591 // Incoming value: jbuf
6594 // str r1, [$jbuf, #+4] ; &jbuf[1]
6595 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6596 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6597 .addConstantPoolIndex(CPI)
6599 .addMemOperand(CPMMO));
6600 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6601 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6602 .addReg(NewVReg1, RegState::Kill)
6603 .addImm(PCLabelId));
6604 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6605 .addReg(NewVReg2, RegState::Kill)
6607 .addImm(36) // &jbuf[1] :: pc
6608 .addMemOperand(FIMMOSt));
6612 MachineBasicBlock *ARMTargetLowering::
6613 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
6614 const TargetInstrInfo *TII =
6615 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6616 DebugLoc dl = MI->getDebugLoc();
6617 MachineFunction *MF = MBB->getParent();
6618 MachineRegisterInfo *MRI = &MF->getRegInfo();
6619 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6620 MachineFrameInfo *MFI = MF->getFrameInfo();
6621 int FI = MFI->getFunctionContextIndex();
6623 const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass
6624 : &ARM::GPRnopcRegClass;
6626 // Get a mapping of the call site numbers to all of the landing pads they're
6628 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
6629 unsigned MaxCSNum = 0;
6630 MachineModuleInfo &MMI = MF->getMMI();
6631 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6633 if (!BB->isLandingPad()) continue;
6635 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6637 for (MachineBasicBlock::iterator
6638 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6639 if (!II->isEHLabel()) continue;
6641 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
6642 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
6644 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6645 for (SmallVectorImpl<unsigned>::iterator
6646 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6647 CSI != CSE; ++CSI) {
6648 CallSiteNumToLPad[*CSI].push_back(BB);
6649 MaxCSNum = std::max(MaxCSNum, *CSI);
6655 // Get an ordered list of the machine basic blocks for the jump table.
6656 std::vector<MachineBasicBlock*> LPadList;
6657 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
6658 LPadList.reserve(CallSiteNumToLPad.size());
6659 for (unsigned I = 1; I <= MaxCSNum; ++I) {
6660 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6661 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6662 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
6663 LPadList.push_back(*II);
6664 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6668 assert(!LPadList.empty() &&
6669 "No landing pad destinations for the dispatch jump table!");
6671 // Create the jump table and associated information.
6672 MachineJumpTableInfo *JTI =
6673 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6674 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6675 unsigned UId = AFI->createJumpTableUId();
6676 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
6678 // Create the MBBs for the dispatch code.
6680 // Shove the dispatch's address into the return slot in the function context.
6681 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6682 DispatchBB->setIsLandingPad();
6684 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
6685 unsigned trap_opcode;
6686 if (Subtarget->isThumb())
6687 trap_opcode = ARM::tTRAP;
6689 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
6691 BuildMI(TrapBB, dl, TII->get(trap_opcode));
6692 DispatchBB->addSuccessor(TrapBB);
6694 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6695 DispatchBB->addSuccessor(DispContBB);
6698 MF->insert(MF->end(), DispatchBB);
6699 MF->insert(MF->end(), DispContBB);
6700 MF->insert(MF->end(), TrapBB);
6702 // Insert code into the entry block that creates and registers the function
6704 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6706 MachineMemOperand *FIMMOLd =
6707 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6708 MachineMemOperand::MOLoad |
6709 MachineMemOperand::MOVolatile, 4, 4);
6711 MachineInstrBuilder MIB;
6712 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6714 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6715 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6717 // Add a register mask with no preserved registers. This results in all
6718 // registers being marked as clobbered.
6719 MIB.addRegMask(RI.getNoPreservedMask());
6721 unsigned NumLPads = LPadList.size();
6722 if (Subtarget->isThumb2()) {
6723 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6724 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6727 .addMemOperand(FIMMOLd));
6729 if (NumLPads < 256) {
6730 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6732 .addImm(LPadList.size()));
6734 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6735 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6736 .addImm(NumLPads & 0xFFFF));
6738 unsigned VReg2 = VReg1;
6739 if ((NumLPads & 0xFFFF0000) != 0) {
6740 VReg2 = MRI->createVirtualRegister(TRC);
6741 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6743 .addImm(NumLPads >> 16));
6746 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6751 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
6756 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6757 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6758 .addJumpTableIndex(MJTI)
6761 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6764 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
6765 .addReg(NewVReg3, RegState::Kill)
6767 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6769 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
6770 .addReg(NewVReg4, RegState::Kill)
6772 .addJumpTableIndex(MJTI)
6774 } else if (Subtarget->isThumb()) {
6775 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6776 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6779 .addMemOperand(FIMMOLd));
6781 if (NumLPads < 256) {
6782 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6786 MachineConstantPool *ConstantPool = MF->getConstantPool();
6787 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6788 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6790 // MachineConstantPool wants an explicit alignment.
6791 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6793 Align = getDataLayout()->getTypeAllocSize(C->getType());
6794 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6796 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6797 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
6798 .addReg(VReg1, RegState::Define)
6799 .addConstantPoolIndex(Idx));
6800 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
6805 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
6810 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6811 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
6812 .addReg(ARM::CPSR, RegState::Define)
6816 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6817 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
6818 .addJumpTableIndex(MJTI)
6821 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6822 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
6823 .addReg(ARM::CPSR, RegState::Define)
6824 .addReg(NewVReg2, RegState::Kill)
6827 MachineMemOperand *JTMMOLd =
6828 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6829 MachineMemOperand::MOLoad, 4, 4);
6831 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6832 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
6833 .addReg(NewVReg4, RegState::Kill)
6835 .addMemOperand(JTMMOLd));
6837 unsigned NewVReg6 = NewVReg5;
6838 if (RelocM == Reloc::PIC_) {
6839 NewVReg6 = MRI->createVirtualRegister(TRC);
6840 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
6841 .addReg(ARM::CPSR, RegState::Define)
6842 .addReg(NewVReg5, RegState::Kill)
6846 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
6847 .addReg(NewVReg6, RegState::Kill)
6848 .addJumpTableIndex(MJTI)
6851 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6852 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
6855 .addMemOperand(FIMMOLd));
6857 if (NumLPads < 256) {
6858 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
6861 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
6862 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6863 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
6864 .addImm(NumLPads & 0xFFFF));
6866 unsigned VReg2 = VReg1;
6867 if ((NumLPads & 0xFFFF0000) != 0) {
6868 VReg2 = MRI->createVirtualRegister(TRC);
6869 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
6871 .addImm(NumLPads >> 16));
6874 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6878 MachineConstantPool *ConstantPool = MF->getConstantPool();
6879 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6880 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6882 // MachineConstantPool wants an explicit alignment.
6883 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6885 Align = getDataLayout()->getTypeAllocSize(C->getType());
6886 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6888 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6889 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
6890 .addReg(VReg1, RegState::Define)
6891 .addConstantPoolIndex(Idx)
6893 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6895 .addReg(VReg1, RegState::Kill));
6898 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
6903 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6905 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
6907 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6908 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6909 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
6910 .addJumpTableIndex(MJTI)
6913 MachineMemOperand *JTMMOLd =
6914 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6915 MachineMemOperand::MOLoad, 4, 4);
6916 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6918 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
6919 .addReg(NewVReg3, RegState::Kill)
6922 .addMemOperand(JTMMOLd));
6924 if (RelocM == Reloc::PIC_) {
6925 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
6926 .addReg(NewVReg5, RegState::Kill)
6928 .addJumpTableIndex(MJTI)
6931 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
6932 .addReg(NewVReg5, RegState::Kill)
6933 .addJumpTableIndex(MJTI)
6938 // Add the jump table entries as successors to the MBB.
6939 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
6940 for (std::vector<MachineBasicBlock*>::iterator
6941 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
6942 MachineBasicBlock *CurMBB = *I;
6943 if (SeenMBBs.insert(CurMBB).second)
6944 DispContBB->addSuccessor(CurMBB);
6947 // N.B. the order the invoke BBs are processed in doesn't matter here.
6948 const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
6949 SmallVector<MachineBasicBlock*, 64> MBBLPads;
6950 for (MachineBasicBlock *BB : InvokeBBs) {
6952 // Remove the landing pad successor from the invoke block and replace it
6953 // with the new dispatch block.
6954 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
6956 while (!Successors.empty()) {
6957 MachineBasicBlock *SMBB = Successors.pop_back_val();
6958 if (SMBB->isLandingPad()) {
6959 BB->removeSuccessor(SMBB);
6960 MBBLPads.push_back(SMBB);
6964 BB->addSuccessor(DispatchBB);
6966 // Find the invoke call and mark all of the callee-saved registers as
6967 // 'implicit defined' so that they're spilled. This prevents code from
6968 // moving instructions to before the EH block, where they will never be
6970 for (MachineBasicBlock::reverse_iterator
6971 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
6972 if (!II->isCall()) continue;
6974 DenseMap<unsigned, bool> DefRegs;
6975 for (MachineInstr::mop_iterator
6976 OI = II->operands_begin(), OE = II->operands_end();
6978 if (!OI->isReg()) continue;
6979 DefRegs[OI->getReg()] = true;
6982 MachineInstrBuilder MIB(*MF, &*II);
6984 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
6985 unsigned Reg = SavedRegs[i];
6986 if (Subtarget->isThumb2() &&
6987 !ARM::tGPRRegClass.contains(Reg) &&
6988 !ARM::hGPRRegClass.contains(Reg))
6990 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
6992 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
6995 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
7002 // Mark all former landing pads as non-landing pads. The dispatch is the only
7004 for (SmallVectorImpl<MachineBasicBlock*>::iterator
7005 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
7006 (*I)->setIsLandingPad(false);
7008 // The instruction is gone now.
7009 MI->eraseFromParent();
7015 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
7016 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
7017 E = MBB->succ_end(); I != E; ++I)
7020 llvm_unreachable("Expecting a BB with two successors!");
7023 /// Return the load opcode for a given load size. If load size >= 8,
7024 /// neon opcode will be returned.
7025 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
7027 return LdSize == 16 ? ARM::VLD1q32wb_fixed
7028 : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
7030 return LdSize == 4 ? ARM::tLDRi
7031 : LdSize == 2 ? ARM::tLDRHi
7032 : LdSize == 1 ? ARM::tLDRBi : 0;
7034 return LdSize == 4 ? ARM::t2LDR_POST
7035 : LdSize == 2 ? ARM::t2LDRH_POST
7036 : LdSize == 1 ? ARM::t2LDRB_POST : 0;
7037 return LdSize == 4 ? ARM::LDR_POST_IMM
7038 : LdSize == 2 ? ARM::LDRH_POST
7039 : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
7042 /// Return the store opcode for a given store size. If store size >= 8,
7043 /// neon opcode will be returned.
7044 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
7046 return StSize == 16 ? ARM::VST1q32wb_fixed
7047 : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
7049 return StSize == 4 ? ARM::tSTRi
7050 : StSize == 2 ? ARM::tSTRHi
7051 : StSize == 1 ? ARM::tSTRBi : 0;
7053 return StSize == 4 ? ARM::t2STR_POST
7054 : StSize == 2 ? ARM::t2STRH_POST
7055 : StSize == 1 ? ARM::t2STRB_POST : 0;
7056 return StSize == 4 ? ARM::STR_POST_IMM
7057 : StSize == 2 ? ARM::STRH_POST
7058 : StSize == 1 ? ARM::STRB_POST_IMM : 0;
7061 /// Emit a post-increment load operation with given size. The instructions
7062 /// will be added to BB at Pos.
7063 static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
7064 const TargetInstrInfo *TII, DebugLoc dl,
7065 unsigned LdSize, unsigned Data, unsigned AddrIn,
7066 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7067 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
7068 assert(LdOpc != 0 && "Should have a load opcode");
7070 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7071 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7073 } else if (IsThumb1) {
7074 // load + update AddrIn
7075 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7076 .addReg(AddrIn).addImm(0));
7077 MachineInstrBuilder MIB =
7078 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7079 MIB = AddDefaultT1CC(MIB);
7080 MIB.addReg(AddrIn).addImm(LdSize);
7081 AddDefaultPred(MIB);
7082 } else if (IsThumb2) {
7083 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7084 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7087 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7088 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7089 .addReg(0).addImm(LdSize));
7093 /// Emit a post-increment store operation with given size. The instructions
7094 /// will be added to BB at Pos.
7095 static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
7096 const TargetInstrInfo *TII, DebugLoc dl,
7097 unsigned StSize, unsigned Data, unsigned AddrIn,
7098 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7099 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
7100 assert(StOpc != 0 && "Should have a store opcode");
7102 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7103 .addReg(AddrIn).addImm(0).addReg(Data));
7104 } else if (IsThumb1) {
7105 // store + update AddrIn
7106 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
7107 .addReg(AddrIn).addImm(0));
7108 MachineInstrBuilder MIB =
7109 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7110 MIB = AddDefaultT1CC(MIB);
7111 MIB.addReg(AddrIn).addImm(StSize);
7112 AddDefaultPred(MIB);
7113 } else if (IsThumb2) {
7114 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7115 .addReg(Data).addReg(AddrIn).addImm(StSize));
7117 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7118 .addReg(Data).addReg(AddrIn).addReg(0)
7124 ARMTargetLowering::EmitStructByval(MachineInstr *MI,
7125 MachineBasicBlock *BB) const {
7126 // This pseudo instruction has 3 operands: dst, src, size
7127 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
7128 // Otherwise, we will generate unrolled scalar copies.
7129 const TargetInstrInfo *TII =
7130 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7131 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7132 MachineFunction::iterator It = BB;
7135 unsigned dest = MI->getOperand(0).getReg();
7136 unsigned src = MI->getOperand(1).getReg();
7137 unsigned SizeVal = MI->getOperand(2).getImm();
7138 unsigned Align = MI->getOperand(3).getImm();
7139 DebugLoc dl = MI->getDebugLoc();
7141 MachineFunction *MF = BB->getParent();
7142 MachineRegisterInfo &MRI = MF->getRegInfo();
7143 unsigned UnitSize = 0;
7144 const TargetRegisterClass *TRC = nullptr;
7145 const TargetRegisterClass *VecTRC = nullptr;
7147 bool IsThumb1 = Subtarget->isThumb1Only();
7148 bool IsThumb2 = Subtarget->isThumb2();
7152 } else if (Align & 2) {
7155 // Check whether we can use NEON instructions.
7156 if (!MF->getFunction()->getAttributes().
7157 hasAttribute(AttributeSet::FunctionIndex,
7158 Attribute::NoImplicitFloat) &&
7159 Subtarget->hasNEON()) {
7160 if ((Align % 16 == 0) && SizeVal >= 16)
7162 else if ((Align % 8 == 0) && SizeVal >= 8)
7165 // Can't use NEON instructions.
7170 // Select the correct opcode and register class for unit size load/store
7171 bool IsNeon = UnitSize >= 8;
7172 TRC = (IsThumb1 || IsThumb2) ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
7174 VecTRC = UnitSize == 16 ? &ARM::DPairRegClass
7175 : UnitSize == 8 ? &ARM::DPRRegClass
7178 unsigned BytesLeft = SizeVal % UnitSize;
7179 unsigned LoopSize = SizeVal - BytesLeft;
7181 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
7182 // Use LDR and STR to copy.
7183 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
7184 // [destOut] = STR_POST(scratch, destIn, UnitSize)
7185 unsigned srcIn = src;
7186 unsigned destIn = dest;
7187 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
7188 unsigned srcOut = MRI.createVirtualRegister(TRC);
7189 unsigned destOut = MRI.createVirtualRegister(TRC);
7190 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7191 emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
7192 IsThumb1, IsThumb2);
7193 emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
7194 IsThumb1, IsThumb2);
7199 // Handle the leftover bytes with LDRB and STRB.
7200 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
7201 // [destOut] = STRB_POST(scratch, destIn, 1)
7202 for (unsigned i = 0; i < BytesLeft; i++) {
7203 unsigned srcOut = MRI.createVirtualRegister(TRC);
7204 unsigned destOut = MRI.createVirtualRegister(TRC);
7205 unsigned scratch = MRI.createVirtualRegister(TRC);
7206 emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
7207 IsThumb1, IsThumb2);
7208 emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
7209 IsThumb1, IsThumb2);
7213 MI->eraseFromParent(); // The instruction is gone now.
7217 // Expand the pseudo op to a loop.
7220 // movw varEnd, # --> with thumb2
7222 // ldrcp varEnd, idx --> without thumb2
7223 // fallthrough --> loopMBB
7225 // PHI varPhi, varEnd, varLoop
7226 // PHI srcPhi, src, srcLoop
7227 // PHI destPhi, dst, destLoop
7228 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7229 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
7230 // subs varLoop, varPhi, #UnitSize
7232 // fallthrough --> exitMBB
7234 // epilogue to handle left-over bytes
7235 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7236 // [destOut] = STRB_POST(scratch, destLoop, 1)
7237 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7238 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7239 MF->insert(It, loopMBB);
7240 MF->insert(It, exitMBB);
7242 // Transfer the remainder of BB and its successor edges to exitMBB.
7243 exitMBB->splice(exitMBB->begin(), BB,
7244 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7245 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7247 // Load an immediate to varEnd.
7248 unsigned varEnd = MRI.createVirtualRegister(TRC);
7250 unsigned Vtmp = varEnd;
7251 if ((LoopSize & 0xFFFF0000) != 0)
7252 Vtmp = MRI.createVirtualRegister(TRC);
7253 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), Vtmp)
7254 .addImm(LoopSize & 0xFFFF));
7256 if ((LoopSize & 0xFFFF0000) != 0)
7257 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
7258 .addReg(Vtmp).addImm(LoopSize >> 16));
7260 MachineConstantPool *ConstantPool = MF->getConstantPool();
7261 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7262 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7264 // MachineConstantPool wants an explicit alignment.
7265 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
7267 Align = getDataLayout()->getTypeAllocSize(C->getType());
7268 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7271 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7272 varEnd, RegState::Define).addConstantPoolIndex(Idx));
7274 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7275 varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
7277 BB->addSuccessor(loopMBB);
7279 // Generate the loop body:
7280 // varPhi = PHI(varLoop, varEnd)
7281 // srcPhi = PHI(srcLoop, src)
7282 // destPhi = PHI(destLoop, dst)
7283 MachineBasicBlock *entryBB = BB;
7285 unsigned varLoop = MRI.createVirtualRegister(TRC);
7286 unsigned varPhi = MRI.createVirtualRegister(TRC);
7287 unsigned srcLoop = MRI.createVirtualRegister(TRC);
7288 unsigned srcPhi = MRI.createVirtualRegister(TRC);
7289 unsigned destLoop = MRI.createVirtualRegister(TRC);
7290 unsigned destPhi = MRI.createVirtualRegister(TRC);
7292 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
7293 .addReg(varLoop).addMBB(loopMBB)
7294 .addReg(varEnd).addMBB(entryBB);
7295 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
7296 .addReg(srcLoop).addMBB(loopMBB)
7297 .addReg(src).addMBB(entryBB);
7298 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
7299 .addReg(destLoop).addMBB(loopMBB)
7300 .addReg(dest).addMBB(entryBB);
7302 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7303 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
7304 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7305 emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
7306 IsThumb1, IsThumb2);
7307 emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
7308 IsThumb1, IsThumb2);
7310 // Decrement loop variable by UnitSize.
7312 MachineInstrBuilder MIB =
7313 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
7314 MIB = AddDefaultT1CC(MIB);
7315 MIB.addReg(varPhi).addImm(UnitSize);
7316 AddDefaultPred(MIB);
7318 MachineInstrBuilder MIB =
7319 BuildMI(*BB, BB->end(), dl,
7320 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
7321 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7322 MIB->getOperand(5).setReg(ARM::CPSR);
7323 MIB->getOperand(5).setIsDef(true);
7325 BuildMI(*BB, BB->end(), dl,
7326 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
7327 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
7329 // loopMBB can loop back to loopMBB or fall through to exitMBB.
7330 BB->addSuccessor(loopMBB);
7331 BB->addSuccessor(exitMBB);
7333 // Add epilogue to handle BytesLeft.
7335 MachineInstr *StartOfExit = exitMBB->begin();
7337 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7338 // [destOut] = STRB_POST(scratch, destLoop, 1)
7339 unsigned srcIn = srcLoop;
7340 unsigned destIn = destLoop;
7341 for (unsigned i = 0; i < BytesLeft; i++) {
7342 unsigned srcOut = MRI.createVirtualRegister(TRC);
7343 unsigned destOut = MRI.createVirtualRegister(TRC);
7344 unsigned scratch = MRI.createVirtualRegister(TRC);
7345 emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
7346 IsThumb1, IsThumb2);
7347 emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
7348 IsThumb1, IsThumb2);
7353 MI->eraseFromParent(); // The instruction is gone now.
7358 ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI,
7359 MachineBasicBlock *MBB) const {
7360 const TargetMachine &TM = getTargetMachine();
7361 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
7362 DebugLoc DL = MI->getDebugLoc();
7364 assert(Subtarget->isTargetWindows() &&
7365 "__chkstk is only supported on Windows");
7366 assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
7368 // __chkstk takes the number of words to allocate on the stack in R4, and
7369 // returns the stack adjustment in number of bytes in R4. This will not
7370 // clober any other registers (other than the obvious lr).
7372 // Although, technically, IP should be considered a register which may be
7373 // clobbered, the call itself will not touch it. Windows on ARM is a pure
7374 // thumb-2 environment, so there is no interworking required. As a result, we
7375 // do not expect a veneer to be emitted by the linker, clobbering IP.
7377 // Each module receives its own copy of __chkstk, so no import thunk is
7378 // required, again, ensuring that IP is not clobbered.
7380 // Finally, although some linkers may theoretically provide a trampoline for
7381 // out of range calls (which is quite common due to a 32M range limitation of
7382 // branches for Thumb), we can generate the long-call version via
7383 // -mcmodel=large, alleviating the need for the trampoline which may clobber
7386 switch (TM.getCodeModel()) {
7387 case CodeModel::Small:
7388 case CodeModel::Medium:
7389 case CodeModel::Default:
7390 case CodeModel::Kernel:
7391 BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
7392 .addImm((unsigned)ARMCC::AL).addReg(0)
7393 .addExternalSymbol("__chkstk")
7394 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7395 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7396 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7398 case CodeModel::Large:
7399 case CodeModel::JITDefault: {
7400 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
7401 unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
7403 BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
7404 .addExternalSymbol("__chkstk");
7405 BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
7406 .addImm((unsigned)ARMCC::AL).addReg(0)
7407 .addReg(Reg, RegState::Kill)
7408 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7409 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7410 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7415 AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr),
7417 .addReg(ARM::SP).addReg(ARM::R4)));
7419 MI->eraseFromParent();
7424 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7425 MachineBasicBlock *BB) const {
7426 const TargetInstrInfo *TII =
7427 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7428 DebugLoc dl = MI->getDebugLoc();
7429 bool isThumb2 = Subtarget->isThumb2();
7430 switch (MI->getOpcode()) {
7433 llvm_unreachable("Unexpected instr type to insert");
7435 // The Thumb2 pre-indexed stores have the same MI operands, they just
7436 // define them differently in the .td files from the isel patterns, so
7437 // they need pseudos.
7438 case ARM::t2STR_preidx:
7439 MI->setDesc(TII->get(ARM::t2STR_PRE));
7441 case ARM::t2STRB_preidx:
7442 MI->setDesc(TII->get(ARM::t2STRB_PRE));
7444 case ARM::t2STRH_preidx:
7445 MI->setDesc(TII->get(ARM::t2STRH_PRE));
7448 case ARM::STRi_preidx:
7449 case ARM::STRBi_preidx: {
7450 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7451 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7452 // Decode the offset.
7453 unsigned Offset = MI->getOperand(4).getImm();
7454 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7455 Offset = ARM_AM::getAM2Offset(Offset);
7459 MachineMemOperand *MMO = *MI->memoperands_begin();
7460 BuildMI(*BB, MI, dl, TII->get(NewOpc))
7461 .addOperand(MI->getOperand(0)) // Rn_wb
7462 .addOperand(MI->getOperand(1)) // Rt
7463 .addOperand(MI->getOperand(2)) // Rn
7464 .addImm(Offset) // offset (skip GPR==zero_reg)
7465 .addOperand(MI->getOperand(5)) // pred
7466 .addOperand(MI->getOperand(6))
7467 .addMemOperand(MMO);
7468 MI->eraseFromParent();
7471 case ARM::STRr_preidx:
7472 case ARM::STRBr_preidx:
7473 case ARM::STRH_preidx: {
7475 switch (MI->getOpcode()) {
7476 default: llvm_unreachable("unexpected opcode!");
7477 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7478 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7479 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7481 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7482 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7483 MIB.addOperand(MI->getOperand(i));
7484 MI->eraseFromParent();
7488 case ARM::tMOVCCr_pseudo: {
7489 // To "insert" a SELECT_CC instruction, we actually have to insert the
7490 // diamond control-flow pattern. The incoming instruction knows the
7491 // destination vreg to set, the condition code register to branch on, the
7492 // true/false values to select between, and a branch opcode to use.
7493 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7494 MachineFunction::iterator It = BB;
7500 // cmpTY ccX, r1, r2
7502 // fallthrough --> copy0MBB
7503 MachineBasicBlock *thisMBB = BB;
7504 MachineFunction *F = BB->getParent();
7505 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7506 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7507 F->insert(It, copy0MBB);
7508 F->insert(It, sinkMBB);
7510 // Transfer the remainder of BB and its successor edges to sinkMBB.
7511 sinkMBB->splice(sinkMBB->begin(), BB,
7512 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7513 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7515 BB->addSuccessor(copy0MBB);
7516 BB->addSuccessor(sinkMBB);
7518 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7519 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7522 // %FalseValue = ...
7523 // # fallthrough to sinkMBB
7526 // Update machine-CFG edges
7527 BB->addSuccessor(sinkMBB);
7530 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7533 BuildMI(*BB, BB->begin(), dl,
7534 TII->get(ARM::PHI), MI->getOperand(0).getReg())
7535 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7536 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7538 MI->eraseFromParent(); // The pseudo instruction is gone now.
7543 case ARM::BCCZi64: {
7544 // If there is an unconditional branch to the other successor, remove it.
7545 BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
7547 // Compare both parts that make up the double comparison separately for
7549 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7551 unsigned LHS1 = MI->getOperand(1).getReg();
7552 unsigned LHS2 = MI->getOperand(2).getReg();
7554 AddDefaultPred(BuildMI(BB, dl,
7555 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7556 .addReg(LHS1).addImm(0));
7557 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7558 .addReg(LHS2).addImm(0)
7559 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7561 unsigned RHS1 = MI->getOperand(3).getReg();
7562 unsigned RHS2 = MI->getOperand(4).getReg();
7563 AddDefaultPred(BuildMI(BB, dl,
7564 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7565 .addReg(LHS1).addReg(RHS1));
7566 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7567 .addReg(LHS2).addReg(RHS2)
7568 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7571 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7572 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7573 if (MI->getOperand(0).getImm() == ARMCC::NE)
7574 std::swap(destMBB, exitMBB);
7576 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7577 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
7579 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7581 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
7583 MI->eraseFromParent(); // The pseudo instruction is gone now.
7587 case ARM::Int_eh_sjlj_setjmp:
7588 case ARM::Int_eh_sjlj_setjmp_nofp:
7589 case ARM::tInt_eh_sjlj_setjmp:
7590 case ARM::t2Int_eh_sjlj_setjmp:
7591 case ARM::t2Int_eh_sjlj_setjmp_nofp:
7592 EmitSjLjDispatchBlock(MI, BB);
7597 // To insert an ABS instruction, we have to insert the
7598 // diamond control-flow pattern. The incoming instruction knows the
7599 // source vreg to test against 0, the destination vreg to set,
7600 // the condition code register to branch on, the
7601 // true/false values to select between, and a branch opcode to use.
7606 // BCC (branch to SinkBB if V0 >= 0)
7607 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
7608 // SinkBB: V1 = PHI(V2, V3)
7609 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7610 MachineFunction::iterator BBI = BB;
7612 MachineFunction *Fn = BB->getParent();
7613 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7614 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7615 Fn->insert(BBI, RSBBB);
7616 Fn->insert(BBI, SinkBB);
7618 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7619 unsigned int ABSDstReg = MI->getOperand(0).getReg();
7620 bool isThumb2 = Subtarget->isThumb2();
7621 MachineRegisterInfo &MRI = Fn->getRegInfo();
7622 // In Thumb mode S must not be specified if source register is the SP or
7623 // PC and if destination register is the SP, so restrict register class
7624 unsigned NewRsbDstReg =
7625 MRI.createVirtualRegister(isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass);
7627 // Transfer the remainder of BB and its successor edges to sinkMBB.
7628 SinkBB->splice(SinkBB->begin(), BB,
7629 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7630 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7632 BB->addSuccessor(RSBBB);
7633 BB->addSuccessor(SinkBB);
7635 // fall through to SinkMBB
7636 RSBBB->addSuccessor(SinkBB);
7638 // insert a cmp at the end of BB
7639 AddDefaultPred(BuildMI(BB, dl,
7640 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7641 .addReg(ABSSrcReg).addImm(0));
7643 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7645 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7646 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
7648 // insert rsbri in RSBBB
7649 // Note: BCC and rsbri will be converted into predicated rsbmi
7650 // by if-conversion pass
7651 BuildMI(*RSBBB, RSBBB->begin(), dl,
7652 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
7653 .addReg(ABSSrcReg, RegState::Kill)
7654 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7656 // insert PHI in SinkBB,
7657 // reuse ABSDstReg to not change uses of ABS instruction
7658 BuildMI(*SinkBB, SinkBB->begin(), dl,
7659 TII->get(ARM::PHI), ABSDstReg)
7660 .addReg(NewRsbDstReg).addMBB(RSBBB)
7661 .addReg(ABSSrcReg).addMBB(BB);
7663 // remove ABS instruction
7664 MI->eraseFromParent();
7666 // return last added BB
7669 case ARM::COPY_STRUCT_BYVAL_I32:
7671 return EmitStructByval(MI, BB);
7672 case ARM::WIN__CHKSTK:
7673 return EmitLowered__chkstk(MI, BB);
7677 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
7678 SDNode *Node) const {
7679 const MCInstrDesc *MCID = &MI->getDesc();
7680 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7681 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7682 // operand is still set to noreg. If needed, set the optional operand's
7683 // register to CPSR, and remove the redundant implicit def.
7685 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7687 // Rename pseudo opcodes.
7688 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7690 const ARMBaseInstrInfo *TII = static_cast<const ARMBaseInstrInfo *>(
7691 getTargetMachine().getSubtargetImpl()->getInstrInfo());
7692 MCID = &TII->get(NewOpc);
7694 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7695 "converted opcode should be the same except for cc_out");
7699 // Add the optional cc_out operand
7700 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7702 unsigned ccOutIdx = MCID->getNumOperands() - 1;
7704 // Any ARM instruction that sets the 's' bit should specify an optional
7705 // "cc_out" operand in the last operand position.
7706 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7707 assert(!NewOpc && "Optional cc_out operand required");
7710 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7711 // since we already have an optional CPSR def.
7712 bool definesCPSR = false;
7713 bool deadCPSR = false;
7714 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
7716 const MachineOperand &MO = MI->getOperand(i);
7717 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7721 MI->RemoveOperand(i);
7726 assert(!NewOpc && "Optional cc_out operand required");
7729 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
7731 assert(!MI->getOperand(ccOutIdx).getReg() &&
7732 "expect uninitialized optional cc_out operand");
7736 // If this instruction was defined with an optional CPSR def and its dag node
7737 // had a live implicit CPSR def, then activate the optional CPSR def.
7738 MachineOperand &MO = MI->getOperand(ccOutIdx);
7739 MO.setReg(ARM::CPSR);
7743 //===----------------------------------------------------------------------===//
7744 // ARM Optimization Hooks
7745 //===----------------------------------------------------------------------===//
7747 // Helper function that checks if N is a null or all ones constant.
7748 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
7749 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
7752 return AllOnes ? C->isAllOnesValue() : C->isNullValue();
7755 // Return true if N is conditionally 0 or all ones.
7756 // Detects these expressions where cc is an i1 value:
7758 // (select cc 0, y) [AllOnes=0]
7759 // (select cc y, 0) [AllOnes=0]
7760 // (zext cc) [AllOnes=0]
7761 // (sext cc) [AllOnes=0/1]
7762 // (select cc -1, y) [AllOnes=1]
7763 // (select cc y, -1) [AllOnes=1]
7765 // Invert is set when N is the null/all ones constant when CC is false.
7766 // OtherOp is set to the alternative value of N.
7767 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
7768 SDValue &CC, bool &Invert,
7770 SelectionDAG &DAG) {
7771 switch (N->getOpcode()) {
7772 default: return false;
7774 CC = N->getOperand(0);
7775 SDValue N1 = N->getOperand(1);
7776 SDValue N2 = N->getOperand(2);
7777 if (isZeroOrAllOnes(N1, AllOnes)) {
7782 if (isZeroOrAllOnes(N2, AllOnes)) {
7789 case ISD::ZERO_EXTEND:
7790 // (zext cc) can never be the all ones value.
7794 case ISD::SIGN_EXTEND: {
7795 EVT VT = N->getValueType(0);
7796 CC = N->getOperand(0);
7797 if (CC.getValueType() != MVT::i1)
7801 // When looking for an AllOnes constant, N is an sext, and the 'other'
7803 OtherOp = DAG.getConstant(0, VT);
7804 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7805 // When looking for a 0 constant, N can be zext or sext.
7806 OtherOp = DAG.getConstant(1, VT);
7808 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
7814 // Combine a constant select operand into its use:
7816 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
7817 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
7818 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
7819 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
7820 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
7822 // The transform is rejected if the select doesn't have a constant operand that
7823 // is null, or all ones when AllOnes is set.
7825 // Also recognize sext/zext from i1:
7827 // (add (zext cc), x) -> (select cc (add x, 1), x)
7828 // (add (sext cc), x) -> (select cc (add x, -1), x)
7830 // These transformations eventually create predicated instructions.
7832 // @param N The node to transform.
7833 // @param Slct The N operand that is a select.
7834 // @param OtherOp The other N operand (x above).
7835 // @param DCI Context.
7836 // @param AllOnes Require the select constant to be all ones instead of null.
7837 // @returns The new node, or SDValue() on failure.
7839 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
7840 TargetLowering::DAGCombinerInfo &DCI,
7841 bool AllOnes = false) {
7842 SelectionDAG &DAG = DCI.DAG;
7843 EVT VT = N->getValueType(0);
7844 SDValue NonConstantVal;
7847 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
7848 NonConstantVal, DAG))
7851 // Slct is now know to be the desired identity constant when CC is true.
7852 SDValue TrueVal = OtherOp;
7853 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
7854 OtherOp, NonConstantVal);
7855 // Unless SwapSelectOps says CC should be false.
7857 std::swap(TrueVal, FalseVal);
7859 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
7860 CCOp, TrueVal, FalseVal);
7863 // Attempt combineSelectAndUse on each operand of a commutative operator N.
7865 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
7866 TargetLowering::DAGCombinerInfo &DCI) {
7867 SDValue N0 = N->getOperand(0);
7868 SDValue N1 = N->getOperand(1);
7869 if (N0.getNode()->hasOneUse()) {
7870 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
7871 if (Result.getNode())
7874 if (N1.getNode()->hasOneUse()) {
7875 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
7876 if (Result.getNode())
7882 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
7883 // (only after legalization).
7884 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
7885 TargetLowering::DAGCombinerInfo &DCI,
7886 const ARMSubtarget *Subtarget) {
7888 // Only perform optimization if after legalize, and if NEON is available. We
7889 // also expected both operands to be BUILD_VECTORs.
7890 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
7891 || N0.getOpcode() != ISD::BUILD_VECTOR
7892 || N1.getOpcode() != ISD::BUILD_VECTOR)
7895 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
7896 EVT VT = N->getValueType(0);
7897 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
7900 // Check that the vector operands are of the right form.
7901 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7902 // operands, where N is the size of the formed vector.
7903 // Each EXTRACT_VECTOR should have the same input vector and odd or even
7904 // index such that we have a pair wise add pattern.
7906 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
7907 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7909 SDValue Vec = N0->getOperand(0)->getOperand(0);
7910 SDNode *V = Vec.getNode();
7911 unsigned nextIndex = 0;
7913 // For each operands to the ADD which are BUILD_VECTORs,
7914 // check to see if each of their operands are an EXTRACT_VECTOR with
7915 // the same vector and appropriate index.
7916 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
7917 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7918 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7920 SDValue ExtVec0 = N0->getOperand(i);
7921 SDValue ExtVec1 = N1->getOperand(i);
7923 // First operand is the vector, verify its the same.
7924 if (V != ExtVec0->getOperand(0).getNode() ||
7925 V != ExtVec1->getOperand(0).getNode())
7928 // Second is the constant, verify its correct.
7929 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
7930 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
7932 // For the constant, we want to see all the even or all the odd.
7933 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
7934 || C1->getZExtValue() != nextIndex+1)
7943 // Create VPADDL node.
7944 SelectionDAG &DAG = DCI.DAG;
7945 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7947 // Build operand list.
7948 SmallVector<SDValue, 8> Ops;
7949 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
7950 TLI.getPointerTy()));
7952 // Input is the vector.
7955 // Get widened type and narrowed type.
7957 unsigned numElem = VT.getVectorNumElements();
7959 EVT inputLaneType = Vec.getValueType().getVectorElementType();
7960 switch (inputLaneType.getSimpleVT().SimpleTy) {
7961 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
7962 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
7963 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
7965 llvm_unreachable("Invalid vector element type for padd optimization.");
7968 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), widenType, Ops);
7969 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
7970 return DAG.getNode(ExtOp, SDLoc(N), VT, tmp);
7973 static SDValue findMUL_LOHI(SDValue V) {
7974 if (V->getOpcode() == ISD::UMUL_LOHI ||
7975 V->getOpcode() == ISD::SMUL_LOHI)
7980 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
7981 TargetLowering::DAGCombinerInfo &DCI,
7982 const ARMSubtarget *Subtarget) {
7984 if (Subtarget->isThumb1Only()) return SDValue();
7986 // Only perform the checks after legalize when the pattern is available.
7987 if (DCI.isBeforeLegalize()) return SDValue();
7989 // Look for multiply add opportunities.
7990 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
7991 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
7992 // a glue link from the first add to the second add.
7993 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
7994 // a S/UMLAL instruction.
7997 // \ / \ [no multiline comment]
8003 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
8004 SDValue AddcOp0 = AddcNode->getOperand(0);
8005 SDValue AddcOp1 = AddcNode->getOperand(1);
8007 // Check if the two operands are from the same mul_lohi node.
8008 if (AddcOp0.getNode() == AddcOp1.getNode())
8011 assert(AddcNode->getNumValues() == 2 &&
8012 AddcNode->getValueType(0) == MVT::i32 &&
8013 "Expect ADDC with two result values. First: i32");
8015 // Check that we have a glued ADDC node.
8016 if (AddcNode->getValueType(1) != MVT::Glue)
8019 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
8020 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
8021 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
8022 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
8023 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
8026 // Look for the glued ADDE.
8027 SDNode* AddeNode = AddcNode->getGluedUser();
8031 // Make sure it is really an ADDE.
8032 if (AddeNode->getOpcode() != ISD::ADDE)
8035 assert(AddeNode->getNumOperands() == 3 &&
8036 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
8037 "ADDE node has the wrong inputs");
8039 // Check for the triangle shape.
8040 SDValue AddeOp0 = AddeNode->getOperand(0);
8041 SDValue AddeOp1 = AddeNode->getOperand(1);
8043 // Make sure that the ADDE operands are not coming from the same node.
8044 if (AddeOp0.getNode() == AddeOp1.getNode())
8047 // Find the MUL_LOHI node walking up ADDE's operands.
8048 bool IsLeftOperandMUL = false;
8049 SDValue MULOp = findMUL_LOHI(AddeOp0);
8050 if (MULOp == SDValue())
8051 MULOp = findMUL_LOHI(AddeOp1);
8053 IsLeftOperandMUL = true;
8054 if (MULOp == SDValue())
8057 // Figure out the right opcode.
8058 unsigned Opc = MULOp->getOpcode();
8059 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
8061 // Figure out the high and low input values to the MLAL node.
8062 SDValue* HiMul = &MULOp;
8063 SDValue* HiAdd = nullptr;
8064 SDValue* LoMul = nullptr;
8065 SDValue* LowAdd = nullptr;
8067 if (IsLeftOperandMUL)
8073 if (AddcOp0->getOpcode() == Opc) {
8077 if (AddcOp1->getOpcode() == Opc) {
8085 if (LoMul->getNode() != HiMul->getNode())
8088 // Create the merged node.
8089 SelectionDAG &DAG = DCI.DAG;
8091 // Build operand list.
8092 SmallVector<SDValue, 8> Ops;
8093 Ops.push_back(LoMul->getOperand(0));
8094 Ops.push_back(LoMul->getOperand(1));
8095 Ops.push_back(*LowAdd);
8096 Ops.push_back(*HiAdd);
8098 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
8099 DAG.getVTList(MVT::i32, MVT::i32), Ops);
8101 // Replace the ADDs' nodes uses by the MLA node's values.
8102 SDValue HiMLALResult(MLALNode.getNode(), 1);
8103 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
8105 SDValue LoMLALResult(MLALNode.getNode(), 0);
8106 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
8108 // Return original node to notify the driver to stop replacing.
8109 SDValue resNode(AddcNode, 0);
8113 /// PerformADDCCombine - Target-specific dag combine transform from
8114 /// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
8115 static SDValue PerformADDCCombine(SDNode *N,
8116 TargetLowering::DAGCombinerInfo &DCI,
8117 const ARMSubtarget *Subtarget) {
8119 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
8123 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
8124 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8125 /// called with the default operands, and if that fails, with commuted
8127 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8128 TargetLowering::DAGCombinerInfo &DCI,
8129 const ARMSubtarget *Subtarget){
8131 // Attempt to create vpaddl for this add.
8132 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8133 if (Result.getNode())
8136 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8137 if (N0.getNode()->hasOneUse()) {
8138 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8139 if (Result.getNode()) return Result;
8144 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
8146 static SDValue PerformADDCombine(SDNode *N,
8147 TargetLowering::DAGCombinerInfo &DCI,
8148 const ARMSubtarget *Subtarget) {
8149 SDValue N0 = N->getOperand(0);
8150 SDValue N1 = N->getOperand(1);
8152 // First try with the default operand order.
8153 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8154 if (Result.getNode())
8157 // If that didn't work, try again with the operands commuted.
8158 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
8161 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
8163 static SDValue PerformSUBCombine(SDNode *N,
8164 TargetLowering::DAGCombinerInfo &DCI) {
8165 SDValue N0 = N->getOperand(0);
8166 SDValue N1 = N->getOperand(1);
8168 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8169 if (N1.getNode()->hasOneUse()) {
8170 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8171 if (Result.getNode()) return Result;
8177 /// PerformVMULCombine
8178 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
8179 /// special multiplier accumulator forwarding.
8185 // However, for (A + B) * (A + B),
8192 static SDValue PerformVMULCombine(SDNode *N,
8193 TargetLowering::DAGCombinerInfo &DCI,
8194 const ARMSubtarget *Subtarget) {
8195 if (!Subtarget->hasVMLxForwarding())
8198 SelectionDAG &DAG = DCI.DAG;
8199 SDValue N0 = N->getOperand(0);
8200 SDValue N1 = N->getOperand(1);
8201 unsigned Opcode = N0.getOpcode();
8202 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8203 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8204 Opcode = N1.getOpcode();
8205 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8206 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8214 EVT VT = N->getValueType(0);
8216 SDValue N00 = N0->getOperand(0);
8217 SDValue N01 = N0->getOperand(1);
8218 return DAG.getNode(Opcode, DL, VT,
8219 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
8220 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
8223 static SDValue PerformMULCombine(SDNode *N,
8224 TargetLowering::DAGCombinerInfo &DCI,
8225 const ARMSubtarget *Subtarget) {
8226 SelectionDAG &DAG = DCI.DAG;
8228 if (Subtarget->isThumb1Only())
8231 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8234 EVT VT = N->getValueType(0);
8235 if (VT.is64BitVector() || VT.is128BitVector())
8236 return PerformVMULCombine(N, DCI, Subtarget);
8240 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8244 int64_t MulAmt = C->getSExtValue();
8245 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
8247 ShiftAmt = ShiftAmt & (32 - 1);
8248 SDValue V = N->getOperand(0);
8252 MulAmt >>= ShiftAmt;
8255 if (isPowerOf2_32(MulAmt - 1)) {
8256 // (mul x, 2^N + 1) => (add (shl x, N), x)
8257 Res = DAG.getNode(ISD::ADD, DL, VT,
8259 DAG.getNode(ISD::SHL, DL, VT,
8261 DAG.getConstant(Log2_32(MulAmt - 1),
8263 } else if (isPowerOf2_32(MulAmt + 1)) {
8264 // (mul x, 2^N - 1) => (sub (shl x, N), x)
8265 Res = DAG.getNode(ISD::SUB, DL, VT,
8266 DAG.getNode(ISD::SHL, DL, VT,
8268 DAG.getConstant(Log2_32(MulAmt + 1),
8274 uint64_t MulAmtAbs = -MulAmt;
8275 if (isPowerOf2_32(MulAmtAbs + 1)) {
8276 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
8277 Res = DAG.getNode(ISD::SUB, DL, VT,
8279 DAG.getNode(ISD::SHL, DL, VT,
8281 DAG.getConstant(Log2_32(MulAmtAbs + 1),
8283 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
8284 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
8285 Res = DAG.getNode(ISD::ADD, DL, VT,
8287 DAG.getNode(ISD::SHL, DL, VT,
8289 DAG.getConstant(Log2_32(MulAmtAbs-1),
8291 Res = DAG.getNode(ISD::SUB, DL, VT,
8292 DAG.getConstant(0, MVT::i32),Res);
8299 Res = DAG.getNode(ISD::SHL, DL, VT,
8300 Res, DAG.getConstant(ShiftAmt, MVT::i32));
8302 // Do not add new nodes to DAG combiner worklist.
8303 DCI.CombineTo(N, Res, false);
8307 static SDValue PerformANDCombine(SDNode *N,
8308 TargetLowering::DAGCombinerInfo &DCI,
8309 const ARMSubtarget *Subtarget) {
8311 // Attempt to use immediate-form VBIC
8312 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8314 EVT VT = N->getValueType(0);
8315 SelectionDAG &DAG = DCI.DAG;
8317 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8320 APInt SplatBits, SplatUndef;
8321 unsigned SplatBitSize;
8324 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8325 if (SplatBitSize <= 64) {
8327 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
8328 SplatUndef.getZExtValue(), SplatBitSize,
8329 DAG, VbicVT, VT.is128BitVector(),
8331 if (Val.getNode()) {
8333 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
8334 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
8335 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
8340 if (!Subtarget->isThumb1Only()) {
8341 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
8342 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
8343 if (Result.getNode())
8350 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
8351 static SDValue PerformORCombine(SDNode *N,
8352 TargetLowering::DAGCombinerInfo &DCI,
8353 const ARMSubtarget *Subtarget) {
8354 // Attempt to use immediate-form VORR
8355 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8357 EVT VT = N->getValueType(0);
8358 SelectionDAG &DAG = DCI.DAG;
8360 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8363 APInt SplatBits, SplatUndef;
8364 unsigned SplatBitSize;
8366 if (BVN && Subtarget->hasNEON() &&
8367 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8368 if (SplatBitSize <= 64) {
8370 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
8371 SplatUndef.getZExtValue(), SplatBitSize,
8372 DAG, VorrVT, VT.is128BitVector(),
8374 if (Val.getNode()) {
8376 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
8377 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
8378 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
8383 if (!Subtarget->isThumb1Only()) {
8384 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8385 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8386 if (Result.getNode())
8390 // The code below optimizes (or (and X, Y), Z).
8391 // The AND operand needs to have a single user to make these optimizations
8393 SDValue N0 = N->getOperand(0);
8394 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8396 SDValue N1 = N->getOperand(1);
8398 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
8399 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8400 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
8402 unsigned SplatBitSize;
8405 APInt SplatBits0, SplatBits1;
8406 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8407 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8408 // Ensure that the second operand of both ands are constants
8409 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
8410 HasAnyUndefs) && !HasAnyUndefs) {
8411 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
8412 HasAnyUndefs) && !HasAnyUndefs) {
8413 // Ensure that the bit width of the constants are the same and that
8414 // the splat arguments are logical inverses as per the pattern we
8415 // are trying to simplify.
8416 if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
8417 SplatBits0 == ~SplatBits1) {
8418 // Canonicalize the vector type to make instruction selection
8420 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8421 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
8425 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
8431 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
8434 // BFI is only available on V6T2+
8435 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
8439 // 1) or (and A, mask), val => ARMbfi A, val, mask
8440 // iff (val & mask) == val
8442 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8443 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
8444 // && mask == ~mask2
8445 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
8446 // && ~mask == mask2
8447 // (i.e., copy a bitfield value into another bitfield of the same width)
8452 SDValue N00 = N0.getOperand(0);
8454 // The value and the mask need to be constants so we can verify this is
8455 // actually a bitfield set. If the mask is 0xffff, we can do better
8456 // via a movt instruction, so don't use BFI in that case.
8457 SDValue MaskOp = N0.getOperand(1);
8458 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
8461 unsigned Mask = MaskC->getZExtValue();
8465 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
8466 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8468 unsigned Val = N1C->getZExtValue();
8469 if ((Val & ~Mask) != Val)
8472 if (ARM::isBitFieldInvertedMask(Mask)) {
8473 Val >>= countTrailingZeros(~Mask);
8475 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
8476 DAG.getConstant(Val, MVT::i32),
8477 DAG.getConstant(Mask, MVT::i32));
8479 // Do not add new nodes to DAG combiner worklist.
8480 DCI.CombineTo(N, Res, false);
8483 } else if (N1.getOpcode() == ISD::AND) {
8484 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8485 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8488 unsigned Mask2 = N11C->getZExtValue();
8490 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8492 if (ARM::isBitFieldInvertedMask(Mask) &&
8494 // The pack halfword instruction works better for masks that fit it,
8495 // so use that when it's available.
8496 if (Subtarget->hasT2ExtractPack() &&
8497 (Mask == 0xffff || Mask == 0xffff0000))
8500 unsigned amt = countTrailingZeros(Mask2);
8501 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
8502 DAG.getConstant(amt, MVT::i32));
8503 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
8504 DAG.getConstant(Mask, MVT::i32));
8505 // Do not add new nodes to DAG combiner worklist.
8506 DCI.CombineTo(N, Res, false);
8508 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
8510 // The pack halfword instruction works better for masks that fit it,
8511 // so use that when it's available.
8512 if (Subtarget->hasT2ExtractPack() &&
8513 (Mask2 == 0xffff || Mask2 == 0xffff0000))
8516 unsigned lsb = countTrailingZeros(Mask);
8517 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
8518 DAG.getConstant(lsb, MVT::i32));
8519 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
8520 DAG.getConstant(Mask2, MVT::i32));
8521 // Do not add new nodes to DAG combiner worklist.
8522 DCI.CombineTo(N, Res, false);
8527 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8528 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8529 ARM::isBitFieldInvertedMask(~Mask)) {
8530 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
8531 // where lsb(mask) == #shamt and masked bits of B are known zero.
8532 SDValue ShAmt = N00.getOperand(1);
8533 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
8534 unsigned LSB = countTrailingZeros(Mask);
8538 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8539 DAG.getConstant(~Mask, MVT::i32));
8541 // Do not add new nodes to DAG combiner worklist.
8542 DCI.CombineTo(N, Res, false);
8548 static SDValue PerformXORCombine(SDNode *N,
8549 TargetLowering::DAGCombinerInfo &DCI,
8550 const ARMSubtarget *Subtarget) {
8551 EVT VT = N->getValueType(0);
8552 SelectionDAG &DAG = DCI.DAG;
8554 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8557 if (!Subtarget->isThumb1Only()) {
8558 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8559 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8560 if (Result.getNode())
8567 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
8568 /// the bits being cleared by the AND are not demanded by the BFI.
8569 static SDValue PerformBFICombine(SDNode *N,
8570 TargetLowering::DAGCombinerInfo &DCI) {
8571 SDValue N1 = N->getOperand(1);
8572 if (N1.getOpcode() == ISD::AND) {
8573 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8576 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
8577 unsigned LSB = countTrailingZeros(~InvMask);
8578 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
8579 unsigned Mask = (1 << Width)-1;
8580 unsigned Mask2 = N11C->getZExtValue();
8581 if ((Mask & (~Mask2)) == 0)
8582 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
8583 N->getOperand(0), N1.getOperand(0),
8589 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
8590 /// ARMISD::VMOVRRD.
8591 static SDValue PerformVMOVRRDCombine(SDNode *N,
8592 TargetLowering::DAGCombinerInfo &DCI,
8593 const ARMSubtarget *Subtarget) {
8594 // vmovrrd(vmovdrr x, y) -> x,y
8595 SDValue InDouble = N->getOperand(0);
8596 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP())
8597 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
8599 // vmovrrd(load f64) -> (load i32), (load i32)
8600 SDNode *InNode = InDouble.getNode();
8601 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
8602 InNode->getValueType(0) == MVT::f64 &&
8603 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8604 !cast<LoadSDNode>(InNode)->isVolatile()) {
8605 // TODO: Should this be done for non-FrameIndex operands?
8606 LoadSDNode *LD = cast<LoadSDNode>(InNode);
8608 SelectionDAG &DAG = DCI.DAG;
8610 SDValue BasePtr = LD->getBasePtr();
8611 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8612 LD->getPointerInfo(), LD->isVolatile(),
8613 LD->isNonTemporal(), LD->isInvariant(),
8614 LD->getAlignment());
8616 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8617 DAG.getConstant(4, MVT::i32));
8618 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8619 LD->getPointerInfo(), LD->isVolatile(),
8620 LD->isNonTemporal(), LD->isInvariant(),
8621 std::min(4U, LD->getAlignment() / 2));
8623 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
8624 if (DCI.DAG.getTargetLoweringInfo().isBigEndian())
8625 std::swap (NewLD1, NewLD2);
8626 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
8633 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
8634 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
8635 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
8636 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
8637 SDValue Op0 = N->getOperand(0);
8638 SDValue Op1 = N->getOperand(1);
8639 if (Op0.getOpcode() == ISD::BITCAST)
8640 Op0 = Op0.getOperand(0);
8641 if (Op1.getOpcode() == ISD::BITCAST)
8642 Op1 = Op1.getOperand(0);
8643 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8644 Op0.getNode() == Op1.getNode() &&
8645 Op0.getResNo() == 0 && Op1.getResNo() == 1)
8646 return DAG.getNode(ISD::BITCAST, SDLoc(N),
8647 N->getValueType(0), Op0.getOperand(0));
8651 /// PerformSTORECombine - Target-specific dag combine xforms for
8653 static SDValue PerformSTORECombine(SDNode *N,
8654 TargetLowering::DAGCombinerInfo &DCI) {
8655 StoreSDNode *St = cast<StoreSDNode>(N);
8656 if (St->isVolatile())
8659 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
8660 // pack all of the elements in one place. Next, store to memory in fewer
8662 SDValue StVal = St->getValue();
8663 EVT VT = StVal.getValueType();
8664 if (St->isTruncatingStore() && VT.isVector()) {
8665 SelectionDAG &DAG = DCI.DAG;
8666 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8667 EVT StVT = St->getMemoryVT();
8668 unsigned NumElems = VT.getVectorNumElements();
8669 assert(StVT != VT && "Cannot truncate to the same type");
8670 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
8671 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
8673 // From, To sizes and ElemCount must be pow of two
8674 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
8676 // We are going to use the original vector elt for storing.
8677 // Accumulated smaller vector elements must be a multiple of the store size.
8678 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
8680 unsigned SizeRatio = FromEltSz / ToEltSz;
8681 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
8683 // Create a type on which we perform the shuffle.
8684 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
8685 NumElems*SizeRatio);
8686 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
8689 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
8690 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
8691 for (unsigned i = 0; i < NumElems; ++i)
8692 ShuffleVec[i] = TLI.isBigEndian() ? (i+1) * SizeRatio - 1 : i * SizeRatio;
8694 // Can't shuffle using an illegal type.
8695 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
8697 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
8698 DAG.getUNDEF(WideVec.getValueType()),
8700 // At this point all of the data is stored at the bottom of the
8701 // register. We now need to save it to mem.
8703 // Find the largest store unit
8704 MVT StoreType = MVT::i8;
8705 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
8706 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
8707 MVT Tp = (MVT::SimpleValueType)tp;
8708 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
8711 // Didn't find a legal store type.
8712 if (!TLI.isTypeLegal(StoreType))
8715 // Bitcast the original vector into a vector of store-size units
8716 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
8717 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
8718 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
8719 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
8720 SmallVector<SDValue, 8> Chains;
8721 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
8722 TLI.getPointerTy());
8723 SDValue BasePtr = St->getBasePtr();
8725 // Perform one or more big stores into memory.
8726 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
8727 for (unsigned I = 0; I < E; I++) {
8728 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
8729 StoreType, ShuffWide,
8730 DAG.getIntPtrConstant(I));
8731 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
8732 St->getPointerInfo(), St->isVolatile(),
8733 St->isNonTemporal(), St->getAlignment());
8734 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
8736 Chains.push_back(Ch);
8738 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
8741 if (!ISD::isNormalStore(St))
8744 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
8745 // ARM stores of arguments in the same cache line.
8746 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
8747 StVal.getNode()->hasOneUse()) {
8748 SelectionDAG &DAG = DCI.DAG;
8749 bool isBigEndian = DAG.getTargetLoweringInfo().isBigEndian();
8751 SDValue BasePtr = St->getBasePtr();
8752 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
8753 StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ),
8754 BasePtr, St->getPointerInfo(), St->isVolatile(),
8755 St->isNonTemporal(), St->getAlignment());
8757 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8758 DAG.getConstant(4, MVT::i32));
8759 return DAG.getStore(NewST1.getValue(0), DL,
8760 StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
8761 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
8762 St->isNonTemporal(),
8763 std::min(4U, St->getAlignment() / 2));
8766 if (StVal.getValueType() != MVT::i64 ||
8767 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8770 // Bitcast an i64 store extracted from a vector to f64.
8771 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8772 SelectionDAG &DAG = DCI.DAG;
8774 SDValue IntVec = StVal.getOperand(0);
8775 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8776 IntVec.getValueType().getVectorNumElements());
8777 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
8778 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8779 Vec, StVal.getOperand(1));
8781 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
8782 // Make the DAGCombiner fold the bitcasts.
8783 DCI.AddToWorklist(Vec.getNode());
8784 DCI.AddToWorklist(ExtElt.getNode());
8785 DCI.AddToWorklist(V.getNode());
8786 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
8787 St->getPointerInfo(), St->isVolatile(),
8788 St->isNonTemporal(), St->getAlignment(),
8792 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
8793 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
8794 /// i64 vector to have f64 elements, since the value can then be loaded
8795 /// directly into a VFP register.
8796 static bool hasNormalLoadOperand(SDNode *N) {
8797 unsigned NumElts = N->getValueType(0).getVectorNumElements();
8798 for (unsigned i = 0; i < NumElts; ++i) {
8799 SDNode *Elt = N->getOperand(i).getNode();
8800 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
8806 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
8807 /// ISD::BUILD_VECTOR.
8808 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
8809 TargetLowering::DAGCombinerInfo &DCI,
8810 const ARMSubtarget *Subtarget) {
8811 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
8812 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
8813 // into a pair of GPRs, which is fine when the value is used as a scalar,
8814 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
8815 SelectionDAG &DAG = DCI.DAG;
8816 if (N->getNumOperands() == 2) {
8817 SDValue RV = PerformVMOVDRRCombine(N, DAG);
8822 // Load i64 elements as f64 values so that type legalization does not split
8823 // them up into i32 values.
8824 EVT VT = N->getValueType(0);
8825 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8828 SmallVector<SDValue, 8> Ops;
8829 unsigned NumElts = VT.getVectorNumElements();
8830 for (unsigned i = 0; i < NumElts; ++i) {
8831 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
8833 // Make the DAGCombiner fold the bitcast.
8834 DCI.AddToWorklist(V.getNode());
8836 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
8837 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops);
8838 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8841 /// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
8843 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8844 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
8845 // At that time, we may have inserted bitcasts from integer to float.
8846 // If these bitcasts have survived DAGCombine, change the lowering of this
8847 // BUILD_VECTOR in something more vector friendly, i.e., that does not
8848 // force to use floating point types.
8850 // Make sure we can change the type of the vector.
8851 // This is possible iff:
8852 // 1. The vector is only used in a bitcast to a integer type. I.e.,
8853 // 1.1. Vector is used only once.
8854 // 1.2. Use is a bit convert to an integer type.
8855 // 2. The size of its operands are 32-bits (64-bits are not legal).
8856 EVT VT = N->getValueType(0);
8857 EVT EltVT = VT.getVectorElementType();
8859 // Check 1.1. and 2.
8860 if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
8863 // By construction, the input type must be float.
8864 assert(EltVT == MVT::f32 && "Unexpected type!");
8867 SDNode *Use = *N->use_begin();
8868 if (Use->getOpcode() != ISD::BITCAST ||
8869 Use->getValueType(0).isFloatingPoint())
8872 // Check profitability.
8873 // Model is, if more than half of the relevant operands are bitcast from
8874 // i32, turn the build_vector into a sequence of insert_vector_elt.
8875 // Relevant operands are everything that is not statically
8876 // (i.e., at compile time) bitcasted.
8877 unsigned NumOfBitCastedElts = 0;
8878 unsigned NumElts = VT.getVectorNumElements();
8879 unsigned NumOfRelevantElts = NumElts;
8880 for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
8881 SDValue Elt = N->getOperand(Idx);
8882 if (Elt->getOpcode() == ISD::BITCAST) {
8883 // Assume only bit cast to i32 will go away.
8884 if (Elt->getOperand(0).getValueType() == MVT::i32)
8885 ++NumOfBitCastedElts;
8886 } else if (Elt.getOpcode() == ISD::UNDEF || isa<ConstantSDNode>(Elt))
8887 // Constants are statically casted, thus do not count them as
8888 // relevant operands.
8889 --NumOfRelevantElts;
8892 // Check if more than half of the elements require a non-free bitcast.
8893 if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
8896 SelectionDAG &DAG = DCI.DAG;
8897 // Create the new vector type.
8898 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
8899 // Check if the type is legal.
8900 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8901 if (!TLI.isTypeLegal(VecVT))
8905 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
8906 // => BITCAST INSERT_VECTOR_ELT
8907 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
8909 SDValue Vec = DAG.getUNDEF(VecVT);
8911 for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
8912 SDValue V = N->getOperand(Idx);
8913 if (V.getOpcode() == ISD::UNDEF)
8915 if (V.getOpcode() == ISD::BITCAST &&
8916 V->getOperand(0).getValueType() == MVT::i32)
8917 // Fold obvious case.
8918 V = V.getOperand(0);
8920 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
8921 // Make the DAGCombiner fold the bitcasts.
8922 DCI.AddToWorklist(V.getNode());
8924 SDValue LaneIdx = DAG.getConstant(Idx, MVT::i32);
8925 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
8927 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
8928 // Make the DAGCombiner fold the bitcasts.
8929 DCI.AddToWorklist(Vec.getNode());
8933 /// PerformInsertEltCombine - Target-specific dag combine xforms for
8934 /// ISD::INSERT_VECTOR_ELT.
8935 static SDValue PerformInsertEltCombine(SDNode *N,
8936 TargetLowering::DAGCombinerInfo &DCI) {
8937 // Bitcast an i64 load inserted into a vector to f64.
8938 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8939 EVT VT = N->getValueType(0);
8940 SDNode *Elt = N->getOperand(1).getNode();
8941 if (VT.getVectorElementType() != MVT::i64 ||
8942 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
8945 SelectionDAG &DAG = DCI.DAG;
8947 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8948 VT.getVectorNumElements());
8949 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
8950 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
8951 // Make the DAGCombiner fold the bitcasts.
8952 DCI.AddToWorklist(Vec.getNode());
8953 DCI.AddToWorklist(V.getNode());
8954 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
8955 Vec, V, N->getOperand(2));
8956 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
8959 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
8960 /// ISD::VECTOR_SHUFFLE.
8961 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
8962 // The LLVM shufflevector instruction does not require the shuffle mask
8963 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
8964 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
8965 // operands do not match the mask length, they are extended by concatenating
8966 // them with undef vectors. That is probably the right thing for other
8967 // targets, but for NEON it is better to concatenate two double-register
8968 // size vector operands into a single quad-register size vector. Do that
8969 // transformation here:
8970 // shuffle(concat(v1, undef), concat(v2, undef)) ->
8971 // shuffle(concat(v1, v2), undef)
8972 SDValue Op0 = N->getOperand(0);
8973 SDValue Op1 = N->getOperand(1);
8974 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
8975 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
8976 Op0.getNumOperands() != 2 ||
8977 Op1.getNumOperands() != 2)
8979 SDValue Concat0Op1 = Op0.getOperand(1);
8980 SDValue Concat1Op1 = Op1.getOperand(1);
8981 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
8982 Concat1Op1.getOpcode() != ISD::UNDEF)
8984 // Skip the transformation if any of the types are illegal.
8985 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8986 EVT VT = N->getValueType(0);
8987 if (!TLI.isTypeLegal(VT) ||
8988 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
8989 !TLI.isTypeLegal(Concat1Op1.getValueType()))
8992 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
8993 Op0.getOperand(0), Op1.getOperand(0));
8994 // Translate the shuffle mask.
8995 SmallVector<int, 16> NewMask;
8996 unsigned NumElts = VT.getVectorNumElements();
8997 unsigned HalfElts = NumElts/2;
8998 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8999 for (unsigned n = 0; n < NumElts; ++n) {
9000 int MaskElt = SVN->getMaskElt(n);
9002 if (MaskElt < (int)HalfElts)
9004 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
9005 NewElt = HalfElts + MaskElt - NumElts;
9006 NewMask.push_back(NewElt);
9008 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
9009 DAG.getUNDEF(VT), NewMask.data());
9012 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
9013 /// NEON load/store intrinsics to merge base address updates.
9014 static SDValue CombineBaseUpdate(SDNode *N,
9015 TargetLowering::DAGCombinerInfo &DCI) {
9016 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9019 SelectionDAG &DAG = DCI.DAG;
9020 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
9021 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
9022 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
9023 SDValue Addr = N->getOperand(AddrOpIdx);
9025 // Search for a use of the address operand that is an increment.
9026 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
9027 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
9029 if (User->getOpcode() != ISD::ADD ||
9030 UI.getUse().getResNo() != Addr.getResNo())
9033 // Check that the add is independent of the load/store. Otherwise, folding
9034 // it would create a cycle.
9035 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
9038 // Find the new opcode for the updating load/store.
9040 bool isLaneOp = false;
9041 unsigned NewOpc = 0;
9042 unsigned NumVecs = 0;
9044 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
9046 default: llvm_unreachable("unexpected intrinsic for Neon base update");
9047 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
9049 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
9051 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
9053 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
9055 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
9056 NumVecs = 2; isLaneOp = true; break;
9057 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
9058 NumVecs = 3; isLaneOp = true; break;
9059 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
9060 NumVecs = 4; isLaneOp = true; break;
9061 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
9062 NumVecs = 1; isLoad = false; break;
9063 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
9064 NumVecs = 2; isLoad = false; break;
9065 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
9066 NumVecs = 3; isLoad = false; break;
9067 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
9068 NumVecs = 4; isLoad = false; break;
9069 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
9070 NumVecs = 2; isLoad = false; isLaneOp = true; break;
9071 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
9072 NumVecs = 3; isLoad = false; isLaneOp = true; break;
9073 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
9074 NumVecs = 4; isLoad = false; isLaneOp = true; break;
9078 switch (N->getOpcode()) {
9079 default: llvm_unreachable("unexpected opcode for Neon base update");
9080 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
9081 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
9082 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
9086 // Find the size of memory referenced by the load/store.
9089 VecTy = N->getValueType(0);
9091 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
9092 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
9094 NumBytes /= VecTy.getVectorNumElements();
9096 // If the increment is a constant, it must match the memory ref size.
9097 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
9098 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
9099 uint64_t IncVal = CInc->getZExtValue();
9100 if (IncVal != NumBytes)
9102 } else if (NumBytes >= 3 * 16) {
9103 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
9104 // separate instructions that make it harder to use a non-constant update.
9108 // Create the new updating load/store node.
9110 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
9112 for (n = 0; n < NumResultVecs; ++n)
9114 Tys[n++] = MVT::i32;
9115 Tys[n] = MVT::Other;
9116 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2));
9117 SmallVector<SDValue, 8> Ops;
9118 Ops.push_back(N->getOperand(0)); // incoming chain
9119 Ops.push_back(N->getOperand(AddrOpIdx));
9121 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
9122 Ops.push_back(N->getOperand(i));
9124 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
9125 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
9126 Ops, MemInt->getMemoryVT(),
9127 MemInt->getMemOperand());
9130 std::vector<SDValue> NewResults;
9131 for (unsigned i = 0; i < NumResultVecs; ++i) {
9132 NewResults.push_back(SDValue(UpdN.getNode(), i));
9134 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
9135 DCI.CombineTo(N, NewResults);
9136 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
9143 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
9144 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
9145 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
9147 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9148 SelectionDAG &DAG = DCI.DAG;
9149 EVT VT = N->getValueType(0);
9150 // vldN-dup instructions only support 64-bit vectors for N > 1.
9151 if (!VT.is64BitVector())
9154 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
9155 SDNode *VLD = N->getOperand(0).getNode();
9156 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
9158 unsigned NumVecs = 0;
9159 unsigned NewOpc = 0;
9160 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
9161 if (IntNo == Intrinsic::arm_neon_vld2lane) {
9163 NewOpc = ARMISD::VLD2DUP;
9164 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
9166 NewOpc = ARMISD::VLD3DUP;
9167 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
9169 NewOpc = ARMISD::VLD4DUP;
9174 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
9175 // numbers match the load.
9176 unsigned VLDLaneNo =
9177 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
9178 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9180 // Ignore uses of the chain result.
9181 if (UI.getUse().getResNo() == NumVecs)
9184 if (User->getOpcode() != ARMISD::VDUPLANE ||
9185 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
9189 // Create the vldN-dup node.
9192 for (n = 0; n < NumVecs; ++n)
9194 Tys[n] = MVT::Other;
9195 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumVecs+1));
9196 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
9197 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
9198 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
9199 Ops, VLDMemInt->getMemoryVT(),
9200 VLDMemInt->getMemOperand());
9203 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9205 unsigned ResNo = UI.getUse().getResNo();
9206 // Ignore uses of the chain result.
9207 if (ResNo == NumVecs)
9210 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
9213 // Now the vldN-lane intrinsic is dead except for its chain result.
9214 // Update uses of the chain.
9215 std::vector<SDValue> VLDDupResults;
9216 for (unsigned n = 0; n < NumVecs; ++n)
9217 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
9218 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
9219 DCI.CombineTo(VLD, VLDDupResults);
9224 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
9225 /// ARMISD::VDUPLANE.
9226 static SDValue PerformVDUPLANECombine(SDNode *N,
9227 TargetLowering::DAGCombinerInfo &DCI) {
9228 SDValue Op = N->getOperand(0);
9230 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
9231 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
9232 if (CombineVLDDUP(N, DCI))
9233 return SDValue(N, 0);
9235 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
9236 // redundant. Ignore bit_converts for now; element sizes are checked below.
9237 while (Op.getOpcode() == ISD::BITCAST)
9238 Op = Op.getOperand(0);
9239 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
9242 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
9243 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
9244 // The canonical VMOV for a zero vector uses a 32-bit element size.
9245 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9247 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
9249 EVT VT = N->getValueType(0);
9250 if (EltSize > VT.getVectorElementType().getSizeInBits())
9253 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
9256 // isConstVecPow2 - Return true if each vector element is a power of 2, all
9257 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
9258 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
9262 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
9264 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
9269 APFloat APF = C->getValueAPF();
9270 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
9271 != APFloat::opOK || !isExact)
9274 c0 = (I == 0) ? cN : c0;
9275 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
9282 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
9283 /// can replace combinations of VMUL and VCVT (floating-point to integer)
9284 /// when the VMUL has a constant operand that is a power of 2.
9286 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9287 /// vmul.f32 d16, d17, d16
9288 /// vcvt.s32.f32 d16, d16
9290 /// vcvt.s32.f32 d16, d16, #3
9291 static SDValue PerformVCVTCombine(SDNode *N,
9292 TargetLowering::DAGCombinerInfo &DCI,
9293 const ARMSubtarget *Subtarget) {
9294 SelectionDAG &DAG = DCI.DAG;
9295 SDValue Op = N->getOperand(0);
9297 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
9298 Op.getOpcode() != ISD::FMUL)
9302 SDValue N0 = Op->getOperand(0);
9303 SDValue ConstVec = Op->getOperand(1);
9304 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
9306 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9307 !isConstVecPow2(ConstVec, isSigned, C))
9310 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
9311 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
9312 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9313 // These instructions only exist converting from f32 to i32. We can handle
9314 // smaller integers by generating an extra truncate, but larger ones would
9319 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
9320 Intrinsic::arm_neon_vcvtfp2fxu;
9321 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9322 SDValue FixConv = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
9323 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9324 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
9325 DAG.getConstant(Log2_64(C), MVT::i32));
9327 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9328 FixConv = DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), FixConv);
9333 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
9334 /// can replace combinations of VCVT (integer to floating-point) and VDIV
9335 /// when the VDIV has a constant operand that is a power of 2.
9337 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9338 /// vcvt.f32.s32 d16, d16
9339 /// vdiv.f32 d16, d17, d16
9341 /// vcvt.f32.s32 d16, d16, #3
9342 static SDValue PerformVDIVCombine(SDNode *N,
9343 TargetLowering::DAGCombinerInfo &DCI,
9344 const ARMSubtarget *Subtarget) {
9345 SelectionDAG &DAG = DCI.DAG;
9346 SDValue Op = N->getOperand(0);
9347 unsigned OpOpcode = Op.getNode()->getOpcode();
9349 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
9350 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
9354 SDValue ConstVec = N->getOperand(1);
9355 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
9357 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9358 !isConstVecPow2(ConstVec, isSigned, C))
9361 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
9362 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
9363 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9364 // These instructions only exist converting from i32 to f32. We can handle
9365 // smaller integers by generating an extra extend, but larger ones would
9370 SDValue ConvInput = Op.getOperand(0);
9371 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9372 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9373 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
9374 SDLoc(N), NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9377 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
9378 Intrinsic::arm_neon_vcvtfxu2fp;
9379 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
9381 DAG.getConstant(IntrinsicOpcode, MVT::i32),
9382 ConvInput, DAG.getConstant(Log2_64(C), MVT::i32));
9385 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
9386 /// operand of a vector shift operation, where all the elements of the
9387 /// build_vector must have the same constant integer value.
9388 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
9389 // Ignore bit_converts.
9390 while (Op.getOpcode() == ISD::BITCAST)
9391 Op = Op.getOperand(0);
9392 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
9393 APInt SplatBits, SplatUndef;
9394 unsigned SplatBitSize;
9396 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
9397 HasAnyUndefs, ElementBits) ||
9398 SplatBitSize > ElementBits)
9400 Cnt = SplatBits.getSExtValue();
9404 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
9405 /// operand of a vector shift left operation. That value must be in the range:
9406 /// 0 <= Value < ElementBits for a left shift; or
9407 /// 0 <= Value <= ElementBits for a long left shift.
9408 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
9409 assert(VT.isVector() && "vector shift count is not a vector type");
9410 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9411 if (! getVShiftImm(Op, ElementBits, Cnt))
9413 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
9416 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
9417 /// operand of a vector shift right operation. For a shift opcode, the value
9418 /// is positive, but for an intrinsic the value count must be negative. The
9419 /// absolute value must be in the range:
9420 /// 1 <= |Value| <= ElementBits for a right shift; or
9421 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
9422 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
9424 assert(VT.isVector() && "vector shift count is not a vector type");
9425 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9426 if (! getVShiftImm(Op, ElementBits, Cnt))
9430 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
9433 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
9434 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
9435 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
9438 // Don't do anything for most intrinsics.
9441 // Vector shifts: check for immediate versions and lower them.
9442 // Note: This is done during DAG combining instead of DAG legalizing because
9443 // the build_vectors for 64-bit vector element shift counts are generally
9444 // not legal, and it is hard to see their values after they get legalized to
9445 // loads from a constant pool.
9446 case Intrinsic::arm_neon_vshifts:
9447 case Intrinsic::arm_neon_vshiftu:
9448 case Intrinsic::arm_neon_vrshifts:
9449 case Intrinsic::arm_neon_vrshiftu:
9450 case Intrinsic::arm_neon_vrshiftn:
9451 case Intrinsic::arm_neon_vqshifts:
9452 case Intrinsic::arm_neon_vqshiftu:
9453 case Intrinsic::arm_neon_vqshiftsu:
9454 case Intrinsic::arm_neon_vqshiftns:
9455 case Intrinsic::arm_neon_vqshiftnu:
9456 case Intrinsic::arm_neon_vqshiftnsu:
9457 case Intrinsic::arm_neon_vqrshiftns:
9458 case Intrinsic::arm_neon_vqrshiftnu:
9459 case Intrinsic::arm_neon_vqrshiftnsu: {
9460 EVT VT = N->getOperand(1).getValueType();
9462 unsigned VShiftOpc = 0;
9465 case Intrinsic::arm_neon_vshifts:
9466 case Intrinsic::arm_neon_vshiftu:
9467 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
9468 VShiftOpc = ARMISD::VSHL;
9471 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
9472 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
9473 ARMISD::VSHRs : ARMISD::VSHRu);
9478 case Intrinsic::arm_neon_vrshifts:
9479 case Intrinsic::arm_neon_vrshiftu:
9480 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
9484 case Intrinsic::arm_neon_vqshifts:
9485 case Intrinsic::arm_neon_vqshiftu:
9486 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9490 case Intrinsic::arm_neon_vqshiftsu:
9491 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9493 llvm_unreachable("invalid shift count for vqshlu intrinsic");
9495 case Intrinsic::arm_neon_vrshiftn:
9496 case Intrinsic::arm_neon_vqshiftns:
9497 case Intrinsic::arm_neon_vqshiftnu:
9498 case Intrinsic::arm_neon_vqshiftnsu:
9499 case Intrinsic::arm_neon_vqrshiftns:
9500 case Intrinsic::arm_neon_vqrshiftnu:
9501 case Intrinsic::arm_neon_vqrshiftnsu:
9502 // Narrowing shifts require an immediate right shift.
9503 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
9505 llvm_unreachable("invalid shift count for narrowing vector shift "
9509 llvm_unreachable("unhandled vector shift");
9513 case Intrinsic::arm_neon_vshifts:
9514 case Intrinsic::arm_neon_vshiftu:
9515 // Opcode already set above.
9517 case Intrinsic::arm_neon_vrshifts:
9518 VShiftOpc = ARMISD::VRSHRs; break;
9519 case Intrinsic::arm_neon_vrshiftu:
9520 VShiftOpc = ARMISD::VRSHRu; break;
9521 case Intrinsic::arm_neon_vrshiftn:
9522 VShiftOpc = ARMISD::VRSHRN; break;
9523 case Intrinsic::arm_neon_vqshifts:
9524 VShiftOpc = ARMISD::VQSHLs; break;
9525 case Intrinsic::arm_neon_vqshiftu:
9526 VShiftOpc = ARMISD::VQSHLu; break;
9527 case Intrinsic::arm_neon_vqshiftsu:
9528 VShiftOpc = ARMISD::VQSHLsu; break;
9529 case Intrinsic::arm_neon_vqshiftns:
9530 VShiftOpc = ARMISD::VQSHRNs; break;
9531 case Intrinsic::arm_neon_vqshiftnu:
9532 VShiftOpc = ARMISD::VQSHRNu; break;
9533 case Intrinsic::arm_neon_vqshiftnsu:
9534 VShiftOpc = ARMISD::VQSHRNsu; break;
9535 case Intrinsic::arm_neon_vqrshiftns:
9536 VShiftOpc = ARMISD::VQRSHRNs; break;
9537 case Intrinsic::arm_neon_vqrshiftnu:
9538 VShiftOpc = ARMISD::VQRSHRNu; break;
9539 case Intrinsic::arm_neon_vqrshiftnsu:
9540 VShiftOpc = ARMISD::VQRSHRNsu; break;
9543 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9544 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
9547 case Intrinsic::arm_neon_vshiftins: {
9548 EVT VT = N->getOperand(1).getValueType();
9550 unsigned VShiftOpc = 0;
9552 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
9553 VShiftOpc = ARMISD::VSLI;
9554 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
9555 VShiftOpc = ARMISD::VSRI;
9557 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
9560 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9561 N->getOperand(1), N->getOperand(2),
9562 DAG.getConstant(Cnt, MVT::i32));
9565 case Intrinsic::arm_neon_vqrshifts:
9566 case Intrinsic::arm_neon_vqrshiftu:
9567 // No immediate versions of these to check for.
9574 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
9575 /// lowers them. As with the vector shift intrinsics, this is done during DAG
9576 /// combining instead of DAG legalizing because the build_vectors for 64-bit
9577 /// vector element shift counts are generally not legal, and it is hard to see
9578 /// their values after they get legalized to loads from a constant pool.
9579 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
9580 const ARMSubtarget *ST) {
9581 EVT VT = N->getValueType(0);
9582 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9583 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
9584 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
9585 SDValue N1 = N->getOperand(1);
9586 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
9587 SDValue N0 = N->getOperand(0);
9588 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9589 DAG.MaskedValueIsZero(N0.getOperand(0),
9590 APInt::getHighBitsSet(32, 16)))
9591 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
9595 // Nothing to be done for scalar shifts.
9596 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9597 if (!VT.isVector() || !TLI.isTypeLegal(VT))
9600 assert(ST->hasNEON() && "unexpected vector shift");
9603 switch (N->getOpcode()) {
9604 default: llvm_unreachable("unexpected shift opcode");
9607 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
9608 return DAG.getNode(ARMISD::VSHL, SDLoc(N), VT, N->getOperand(0),
9609 DAG.getConstant(Cnt, MVT::i32));
9614 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
9615 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
9616 ARMISD::VSHRs : ARMISD::VSHRu);
9617 return DAG.getNode(VShiftOpc, SDLoc(N), VT, N->getOperand(0),
9618 DAG.getConstant(Cnt, MVT::i32));
9624 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
9625 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
9626 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
9627 const ARMSubtarget *ST) {
9628 SDValue N0 = N->getOperand(0);
9630 // Check for sign- and zero-extensions of vector extract operations of 8-
9631 // and 16-bit vector elements. NEON supports these directly. They are
9632 // handled during DAG combining because type legalization will promote them
9633 // to 32-bit types and it is messy to recognize the operations after that.
9634 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9635 SDValue Vec = N0.getOperand(0);
9636 SDValue Lane = N0.getOperand(1);
9637 EVT VT = N->getValueType(0);
9638 EVT EltVT = N0.getValueType();
9639 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9641 if (VT == MVT::i32 &&
9642 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
9643 TLI.isTypeLegal(Vec.getValueType()) &&
9644 isa<ConstantSDNode>(Lane)) {
9647 switch (N->getOpcode()) {
9648 default: llvm_unreachable("unexpected opcode");
9649 case ISD::SIGN_EXTEND:
9650 Opc = ARMISD::VGETLANEs;
9652 case ISD::ZERO_EXTEND:
9653 case ISD::ANY_EXTEND:
9654 Opc = ARMISD::VGETLANEu;
9657 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
9664 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
9665 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
9666 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
9667 const ARMSubtarget *ST) {
9668 // If the target supports NEON, try to use vmax/vmin instructions for f32
9669 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
9670 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
9671 // a NaN; only do the transformation when it matches that behavior.
9673 // For now only do this when using NEON for FP operations; if using VFP, it
9674 // is not obvious that the benefit outweighs the cost of switching to the
9676 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
9677 N->getValueType(0) != MVT::f32)
9680 SDValue CondLHS = N->getOperand(0);
9681 SDValue CondRHS = N->getOperand(1);
9682 SDValue LHS = N->getOperand(2);
9683 SDValue RHS = N->getOperand(3);
9684 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9686 unsigned Opcode = 0;
9688 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
9689 IsReversed = false; // x CC y ? x : y
9690 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
9691 IsReversed = true ; // x CC y ? y : x
9705 // If LHS is NaN, an ordered comparison will be false and the result will
9706 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
9707 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9708 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
9709 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9711 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
9712 // will return -0, so vmin can only be used for unsafe math or if one of
9713 // the operands is known to be nonzero.
9714 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
9715 !DAG.getTarget().Options.UnsafeFPMath &&
9716 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9718 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
9727 // If LHS is NaN, an ordered comparison will be false and the result will
9728 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
9729 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9730 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
9731 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9733 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
9734 // will return +0, so vmax can only be used for unsafe math or if one of
9735 // the operands is known to be nonzero.
9736 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
9737 !DAG.getTarget().Options.UnsafeFPMath &&
9738 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9740 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
9746 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
9749 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
9751 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
9752 SDValue Cmp = N->getOperand(4);
9753 if (Cmp.getOpcode() != ARMISD::CMPZ)
9754 // Only looking at EQ and NE cases.
9757 EVT VT = N->getValueType(0);
9759 SDValue LHS = Cmp.getOperand(0);
9760 SDValue RHS = Cmp.getOperand(1);
9761 SDValue FalseVal = N->getOperand(0);
9762 SDValue TrueVal = N->getOperand(1);
9763 SDValue ARMcc = N->getOperand(2);
9764 ARMCC::CondCodes CC =
9765 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
9783 /// FIXME: Turn this into a target neutral optimization?
9785 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
9786 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
9787 N->getOperand(3), Cmp);
9788 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
9790 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
9791 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
9792 N->getOperand(3), NewCmp);
9795 if (Res.getNode()) {
9796 APInt KnownZero, KnownOne;
9797 DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
9798 // Capture demanded bits information that would be otherwise lost.
9799 if (KnownZero == 0xfffffffe)
9800 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9801 DAG.getValueType(MVT::i1));
9802 else if (KnownZero == 0xffffff00)
9803 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9804 DAG.getValueType(MVT::i8));
9805 else if (KnownZero == 0xffff0000)
9806 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9807 DAG.getValueType(MVT::i16));
9813 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
9814 DAGCombinerInfo &DCI) const {
9815 switch (N->getOpcode()) {
9817 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
9818 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
9819 case ISD::SUB: return PerformSUBCombine(N, DCI);
9820 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
9821 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
9822 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
9823 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
9824 case ARMISD::BFI: return PerformBFICombine(N, DCI);
9825 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
9826 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
9827 case ISD::STORE: return PerformSTORECombine(N, DCI);
9828 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
9829 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
9830 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
9831 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
9832 case ISD::FP_TO_SINT:
9833 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
9834 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
9835 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
9838 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
9839 case ISD::SIGN_EXTEND:
9840 case ISD::ZERO_EXTEND:
9841 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
9842 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
9843 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
9844 case ARMISD::VLD2DUP:
9845 case ARMISD::VLD3DUP:
9846 case ARMISD::VLD4DUP:
9847 return CombineBaseUpdate(N, DCI);
9848 case ARMISD::BUILD_VECTOR:
9849 return PerformARMBUILD_VECTORCombine(N, DCI);
9850 case ISD::INTRINSIC_VOID:
9851 case ISD::INTRINSIC_W_CHAIN:
9852 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9853 case Intrinsic::arm_neon_vld1:
9854 case Intrinsic::arm_neon_vld2:
9855 case Intrinsic::arm_neon_vld3:
9856 case Intrinsic::arm_neon_vld4:
9857 case Intrinsic::arm_neon_vld2lane:
9858 case Intrinsic::arm_neon_vld3lane:
9859 case Intrinsic::arm_neon_vld4lane:
9860 case Intrinsic::arm_neon_vst1:
9861 case Intrinsic::arm_neon_vst2:
9862 case Intrinsic::arm_neon_vst3:
9863 case Intrinsic::arm_neon_vst4:
9864 case Intrinsic::arm_neon_vst2lane:
9865 case Intrinsic::arm_neon_vst3lane:
9866 case Intrinsic::arm_neon_vst4lane:
9867 return CombineBaseUpdate(N, DCI);
9875 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
9877 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
9880 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9884 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
9885 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
9887 switch (VT.getSimpleVT().SimpleTy) {
9893 // Unaligned access can use (for example) LRDB, LRDH, LDR
9894 if (AllowsUnaligned) {
9896 *Fast = Subtarget->hasV7Ops();
9903 // For any little-endian targets with neon, we can support unaligned ld/st
9904 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
9905 // A big-endian target may also explicitly support unaligned accesses
9906 if (Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian())) {
9916 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
9917 unsigned AlignCheck) {
9918 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
9919 (DstAlign == 0 || DstAlign % AlignCheck == 0));
9922 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
9923 unsigned DstAlign, unsigned SrcAlign,
9924 bool IsMemset, bool ZeroMemset,
9926 MachineFunction &MF) const {
9927 const Function *F = MF.getFunction();
9929 // See if we can use NEON instructions for this...
9930 if ((!IsMemset || ZeroMemset) &&
9931 Subtarget->hasNEON() &&
9932 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
9933 Attribute::NoImplicitFloat)) {
9936 (memOpAlign(SrcAlign, DstAlign, 16) ||
9937 (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) {
9939 } else if (Size >= 8 &&
9940 (memOpAlign(SrcAlign, DstAlign, 8) ||
9941 (allowsMisalignedMemoryAccesses(MVT::f64, 0, 1, &Fast) &&
9947 // Lowering to i32/i16 if the size permits.
9953 // Let the target-independent logic figure it out.
9957 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9958 if (Val.getOpcode() != ISD::LOAD)
9961 EVT VT1 = Val.getValueType();
9962 if (!VT1.isSimple() || !VT1.isInteger() ||
9963 !VT2.isSimple() || !VT2.isInteger())
9966 switch (VT1.getSimpleVT().SimpleTy) {
9971 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
9978 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
9979 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9982 if (!isTypeLegal(EVT::getEVT(Ty1)))
9985 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
9987 // Assuming the caller doesn't have a zeroext or signext return parameter,
9988 // truncation all the way down to i1 is valid.
9993 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
9998 switch (VT.getSimpleVT().SimpleTy) {
9999 default: return false;
10014 if ((V & (Scale - 1)) != 0)
10017 return V == (V & ((1LL << 5) - 1));
10020 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
10021 const ARMSubtarget *Subtarget) {
10022 bool isNeg = false;
10028 switch (VT.getSimpleVT().SimpleTy) {
10029 default: return false;
10034 // + imm12 or - imm8
10036 return V == (V & ((1LL << 8) - 1));
10037 return V == (V & ((1LL << 12) - 1));
10040 // Same as ARM mode. FIXME: NEON?
10041 if (!Subtarget->hasVFP2())
10046 return V == (V & ((1LL << 8) - 1));
10050 /// isLegalAddressImmediate - Return true if the integer value can be used
10051 /// as the offset of the target addressing mode for load / store of the
10053 static bool isLegalAddressImmediate(int64_t V, EVT VT,
10054 const ARMSubtarget *Subtarget) {
10058 if (!VT.isSimple())
10061 if (Subtarget->isThumb1Only())
10062 return isLegalT1AddressImmediate(V, VT);
10063 else if (Subtarget->isThumb2())
10064 return isLegalT2AddressImmediate(V, VT, Subtarget);
10069 switch (VT.getSimpleVT().SimpleTy) {
10070 default: return false;
10075 return V == (V & ((1LL << 12) - 1));
10078 return V == (V & ((1LL << 8) - 1));
10081 if (!Subtarget->hasVFP2()) // FIXME: NEON?
10086 return V == (V & ((1LL << 8) - 1));
10090 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
10092 int Scale = AM.Scale;
10096 switch (VT.getSimpleVT().SimpleTy) {
10097 default: return false;
10105 Scale = Scale & ~1;
10106 return Scale == 2 || Scale == 4 || Scale == 8;
10109 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10113 // Note, we allow "void" uses (basically, uses that aren't loads or
10114 // stores), because arm allows folding a scale into many arithmetic
10115 // operations. This should be made more precise and revisited later.
10117 // Allow r << imm, but the imm has to be a multiple of two.
10118 if (Scale & 1) return false;
10119 return isPowerOf2_32(Scale);
10123 /// isLegalAddressingMode - Return true if the addressing mode represented
10124 /// by AM is legal for this target, for a load/store of the specified type.
10125 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
10127 EVT VT = getValueType(Ty, true);
10128 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
10131 // Can never fold addr of global into load/store.
10135 switch (AM.Scale) {
10136 case 0: // no scale reg, must be "r+i" or "r", or "i".
10139 if (Subtarget->isThumb1Only())
10143 // ARM doesn't support any R+R*scale+imm addr modes.
10147 if (!VT.isSimple())
10150 if (Subtarget->isThumb2())
10151 return isLegalT2ScaledAddressingMode(AM, VT);
10153 int Scale = AM.Scale;
10154 switch (VT.getSimpleVT().SimpleTy) {
10155 default: return false;
10159 if (Scale < 0) Scale = -Scale;
10163 return isPowerOf2_32(Scale & ~1);
10167 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10172 // Note, we allow "void" uses (basically, uses that aren't loads or
10173 // stores), because arm allows folding a scale into many arithmetic
10174 // operations. This should be made more precise and revisited later.
10176 // Allow r << imm, but the imm has to be a multiple of two.
10177 if (Scale & 1) return false;
10178 return isPowerOf2_32(Scale);
10184 /// isLegalICmpImmediate - Return true if the specified immediate is legal
10185 /// icmp immediate, that is the target has icmp instructions which can compare
10186 /// a register against the immediate without having to materialize the
10187 /// immediate into a register.
10188 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
10189 // Thumb2 and ARM modes can use cmn for negative immediates.
10190 if (!Subtarget->isThumb())
10191 return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1;
10192 if (Subtarget->isThumb2())
10193 return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1;
10194 // Thumb1 doesn't have cmn, and only 8-bit immediates.
10195 return Imm >= 0 && Imm <= 255;
10198 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
10199 /// *or sub* immediate, that is the target has add or sub instructions which can
10200 /// add a register with the immediate without having to materialize the
10201 /// immediate into a register.
10202 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
10203 // Same encoding for add/sub, just flip the sign.
10204 int64_t AbsImm = llvm::abs64(Imm);
10205 if (!Subtarget->isThumb())
10206 return ARM_AM::getSOImmVal(AbsImm) != -1;
10207 if (Subtarget->isThumb2())
10208 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
10209 // Thumb1 only has 8-bit unsigned immediate.
10210 return AbsImm >= 0 && AbsImm <= 255;
10213 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
10214 bool isSEXTLoad, SDValue &Base,
10215 SDValue &Offset, bool &isInc,
10216 SelectionDAG &DAG) {
10217 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10220 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
10221 // AddressingMode 3
10222 Base = Ptr->getOperand(0);
10223 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10224 int RHSC = (int)RHS->getZExtValue();
10225 if (RHSC < 0 && RHSC > -256) {
10226 assert(Ptr->getOpcode() == ISD::ADD);
10228 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10232 isInc = (Ptr->getOpcode() == ISD::ADD);
10233 Offset = Ptr->getOperand(1);
10235 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
10236 // AddressingMode 2
10237 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10238 int RHSC = (int)RHS->getZExtValue();
10239 if (RHSC < 0 && RHSC > -0x1000) {
10240 assert(Ptr->getOpcode() == ISD::ADD);
10242 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10243 Base = Ptr->getOperand(0);
10248 if (Ptr->getOpcode() == ISD::ADD) {
10250 ARM_AM::ShiftOpc ShOpcVal=
10251 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
10252 if (ShOpcVal != ARM_AM::no_shift) {
10253 Base = Ptr->getOperand(1);
10254 Offset = Ptr->getOperand(0);
10256 Base = Ptr->getOperand(0);
10257 Offset = Ptr->getOperand(1);
10262 isInc = (Ptr->getOpcode() == ISD::ADD);
10263 Base = Ptr->getOperand(0);
10264 Offset = Ptr->getOperand(1);
10268 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
10272 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
10273 bool isSEXTLoad, SDValue &Base,
10274 SDValue &Offset, bool &isInc,
10275 SelectionDAG &DAG) {
10276 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10279 Base = Ptr->getOperand(0);
10280 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10281 int RHSC = (int)RHS->getZExtValue();
10282 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
10283 assert(Ptr->getOpcode() == ISD::ADD);
10285 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10287 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
10288 isInc = Ptr->getOpcode() == ISD::ADD;
10289 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
10297 /// getPreIndexedAddressParts - returns true by value, base pointer and
10298 /// offset pointer and addressing mode by reference if the node's address
10299 /// can be legally represented as pre-indexed load / store address.
10301 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
10303 ISD::MemIndexedMode &AM,
10304 SelectionDAG &DAG) const {
10305 if (Subtarget->isThumb1Only())
10310 bool isSEXTLoad = false;
10311 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10312 Ptr = LD->getBasePtr();
10313 VT = LD->getMemoryVT();
10314 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10315 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10316 Ptr = ST->getBasePtr();
10317 VT = ST->getMemoryVT();
10322 bool isLegal = false;
10323 if (Subtarget->isThumb2())
10324 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10325 Offset, isInc, DAG);
10327 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10328 Offset, isInc, DAG);
10332 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
10336 /// getPostIndexedAddressParts - returns true by value, base pointer and
10337 /// offset pointer and addressing mode by reference if this node can be
10338 /// combined with a load / store to form a post-indexed load / store.
10339 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
10342 ISD::MemIndexedMode &AM,
10343 SelectionDAG &DAG) const {
10344 if (Subtarget->isThumb1Only())
10349 bool isSEXTLoad = false;
10350 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10351 VT = LD->getMemoryVT();
10352 Ptr = LD->getBasePtr();
10353 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10354 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10355 VT = ST->getMemoryVT();
10356 Ptr = ST->getBasePtr();
10361 bool isLegal = false;
10362 if (Subtarget->isThumb2())
10363 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10366 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10372 // Swap base ptr and offset to catch more post-index load / store when
10373 // it's legal. In Thumb2 mode, offset must be an immediate.
10374 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
10375 !Subtarget->isThumb2())
10376 std::swap(Base, Offset);
10378 // Post-indexed load / store update the base pointer.
10383 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
10387 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10390 const SelectionDAG &DAG,
10391 unsigned Depth) const {
10392 unsigned BitWidth = KnownOne.getBitWidth();
10393 KnownZero = KnownOne = APInt(BitWidth, 0);
10394 switch (Op.getOpcode()) {
10400 // These nodes' second result is a boolean
10401 if (Op.getResNo() == 0)
10403 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
10405 case ARMISD::CMOV: {
10406 // Bits are known zero/one if known on the LHS and RHS.
10407 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
10408 if (KnownZero == 0 && KnownOne == 0) return;
10410 APInt KnownZeroRHS, KnownOneRHS;
10411 DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
10412 KnownZero &= KnownZeroRHS;
10413 KnownOne &= KnownOneRHS;
10416 case ISD::INTRINSIC_W_CHAIN: {
10417 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
10418 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
10421 case Intrinsic::arm_ldaex:
10422 case Intrinsic::arm_ldrex: {
10423 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
10424 unsigned MemBits = VT.getScalarType().getSizeInBits();
10425 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
10433 //===----------------------------------------------------------------------===//
10434 // ARM Inline Assembly Support
10435 //===----------------------------------------------------------------------===//
10437 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
10438 // Looking for "rev" which is V6+.
10439 if (!Subtarget->hasV6Ops())
10442 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10443 std::string AsmStr = IA->getAsmString();
10444 SmallVector<StringRef, 4> AsmPieces;
10445 SplitString(AsmStr, AsmPieces, ";\n");
10447 switch (AsmPieces.size()) {
10448 default: return false;
10450 AsmStr = AsmPieces[0];
10452 SplitString(AsmStr, AsmPieces, " \t,");
10455 if (AsmPieces.size() == 3 &&
10456 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
10457 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
10458 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10459 if (Ty && Ty->getBitWidth() == 32)
10460 return IntrinsicLowering::LowerToByteSwap(CI);
10468 /// getConstraintType - Given a constraint letter, return the type of
10469 /// constraint it is for this target.
10470 ARMTargetLowering::ConstraintType
10471 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
10472 if (Constraint.size() == 1) {
10473 switch (Constraint[0]) {
10475 case 'l': return C_RegisterClass;
10476 case 'w': return C_RegisterClass;
10477 case 'h': return C_RegisterClass;
10478 case 'x': return C_RegisterClass;
10479 case 't': return C_RegisterClass;
10480 case 'j': return C_Other; // Constant for movw.
10481 // An address with a single base register. Due to the way we
10482 // currently handle addresses it is the same as an 'r' memory constraint.
10483 case 'Q': return C_Memory;
10485 } else if (Constraint.size() == 2) {
10486 switch (Constraint[0]) {
10488 // All 'U+' constraints are addresses.
10489 case 'U': return C_Memory;
10492 return TargetLowering::getConstraintType(Constraint);
10495 /// Examine constraint type and operand type and determine a weight value.
10496 /// This object must already have been set up with the operand type
10497 /// and the current alternative constraint selected.
10498 TargetLowering::ConstraintWeight
10499 ARMTargetLowering::getSingleConstraintMatchWeight(
10500 AsmOperandInfo &info, const char *constraint) const {
10501 ConstraintWeight weight = CW_Invalid;
10502 Value *CallOperandVal = info.CallOperandVal;
10503 // If we don't have a value, we can't do a match,
10504 // but allow it at the lowest weight.
10505 if (!CallOperandVal)
10507 Type *type = CallOperandVal->getType();
10508 // Look at the constraint type.
10509 switch (*constraint) {
10511 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10514 if (type->isIntegerTy()) {
10515 if (Subtarget->isThumb())
10516 weight = CW_SpecificReg;
10518 weight = CW_Register;
10522 if (type->isFloatingPointTy())
10523 weight = CW_Register;
10529 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10531 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10533 if (Constraint.size() == 1) {
10534 // GCC ARM Constraint Letters
10535 switch (Constraint[0]) {
10536 case 'l': // Low regs or general regs.
10537 if (Subtarget->isThumb())
10538 return RCPair(0U, &ARM::tGPRRegClass);
10539 return RCPair(0U, &ARM::GPRRegClass);
10540 case 'h': // High regs or no regs.
10541 if (Subtarget->isThumb())
10542 return RCPair(0U, &ARM::hGPRRegClass);
10545 if (Subtarget->isThumb1Only())
10546 return RCPair(0U, &ARM::tGPRRegClass);
10547 return RCPair(0U, &ARM::GPRRegClass);
10549 if (VT == MVT::Other)
10551 if (VT == MVT::f32)
10552 return RCPair(0U, &ARM::SPRRegClass);
10553 if (VT.getSizeInBits() == 64)
10554 return RCPair(0U, &ARM::DPRRegClass);
10555 if (VT.getSizeInBits() == 128)
10556 return RCPair(0U, &ARM::QPRRegClass);
10559 if (VT == MVT::Other)
10561 if (VT == MVT::f32)
10562 return RCPair(0U, &ARM::SPR_8RegClass);
10563 if (VT.getSizeInBits() == 64)
10564 return RCPair(0U, &ARM::DPR_8RegClass);
10565 if (VT.getSizeInBits() == 128)
10566 return RCPair(0U, &ARM::QPR_8RegClass);
10569 if (VT == MVT::f32)
10570 return RCPair(0U, &ARM::SPRRegClass);
10574 if (StringRef("{cc}").equals_lower(Constraint))
10575 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
10577 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10580 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10581 /// vector. If it is invalid, don't add anything to Ops.
10582 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10583 std::string &Constraint,
10584 std::vector<SDValue>&Ops,
10585 SelectionDAG &DAG) const {
10588 // Currently only support length 1 constraints.
10589 if (Constraint.length() != 1) return;
10591 char ConstraintLetter = Constraint[0];
10592 switch (ConstraintLetter) {
10595 case 'I': case 'J': case 'K': case 'L':
10596 case 'M': case 'N': case 'O':
10597 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
10601 int64_t CVal64 = C->getSExtValue();
10602 int CVal = (int) CVal64;
10603 // None of these constraints allow values larger than 32 bits. Check
10604 // that the value fits in an int.
10605 if (CVal != CVal64)
10608 switch (ConstraintLetter) {
10610 // Constant suitable for movw, must be between 0 and
10612 if (Subtarget->hasV6T2Ops())
10613 if (CVal >= 0 && CVal <= 65535)
10617 if (Subtarget->isThumb1Only()) {
10618 // This must be a constant between 0 and 255, for ADD
10620 if (CVal >= 0 && CVal <= 255)
10622 } else if (Subtarget->isThumb2()) {
10623 // A constant that can be used as an immediate value in a
10624 // data-processing instruction.
10625 if (ARM_AM::getT2SOImmVal(CVal) != -1)
10628 // A constant that can be used as an immediate value in a
10629 // data-processing instruction.
10630 if (ARM_AM::getSOImmVal(CVal) != -1)
10636 if (Subtarget->isThumb()) { // FIXME thumb2
10637 // This must be a constant between -255 and -1, for negated ADD
10638 // immediates. This can be used in GCC with an "n" modifier that
10639 // prints the negated value, for use with SUB instructions. It is
10640 // not useful otherwise but is implemented for compatibility.
10641 if (CVal >= -255 && CVal <= -1)
10644 // This must be a constant between -4095 and 4095. It is not clear
10645 // what this constraint is intended for. Implemented for
10646 // compatibility with GCC.
10647 if (CVal >= -4095 && CVal <= 4095)
10653 if (Subtarget->isThumb1Only()) {
10654 // A 32-bit value where only one byte has a nonzero value. Exclude
10655 // zero to match GCC. This constraint is used by GCC internally for
10656 // constants that can be loaded with a move/shift combination.
10657 // It is not useful otherwise but is implemented for compatibility.
10658 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
10660 } else if (Subtarget->isThumb2()) {
10661 // A constant whose bitwise inverse can be used as an immediate
10662 // value in a data-processing instruction. This can be used in GCC
10663 // with a "B" modifier that prints the inverted value, for use with
10664 // BIC and MVN instructions. It is not useful otherwise but is
10665 // implemented for compatibility.
10666 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
10669 // A constant whose bitwise inverse can be used as an immediate
10670 // value in a data-processing instruction. This can be used in GCC
10671 // with a "B" modifier that prints the inverted value, for use with
10672 // BIC and MVN instructions. It is not useful otherwise but is
10673 // implemented for compatibility.
10674 if (ARM_AM::getSOImmVal(~CVal) != -1)
10680 if (Subtarget->isThumb1Only()) {
10681 // This must be a constant between -7 and 7,
10682 // for 3-operand ADD/SUB immediate instructions.
10683 if (CVal >= -7 && CVal < 7)
10685 } else if (Subtarget->isThumb2()) {
10686 // A constant whose negation can be used as an immediate value in a
10687 // data-processing instruction. This can be used in GCC with an "n"
10688 // modifier that prints the negated value, for use with SUB
10689 // instructions. It is not useful otherwise but is implemented for
10691 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
10694 // A constant whose negation can be used as an immediate value in a
10695 // data-processing instruction. This can be used in GCC with an "n"
10696 // modifier that prints the negated value, for use with SUB
10697 // instructions. It is not useful otherwise but is implemented for
10699 if (ARM_AM::getSOImmVal(-CVal) != -1)
10705 if (Subtarget->isThumb()) { // FIXME thumb2
10706 // This must be a multiple of 4 between 0 and 1020, for
10707 // ADD sp + immediate.
10708 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
10711 // A power of two or a constant between 0 and 32. This is used in
10712 // GCC for the shift amount on shifted register operands, but it is
10713 // useful in general for any shift amounts.
10714 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
10720 if (Subtarget->isThumb()) { // FIXME thumb2
10721 // This must be a constant between 0 and 31, for shift amounts.
10722 if (CVal >= 0 && CVal <= 31)
10728 if (Subtarget->isThumb()) { // FIXME thumb2
10729 // This must be a multiple of 4 between -508 and 508, for
10730 // ADD/SUB sp = sp + immediate.
10731 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
10736 Result = DAG.getTargetConstant(CVal, Op.getValueType());
10740 if (Result.getNode()) {
10741 Ops.push_back(Result);
10744 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10747 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
10748 assert(Subtarget->isTargetAEABI() && "Register-based DivRem lowering only");
10749 unsigned Opcode = Op->getOpcode();
10750 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
10751 "Invalid opcode for Div/Rem lowering");
10752 bool isSigned = (Opcode == ISD::SDIVREM);
10753 EVT VT = Op->getValueType(0);
10754 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
10757 switch (VT.getSimpleVT().SimpleTy) {
10758 default: llvm_unreachable("Unexpected request for libcall!");
10759 case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
10760 case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
10761 case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
10762 case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
10765 SDValue InChain = DAG.getEntryNode();
10767 TargetLowering::ArgListTy Args;
10768 TargetLowering::ArgListEntry Entry;
10769 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
10770 EVT ArgVT = Op->getOperand(i).getValueType();
10771 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10772 Entry.Node = Op->getOperand(i);
10774 Entry.isSExt = isSigned;
10775 Entry.isZExt = !isSigned;
10776 Args.push_back(Entry);
10779 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
10782 Type *RetTy = (Type*)StructType::get(Ty, Ty, nullptr);
10785 TargetLowering::CallLoweringInfo CLI(DAG);
10786 CLI.setDebugLoc(dl).setChain(InChain)
10787 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
10788 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
10790 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
10791 return CallInfo.first;
10795 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
10796 assert(Subtarget->isTargetWindows() && "unsupported target platform");
10800 SDValue Chain = Op.getOperand(0);
10801 SDValue Size = Op.getOperand(1);
10803 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,
10804 DAG.getConstant(2, MVT::i32));
10807 Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
10808 Flag = Chain.getValue(1);
10810 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10811 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
10813 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
10814 Chain = NewSP.getValue(1);
10816 SDValue Ops[2] = { NewSP, Chain };
10817 return DAG.getMergeValues(Ops, DL);
10820 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
10821 assert(Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() &&
10822 "Unexpected type for custom-lowering FP_EXTEND");
10825 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
10827 SDValue SrcVal = Op.getOperand(0);
10828 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
10829 /*isSigned*/ false, SDLoc(Op)).first;
10832 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
10833 assert(Op.getOperand(0).getValueType() == MVT::f64 &&
10834 Subtarget->isFPOnlySP() &&
10835 "Unexpected type for custom-lowering FP_ROUND");
10838 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
10840 SDValue SrcVal = Op.getOperand(0);
10841 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
10842 /*isSigned*/ false, SDLoc(Op)).first;
10846 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
10847 // The ARM target isn't yet aware of offsets.
10851 bool ARM::isBitFieldInvertedMask(unsigned v) {
10852 if (v == 0xffffffff)
10855 // there can be 1's on either or both "outsides", all the "inside"
10856 // bits must be 0's
10857 unsigned TO = CountTrailingOnes_32(v);
10858 unsigned LO = CountLeadingOnes_32(v);
10859 v = (v >> TO) << TO;
10860 v = (v << LO) >> LO;
10864 /// isFPImmLegal - Returns true if the target can instruction select the
10865 /// specified FP immediate natively. If false, the legalizer will
10866 /// materialize the FP immediate as a load from a constant pool.
10867 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
10868 if (!Subtarget->hasVFP3())
10870 if (VT == MVT::f32)
10871 return ARM_AM::getFP32Imm(Imm) != -1;
10872 if (VT == MVT::f64 && !Subtarget->isFPOnlySP())
10873 return ARM_AM::getFP64Imm(Imm) != -1;
10877 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
10878 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
10879 /// specified in the intrinsic calls.
10880 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
10882 unsigned Intrinsic) const {
10883 switch (Intrinsic) {
10884 case Intrinsic::arm_neon_vld1:
10885 case Intrinsic::arm_neon_vld2:
10886 case Intrinsic::arm_neon_vld3:
10887 case Intrinsic::arm_neon_vld4:
10888 case Intrinsic::arm_neon_vld2lane:
10889 case Intrinsic::arm_neon_vld3lane:
10890 case Intrinsic::arm_neon_vld4lane: {
10891 Info.opc = ISD::INTRINSIC_W_CHAIN;
10892 // Conservatively set memVT to the entire set of vectors loaded.
10893 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
10894 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10895 Info.ptrVal = I.getArgOperand(0);
10897 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10898 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10899 Info.vol = false; // volatile loads with NEON intrinsics not supported
10900 Info.readMem = true;
10901 Info.writeMem = false;
10904 case Intrinsic::arm_neon_vst1:
10905 case Intrinsic::arm_neon_vst2:
10906 case Intrinsic::arm_neon_vst3:
10907 case Intrinsic::arm_neon_vst4:
10908 case Intrinsic::arm_neon_vst2lane:
10909 case Intrinsic::arm_neon_vst3lane:
10910 case Intrinsic::arm_neon_vst4lane: {
10911 Info.opc = ISD::INTRINSIC_VOID;
10912 // Conservatively set memVT to the entire set of vectors stored.
10913 unsigned NumElts = 0;
10914 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
10915 Type *ArgTy = I.getArgOperand(ArgI)->getType();
10916 if (!ArgTy->isVectorTy())
10918 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
10920 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10921 Info.ptrVal = I.getArgOperand(0);
10923 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10924 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10925 Info.vol = false; // volatile stores with NEON intrinsics not supported
10926 Info.readMem = false;
10927 Info.writeMem = true;
10930 case Intrinsic::arm_ldaex:
10931 case Intrinsic::arm_ldrex: {
10932 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
10933 Info.opc = ISD::INTRINSIC_W_CHAIN;
10934 Info.memVT = MVT::getVT(PtrTy->getElementType());
10935 Info.ptrVal = I.getArgOperand(0);
10937 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10939 Info.readMem = true;
10940 Info.writeMem = false;
10943 case Intrinsic::arm_stlex:
10944 case Intrinsic::arm_strex: {
10945 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
10946 Info.opc = ISD::INTRINSIC_W_CHAIN;
10947 Info.memVT = MVT::getVT(PtrTy->getElementType());
10948 Info.ptrVal = I.getArgOperand(1);
10950 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10952 Info.readMem = false;
10953 Info.writeMem = true;
10956 case Intrinsic::arm_stlexd:
10957 case Intrinsic::arm_strexd: {
10958 Info.opc = ISD::INTRINSIC_W_CHAIN;
10959 Info.memVT = MVT::i64;
10960 Info.ptrVal = I.getArgOperand(2);
10964 Info.readMem = false;
10965 Info.writeMem = true;
10968 case Intrinsic::arm_ldaexd:
10969 case Intrinsic::arm_ldrexd: {
10970 Info.opc = ISD::INTRINSIC_W_CHAIN;
10971 Info.memVT = MVT::i64;
10972 Info.ptrVal = I.getArgOperand(0);
10976 Info.readMem = true;
10977 Info.writeMem = false;
10987 /// \brief Returns true if it is beneficial to convert a load of a constant
10988 /// to just the constant itself.
10989 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
10991 assert(Ty->isIntegerTy());
10993 unsigned Bits = Ty->getPrimitiveSizeInBits();
10994 if (Bits == 0 || Bits > 32)
10999 bool ARMTargetLowering::hasLoadLinkedStoreConditional() const { return true; }
11001 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
11002 ARM_MB::MemBOpt Domain) const {
11003 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11005 // First, if the target has no DMB, see what fallback we can use.
11006 if (!Subtarget->hasDataBarrier()) {
11007 // Some ARMv6 cpus can support data barriers with an mcr instruction.
11008 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
11010 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {
11011 Function *MCR = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
11012 Value* args[6] = {Builder.getInt32(15), Builder.getInt32(0),
11013 Builder.getInt32(0), Builder.getInt32(7),
11014 Builder.getInt32(10), Builder.getInt32(5)};
11015 return Builder.CreateCall(MCR, args);
11017 // Instead of using barriers, atomic accesses on these subtargets use
11019 llvm_unreachable("makeDMB on a target so old that it has no barriers");
11022 Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
11023 // Only a full system barrier exists in the M-class architectures.
11024 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain;
11025 Constant *CDomain = Builder.getInt32(Domain);
11026 return Builder.CreateCall(DMB, CDomain);
11030 // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
11031 Instruction* ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
11032 AtomicOrdering Ord, bool IsStore,
11033 bool IsLoad) const {
11034 if (!getInsertFencesForAtomic())
11040 llvm_unreachable("Invalid fence: unordered/non-atomic");
11043 return nullptr; // Nothing to do
11044 case SequentiallyConsistent:
11046 return nullptr; // Nothing to do
11049 case AcquireRelease:
11050 if (Subtarget->isSwift())
11051 return makeDMB(Builder, ARM_MB::ISHST);
11052 // FIXME: add a comment with a link to documentation justifying this.
11054 return makeDMB(Builder, ARM_MB::ISH);
11056 llvm_unreachable("Unknown fence ordering in emitLeadingFence");
11059 Instruction* ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
11060 AtomicOrdering Ord, bool IsStore,
11061 bool IsLoad) const {
11062 if (!getInsertFencesForAtomic())
11068 llvm_unreachable("Invalid fence: unordered/not-atomic");
11071 return nullptr; // Nothing to do
11073 case AcquireRelease:
11074 case SequentiallyConsistent:
11075 return makeDMB(Builder, ARM_MB::ISH);
11077 llvm_unreachable("Unknown fence ordering in emitTrailingFence");
11080 // Loads and stores less than 64-bits are already atomic; ones above that
11081 // are doomed anyway, so defer to the default libcall and blame the OS when
11082 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11083 // anything for those.
11084 bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
11085 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
11086 return (Size == 64) && !Subtarget->isMClass();
11089 // Loads and stores less than 64-bits are already atomic; ones above that
11090 // are doomed anyway, so defer to the default libcall and blame the OS when
11091 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11092 // anything for those.
11093 // FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that
11094 // guarantee, see DDI0406C ARM architecture reference manual,
11095 // sections A8.8.72-74 LDRD)
11096 bool ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
11097 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
11098 return (Size == 64) && !Subtarget->isMClass();
11101 // For the real atomic operations, we have ldrex/strex up to 32 bits,
11102 // and up to 64 bits on the non-M profiles
11103 bool ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
11104 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
11105 return Size <= (Subtarget->isMClass() ? 32U : 64U);
11108 // This has so far only been implemented for MachO.
11109 bool ARMTargetLowering::useLoadStackGuardNode() const {
11110 return Subtarget->isTargetMachO();
11113 bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
11114 unsigned &Cost) const {
11115 // If we do not have NEON, vector types are not natively supported.
11116 if (!Subtarget->hasNEON())
11119 // Floating point values and vector values map to the same register file.
11120 // Therefore, althought we could do a store extract of a vector type, this is
11121 // better to leave at float as we have more freedom in the addressing mode for
11123 if (VectorTy->isFPOrFPVectorTy())
11126 // If the index is unknown at compile time, this is very expensive to lower
11127 // and it is not possible to combine the store with the extract.
11128 if (!isa<ConstantInt>(Idx))
11131 assert(VectorTy->isVectorTy() && "VectorTy is not a vector type");
11132 unsigned BitWidth = cast<VectorType>(VectorTy)->getBitWidth();
11133 // We can do a store + vector extract on any vector that fits perfectly in a D
11135 if (BitWidth == 64 || BitWidth == 128) {
11142 Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
11143 AtomicOrdering Ord) const {
11144 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11145 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
11146 bool IsAcquire = isAtLeastAcquire(Ord);
11148 // Since i64 isn't legal and intrinsics don't get type-lowered, the ldrexd
11149 // intrinsic must return {i32, i32} and we have to recombine them into a
11150 // single i64 here.
11151 if (ValTy->getPrimitiveSizeInBits() == 64) {
11152 Intrinsic::ID Int =
11153 IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd;
11154 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int);
11156 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11157 Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi");
11159 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
11160 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
11161 if (!Subtarget->isLittle())
11162 std::swap (Lo, Hi);
11163 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
11164 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
11165 return Builder.CreateOr(
11166 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 32)), "val64");
11169 Type *Tys[] = { Addr->getType() };
11170 Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
11171 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int, Tys);
11173 return Builder.CreateTruncOrBitCast(
11174 Builder.CreateCall(Ldrex, Addr),
11175 cast<PointerType>(Addr->getType())->getElementType());
11178 Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
11180 AtomicOrdering Ord) const {
11181 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11182 bool IsRelease = isAtLeastRelease(Ord);
11184 // Since the intrinsics must have legal type, the i64 intrinsics take two
11185 // parameters: "i32, i32". We must marshal Val into the appropriate form
11186 // before the call.
11187 if (Val->getType()->getPrimitiveSizeInBits() == 64) {
11188 Intrinsic::ID Int =
11189 IsRelease ? Intrinsic::arm_stlexd : Intrinsic::arm_strexd;
11190 Function *Strex = Intrinsic::getDeclaration(M, Int);
11191 Type *Int32Ty = Type::getInt32Ty(M->getContext());
11193 Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
11194 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
11195 if (!Subtarget->isLittle())
11196 std::swap (Lo, Hi);
11197 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11198 return Builder.CreateCall3(Strex, Lo, Hi, Addr);
11201 Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex;
11202 Type *Tys[] = { Addr->getType() };
11203 Function *Strex = Intrinsic::getDeclaration(M, Int, Tys);
11205 return Builder.CreateCall2(
11206 Strex, Builder.CreateZExtOrBitCast(
11207 Val, Strex->getFunctionType()->getParamType(0)),
11219 static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base,
11220 uint64_t &Members) {
11221 if (const StructType *ST = dyn_cast<StructType>(Ty)) {
11222 for (unsigned i = 0; i < ST->getNumElements(); ++i) {
11223 uint64_t SubMembers = 0;
11224 if (!isHomogeneousAggregate(ST->getElementType(i), Base, SubMembers))
11226 Members += SubMembers;
11228 } else if (const ArrayType *AT = dyn_cast<ArrayType>(Ty)) {
11229 uint64_t SubMembers = 0;
11230 if (!isHomogeneousAggregate(AT->getElementType(), Base, SubMembers))
11232 Members += SubMembers * AT->getNumElements();
11233 } else if (Ty->isFloatTy()) {
11234 if (Base != HA_UNKNOWN && Base != HA_FLOAT)
11238 } else if (Ty->isDoubleTy()) {
11239 if (Base != HA_UNKNOWN && Base != HA_DOUBLE)
11243 } else if (const VectorType *VT = dyn_cast<VectorType>(Ty)) {
11250 return VT->getBitWidth() == 64;
11252 return VT->getBitWidth() == 128;
11254 switch (VT->getBitWidth()) {
11267 return (Members > 0 && Members <= 4);
11270 /// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate.
11271 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(
11272 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
11273 if (getEffectiveCallingConv(CallConv, isVarArg) !=
11274 CallingConv::ARM_AAPCS_VFP)
11277 HABaseType Base = HA_UNKNOWN;
11278 uint64_t Members = 0;
11279 bool result = isHomogeneousAggregate(Ty, Base, Members);
11280 DEBUG(dbgs() << "isHA: " << result << " "; Ty->dump());