1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Instruction.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Type.h"
33 #include "llvm/CodeGen/CallingConvLower.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/MC/MCSectionMachO.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/ADT/VectorExtras.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
52 STATISTIC(NumTailCalls, "Number of tail calls");
54 // This option should go away when tail calls fully work.
56 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
57 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
61 EnableARMLongCalls("arm-long-calls", cl::Hidden,
62 cl::desc("Generate calls via indirect call instructions"),
66 ARMInterworking("arm-interworking", cl::Hidden,
67 cl::desc("Enable / disable ARM interworking (for debugging only)"),
71 EnableARMCodePlacement("arm-code-placement", cl::Hidden,
72 cl::desc("Enable code placement pass for ARM"),
75 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
76 CCValAssign::LocInfo &LocInfo,
77 ISD::ArgFlagsTy &ArgFlags,
79 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
80 CCValAssign::LocInfo &LocInfo,
81 ISD::ArgFlagsTy &ArgFlags,
83 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
84 CCValAssign::LocInfo &LocInfo,
85 ISD::ArgFlagsTy &ArgFlags,
87 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
88 CCValAssign::LocInfo &LocInfo,
89 ISD::ArgFlagsTy &ArgFlags,
92 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
93 EVT PromotedBitwiseVT) {
94 if (VT != PromotedLdStVT) {
95 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
96 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
97 PromotedLdStVT.getSimpleVT());
99 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
100 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
101 PromotedLdStVT.getSimpleVT());
104 EVT ElemTy = VT.getVectorElementType();
105 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
106 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
107 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
108 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
109 if (ElemTy != MVT::i32) {
110 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
111 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
112 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
113 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
116 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
117 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
118 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
119 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
120 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
121 if (VT.isInteger()) {
122 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
123 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
124 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
127 // Promote all bit-wise operations.
128 if (VT.isInteger() && VT != PromotedBitwiseVT) {
129 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
130 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
131 PromotedBitwiseVT.getSimpleVT());
132 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
133 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
134 PromotedBitwiseVT.getSimpleVT());
135 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
136 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
137 PromotedBitwiseVT.getSimpleVT());
140 // Neon does not support vector divide/remainder operations.
141 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
142 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
143 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
144 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
145 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
146 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
149 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
150 addRegisterClass(VT, ARM::DPRRegisterClass);
151 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
154 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
155 addRegisterClass(VT, ARM::QPRRegisterClass);
156 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
159 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
160 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
161 return new TargetLoweringObjectFileMachO();
163 return new ARMElfTargetObjectFile();
166 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
167 : TargetLowering(TM, createTLOF(TM)) {
168 Subtarget = &TM.getSubtarget<ARMSubtarget>();
170 if (Subtarget->isTargetDarwin()) {
171 // Uses VFP for Thumb libfuncs if available.
172 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
173 // Single-precision floating-point arithmetic.
174 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
175 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
176 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
177 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
179 // Double-precision floating-point arithmetic.
180 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
181 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
182 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
183 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
185 // Single-precision comparisons.
186 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
187 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
188 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
189 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
190 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
191 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
192 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
193 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
195 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
196 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
201 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
202 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
204 // Double-precision comparisons.
205 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
206 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
207 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
208 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
209 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
210 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
211 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
212 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
214 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
218 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
219 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
220 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
221 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
223 // Floating-point to integer conversions.
224 // i64 conversions are done via library routines even when generating VFP
225 // instructions, so use the same ones.
226 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
227 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
228 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
229 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
231 // Conversions between floating types.
232 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
233 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
235 // Integer to floating-point conversions.
236 // i64 conversions are done via library routines even when generating VFP
237 // instructions, so use the same ones.
238 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
239 // e.g., __floatunsidf vs. __floatunssidfvfp.
240 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
241 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
242 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
243 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
247 // These libcalls are not available in 32-bit.
248 setLibcallName(RTLIB::SHL_I128, 0);
249 setLibcallName(RTLIB::SRL_I128, 0);
250 setLibcallName(RTLIB::SRA_I128, 0);
252 // Libcalls should use the AAPCS base standard ABI, even if hard float
253 // is in effect, as per the ARM RTABI specification, section 4.1.2.
254 if (Subtarget->isAAPCS_ABI()) {
255 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
256 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
257 CallingConv::ARM_AAPCS);
261 if (Subtarget->isThumb1Only())
262 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
264 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
265 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
266 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
267 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
269 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
272 if (Subtarget->hasNEON()) {
273 addDRTypeForNEON(MVT::v2f32);
274 addDRTypeForNEON(MVT::v8i8);
275 addDRTypeForNEON(MVT::v4i16);
276 addDRTypeForNEON(MVT::v2i32);
277 addDRTypeForNEON(MVT::v1i64);
279 addQRTypeForNEON(MVT::v4f32);
280 addQRTypeForNEON(MVT::v2f64);
281 addQRTypeForNEON(MVT::v16i8);
282 addQRTypeForNEON(MVT::v8i16);
283 addQRTypeForNEON(MVT::v4i32);
284 addQRTypeForNEON(MVT::v2i64);
286 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
287 // neither Neon nor VFP support any arithmetic operations on it.
288 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
289 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
290 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
291 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
292 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
293 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
294 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
295 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
296 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
297 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
298 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
299 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
300 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
301 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
302 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
303 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
304 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
305 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
306 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
307 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
308 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
309 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
310 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
311 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
313 // Neon does not support some operations on v1i64 and v2i64 types.
314 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
315 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
316 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
317 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
319 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
320 setTargetDAGCombine(ISD::SHL);
321 setTargetDAGCombine(ISD::SRL);
322 setTargetDAGCombine(ISD::SRA);
323 setTargetDAGCombine(ISD::SIGN_EXTEND);
324 setTargetDAGCombine(ISD::ZERO_EXTEND);
325 setTargetDAGCombine(ISD::ANY_EXTEND);
326 setTargetDAGCombine(ISD::SELECT_CC);
329 computeRegisterProperties();
331 // ARM does not have f32 extending load.
332 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
334 // ARM does not have i1 sign extending load.
335 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
337 // ARM supports all 4 flavors of integer indexed load / store.
338 if (!Subtarget->isThumb1Only()) {
339 for (unsigned im = (unsigned)ISD::PRE_INC;
340 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
341 setIndexedLoadAction(im, MVT::i1, Legal);
342 setIndexedLoadAction(im, MVT::i8, Legal);
343 setIndexedLoadAction(im, MVT::i16, Legal);
344 setIndexedLoadAction(im, MVT::i32, Legal);
345 setIndexedStoreAction(im, MVT::i1, Legal);
346 setIndexedStoreAction(im, MVT::i8, Legal);
347 setIndexedStoreAction(im, MVT::i16, Legal);
348 setIndexedStoreAction(im, MVT::i32, Legal);
352 // i64 operation support.
353 if (Subtarget->isThumb1Only()) {
354 setOperationAction(ISD::MUL, MVT::i64, Expand);
355 setOperationAction(ISD::MULHU, MVT::i32, Expand);
356 setOperationAction(ISD::MULHS, MVT::i32, Expand);
357 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
358 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
360 setOperationAction(ISD::MUL, MVT::i64, Expand);
361 setOperationAction(ISD::MULHU, MVT::i32, Expand);
362 if (!Subtarget->hasV6Ops())
363 setOperationAction(ISD::MULHS, MVT::i32, Expand);
365 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
366 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
367 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
368 setOperationAction(ISD::SRL, MVT::i64, Custom);
369 setOperationAction(ISD::SRA, MVT::i64, Custom);
371 // ARM does not have ROTL.
372 setOperationAction(ISD::ROTL, MVT::i32, Expand);
373 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
374 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
375 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
376 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
378 // Only ARMv6 has BSWAP.
379 if (!Subtarget->hasV6Ops())
380 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
382 // These are expanded into libcalls.
383 if (!Subtarget->hasDivide()) {
384 // v7M has a hardware divider
385 setOperationAction(ISD::SDIV, MVT::i32, Expand);
386 setOperationAction(ISD::UDIV, MVT::i32, Expand);
388 setOperationAction(ISD::SREM, MVT::i32, Expand);
389 setOperationAction(ISD::UREM, MVT::i32, Expand);
390 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
391 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
393 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
394 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
395 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
396 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
397 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
399 setOperationAction(ISD::TRAP, MVT::Other, Legal);
401 // Use the default implementation.
402 setOperationAction(ISD::VASTART, MVT::Other, Custom);
403 setOperationAction(ISD::VAARG, MVT::Other, Expand);
404 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
405 setOperationAction(ISD::VAEND, MVT::Other, Expand);
406 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
407 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
408 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
409 // FIXME: Shouldn't need this, since no register is used, but the legalizer
410 // doesn't yet know how to not do that for SjLj.
411 setExceptionSelectorRegister(ARM::R0);
412 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
413 // Handle atomics directly for ARMv[67] (except for Thumb1), otherwise
414 // use the default expansion.
415 bool canHandleAtomics =
416 (Subtarget->hasV7Ops() ||
417 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only()));
418 if (canHandleAtomics) {
419 // membarrier needs custom lowering; the rest are legal and handled
421 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
423 // Set them all for expansion, which will force libcalls.
424 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
425 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
426 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
427 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
428 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
429 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
430 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
431 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
432 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
433 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
434 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
435 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
436 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
437 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
438 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
439 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
440 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
441 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
442 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
443 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
444 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
445 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
446 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
447 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
448 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
449 // Since the libcalls include locking, fold in the fences
450 setShouldFoldAtomicFences(true);
452 // 64-bit versions are always libcalls (for now)
453 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
454 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
455 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
456 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
457 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
458 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
459 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
460 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
462 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
463 if (!Subtarget->hasV6Ops()) {
464 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
465 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
469 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
470 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
471 // iff target supports vfp2.
472 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
474 // We want to custom lower some of our intrinsics.
475 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
476 if (Subtarget->isTargetDarwin()) {
477 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
478 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
481 setOperationAction(ISD::SETCC, MVT::i32, Expand);
482 setOperationAction(ISD::SETCC, MVT::f32, Expand);
483 setOperationAction(ISD::SETCC, MVT::f64, Expand);
484 setOperationAction(ISD::SELECT, MVT::i32, Expand);
485 setOperationAction(ISD::SELECT, MVT::f32, Expand);
486 setOperationAction(ISD::SELECT, MVT::f64, Expand);
487 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
488 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
489 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
491 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
492 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
493 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
494 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
495 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
497 // We don't support sin/cos/fmod/copysign/pow
498 setOperationAction(ISD::FSIN, MVT::f64, Expand);
499 setOperationAction(ISD::FSIN, MVT::f32, Expand);
500 setOperationAction(ISD::FCOS, MVT::f32, Expand);
501 setOperationAction(ISD::FCOS, MVT::f64, Expand);
502 setOperationAction(ISD::FREM, MVT::f64, Expand);
503 setOperationAction(ISD::FREM, MVT::f32, Expand);
504 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
505 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
506 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
508 setOperationAction(ISD::FPOW, MVT::f64, Expand);
509 setOperationAction(ISD::FPOW, MVT::f32, Expand);
511 // Various VFP goodness
512 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
513 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
514 if (Subtarget->hasVFP2()) {
515 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
516 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
517 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
518 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
520 // Special handling for half-precision FP.
521 if (!Subtarget->hasFP16()) {
522 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
523 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
527 // We have target-specific dag combine patterns for the following nodes:
528 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
529 setTargetDAGCombine(ISD::ADD);
530 setTargetDAGCombine(ISD::SUB);
531 setTargetDAGCombine(ISD::MUL);
533 setStackPointerRegisterToSaveRestore(ARM::SP);
535 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
536 setSchedulingPreference(Sched::RegPressure);
538 setSchedulingPreference(Sched::Hybrid);
540 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
542 // On ARM arguments smaller than 4 bytes are extended, so all arguments
543 // are at least 4 bytes aligned.
544 setMinStackArgumentAlignment(4);
546 if (EnableARMCodePlacement)
547 benefitFromCodePlacementOpt = true;
550 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
553 case ARMISD::Wrapper: return "ARMISD::Wrapper";
554 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
555 case ARMISD::CALL: return "ARMISD::CALL";
556 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
557 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
558 case ARMISD::tCALL: return "ARMISD::tCALL";
559 case ARMISD::BRCOND: return "ARMISD::BRCOND";
560 case ARMISD::BR_JT: return "ARMISD::BR_JT";
561 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
562 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
563 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
564 case ARMISD::CMP: return "ARMISD::CMP";
565 case ARMISD::CMPZ: return "ARMISD::CMPZ";
566 case ARMISD::CMPFP: return "ARMISD::CMPFP";
567 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
568 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
569 case ARMISD::CMOV: return "ARMISD::CMOV";
570 case ARMISD::CNEG: return "ARMISD::CNEG";
572 case ARMISD::RBIT: return "ARMISD::RBIT";
574 case ARMISD::FTOSI: return "ARMISD::FTOSI";
575 case ARMISD::FTOUI: return "ARMISD::FTOUI";
576 case ARMISD::SITOF: return "ARMISD::SITOF";
577 case ARMISD::UITOF: return "ARMISD::UITOF";
579 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
580 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
581 case ARMISD::RRX: return "ARMISD::RRX";
583 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
584 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
586 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
587 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
589 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
591 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
593 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
595 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
596 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
598 case ARMISD::VCEQ: return "ARMISD::VCEQ";
599 case ARMISD::VCGE: return "ARMISD::VCGE";
600 case ARMISD::VCGEU: return "ARMISD::VCGEU";
601 case ARMISD::VCGT: return "ARMISD::VCGT";
602 case ARMISD::VCGTU: return "ARMISD::VCGTU";
603 case ARMISD::VTST: return "ARMISD::VTST";
605 case ARMISD::VSHL: return "ARMISD::VSHL";
606 case ARMISD::VSHRs: return "ARMISD::VSHRs";
607 case ARMISD::VSHRu: return "ARMISD::VSHRu";
608 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
609 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
610 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
611 case ARMISD::VSHRN: return "ARMISD::VSHRN";
612 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
613 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
614 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
615 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
616 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
617 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
618 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
619 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
620 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
621 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
622 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
623 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
624 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
625 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
626 case ARMISD::VDUP: return "ARMISD::VDUP";
627 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
628 case ARMISD::VEXT: return "ARMISD::VEXT";
629 case ARMISD::VREV64: return "ARMISD::VREV64";
630 case ARMISD::VREV32: return "ARMISD::VREV32";
631 case ARMISD::VREV16: return "ARMISD::VREV16";
632 case ARMISD::VZIP: return "ARMISD::VZIP";
633 case ARMISD::VUZP: return "ARMISD::VUZP";
634 case ARMISD::VTRN: return "ARMISD::VTRN";
635 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
636 case ARMISD::FMAX: return "ARMISD::FMAX";
637 case ARMISD::FMIN: return "ARMISD::FMIN";
641 /// getRegClassFor - Return the register class that should be used for the
642 /// specified value type.
643 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
644 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
645 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
646 // load / store 4 to 8 consecutive D registers.
647 if (Subtarget->hasNEON()) {
648 if (VT == MVT::v4i64)
649 return ARM::QQPRRegisterClass;
650 else if (VT == MVT::v8i64)
651 return ARM::QQQQPRRegisterClass;
653 return TargetLowering::getRegClassFor(VT);
656 /// getFunctionAlignment - Return the Log2 alignment of this function.
657 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
658 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
661 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
662 unsigned NumVals = N->getNumValues();
664 return Sched::RegPressure;
666 for (unsigned i = 0; i != NumVals; ++i) {
667 EVT VT = N->getValueType(i);
668 if (VT.isFloatingPoint() || VT.isVector())
669 return Sched::Latency;
672 if (!N->isMachineOpcode())
673 return Sched::RegPressure;
675 // Load are scheduled for latency even if there instruction itinerary
677 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
678 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
680 return Sched::Latency;
682 const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData();
683 if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2)
684 return Sched::Latency;
685 return Sched::RegPressure;
688 //===----------------------------------------------------------------------===//
690 //===----------------------------------------------------------------------===//
692 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
693 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
695 default: llvm_unreachable("Unknown condition code!");
696 case ISD::SETNE: return ARMCC::NE;
697 case ISD::SETEQ: return ARMCC::EQ;
698 case ISD::SETGT: return ARMCC::GT;
699 case ISD::SETGE: return ARMCC::GE;
700 case ISD::SETLT: return ARMCC::LT;
701 case ISD::SETLE: return ARMCC::LE;
702 case ISD::SETUGT: return ARMCC::HI;
703 case ISD::SETUGE: return ARMCC::HS;
704 case ISD::SETULT: return ARMCC::LO;
705 case ISD::SETULE: return ARMCC::LS;
709 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
710 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
711 ARMCC::CondCodes &CondCode2) {
712 CondCode2 = ARMCC::AL;
714 default: llvm_unreachable("Unknown FP condition!");
716 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
718 case ISD::SETOGT: CondCode = ARMCC::GT; break;
720 case ISD::SETOGE: CondCode = ARMCC::GE; break;
721 case ISD::SETOLT: CondCode = ARMCC::MI; break;
722 case ISD::SETOLE: CondCode = ARMCC::LS; break;
723 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
724 case ISD::SETO: CondCode = ARMCC::VC; break;
725 case ISD::SETUO: CondCode = ARMCC::VS; break;
726 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
727 case ISD::SETUGT: CondCode = ARMCC::HI; break;
728 case ISD::SETUGE: CondCode = ARMCC::PL; break;
730 case ISD::SETULT: CondCode = ARMCC::LT; break;
732 case ISD::SETULE: CondCode = ARMCC::LE; break;
734 case ISD::SETUNE: CondCode = ARMCC::NE; break;
738 //===----------------------------------------------------------------------===//
739 // Calling Convention Implementation
740 //===----------------------------------------------------------------------===//
742 #include "ARMGenCallingConv.inc"
744 // APCS f64 is in register pairs, possibly split to stack
745 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
746 CCValAssign::LocInfo &LocInfo,
747 CCState &State, bool CanFail) {
748 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
750 // Try to get the first register.
751 if (unsigned Reg = State.AllocateReg(RegList, 4))
752 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
754 // For the 2nd half of a v2f64, do not fail.
758 // Put the whole thing on the stack.
759 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
760 State.AllocateStack(8, 4),
765 // Try to get the second register.
766 if (unsigned Reg = State.AllocateReg(RegList, 4))
767 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
769 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
770 State.AllocateStack(4, 4),
775 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
776 CCValAssign::LocInfo &LocInfo,
777 ISD::ArgFlagsTy &ArgFlags,
779 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
781 if (LocVT == MVT::v2f64 &&
782 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
784 return true; // we handled it
787 // AAPCS f64 is in aligned register pairs
788 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
789 CCValAssign::LocInfo &LocInfo,
790 CCState &State, bool CanFail) {
791 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
792 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
794 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
796 // For the 2nd half of a v2f64, do not just fail.
800 // Put the whole thing on the stack.
801 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
802 State.AllocateStack(8, 8),
808 for (i = 0; i < 2; ++i)
809 if (HiRegList[i] == Reg)
812 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
813 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
818 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
819 CCValAssign::LocInfo &LocInfo,
820 ISD::ArgFlagsTy &ArgFlags,
822 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
824 if (LocVT == MVT::v2f64 &&
825 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
827 return true; // we handled it
830 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
831 CCValAssign::LocInfo &LocInfo, CCState &State) {
832 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
833 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
835 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
837 return false; // we didn't handle it
840 for (i = 0; i < 2; ++i)
841 if (HiRegList[i] == Reg)
844 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
845 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
850 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
851 CCValAssign::LocInfo &LocInfo,
852 ISD::ArgFlagsTy &ArgFlags,
854 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
856 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
858 return true; // we handled it
861 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
862 CCValAssign::LocInfo &LocInfo,
863 ISD::ArgFlagsTy &ArgFlags,
865 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
869 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
870 /// given CallingConvention value.
871 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
873 bool isVarArg) const {
876 llvm_unreachable("Unsupported calling convention");
878 case CallingConv::Fast:
879 // Use target triple & subtarget features to do actual dispatch.
880 if (Subtarget->isAAPCS_ABI()) {
881 if (Subtarget->hasVFP2() &&
882 FloatABIType == FloatABI::Hard && !isVarArg)
883 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
885 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
887 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
888 case CallingConv::ARM_AAPCS_VFP:
889 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
890 case CallingConv::ARM_AAPCS:
891 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
892 case CallingConv::ARM_APCS:
893 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
897 /// LowerCallResult - Lower the result values of a call into the
898 /// appropriate copies out of appropriate physical registers.
900 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
901 CallingConv::ID CallConv, bool isVarArg,
902 const SmallVectorImpl<ISD::InputArg> &Ins,
903 DebugLoc dl, SelectionDAG &DAG,
904 SmallVectorImpl<SDValue> &InVals) const {
906 // Assign locations to each value returned by this call.
907 SmallVector<CCValAssign, 16> RVLocs;
908 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
909 RVLocs, *DAG.getContext());
910 CCInfo.AnalyzeCallResult(Ins,
911 CCAssignFnForNode(CallConv, /* Return*/ true,
914 // Copy all of the result registers out of their specified physreg.
915 for (unsigned i = 0; i != RVLocs.size(); ++i) {
916 CCValAssign VA = RVLocs[i];
919 if (VA.needsCustom()) {
920 // Handle f64 or half of a v2f64.
921 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
923 Chain = Lo.getValue(1);
924 InFlag = Lo.getValue(2);
925 VA = RVLocs[++i]; // skip ahead to next loc
926 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
928 Chain = Hi.getValue(1);
929 InFlag = Hi.getValue(2);
930 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
932 if (VA.getLocVT() == MVT::v2f64) {
933 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
934 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
935 DAG.getConstant(0, MVT::i32));
937 VA = RVLocs[++i]; // skip ahead to next loc
938 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
939 Chain = Lo.getValue(1);
940 InFlag = Lo.getValue(2);
941 VA = RVLocs[++i]; // skip ahead to next loc
942 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
943 Chain = Hi.getValue(1);
944 InFlag = Hi.getValue(2);
945 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
946 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
947 DAG.getConstant(1, MVT::i32));
950 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
952 Chain = Val.getValue(1);
953 InFlag = Val.getValue(2);
956 switch (VA.getLocInfo()) {
957 default: llvm_unreachable("Unknown loc info!");
958 case CCValAssign::Full: break;
959 case CCValAssign::BCvt:
960 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
964 InVals.push_back(Val);
970 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
971 /// by "Src" to address "Dst" of size "Size". Alignment information is
972 /// specified by the specific parameter attribute. The copy will be passed as
973 /// a byval function parameter.
974 /// Sometimes what we are copying is the end of a larger object, the part that
975 /// does not fit in registers.
977 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
978 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
980 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
981 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
982 /*isVolatile=*/false, /*AlwaysInline=*/false,
986 /// LowerMemOpCallTo - Store the argument to the stack.
988 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
989 SDValue StackPtr, SDValue Arg,
990 DebugLoc dl, SelectionDAG &DAG,
991 const CCValAssign &VA,
992 ISD::ArgFlagsTy Flags) const {
993 unsigned LocMemOffset = VA.getLocMemOffset();
994 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
995 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
996 if (Flags.isByVal()) {
997 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
999 return DAG.getStore(Chain, dl, Arg, PtrOff,
1000 PseudoSourceValue::getStack(), LocMemOffset,
1004 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1005 SDValue Chain, SDValue &Arg,
1006 RegsToPassVector &RegsToPass,
1007 CCValAssign &VA, CCValAssign &NextVA,
1009 SmallVector<SDValue, 8> &MemOpChains,
1010 ISD::ArgFlagsTy Flags) const {
1012 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1013 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1014 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1016 if (NextVA.isRegLoc())
1017 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1019 assert(NextVA.isMemLoc());
1020 if (StackPtr.getNode() == 0)
1021 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1023 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1029 /// LowerCall - Lowering a call into a callseq_start <-
1030 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1033 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1034 CallingConv::ID CallConv, bool isVarArg,
1036 const SmallVectorImpl<ISD::OutputArg> &Outs,
1037 const SmallVectorImpl<SDValue> &OutVals,
1038 const SmallVectorImpl<ISD::InputArg> &Ins,
1039 DebugLoc dl, SelectionDAG &DAG,
1040 SmallVectorImpl<SDValue> &InVals) const {
1041 MachineFunction &MF = DAG.getMachineFunction();
1042 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1043 bool IsSibCall = false;
1044 // Temporarily disable tail calls so things don't break.
1045 if (!EnableARMTailCalls)
1048 // Check if it's really possible to do a tail call.
1049 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1050 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1051 Outs, OutVals, Ins, DAG);
1052 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1053 // detected sibcalls.
1060 // Analyze operands of the call, assigning locations to each operand.
1061 SmallVector<CCValAssign, 16> ArgLocs;
1062 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1064 CCInfo.AnalyzeCallOperands(Outs,
1065 CCAssignFnForNode(CallConv, /* Return*/ false,
1068 // Get a count of how many bytes are to be pushed on the stack.
1069 unsigned NumBytes = CCInfo.getNextStackOffset();
1071 // For tail calls, memory operands are available in our caller's stack.
1075 // Adjust the stack pointer for the new arguments...
1076 // These operations are automatically eliminated by the prolog/epilog pass
1078 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1080 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1082 RegsToPassVector RegsToPass;
1083 SmallVector<SDValue, 8> MemOpChains;
1085 // Walk the register/memloc assignments, inserting copies/loads. In the case
1086 // of tail call optimization, arguments are handled later.
1087 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1089 ++i, ++realArgIdx) {
1090 CCValAssign &VA = ArgLocs[i];
1091 SDValue Arg = OutVals[realArgIdx];
1092 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1094 // Promote the value if needed.
1095 switch (VA.getLocInfo()) {
1096 default: llvm_unreachable("Unknown loc info!");
1097 case CCValAssign::Full: break;
1098 case CCValAssign::SExt:
1099 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1101 case CCValAssign::ZExt:
1102 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1104 case CCValAssign::AExt:
1105 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1107 case CCValAssign::BCvt:
1108 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1112 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1113 if (VA.needsCustom()) {
1114 if (VA.getLocVT() == MVT::v2f64) {
1115 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1116 DAG.getConstant(0, MVT::i32));
1117 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1118 DAG.getConstant(1, MVT::i32));
1120 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1121 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1123 VA = ArgLocs[++i]; // skip ahead to next loc
1124 if (VA.isRegLoc()) {
1125 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1126 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1128 assert(VA.isMemLoc());
1130 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1131 dl, DAG, VA, Flags));
1134 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1135 StackPtr, MemOpChains, Flags);
1137 } else if (VA.isRegLoc()) {
1138 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1139 } else if (!IsSibCall) {
1140 assert(VA.isMemLoc());
1142 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1143 dl, DAG, VA, Flags));
1147 if (!MemOpChains.empty())
1148 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1149 &MemOpChains[0], MemOpChains.size());
1151 // Build a sequence of copy-to-reg nodes chained together with token chain
1152 // and flag operands which copy the outgoing args into the appropriate regs.
1154 // Tail call byval lowering might overwrite argument registers so in case of
1155 // tail call optimization the copies to registers are lowered later.
1157 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1158 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1159 RegsToPass[i].second, InFlag);
1160 InFlag = Chain.getValue(1);
1163 // For tail calls lower the arguments to the 'real' stack slot.
1165 // Force all the incoming stack arguments to be loaded from the stack
1166 // before any new outgoing arguments are stored to the stack, because the
1167 // outgoing stack slots may alias the incoming argument stack slots, and
1168 // the alias isn't otherwise explicit. This is slightly more conservative
1169 // than necessary, because it means that each store effectively depends
1170 // on every argument instead of just those arguments it would clobber.
1172 // Do not flag preceeding copytoreg stuff together with the following stuff.
1174 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1175 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1176 RegsToPass[i].second, InFlag);
1177 InFlag = Chain.getValue(1);
1182 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1183 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1184 // node so that legalize doesn't hack it.
1185 bool isDirect = false;
1186 bool isARMFunc = false;
1187 bool isLocalARMFunc = false;
1188 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1190 if (EnableARMLongCalls) {
1191 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1192 && "long-calls with non-static relocation model!");
1193 // Handle a global address or an external symbol. If it's not one of
1194 // those, the target's already in a register, so we don't need to do
1196 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1197 const GlobalValue *GV = G->getGlobal();
1198 // Create a constant pool entry for the callee address
1199 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1200 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1203 // Get the address of the callee into a register
1204 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1205 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1206 Callee = DAG.getLoad(getPointerTy(), dl,
1207 DAG.getEntryNode(), CPAddr,
1208 PseudoSourceValue::getConstantPool(), 0,
1210 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1211 const char *Sym = S->getSymbol();
1213 // Create a constant pool entry for the callee address
1214 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1215 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1216 Sym, ARMPCLabelIndex, 0);
1217 // Get the address of the callee into a register
1218 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1219 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1220 Callee = DAG.getLoad(getPointerTy(), dl,
1221 DAG.getEntryNode(), CPAddr,
1222 PseudoSourceValue::getConstantPool(), 0,
1225 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1226 const GlobalValue *GV = G->getGlobal();
1228 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1229 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1230 getTargetMachine().getRelocationModel() != Reloc::Static;
1231 isARMFunc = !Subtarget->isThumb() || isStub;
1232 // ARM call to a local ARM function is predicable.
1233 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1234 // tBX takes a register source operand.
1235 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1236 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1237 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1240 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1241 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1242 Callee = DAG.getLoad(getPointerTy(), dl,
1243 DAG.getEntryNode(), CPAddr,
1244 PseudoSourceValue::getConstantPool(), 0,
1246 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1247 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1248 getPointerTy(), Callee, PICLabel);
1250 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
1251 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1253 bool isStub = Subtarget->isTargetDarwin() &&
1254 getTargetMachine().getRelocationModel() != Reloc::Static;
1255 isARMFunc = !Subtarget->isThumb() || isStub;
1256 // tBX takes a register source operand.
1257 const char *Sym = S->getSymbol();
1258 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1259 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1260 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1261 Sym, ARMPCLabelIndex, 4);
1262 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1263 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1264 Callee = DAG.getLoad(getPointerTy(), dl,
1265 DAG.getEntryNode(), CPAddr,
1266 PseudoSourceValue::getConstantPool(), 0,
1268 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1269 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1270 getPointerTy(), Callee, PICLabel);
1272 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1275 // FIXME: handle tail calls differently.
1277 if (Subtarget->isThumb()) {
1278 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1279 CallOpc = ARMISD::CALL_NOLINK;
1281 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1283 CallOpc = (isDirect || Subtarget->hasV5TOps())
1284 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1285 : ARMISD::CALL_NOLINK;
1288 std::vector<SDValue> Ops;
1289 Ops.push_back(Chain);
1290 Ops.push_back(Callee);
1292 // Add argument registers to the end of the list so that they are known live
1294 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1295 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1296 RegsToPass[i].second.getValueType()));
1298 if (InFlag.getNode())
1299 Ops.push_back(InFlag);
1301 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1303 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1305 // Returns a chain and a flag for retval copy to use.
1306 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1307 InFlag = Chain.getValue(1);
1309 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1310 DAG.getIntPtrConstant(0, true), InFlag);
1312 InFlag = Chain.getValue(1);
1314 // Handle result values, copying them out of physregs into vregs that we
1316 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1320 /// MatchingStackOffset - Return true if the given stack call argument is
1321 /// already available in the same position (relatively) of the caller's
1322 /// incoming argument stack.
1324 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1325 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1326 const ARMInstrInfo *TII) {
1327 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1329 if (Arg.getOpcode() == ISD::CopyFromReg) {
1330 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1331 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1333 MachineInstr *Def = MRI->getVRegDef(VR);
1336 if (!Flags.isByVal()) {
1337 if (!TII->isLoadFromStackSlot(Def, FI))
1342 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1343 if (Flags.isByVal())
1344 // ByVal argument is passed in as a pointer but it's now being
1345 // dereferenced. e.g.
1346 // define @foo(%struct.X* %A) {
1347 // tail call @bar(%struct.X* byval %A)
1350 SDValue Ptr = Ld->getBasePtr();
1351 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1354 FI = FINode->getIndex();
1358 assert(FI != INT_MAX);
1359 if (!MFI->isFixedObjectIndex(FI))
1361 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1364 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1365 /// for tail call optimization. Targets which want to do tail call
1366 /// optimization should implement this function.
1368 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1369 CallingConv::ID CalleeCC,
1371 bool isCalleeStructRet,
1372 bool isCallerStructRet,
1373 const SmallVectorImpl<ISD::OutputArg> &Outs,
1374 const SmallVectorImpl<SDValue> &OutVals,
1375 const SmallVectorImpl<ISD::InputArg> &Ins,
1376 SelectionDAG& DAG) const {
1377 const Function *CallerF = DAG.getMachineFunction().getFunction();
1378 CallingConv::ID CallerCC = CallerF->getCallingConv();
1379 bool CCMatch = CallerCC == CalleeCC;
1381 // Look for obvious safe cases to perform tail call optimization that do not
1382 // require ABI changes. This is what gcc calls sibcall.
1384 // Do not sibcall optimize vararg calls unless the call site is not passing
1386 if (isVarArg && !Outs.empty())
1389 // Also avoid sibcall optimization if either caller or callee uses struct
1390 // return semantics.
1391 if (isCalleeStructRet || isCallerStructRet)
1394 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1395 // emitEpilogue is not ready for them.
1396 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1397 // LR. This means if we need to reload LR, it takes an extra instructions,
1398 // which outweighs the value of the tail call; but here we don't know yet
1399 // whether LR is going to be used. Probably the right approach is to
1400 // generate the tail call here and turn it back into CALL/RET in
1401 // emitEpilogue if LR is used.
1402 if (Subtarget->isThumb1Only())
1405 // For the moment, we can only do this to functions defined in this
1406 // compilation, or to indirect calls. A Thumb B to an ARM function,
1407 // or vice versa, is not easily fixed up in the linker unlike BL.
1408 // (We could do this by loading the address of the callee into a register;
1409 // that is an extra instruction over the direct call and burns a register
1410 // as well, so is not likely to be a win.)
1412 // It might be safe to remove this restriction on non-Darwin.
1414 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1415 // but we need to make sure there are enough registers; the only valid
1416 // registers are the 4 used for parameters. We don't currently do this
1418 if (isa<ExternalSymbolSDNode>(Callee))
1421 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1422 const GlobalValue *GV = G->getGlobal();
1423 if (GV->isDeclaration() || GV->isWeakForLinker())
1427 // If the calling conventions do not match, then we'd better make sure the
1428 // results are returned in the same way as what the caller expects.
1430 SmallVector<CCValAssign, 16> RVLocs1;
1431 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1432 RVLocs1, *DAG.getContext());
1433 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1435 SmallVector<CCValAssign, 16> RVLocs2;
1436 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1437 RVLocs2, *DAG.getContext());
1438 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1440 if (RVLocs1.size() != RVLocs2.size())
1442 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1443 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1445 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1447 if (RVLocs1[i].isRegLoc()) {
1448 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1451 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1457 // If the callee takes no arguments then go on to check the results of the
1459 if (!Outs.empty()) {
1460 // Check if stack adjustment is needed. For now, do not do this if any
1461 // argument is passed on the stack.
1462 SmallVector<CCValAssign, 16> ArgLocs;
1463 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1464 ArgLocs, *DAG.getContext());
1465 CCInfo.AnalyzeCallOperands(Outs,
1466 CCAssignFnForNode(CalleeCC, false, isVarArg));
1467 if (CCInfo.getNextStackOffset()) {
1468 MachineFunction &MF = DAG.getMachineFunction();
1470 // Check if the arguments are already laid out in the right way as
1471 // the caller's fixed stack objects.
1472 MachineFrameInfo *MFI = MF.getFrameInfo();
1473 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1474 const ARMInstrInfo *TII =
1475 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1476 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1478 ++i, ++realArgIdx) {
1479 CCValAssign &VA = ArgLocs[i];
1480 EVT RegVT = VA.getLocVT();
1481 SDValue Arg = OutVals[realArgIdx];
1482 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1483 if (VA.getLocInfo() == CCValAssign::Indirect)
1485 if (VA.needsCustom()) {
1486 // f64 and vector types are split into multiple registers or
1487 // register/stack-slot combinations. The types will not match
1488 // the registers; give up on memory f64 refs until we figure
1489 // out what to do about this.
1492 if (!ArgLocs[++i].isRegLoc())
1494 if (RegVT == MVT::v2f64) {
1495 if (!ArgLocs[++i].isRegLoc())
1497 if (!ArgLocs[++i].isRegLoc())
1500 } else if (!VA.isRegLoc()) {
1501 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1513 ARMTargetLowering::LowerReturn(SDValue Chain,
1514 CallingConv::ID CallConv, bool isVarArg,
1515 const SmallVectorImpl<ISD::OutputArg> &Outs,
1516 const SmallVectorImpl<SDValue> &OutVals,
1517 DebugLoc dl, SelectionDAG &DAG) const {
1519 // CCValAssign - represent the assignment of the return value to a location.
1520 SmallVector<CCValAssign, 16> RVLocs;
1522 // CCState - Info about the registers and stack slots.
1523 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1526 // Analyze outgoing return values.
1527 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1530 // If this is the first return lowered for this function, add
1531 // the regs to the liveout set for the function.
1532 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1533 for (unsigned i = 0; i != RVLocs.size(); ++i)
1534 if (RVLocs[i].isRegLoc())
1535 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1540 // Copy the result values into the output registers.
1541 for (unsigned i = 0, realRVLocIdx = 0;
1543 ++i, ++realRVLocIdx) {
1544 CCValAssign &VA = RVLocs[i];
1545 assert(VA.isRegLoc() && "Can only return in registers!");
1547 SDValue Arg = OutVals[realRVLocIdx];
1549 switch (VA.getLocInfo()) {
1550 default: llvm_unreachable("Unknown loc info!");
1551 case CCValAssign::Full: break;
1552 case CCValAssign::BCvt:
1553 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1557 if (VA.needsCustom()) {
1558 if (VA.getLocVT() == MVT::v2f64) {
1559 // Extract the first half and return it in two registers.
1560 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1561 DAG.getConstant(0, MVT::i32));
1562 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1563 DAG.getVTList(MVT::i32, MVT::i32), Half);
1565 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1566 Flag = Chain.getValue(1);
1567 VA = RVLocs[++i]; // skip ahead to next loc
1568 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1569 HalfGPRs.getValue(1), Flag);
1570 Flag = Chain.getValue(1);
1571 VA = RVLocs[++i]; // skip ahead to next loc
1573 // Extract the 2nd half and fall through to handle it as an f64 value.
1574 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1575 DAG.getConstant(1, MVT::i32));
1577 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1579 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1580 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1581 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1582 Flag = Chain.getValue(1);
1583 VA = RVLocs[++i]; // skip ahead to next loc
1584 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1587 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1589 // Guarantee that all emitted copies are
1590 // stuck together, avoiding something bad.
1591 Flag = Chain.getValue(1);
1596 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1598 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1603 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1604 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1605 // one of the above mentioned nodes. It has to be wrapped because otherwise
1606 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1607 // be used to form addressing mode. These wrapped nodes will be selected
1609 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1610 EVT PtrVT = Op.getValueType();
1611 // FIXME there is no actual debug info here
1612 DebugLoc dl = Op.getDebugLoc();
1613 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1615 if (CP->isMachineConstantPoolEntry())
1616 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1617 CP->getAlignment());
1619 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1620 CP->getAlignment());
1621 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1624 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1625 SelectionDAG &DAG) const {
1626 MachineFunction &MF = DAG.getMachineFunction();
1627 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1628 unsigned ARMPCLabelIndex = 0;
1629 DebugLoc DL = Op.getDebugLoc();
1630 EVT PtrVT = getPointerTy();
1631 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1632 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1634 if (RelocM == Reloc::Static) {
1635 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1637 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1638 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1639 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1640 ARMCP::CPBlockAddress,
1642 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1644 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1645 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1646 PseudoSourceValue::getConstantPool(), 0,
1648 if (RelocM == Reloc::Static)
1650 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1651 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1654 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1656 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1657 SelectionDAG &DAG) const {
1658 DebugLoc dl = GA->getDebugLoc();
1659 EVT PtrVT = getPointerTy();
1660 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1661 MachineFunction &MF = DAG.getMachineFunction();
1662 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1663 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1664 ARMConstantPoolValue *CPV =
1665 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1666 ARMCP::CPValue, PCAdj, "tlsgd", true);
1667 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1668 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1669 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1670 PseudoSourceValue::getConstantPool(), 0,
1672 SDValue Chain = Argument.getValue(1);
1674 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1675 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1677 // call __tls_get_addr.
1680 Entry.Node = Argument;
1681 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1682 Args.push_back(Entry);
1683 // FIXME: is there useful debug info available here?
1684 std::pair<SDValue, SDValue> CallResult =
1685 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1686 false, false, false, false,
1687 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1688 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1689 return CallResult.first;
1692 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1693 // "local exec" model.
1695 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1696 SelectionDAG &DAG) const {
1697 const GlobalValue *GV = GA->getGlobal();
1698 DebugLoc dl = GA->getDebugLoc();
1700 SDValue Chain = DAG.getEntryNode();
1701 EVT PtrVT = getPointerTy();
1702 // Get the Thread Pointer
1703 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1705 if (GV->isDeclaration()) {
1706 MachineFunction &MF = DAG.getMachineFunction();
1707 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1708 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1709 // Initial exec model.
1710 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1711 ARMConstantPoolValue *CPV =
1712 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1713 ARMCP::CPValue, PCAdj, "gottpoff", true);
1714 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1715 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1716 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1717 PseudoSourceValue::getConstantPool(), 0,
1719 Chain = Offset.getValue(1);
1721 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1722 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1724 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1725 PseudoSourceValue::getConstantPool(), 0,
1729 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1730 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1731 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1732 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1733 PseudoSourceValue::getConstantPool(), 0,
1737 // The address of the thread local variable is the add of the thread
1738 // pointer with the offset of the variable.
1739 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1743 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1744 // TODO: implement the "local dynamic" model
1745 assert(Subtarget->isTargetELF() &&
1746 "TLS not implemented for non-ELF targets");
1747 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1748 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1749 // otherwise use the "Local Exec" TLS Model
1750 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1751 return LowerToTLSGeneralDynamicModel(GA, DAG);
1753 return LowerToTLSExecModels(GA, DAG);
1756 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1757 SelectionDAG &DAG) const {
1758 EVT PtrVT = getPointerTy();
1759 DebugLoc dl = Op.getDebugLoc();
1760 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1761 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1762 if (RelocM == Reloc::PIC_) {
1763 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1764 ARMConstantPoolValue *CPV =
1765 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1766 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1767 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1768 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1770 PseudoSourceValue::getConstantPool(), 0,
1772 SDValue Chain = Result.getValue(1);
1773 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1774 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1776 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1777 PseudoSourceValue::getGOT(), 0,
1781 // If we have T2 ops, we can materialize the address directly via movt/movw
1782 // pair. This is always cheaper.
1783 if (Subtarget->useMovt()) {
1784 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1785 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1787 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1788 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1789 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1790 PseudoSourceValue::getConstantPool(), 0,
1796 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1797 SelectionDAG &DAG) const {
1798 MachineFunction &MF = DAG.getMachineFunction();
1799 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1800 unsigned ARMPCLabelIndex = 0;
1801 EVT PtrVT = getPointerTy();
1802 DebugLoc dl = Op.getDebugLoc();
1803 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1804 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1806 if (RelocM == Reloc::Static)
1807 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1809 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1810 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1811 ARMConstantPoolValue *CPV =
1812 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1813 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1815 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1817 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1818 PseudoSourceValue::getConstantPool(), 0,
1820 SDValue Chain = Result.getValue(1);
1822 if (RelocM == Reloc::PIC_) {
1823 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1824 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1827 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1828 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1829 PseudoSourceValue::getGOT(), 0,
1835 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1836 SelectionDAG &DAG) const {
1837 assert(Subtarget->isTargetELF() &&
1838 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1839 MachineFunction &MF = DAG.getMachineFunction();
1840 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1841 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1842 EVT PtrVT = getPointerTy();
1843 DebugLoc dl = Op.getDebugLoc();
1844 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1845 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1846 "_GLOBAL_OFFSET_TABLE_",
1847 ARMPCLabelIndex, PCAdj);
1848 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1849 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1850 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1851 PseudoSourceValue::getConstantPool(), 0,
1853 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1854 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1858 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1859 DebugLoc dl = Op.getDebugLoc();
1860 SDValue Val = DAG.getConstant(0, MVT::i32);
1861 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1862 Op.getOperand(1), Val);
1866 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1867 DebugLoc dl = Op.getDebugLoc();
1868 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1869 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1873 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1874 const ARMSubtarget *Subtarget) const {
1875 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1876 DebugLoc dl = Op.getDebugLoc();
1878 default: return SDValue(); // Don't custom lower most intrinsics.
1879 case Intrinsic::arm_thread_pointer: {
1880 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1881 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1883 case Intrinsic::eh_sjlj_lsda: {
1884 MachineFunction &MF = DAG.getMachineFunction();
1885 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1886 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1887 EVT PtrVT = getPointerTy();
1888 DebugLoc dl = Op.getDebugLoc();
1889 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1891 unsigned PCAdj = (RelocM != Reloc::PIC_)
1892 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1893 ARMConstantPoolValue *CPV =
1894 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1895 ARMCP::CPLSDA, PCAdj);
1896 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1897 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1899 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1900 PseudoSourceValue::getConstantPool(), 0,
1903 if (RelocM == Reloc::PIC_) {
1904 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1905 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1912 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1913 const ARMSubtarget *Subtarget) {
1914 DebugLoc dl = Op.getDebugLoc();
1915 SDValue Op5 = Op.getOperand(5);
1916 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1917 // v6 and v7 can both handle barriers directly, but need handled a bit
1918 // differently. Thumb1 and pre-v6 ARM mode use a libcall instead and should
1920 unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER;
1921 if (Subtarget->hasV7Ops())
1922 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0));
1923 else if (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())
1924 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0),
1925 DAG.getConstant(0, MVT::i32));
1926 assert(0 && "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
1930 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
1931 MachineFunction &MF = DAG.getMachineFunction();
1932 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
1934 // vastart just stores the address of the VarArgsFrameIndex slot into the
1935 // memory location argument.
1936 DebugLoc dl = Op.getDebugLoc();
1937 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1938 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1939 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1940 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
1945 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1946 SelectionDAG &DAG) const {
1947 SDNode *Node = Op.getNode();
1948 DebugLoc dl = Node->getDebugLoc();
1949 EVT VT = Node->getValueType(0);
1950 SDValue Chain = Op.getOperand(0);
1951 SDValue Size = Op.getOperand(1);
1952 SDValue Align = Op.getOperand(2);
1954 // Chain the dynamic stack allocation so that it doesn't modify the stack
1955 // pointer when other instructions are using the stack.
1956 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1958 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1959 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1960 if (AlignVal > StackAlign)
1961 // Do this now since selection pass cannot introduce new target
1962 // independent node.
1963 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1965 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1966 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1967 // do even more horrible hack later.
1968 MachineFunction &MF = DAG.getMachineFunction();
1969 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1970 if (AFI->isThumb1OnlyFunction()) {
1972 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1974 uint32_t Val = C->getZExtValue();
1975 if (Val <= 508 && ((Val & 3) == 0))
1979 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1982 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1983 SDValue Ops1[] = { Chain, Size, Align };
1984 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1985 Chain = Res.getValue(1);
1986 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1987 DAG.getIntPtrConstant(0, true), SDValue());
1988 SDValue Ops2[] = { Res, Chain };
1989 return DAG.getMergeValues(Ops2, 2, dl);
1993 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1994 SDValue &Root, SelectionDAG &DAG,
1995 DebugLoc dl) const {
1996 MachineFunction &MF = DAG.getMachineFunction();
1997 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1999 TargetRegisterClass *RC;
2000 if (AFI->isThumb1OnlyFunction())
2001 RC = ARM::tGPRRegisterClass;
2003 RC = ARM::GPRRegisterClass;
2005 // Transform the arguments stored in physical registers into virtual ones.
2006 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2007 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2010 if (NextVA.isMemLoc()) {
2011 MachineFrameInfo *MFI = MF.getFrameInfo();
2012 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2014 // Create load node to retrieve arguments from the stack.
2015 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2016 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2017 PseudoSourceValue::getFixedStack(FI), 0,
2020 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2021 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2024 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2028 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2029 CallingConv::ID CallConv, bool isVarArg,
2030 const SmallVectorImpl<ISD::InputArg>
2032 DebugLoc dl, SelectionDAG &DAG,
2033 SmallVectorImpl<SDValue> &InVals)
2036 MachineFunction &MF = DAG.getMachineFunction();
2037 MachineFrameInfo *MFI = MF.getFrameInfo();
2039 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2041 // Assign locations to all of the incoming arguments.
2042 SmallVector<CCValAssign, 16> ArgLocs;
2043 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2045 CCInfo.AnalyzeFormalArguments(Ins,
2046 CCAssignFnForNode(CallConv, /* Return*/ false,
2049 SmallVector<SDValue, 16> ArgValues;
2051 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2052 CCValAssign &VA = ArgLocs[i];
2054 // Arguments stored in registers.
2055 if (VA.isRegLoc()) {
2056 EVT RegVT = VA.getLocVT();
2059 if (VA.needsCustom()) {
2060 // f64 and vector types are split up into multiple registers or
2061 // combinations of registers and stack slots.
2062 if (VA.getLocVT() == MVT::v2f64) {
2063 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2065 VA = ArgLocs[++i]; // skip ahead to next loc
2067 if (VA.isMemLoc()) {
2068 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2069 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2070 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2071 PseudoSourceValue::getFixedStack(FI), 0,
2074 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2077 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2078 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2079 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2080 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2081 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2083 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2086 TargetRegisterClass *RC;
2088 if (RegVT == MVT::f32)
2089 RC = ARM::SPRRegisterClass;
2090 else if (RegVT == MVT::f64)
2091 RC = ARM::DPRRegisterClass;
2092 else if (RegVT == MVT::v2f64)
2093 RC = ARM::QPRRegisterClass;
2094 else if (RegVT == MVT::i32)
2095 RC = (AFI->isThumb1OnlyFunction() ?
2096 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2098 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2100 // Transform the arguments in physical registers into virtual ones.
2101 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2102 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2105 // If this is an 8 or 16-bit value, it is really passed promoted
2106 // to 32 bits. Insert an assert[sz]ext to capture this, then
2107 // truncate to the right size.
2108 switch (VA.getLocInfo()) {
2109 default: llvm_unreachable("Unknown loc info!");
2110 case CCValAssign::Full: break;
2111 case CCValAssign::BCvt:
2112 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2114 case CCValAssign::SExt:
2115 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2116 DAG.getValueType(VA.getValVT()));
2117 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2119 case CCValAssign::ZExt:
2120 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2121 DAG.getValueType(VA.getValVT()));
2122 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2126 InVals.push_back(ArgValue);
2128 } else { // VA.isRegLoc()
2131 assert(VA.isMemLoc());
2132 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2134 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2135 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2137 // Create load nodes to retrieve arguments from the stack.
2138 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2139 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2140 PseudoSourceValue::getFixedStack(FI), 0,
2147 static const unsigned GPRArgRegs[] = {
2148 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2151 unsigned NumGPRs = CCInfo.getFirstUnallocated
2152 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2154 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2155 unsigned VARegSize = (4 - NumGPRs) * 4;
2156 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2157 unsigned ArgOffset = CCInfo.getNextStackOffset();
2158 if (VARegSaveSize) {
2159 // If this function is vararg, store any remaining integer argument regs
2160 // to their spots on the stack so that they may be loaded by deferencing
2161 // the result of va_next.
2162 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2163 AFI->setVarArgsFrameIndex(
2164 MFI->CreateFixedObject(VARegSaveSize,
2165 ArgOffset + VARegSaveSize - VARegSize,
2167 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2170 SmallVector<SDValue, 4> MemOps;
2171 for (; NumGPRs < 4; ++NumGPRs) {
2172 TargetRegisterClass *RC;
2173 if (AFI->isThumb1OnlyFunction())
2174 RC = ARM::tGPRRegisterClass;
2176 RC = ARM::GPRRegisterClass;
2178 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2179 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2181 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2182 PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()),
2183 0, false, false, 0);
2184 MemOps.push_back(Store);
2185 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2186 DAG.getConstant(4, getPointerTy()));
2188 if (!MemOps.empty())
2189 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2190 &MemOps[0], MemOps.size());
2192 // This will point to the next argument passed via stack.
2193 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2199 /// isFloatingPointZero - Return true if this is +0.0.
2200 static bool isFloatingPointZero(SDValue Op) {
2201 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2202 return CFP->getValueAPF().isPosZero();
2203 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2204 // Maybe this has already been legalized into the constant pool?
2205 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2206 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2207 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2208 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2209 return CFP->getValueAPF().isPosZero();
2215 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2216 /// the given operands.
2218 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2219 SDValue &ARMCC, SelectionDAG &DAG,
2220 DebugLoc dl) const {
2221 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2222 unsigned C = RHSC->getZExtValue();
2223 if (!isLegalICmpImmediate(C)) {
2224 // Constant does not fit, try adjusting it by one?
2229 if (isLegalICmpImmediate(C-1)) {
2230 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2231 RHS = DAG.getConstant(C-1, MVT::i32);
2236 if (C > 0 && isLegalICmpImmediate(C-1)) {
2237 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2238 RHS = DAG.getConstant(C-1, MVT::i32);
2243 if (isLegalICmpImmediate(C+1)) {
2244 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2245 RHS = DAG.getConstant(C+1, MVT::i32);
2250 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
2251 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2252 RHS = DAG.getConstant(C+1, MVT::i32);
2259 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2260 ARMISD::NodeType CompareType;
2263 CompareType = ARMISD::CMP;
2268 CompareType = ARMISD::CMPZ;
2271 ARMCC = DAG.getConstant(CondCode, MVT::i32);
2272 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2275 static bool canBitcastToInt(SDNode *Op) {
2276 return Op->hasOneUse() &&
2277 ISD::isNormalLoad(Op) &&
2278 Op->getValueType(0) == MVT::f32;
2281 static SDValue bitcastToInt(SDValue Op, SelectionDAG &DAG) {
2282 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2283 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2284 Ld->getChain(), Ld->getBasePtr(),
2285 Ld->getSrcValue(), Ld->getSrcValueOffset(),
2286 Ld->isVolatile(), Ld->isNonTemporal(),
2287 Ld->getAlignment());
2289 llvm_unreachable("Unknown VFP cmp argument!");
2292 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2294 ARMTargetLowering::getVFPCmp(SDValue &LHS, SDValue &RHS, ISD::CondCode CC,
2295 SDValue &ARMCC, SelectionDAG &DAG,
2296 DebugLoc dl) const {
2297 if (UnsafeFPMath && FiniteOnlyFPMath() &&
2298 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2299 CC == ISD::SETNE || CC == ISD::SETUNE) &&
2300 canBitcastToInt(LHS.getNode()) && canBitcastToInt(RHS.getNode())) {
2301 // If unsafe fp math optimization is enabled and there are no othter uses of
2302 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2303 // to an integer comparison.
2304 if (CC == ISD::SETOEQ)
2306 else if (CC == ISD::SETUNE)
2308 LHS = bitcastToInt(LHS, DAG);
2309 RHS = bitcastToInt(RHS, DAG);
2310 return getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2314 if (!isFloatingPointZero(RHS))
2315 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2317 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2318 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2321 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2322 EVT VT = Op.getValueType();
2323 SDValue LHS = Op.getOperand(0);
2324 SDValue RHS = Op.getOperand(1);
2325 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2326 SDValue TrueVal = Op.getOperand(2);
2327 SDValue FalseVal = Op.getOperand(3);
2328 DebugLoc dl = Op.getDebugLoc();
2330 if (LHS.getValueType() == MVT::i32) {
2332 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2333 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2334 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
2337 ARMCC::CondCodes CondCode, CondCode2;
2338 FPCCToARMCC(CC, CondCode, CondCode2);
2340 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
2341 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2342 SDValue Cmp = getVFPCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2343 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2345 if (CondCode2 != ARMCC::AL) {
2346 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
2347 // FIXME: Needs another CMP because flag can have but one use.
2348 SDValue Cmp2 = getVFPCmp(LHS, RHS, CC, ARMCC2, DAG, dl);
2349 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2350 Result, TrueVal, ARMCC2, CCR, Cmp2);
2355 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2356 SDValue Chain = Op.getOperand(0);
2357 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2358 SDValue LHS = Op.getOperand(2);
2359 SDValue RHS = Op.getOperand(3);
2360 SDValue Dest = Op.getOperand(4);
2361 DebugLoc dl = Op.getDebugLoc();
2363 if (LHS.getValueType() == MVT::i32) {
2365 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2366 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2367 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2368 Chain, Dest, ARMCC, CCR,Cmp);
2371 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2372 ARMCC::CondCodes CondCode, CondCode2;
2373 FPCCToARMCC(CC, CondCode, CondCode2);
2375 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
2376 SDValue Cmp = getVFPCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2377 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2378 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2379 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
2380 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2381 if (CondCode2 != ARMCC::AL) {
2382 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
2383 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
2384 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2389 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2390 SDValue Chain = Op.getOperand(0);
2391 SDValue Table = Op.getOperand(1);
2392 SDValue Index = Op.getOperand(2);
2393 DebugLoc dl = Op.getDebugLoc();
2395 EVT PTy = getPointerTy();
2396 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2397 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2398 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2399 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2400 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2401 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2402 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2403 if (Subtarget->isThumb2()) {
2404 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2405 // which does another jump to the destination. This also makes it easier
2406 // to translate it to TBB / TBH later.
2407 // FIXME: This might not work if the function is extremely large.
2408 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2409 Addr, Op.getOperand(2), JTI, UId);
2411 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2412 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2413 PseudoSourceValue::getJumpTable(), 0,
2415 Chain = Addr.getValue(1);
2416 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2417 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2419 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2420 PseudoSourceValue::getJumpTable(), 0, false, false, 0);
2421 Chain = Addr.getValue(1);
2422 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2426 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2427 DebugLoc dl = Op.getDebugLoc();
2430 switch (Op.getOpcode()) {
2432 assert(0 && "Invalid opcode!");
2433 case ISD::FP_TO_SINT:
2434 Opc = ARMISD::FTOSI;
2436 case ISD::FP_TO_UINT:
2437 Opc = ARMISD::FTOUI;
2440 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2441 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2444 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2445 EVT VT = Op.getValueType();
2446 DebugLoc dl = Op.getDebugLoc();
2449 switch (Op.getOpcode()) {
2451 assert(0 && "Invalid opcode!");
2452 case ISD::SINT_TO_FP:
2453 Opc = ARMISD::SITOF;
2455 case ISD::UINT_TO_FP:
2456 Opc = ARMISD::UITOF;
2460 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2461 return DAG.getNode(Opc, dl, VT, Op);
2464 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2465 // Implement fcopysign with a fabs and a conditional fneg.
2466 SDValue Tmp0 = Op.getOperand(0);
2467 SDValue Tmp1 = Op.getOperand(1);
2468 DebugLoc dl = Op.getDebugLoc();
2469 EVT VT = Op.getValueType();
2470 EVT SrcVT = Tmp1.getValueType();
2471 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2472 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
2473 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2474 SDValue Cmp = getVFPCmp(Tmp1, FP0,
2475 ISD::SETLT, ARMCC, DAG, dl);
2476 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2477 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
2480 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2481 MachineFunction &MF = DAG.getMachineFunction();
2482 MachineFrameInfo *MFI = MF.getFrameInfo();
2483 MFI->setReturnAddressIsTaken(true);
2485 EVT VT = Op.getValueType();
2486 DebugLoc dl = Op.getDebugLoc();
2487 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2489 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2490 SDValue Offset = DAG.getConstant(4, MVT::i32);
2491 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2492 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2493 NULL, 0, false, false, 0);
2496 // Return LR, which contains the return address. Mark it an implicit live-in.
2497 unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass);
2498 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2501 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2502 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2503 MFI->setFrameAddressIsTaken(true);
2505 EVT VT = Op.getValueType();
2506 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2507 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2508 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2509 ? ARM::R7 : ARM::R11;
2510 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2512 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
2517 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2518 /// expand a bit convert where either the source or destination type is i64 to
2519 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2520 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2521 /// vectors), since the legalizer won't know what to do with that.
2522 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2523 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2524 DebugLoc dl = N->getDebugLoc();
2525 SDValue Op = N->getOperand(0);
2527 // This function is only supposed to be called for i64 types, either as the
2528 // source or destination of the bit convert.
2529 EVT SrcVT = Op.getValueType();
2530 EVT DstVT = N->getValueType(0);
2531 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2532 "ExpandBIT_CONVERT called for non-i64 type");
2534 // Turn i64->f64 into VMOVDRR.
2535 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2536 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2537 DAG.getConstant(0, MVT::i32));
2538 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2539 DAG.getConstant(1, MVT::i32));
2540 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2541 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2544 // Turn f64->i64 into VMOVRRD.
2545 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2546 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2547 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2548 // Merge the pieces into a single i64 value.
2549 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2555 /// getZeroVector - Returns a vector of specified type with all zero elements.
2557 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2558 assert(VT.isVector() && "Expected a vector type");
2560 // Zero vectors are used to represent vector negation and in those cases
2561 // will be implemented with the NEON VNEG instruction. However, VNEG does
2562 // not support i64 elements, so sometimes the zero vectors will need to be
2563 // explicitly constructed. For those cases, and potentially other uses in
2564 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
2565 // to their dest type. This ensures they get CSE'd.
2567 SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
2568 SmallVector<SDValue, 8> Ops;
2571 if (VT.getSizeInBits() == 64) {
2572 Ops.assign(8, Cst); TVT = MVT::v8i8;
2574 Ops.assign(16, Cst); TVT = MVT::v16i8;
2576 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2578 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2581 /// getOnesVector - Returns a vector of specified type with all bits set.
2583 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2584 assert(VT.isVector() && "Expected a vector type");
2586 // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their
2587 // dest type. This ensures they get CSE'd.
2589 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
2590 SmallVector<SDValue, 8> Ops;
2593 if (VT.getSizeInBits() == 64) {
2594 Ops.assign(8, Cst); TVT = MVT::v8i8;
2596 Ops.assign(16, Cst); TVT = MVT::v16i8;
2598 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2600 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2603 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2604 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2605 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2606 SelectionDAG &DAG) const {
2607 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2608 EVT VT = Op.getValueType();
2609 unsigned VTBits = VT.getSizeInBits();
2610 DebugLoc dl = Op.getDebugLoc();
2611 SDValue ShOpLo = Op.getOperand(0);
2612 SDValue ShOpHi = Op.getOperand(1);
2613 SDValue ShAmt = Op.getOperand(2);
2615 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2617 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2619 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2620 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2621 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2622 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2623 DAG.getConstant(VTBits, MVT::i32));
2624 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2625 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2626 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2628 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2629 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2631 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2632 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC,
2635 SDValue Ops[2] = { Lo, Hi };
2636 return DAG.getMergeValues(Ops, 2, dl);
2639 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2640 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2641 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2642 SelectionDAG &DAG) const {
2643 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2644 EVT VT = Op.getValueType();
2645 unsigned VTBits = VT.getSizeInBits();
2646 DebugLoc dl = Op.getDebugLoc();
2647 SDValue ShOpLo = Op.getOperand(0);
2648 SDValue ShOpHi = Op.getOperand(1);
2649 SDValue ShAmt = Op.getOperand(2);
2652 assert(Op.getOpcode() == ISD::SHL_PARTS);
2653 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2654 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2655 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2656 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2657 DAG.getConstant(VTBits, MVT::i32));
2658 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2659 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2661 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2662 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2663 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2665 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2666 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC,
2669 SDValue Ops[2] = { Lo, Hi };
2670 return DAG.getMergeValues(Ops, 2, dl);
2673 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2674 const ARMSubtarget *ST) {
2675 EVT VT = N->getValueType(0);
2676 DebugLoc dl = N->getDebugLoc();
2678 if (!ST->hasV6T2Ops())
2681 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2682 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2685 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2686 const ARMSubtarget *ST) {
2687 EVT VT = N->getValueType(0);
2688 DebugLoc dl = N->getDebugLoc();
2690 // Lower vector shifts on NEON to use VSHL.
2691 if (VT.isVector()) {
2692 assert(ST->hasNEON() && "unexpected vector shift");
2694 // Left shifts translate directly to the vshiftu intrinsic.
2695 if (N->getOpcode() == ISD::SHL)
2696 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2697 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2698 N->getOperand(0), N->getOperand(1));
2700 assert((N->getOpcode() == ISD::SRA ||
2701 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2703 // NEON uses the same intrinsics for both left and right shifts. For
2704 // right shifts, the shift amounts are negative, so negate the vector of
2706 EVT ShiftVT = N->getOperand(1).getValueType();
2707 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2708 getZeroVector(ShiftVT, DAG, dl),
2710 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2711 Intrinsic::arm_neon_vshifts :
2712 Intrinsic::arm_neon_vshiftu);
2713 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2714 DAG.getConstant(vshiftInt, MVT::i32),
2715 N->getOperand(0), NegatedCount);
2718 // We can get here for a node like i32 = ISD::SHL i32, i64
2722 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2723 "Unknown shift to lower!");
2725 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2726 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2727 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2730 // If we are in thumb mode, we don't have RRX.
2731 if (ST->isThumb1Only()) return SDValue();
2733 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2734 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2735 DAG.getConstant(0, MVT::i32));
2736 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2737 DAG.getConstant(1, MVT::i32));
2739 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2740 // captures the result into a carry flag.
2741 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2742 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2744 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2745 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2747 // Merge the pieces into a single i64 value.
2748 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2751 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2752 SDValue TmpOp0, TmpOp1;
2753 bool Invert = false;
2757 SDValue Op0 = Op.getOperand(0);
2758 SDValue Op1 = Op.getOperand(1);
2759 SDValue CC = Op.getOperand(2);
2760 EVT VT = Op.getValueType();
2761 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2762 DebugLoc dl = Op.getDebugLoc();
2764 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2765 switch (SetCCOpcode) {
2766 default: llvm_unreachable("Illegal FP comparison"); break;
2768 case ISD::SETNE: Invert = true; // Fallthrough
2770 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2772 case ISD::SETLT: Swap = true; // Fallthrough
2774 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2776 case ISD::SETLE: Swap = true; // Fallthrough
2778 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2779 case ISD::SETUGE: Swap = true; // Fallthrough
2780 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2781 case ISD::SETUGT: Swap = true; // Fallthrough
2782 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2783 case ISD::SETUEQ: Invert = true; // Fallthrough
2785 // Expand this to (OLT | OGT).
2789 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2790 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2792 case ISD::SETUO: Invert = true; // Fallthrough
2794 // Expand this to (OLT | OGE).
2798 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2799 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2803 // Integer comparisons.
2804 switch (SetCCOpcode) {
2805 default: llvm_unreachable("Illegal integer comparison"); break;
2806 case ISD::SETNE: Invert = true;
2807 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2808 case ISD::SETLT: Swap = true;
2809 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2810 case ISD::SETLE: Swap = true;
2811 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2812 case ISD::SETULT: Swap = true;
2813 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2814 case ISD::SETULE: Swap = true;
2815 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2818 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2819 if (Opc == ARMISD::VCEQ) {
2822 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2824 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2827 // Ignore bitconvert.
2828 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2829 AndOp = AndOp.getOperand(0);
2831 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2833 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2834 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2841 std::swap(Op0, Op1);
2843 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2846 Result = DAG.getNOT(dl, Result, VT);
2851 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
2852 /// valid vector constant for a NEON instruction with a "modified immediate"
2853 /// operand (e.g., VMOV). If so, return either the constant being
2854 /// splatted or the encoded value, depending on the DoEncode parameter.
2855 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
2856 unsigned SplatBitSize, SelectionDAG &DAG,
2857 bool isVMOV, bool DoEncode) {
2858 unsigned OpCmode, Imm;
2861 // SplatBitSize is set to the smallest size that splats the vector, so a
2862 // zero vector will always have SplatBitSize == 8. However, NEON modified
2863 // immediate instructions others than VMOV do not support the 8-bit encoding
2864 // of a zero vector, and the default encoding of zero is supposed to be the
2869 switch (SplatBitSize) {
2871 // Any 1-byte value is OK. Op=0, Cmode=1110.
2872 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2879 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2881 if ((SplatBits & ~0xff) == 0) {
2882 // Value = 0x00nn: Op=x, Cmode=100x.
2887 if ((SplatBits & ~0xff00) == 0) {
2888 // Value = 0xnn00: Op=x, Cmode=101x.
2890 Imm = SplatBits >> 8;
2896 // NEON's 32-bit VMOV supports splat values where:
2897 // * only one byte is nonzero, or
2898 // * the least significant byte is 0xff and the second byte is nonzero, or
2899 // * the least significant 2 bytes are 0xff and the third is nonzero.
2901 if ((SplatBits & ~0xff) == 0) {
2902 // Value = 0x000000nn: Op=x, Cmode=000x.
2907 if ((SplatBits & ~0xff00) == 0) {
2908 // Value = 0x0000nn00: Op=x, Cmode=001x.
2910 Imm = SplatBits >> 8;
2913 if ((SplatBits & ~0xff0000) == 0) {
2914 // Value = 0x00nn0000: Op=x, Cmode=010x.
2916 Imm = SplatBits >> 16;
2919 if ((SplatBits & ~0xff000000) == 0) {
2920 // Value = 0xnn000000: Op=x, Cmode=011x.
2922 Imm = SplatBits >> 24;
2926 if ((SplatBits & ~0xffff) == 0 &&
2927 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
2928 // Value = 0x0000nnff: Op=x, Cmode=1100.
2930 Imm = SplatBits >> 8;
2935 if ((SplatBits & ~0xffffff) == 0 &&
2936 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
2937 // Value = 0x00nnffff: Op=x, Cmode=1101.
2939 Imm = SplatBits >> 16;
2940 SplatBits |= 0xffff;
2944 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2945 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2946 // VMOV.I32. A (very) minor optimization would be to replicate the value
2947 // and fall through here to test for a valid 64-bit splat. But, then the
2948 // caller would also need to check and handle the change in size.
2952 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2955 uint64_t BitMask = 0xff;
2957 unsigned ImmMask = 1;
2959 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2960 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
2963 } else if ((SplatBits & BitMask) != 0) {
2969 // Op=1, Cmode=1110.
2977 llvm_unreachable("unexpected size for isNEONModifiedImm");
2982 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
2983 return DAG.getTargetConstant(EncodedVal, MVT::i32);
2985 return DAG.getTargetConstant(SplatBits, VT);
2988 /// getNEONModImm - If this is a valid vector constant for a NEON instruction
2989 /// with a "modified immediate" operand (e.g., VMOV) of the specified element
2990 /// size, return the encoded value for that immediate. The ByteSize field
2991 /// indicates the number of bytes of each element [1248].
2992 SDValue ARM::getNEONModImm(SDNode *N, unsigned ByteSize, bool isVMOV,
2993 SelectionDAG &DAG) {
2994 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2995 APInt SplatBits, SplatUndef;
2996 unsigned SplatBitSize;
2998 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2999 HasAnyUndefs, ByteSize * 8))
3002 if (SplatBitSize > ByteSize * 8)
3005 return isNEONModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
3006 SplatBitSize, DAG, isVMOV, true);
3009 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3010 bool &ReverseVEXT, unsigned &Imm) {
3011 unsigned NumElts = VT.getVectorNumElements();
3012 ReverseVEXT = false;
3015 // If this is a VEXT shuffle, the immediate value is the index of the first
3016 // element. The other shuffle indices must be the successive elements after
3018 unsigned ExpectedElt = Imm;
3019 for (unsigned i = 1; i < NumElts; ++i) {
3020 // Increment the expected index. If it wraps around, it may still be
3021 // a VEXT but the source vectors must be swapped.
3023 if (ExpectedElt == NumElts * 2) {
3028 if (ExpectedElt != static_cast<unsigned>(M[i]))
3032 // Adjust the index value if the source operands will be swapped.
3039 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3040 /// instruction with the specified blocksize. (The order of the elements
3041 /// within each block of the vector is reversed.)
3042 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3043 unsigned BlockSize) {
3044 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3045 "Only possible block sizes for VREV are: 16, 32, 64");
3047 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3051 unsigned NumElts = VT.getVectorNumElements();
3052 unsigned BlockElts = M[0] + 1;
3054 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3057 for (unsigned i = 0; i < NumElts; ++i) {
3058 if ((unsigned) M[i] !=
3059 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3066 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3067 unsigned &WhichResult) {
3068 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3072 unsigned NumElts = VT.getVectorNumElements();
3073 WhichResult = (M[0] == 0 ? 0 : 1);
3074 for (unsigned i = 0; i < NumElts; i += 2) {
3075 if ((unsigned) M[i] != i + WhichResult ||
3076 (unsigned) M[i+1] != i + NumElts + WhichResult)
3082 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3083 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3084 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3085 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3086 unsigned &WhichResult) {
3087 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3091 unsigned NumElts = VT.getVectorNumElements();
3092 WhichResult = (M[0] == 0 ? 0 : 1);
3093 for (unsigned i = 0; i < NumElts; i += 2) {
3094 if ((unsigned) M[i] != i + WhichResult ||
3095 (unsigned) M[i+1] != i + WhichResult)
3101 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3102 unsigned &WhichResult) {
3103 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3107 unsigned NumElts = VT.getVectorNumElements();
3108 WhichResult = (M[0] == 0 ? 0 : 1);
3109 for (unsigned i = 0; i != NumElts; ++i) {
3110 if ((unsigned) M[i] != 2 * i + WhichResult)
3114 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3115 if (VT.is64BitVector() && EltSz == 32)
3121 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3122 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3123 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3124 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3125 unsigned &WhichResult) {
3126 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3130 unsigned Half = VT.getVectorNumElements() / 2;
3131 WhichResult = (M[0] == 0 ? 0 : 1);
3132 for (unsigned j = 0; j != 2; ++j) {
3133 unsigned Idx = WhichResult;
3134 for (unsigned i = 0; i != Half; ++i) {
3135 if ((unsigned) M[i + j * Half] != Idx)
3141 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3142 if (VT.is64BitVector() && EltSz == 32)
3148 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3149 unsigned &WhichResult) {
3150 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3154 unsigned NumElts = VT.getVectorNumElements();
3155 WhichResult = (M[0] == 0 ? 0 : 1);
3156 unsigned Idx = WhichResult * NumElts / 2;
3157 for (unsigned i = 0; i != NumElts; i += 2) {
3158 if ((unsigned) M[i] != Idx ||
3159 (unsigned) M[i+1] != Idx + NumElts)
3164 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3165 if (VT.is64BitVector() && EltSz == 32)
3171 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3172 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3173 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3174 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3175 unsigned &WhichResult) {
3176 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3180 unsigned NumElts = VT.getVectorNumElements();
3181 WhichResult = (M[0] == 0 ? 0 : 1);
3182 unsigned Idx = WhichResult * NumElts / 2;
3183 for (unsigned i = 0; i != NumElts; i += 2) {
3184 if ((unsigned) M[i] != Idx ||
3185 (unsigned) M[i+1] != Idx)
3190 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3191 if (VT.is64BitVector() && EltSz == 32)
3198 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3199 // Canonicalize all-zeros and all-ones vectors.
3200 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
3201 if (ConstVal->isNullValue())
3202 return getZeroVector(VT, DAG, dl);
3203 if (ConstVal->isAllOnesValue())
3204 return getOnesVector(VT, DAG, dl);
3207 if (VT.is64BitVector()) {
3208 switch (Val.getValueType().getSizeInBits()) {
3209 case 8: CanonicalVT = MVT::v8i8; break;
3210 case 16: CanonicalVT = MVT::v4i16; break;
3211 case 32: CanonicalVT = MVT::v2i32; break;
3212 case 64: CanonicalVT = MVT::v1i64; break;
3213 default: llvm_unreachable("unexpected splat element type"); break;
3216 assert(VT.is128BitVector() && "unknown splat vector size");
3217 switch (Val.getValueType().getSizeInBits()) {
3218 case 8: CanonicalVT = MVT::v16i8; break;
3219 case 16: CanonicalVT = MVT::v8i16; break;
3220 case 32: CanonicalVT = MVT::v4i32; break;
3221 case 64: CanonicalVT = MVT::v2i64; break;
3222 default: llvm_unreachable("unexpected splat element type"); break;
3226 // Build a canonical splat for this value.
3227 SmallVector<SDValue, 8> Ops;
3228 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
3229 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
3231 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
3234 // If this is a case we can't handle, return null and let the default
3235 // expansion code take care of it.
3236 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3237 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3238 DebugLoc dl = Op.getDebugLoc();
3239 EVT VT = Op.getValueType();
3241 APInt SplatBits, SplatUndef;
3242 unsigned SplatBitSize;
3244 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3245 if (SplatBitSize <= 64) {
3246 // Check if an immediate VMOV works.
3247 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3248 SplatUndef.getZExtValue(),
3249 SplatBitSize, DAG, true, false);
3251 return BuildSplat(Val, VT, DAG, dl);
3255 // Scan through the operands to see if only one value is used.
3256 unsigned NumElts = VT.getVectorNumElements();
3257 bool isOnlyLowElement = true;
3258 bool usesOnlyOneValue = true;
3259 bool isConstant = true;
3261 for (unsigned i = 0; i < NumElts; ++i) {
3262 SDValue V = Op.getOperand(i);
3263 if (V.getOpcode() == ISD::UNDEF)
3266 isOnlyLowElement = false;
3267 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3270 if (!Value.getNode())
3272 else if (V != Value)
3273 usesOnlyOneValue = false;
3276 if (!Value.getNode())
3277 return DAG.getUNDEF(VT);
3279 if (isOnlyLowElement)
3280 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3282 // If all elements are constants, fall back to the default expansion, which
3283 // will generate a load from the constant pool.
3287 // Use VDUP for non-constant splats.
3288 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3289 if (usesOnlyOneValue && EltSize <= 32)
3290 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3292 // Vectors with 32- or 64-bit elements can be built by directly assigning
3293 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3294 // will be legalized.
3295 if (EltSize >= 32) {
3296 // Do the expansion with floating-point types, since that is what the VFP
3297 // registers are defined to use, and since i64 is not legal.
3298 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3299 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3300 SmallVector<SDValue, 8> Ops;
3301 for (unsigned i = 0; i < NumElts; ++i)
3302 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3303 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3304 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3310 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3311 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3312 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3313 /// are assumed to be legal.
3315 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3317 if (VT.getVectorNumElements() == 4 &&
3318 (VT.is128BitVector() || VT.is64BitVector())) {
3319 unsigned PFIndexes[4];
3320 for (unsigned i = 0; i != 4; ++i) {
3324 PFIndexes[i] = M[i];
3327 // Compute the index in the perfect shuffle table.
3328 unsigned PFTableIndex =
3329 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3330 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3331 unsigned Cost = (PFEntry >> 30);
3338 unsigned Imm, WhichResult;
3340 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3341 return (EltSize >= 32 ||
3342 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3343 isVREVMask(M, VT, 64) ||
3344 isVREVMask(M, VT, 32) ||
3345 isVREVMask(M, VT, 16) ||
3346 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3347 isVTRNMask(M, VT, WhichResult) ||
3348 isVUZPMask(M, VT, WhichResult) ||
3349 isVZIPMask(M, VT, WhichResult) ||
3350 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3351 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3352 isVZIP_v_undef_Mask(M, VT, WhichResult));
3355 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3356 /// the specified operations to build the shuffle.
3357 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3358 SDValue RHS, SelectionDAG &DAG,
3360 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3361 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3362 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3365 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3374 OP_VUZPL, // VUZP, left result
3375 OP_VUZPR, // VUZP, right result
3376 OP_VZIPL, // VZIP, left result
3377 OP_VZIPR, // VZIP, right result
3378 OP_VTRNL, // VTRN, left result
3379 OP_VTRNR // VTRN, right result
3382 if (OpNum == OP_COPY) {
3383 if (LHSID == (1*9+2)*9+3) return LHS;
3384 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3388 SDValue OpLHS, OpRHS;
3389 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3390 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3391 EVT VT = OpLHS.getValueType();
3394 default: llvm_unreachable("Unknown shuffle opcode!");
3396 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3401 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3402 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3406 return DAG.getNode(ARMISD::VEXT, dl, VT,
3408 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3411 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3412 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3415 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3416 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3419 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3420 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3424 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3425 SDValue V1 = Op.getOperand(0);
3426 SDValue V2 = Op.getOperand(1);
3427 DebugLoc dl = Op.getDebugLoc();
3428 EVT VT = Op.getValueType();
3429 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3430 SmallVector<int, 8> ShuffleMask;
3432 // Convert shuffles that are directly supported on NEON to target-specific
3433 // DAG nodes, instead of keeping them as shuffles and matching them again
3434 // during code selection. This is more efficient and avoids the possibility
3435 // of inconsistencies between legalization and selection.
3436 // FIXME: floating-point vectors should be canonicalized to integer vectors
3437 // of the same time so that they get CSEd properly.
3438 SVN->getMask(ShuffleMask);
3440 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3441 if (EltSize <= 32) {
3442 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3443 int Lane = SVN->getSplatIndex();
3444 // If this is undef splat, generate it via "just" vdup, if possible.
3445 if (Lane == -1) Lane = 0;
3447 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3448 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3450 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3451 DAG.getConstant(Lane, MVT::i32));
3456 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3459 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3460 DAG.getConstant(Imm, MVT::i32));
3463 if (isVREVMask(ShuffleMask, VT, 64))
3464 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3465 if (isVREVMask(ShuffleMask, VT, 32))
3466 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3467 if (isVREVMask(ShuffleMask, VT, 16))
3468 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3470 // Check for Neon shuffles that modify both input vectors in place.
3471 // If both results are used, i.e., if there are two shuffles with the same
3472 // source operands and with masks corresponding to both results of one of
3473 // these operations, DAG memoization will ensure that a single node is
3474 // used for both shuffles.
3475 unsigned WhichResult;
3476 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3477 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3478 V1, V2).getValue(WhichResult);
3479 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3480 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3481 V1, V2).getValue(WhichResult);
3482 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3483 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3484 V1, V2).getValue(WhichResult);
3486 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3487 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3488 V1, V1).getValue(WhichResult);
3489 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3490 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3491 V1, V1).getValue(WhichResult);
3492 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3493 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3494 V1, V1).getValue(WhichResult);
3497 // If the shuffle is not directly supported and it has 4 elements, use
3498 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3499 unsigned NumElts = VT.getVectorNumElements();
3501 unsigned PFIndexes[4];
3502 for (unsigned i = 0; i != 4; ++i) {
3503 if (ShuffleMask[i] < 0)
3506 PFIndexes[i] = ShuffleMask[i];
3509 // Compute the index in the perfect shuffle table.
3510 unsigned PFTableIndex =
3511 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3512 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3513 unsigned Cost = (PFEntry >> 30);
3516 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3519 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3520 if (EltSize >= 32) {
3521 // Do the expansion with floating-point types, since that is what the VFP
3522 // registers are defined to use, and since i64 is not legal.
3523 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3524 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3525 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3526 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3527 SmallVector<SDValue, 8> Ops;
3528 for (unsigned i = 0; i < NumElts; ++i) {
3529 if (ShuffleMask[i] < 0)
3530 Ops.push_back(DAG.getUNDEF(EltVT));
3532 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3533 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3534 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3537 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3538 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3544 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3545 EVT VT = Op.getValueType();
3546 DebugLoc dl = Op.getDebugLoc();
3547 SDValue Vec = Op.getOperand(0);
3548 SDValue Lane = Op.getOperand(1);
3549 assert(VT == MVT::i32 &&
3550 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3551 "unexpected type for custom-lowering vector extract");
3552 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3555 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3556 // The only time a CONCAT_VECTORS operation can have legal types is when
3557 // two 64-bit vectors are concatenated to a 128-bit vector.
3558 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3559 "unexpected CONCAT_VECTORS");
3560 DebugLoc dl = Op.getDebugLoc();
3561 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3562 SDValue Op0 = Op.getOperand(0);
3563 SDValue Op1 = Op.getOperand(1);
3564 if (Op0.getOpcode() != ISD::UNDEF)
3565 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3566 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3567 DAG.getIntPtrConstant(0));
3568 if (Op1.getOpcode() != ISD::UNDEF)
3569 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3570 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3571 DAG.getIntPtrConstant(1));
3572 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3575 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3576 switch (Op.getOpcode()) {
3577 default: llvm_unreachable("Don't know how to custom lower this!");
3578 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3579 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3580 case ISD::GlobalAddress:
3581 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3582 LowerGlobalAddressELF(Op, DAG);
3583 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3584 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3585 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3586 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3587 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3588 case ISD::VASTART: return LowerVASTART(Op, DAG);
3589 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3590 case ISD::SINT_TO_FP:
3591 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3592 case ISD::FP_TO_SINT:
3593 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3594 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3595 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3596 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3597 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3598 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3599 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3600 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3602 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3605 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3606 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3607 case ISD::SRL_PARTS:
3608 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3609 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3610 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3611 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3612 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3613 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3614 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3619 /// ReplaceNodeResults - Replace the results of node with an illegal result
3620 /// type with new values built out of custom code.
3621 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3622 SmallVectorImpl<SDValue>&Results,
3623 SelectionDAG &DAG) const {
3625 switch (N->getOpcode()) {
3627 llvm_unreachable("Don't know how to custom expand this!");
3629 case ISD::BIT_CONVERT:
3630 Res = ExpandBIT_CONVERT(N, DAG);
3634 Res = LowerShift(N, DAG, Subtarget);
3638 Results.push_back(Res);
3641 //===----------------------------------------------------------------------===//
3642 // ARM Scheduler Hooks
3643 //===----------------------------------------------------------------------===//
3646 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3647 MachineBasicBlock *BB,
3648 unsigned Size) const {
3649 unsigned dest = MI->getOperand(0).getReg();
3650 unsigned ptr = MI->getOperand(1).getReg();
3651 unsigned oldval = MI->getOperand(2).getReg();
3652 unsigned newval = MI->getOperand(3).getReg();
3653 unsigned scratch = BB->getParent()->getRegInfo()
3654 .createVirtualRegister(ARM::GPRRegisterClass);
3655 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3656 DebugLoc dl = MI->getDebugLoc();
3657 bool isThumb2 = Subtarget->isThumb2();
3659 unsigned ldrOpc, strOpc;
3661 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3663 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3664 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3667 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3668 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3671 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3672 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3676 MachineFunction *MF = BB->getParent();
3677 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3678 MachineFunction::iterator It = BB;
3679 ++It; // insert the new blocks after the current block
3681 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3682 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3683 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3684 MF->insert(It, loop1MBB);
3685 MF->insert(It, loop2MBB);
3686 MF->insert(It, exitMBB);
3688 // Transfer the remainder of BB and its successor edges to exitMBB.
3689 exitMBB->splice(exitMBB->begin(), BB,
3690 llvm::next(MachineBasicBlock::iterator(MI)),
3692 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3696 // fallthrough --> loop1MBB
3697 BB->addSuccessor(loop1MBB);
3700 // ldrex dest, [ptr]
3704 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3705 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3706 .addReg(dest).addReg(oldval));
3707 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3708 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3709 BB->addSuccessor(loop2MBB);
3710 BB->addSuccessor(exitMBB);
3713 // strex scratch, newval, [ptr]
3717 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3719 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3720 .addReg(scratch).addImm(0));
3721 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3722 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3723 BB->addSuccessor(loop1MBB);
3724 BB->addSuccessor(exitMBB);
3730 MI->eraseFromParent(); // The instruction is gone now.
3736 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3737 unsigned Size, unsigned BinOpcode) const {
3738 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3739 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3741 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3742 MachineFunction *MF = BB->getParent();
3743 MachineFunction::iterator It = BB;
3746 unsigned dest = MI->getOperand(0).getReg();
3747 unsigned ptr = MI->getOperand(1).getReg();
3748 unsigned incr = MI->getOperand(2).getReg();
3749 DebugLoc dl = MI->getDebugLoc();
3751 bool isThumb2 = Subtarget->isThumb2();
3752 unsigned ldrOpc, strOpc;
3754 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3756 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3757 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3760 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3761 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3764 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3765 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3769 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3770 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3771 MF->insert(It, loopMBB);
3772 MF->insert(It, exitMBB);
3774 // Transfer the remainder of BB and its successor edges to exitMBB.
3775 exitMBB->splice(exitMBB->begin(), BB,
3776 llvm::next(MachineBasicBlock::iterator(MI)),
3778 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3780 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3781 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3782 unsigned scratch2 = (!BinOpcode) ? incr :
3783 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3787 // fallthrough --> loopMBB
3788 BB->addSuccessor(loopMBB);
3792 // <binop> scratch2, dest, incr
3793 // strex scratch, scratch2, ptr
3796 // fallthrough --> exitMBB
3798 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3800 // operand order needs to go the other way for NAND
3801 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3802 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3803 addReg(incr).addReg(dest)).addReg(0);
3805 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3806 addReg(dest).addReg(incr)).addReg(0);
3809 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3811 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3812 .addReg(scratch).addImm(0));
3813 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3814 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3816 BB->addSuccessor(loopMBB);
3817 BB->addSuccessor(exitMBB);
3823 MI->eraseFromParent(); // The instruction is gone now.
3829 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3830 MachineBasicBlock *BB) const {
3831 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3832 DebugLoc dl = MI->getDebugLoc();
3833 bool isThumb2 = Subtarget->isThumb2();
3834 switch (MI->getOpcode()) {
3837 llvm_unreachable("Unexpected instr type to insert");
3839 case ARM::ATOMIC_LOAD_ADD_I8:
3840 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3841 case ARM::ATOMIC_LOAD_ADD_I16:
3842 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3843 case ARM::ATOMIC_LOAD_ADD_I32:
3844 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3846 case ARM::ATOMIC_LOAD_AND_I8:
3847 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3848 case ARM::ATOMIC_LOAD_AND_I16:
3849 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3850 case ARM::ATOMIC_LOAD_AND_I32:
3851 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3853 case ARM::ATOMIC_LOAD_OR_I8:
3854 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3855 case ARM::ATOMIC_LOAD_OR_I16:
3856 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3857 case ARM::ATOMIC_LOAD_OR_I32:
3858 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3860 case ARM::ATOMIC_LOAD_XOR_I8:
3861 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3862 case ARM::ATOMIC_LOAD_XOR_I16:
3863 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3864 case ARM::ATOMIC_LOAD_XOR_I32:
3865 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3867 case ARM::ATOMIC_LOAD_NAND_I8:
3868 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3869 case ARM::ATOMIC_LOAD_NAND_I16:
3870 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3871 case ARM::ATOMIC_LOAD_NAND_I32:
3872 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3874 case ARM::ATOMIC_LOAD_SUB_I8:
3875 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3876 case ARM::ATOMIC_LOAD_SUB_I16:
3877 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3878 case ARM::ATOMIC_LOAD_SUB_I32:
3879 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3881 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3882 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3883 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
3885 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3886 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3887 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
3889 case ARM::tMOVCCr_pseudo: {
3890 // To "insert" a SELECT_CC instruction, we actually have to insert the
3891 // diamond control-flow pattern. The incoming instruction knows the
3892 // destination vreg to set, the condition code register to branch on, the
3893 // true/false values to select between, and a branch opcode to use.
3894 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3895 MachineFunction::iterator It = BB;
3901 // cmpTY ccX, r1, r2
3903 // fallthrough --> copy0MBB
3904 MachineBasicBlock *thisMBB = BB;
3905 MachineFunction *F = BB->getParent();
3906 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3907 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3908 F->insert(It, copy0MBB);
3909 F->insert(It, sinkMBB);
3911 // Transfer the remainder of BB and its successor edges to sinkMBB.
3912 sinkMBB->splice(sinkMBB->begin(), BB,
3913 llvm::next(MachineBasicBlock::iterator(MI)),
3915 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3917 BB->addSuccessor(copy0MBB);
3918 BB->addSuccessor(sinkMBB);
3920 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
3921 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
3924 // %FalseValue = ...
3925 // # fallthrough to sinkMBB
3928 // Update machine-CFG edges
3929 BB->addSuccessor(sinkMBB);
3932 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3935 BuildMI(*BB, BB->begin(), dl,
3936 TII->get(ARM::PHI), MI->getOperand(0).getReg())
3937 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
3938 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3940 MI->eraseFromParent(); // The pseudo instruction is gone now.
3947 case ARM::t2SUBrSPi_:
3948 case ARM::t2SUBrSPi12_:
3949 case ARM::t2SUBrSPs_: {
3950 MachineFunction *MF = BB->getParent();
3951 unsigned DstReg = MI->getOperand(0).getReg();
3952 unsigned SrcReg = MI->getOperand(1).getReg();
3953 bool DstIsDead = MI->getOperand(0).isDead();
3954 bool SrcIsKill = MI->getOperand(1).isKill();
3956 if (SrcReg != ARM::SP) {
3957 // Copy the source to SP from virtual register.
3958 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
3959 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3960 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
3961 BuildMI(*BB, MI, dl, TII->get(CopyOpc), ARM::SP)
3962 .addReg(SrcReg, getKillRegState(SrcIsKill));
3966 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
3967 switch (MI->getOpcode()) {
3969 llvm_unreachable("Unexpected pseudo instruction!");
3975 OpOpc = ARM::tADDspr;
3978 OpOpc = ARM::tSUBspi;
3980 case ARM::t2SUBrSPi_:
3981 OpOpc = ARM::t2SUBrSPi;
3982 NeedPred = true; NeedCC = true;
3984 case ARM::t2SUBrSPi12_:
3985 OpOpc = ARM::t2SUBrSPi12;
3988 case ARM::t2SUBrSPs_:
3989 OpOpc = ARM::t2SUBrSPs;
3990 NeedPred = true; NeedCC = true; NeedOp3 = true;
3993 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(OpOpc), ARM::SP);
3994 if (OpOpc == ARM::tAND)
3995 AddDefaultT1CC(MIB);
3996 MIB.addReg(ARM::SP);
3997 MIB.addOperand(MI->getOperand(2));
3999 MIB.addOperand(MI->getOperand(3));
4001 AddDefaultPred(MIB);
4005 // Copy the result from SP to virtual register.
4006 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
4007 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
4008 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
4009 BuildMI(*BB, MI, dl, TII->get(CopyOpc))
4010 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
4012 MI->eraseFromParent(); // The pseudo instruction is gone now.
4018 //===----------------------------------------------------------------------===//
4019 // ARM Optimization Hooks
4020 //===----------------------------------------------------------------------===//
4023 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4024 TargetLowering::DAGCombinerInfo &DCI) {
4025 SelectionDAG &DAG = DCI.DAG;
4026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4027 EVT VT = N->getValueType(0);
4028 unsigned Opc = N->getOpcode();
4029 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4030 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4031 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4032 ISD::CondCode CC = ISD::SETCC_INVALID;
4035 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4037 SDValue CCOp = Slct.getOperand(0);
4038 if (CCOp.getOpcode() == ISD::SETCC)
4039 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4042 bool DoXform = false;
4044 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4047 if (LHS.getOpcode() == ISD::Constant &&
4048 cast<ConstantSDNode>(LHS)->isNullValue()) {
4050 } else if (CC != ISD::SETCC_INVALID &&
4051 RHS.getOpcode() == ISD::Constant &&
4052 cast<ConstantSDNode>(RHS)->isNullValue()) {
4053 std::swap(LHS, RHS);
4054 SDValue Op0 = Slct.getOperand(0);
4055 EVT OpVT = isSlctCC ? Op0.getValueType() :
4056 Op0.getOperand(0).getValueType();
4057 bool isInt = OpVT.isInteger();
4058 CC = ISD::getSetCCInverse(CC, isInt);
4060 if (!TLI.isCondCodeLegal(CC, OpVT))
4061 return SDValue(); // Inverse operator isn't legal.
4068 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4070 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4071 Slct.getOperand(0), Slct.getOperand(1), CC);
4072 SDValue CCOp = Slct.getOperand(0);
4074 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4075 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4076 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4077 CCOp, OtherOp, Result);
4082 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4083 static SDValue PerformADDCombine(SDNode *N,
4084 TargetLowering::DAGCombinerInfo &DCI) {
4085 // added by evan in r37685 with no testcase.
4086 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4088 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4089 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4090 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4091 if (Result.getNode()) return Result;
4093 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4094 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4095 if (Result.getNode()) return Result;
4101 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4102 static SDValue PerformSUBCombine(SDNode *N,
4103 TargetLowering::DAGCombinerInfo &DCI) {
4104 // added by evan in r37685 with no testcase.
4105 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4107 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4108 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4109 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4110 if (Result.getNode()) return Result;
4116 static SDValue PerformMULCombine(SDNode *N,
4117 TargetLowering::DAGCombinerInfo &DCI,
4118 const ARMSubtarget *Subtarget) {
4119 SelectionDAG &DAG = DCI.DAG;
4121 if (Subtarget->isThumb1Only())
4124 if (DAG.getMachineFunction().
4125 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
4128 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4131 EVT VT = N->getValueType(0);
4135 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4139 uint64_t MulAmt = C->getZExtValue();
4140 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4141 ShiftAmt = ShiftAmt & (32 - 1);
4142 SDValue V = N->getOperand(0);
4143 DebugLoc DL = N->getDebugLoc();
4146 MulAmt >>= ShiftAmt;
4147 if (isPowerOf2_32(MulAmt - 1)) {
4148 // (mul x, 2^N + 1) => (add (shl x, N), x)
4149 Res = DAG.getNode(ISD::ADD, DL, VT,
4150 V, DAG.getNode(ISD::SHL, DL, VT,
4151 V, DAG.getConstant(Log2_32(MulAmt-1),
4153 } else if (isPowerOf2_32(MulAmt + 1)) {
4154 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4155 Res = DAG.getNode(ISD::SUB, DL, VT,
4156 DAG.getNode(ISD::SHL, DL, VT,
4157 V, DAG.getConstant(Log2_32(MulAmt+1),
4164 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4165 DAG.getConstant(ShiftAmt, MVT::i32));
4167 // Do not add new nodes to DAG combiner worklist.
4168 DCI.CombineTo(N, Res, false);
4172 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4173 /// ARMISD::VMOVRRD.
4174 static SDValue PerformVMOVRRDCombine(SDNode *N,
4175 TargetLowering::DAGCombinerInfo &DCI) {
4176 // fmrrd(fmdrr x, y) -> x,y
4177 SDValue InDouble = N->getOperand(0);
4178 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4179 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4183 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4184 /// operand of a vector shift operation, where all the elements of the
4185 /// build_vector must have the same constant integer value.
4186 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4187 // Ignore bit_converts.
4188 while (Op.getOpcode() == ISD::BIT_CONVERT)
4189 Op = Op.getOperand(0);
4190 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4191 APInt SplatBits, SplatUndef;
4192 unsigned SplatBitSize;
4194 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4195 HasAnyUndefs, ElementBits) ||
4196 SplatBitSize > ElementBits)
4198 Cnt = SplatBits.getSExtValue();
4202 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4203 /// operand of a vector shift left operation. That value must be in the range:
4204 /// 0 <= Value < ElementBits for a left shift; or
4205 /// 0 <= Value <= ElementBits for a long left shift.
4206 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4207 assert(VT.isVector() && "vector shift count is not a vector type");
4208 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4209 if (! getVShiftImm(Op, ElementBits, Cnt))
4211 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4214 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4215 /// operand of a vector shift right operation. For a shift opcode, the value
4216 /// is positive, but for an intrinsic the value count must be negative. The
4217 /// absolute value must be in the range:
4218 /// 1 <= |Value| <= ElementBits for a right shift; or
4219 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4220 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4222 assert(VT.isVector() && "vector shift count is not a vector type");
4223 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4224 if (! getVShiftImm(Op, ElementBits, Cnt))
4228 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4231 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4232 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4233 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4236 // Don't do anything for most intrinsics.
4239 // Vector shifts: check for immediate versions and lower them.
4240 // Note: This is done during DAG combining instead of DAG legalizing because
4241 // the build_vectors for 64-bit vector element shift counts are generally
4242 // not legal, and it is hard to see their values after they get legalized to
4243 // loads from a constant pool.
4244 case Intrinsic::arm_neon_vshifts:
4245 case Intrinsic::arm_neon_vshiftu:
4246 case Intrinsic::arm_neon_vshiftls:
4247 case Intrinsic::arm_neon_vshiftlu:
4248 case Intrinsic::arm_neon_vshiftn:
4249 case Intrinsic::arm_neon_vrshifts:
4250 case Intrinsic::arm_neon_vrshiftu:
4251 case Intrinsic::arm_neon_vrshiftn:
4252 case Intrinsic::arm_neon_vqshifts:
4253 case Intrinsic::arm_neon_vqshiftu:
4254 case Intrinsic::arm_neon_vqshiftsu:
4255 case Intrinsic::arm_neon_vqshiftns:
4256 case Intrinsic::arm_neon_vqshiftnu:
4257 case Intrinsic::arm_neon_vqshiftnsu:
4258 case Intrinsic::arm_neon_vqrshiftns:
4259 case Intrinsic::arm_neon_vqrshiftnu:
4260 case Intrinsic::arm_neon_vqrshiftnsu: {
4261 EVT VT = N->getOperand(1).getValueType();
4263 unsigned VShiftOpc = 0;
4266 case Intrinsic::arm_neon_vshifts:
4267 case Intrinsic::arm_neon_vshiftu:
4268 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4269 VShiftOpc = ARMISD::VSHL;
4272 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4273 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4274 ARMISD::VSHRs : ARMISD::VSHRu);
4279 case Intrinsic::arm_neon_vshiftls:
4280 case Intrinsic::arm_neon_vshiftlu:
4281 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4283 llvm_unreachable("invalid shift count for vshll intrinsic");
4285 case Intrinsic::arm_neon_vrshifts:
4286 case Intrinsic::arm_neon_vrshiftu:
4287 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4291 case Intrinsic::arm_neon_vqshifts:
4292 case Intrinsic::arm_neon_vqshiftu:
4293 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4297 case Intrinsic::arm_neon_vqshiftsu:
4298 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4300 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4302 case Intrinsic::arm_neon_vshiftn:
4303 case Intrinsic::arm_neon_vrshiftn:
4304 case Intrinsic::arm_neon_vqshiftns:
4305 case Intrinsic::arm_neon_vqshiftnu:
4306 case Intrinsic::arm_neon_vqshiftnsu:
4307 case Intrinsic::arm_neon_vqrshiftns:
4308 case Intrinsic::arm_neon_vqrshiftnu:
4309 case Intrinsic::arm_neon_vqrshiftnsu:
4310 // Narrowing shifts require an immediate right shift.
4311 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4313 llvm_unreachable("invalid shift count for narrowing vector shift "
4317 llvm_unreachable("unhandled vector shift");
4321 case Intrinsic::arm_neon_vshifts:
4322 case Intrinsic::arm_neon_vshiftu:
4323 // Opcode already set above.
4325 case Intrinsic::arm_neon_vshiftls:
4326 case Intrinsic::arm_neon_vshiftlu:
4327 if (Cnt == VT.getVectorElementType().getSizeInBits())
4328 VShiftOpc = ARMISD::VSHLLi;
4330 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4331 ARMISD::VSHLLs : ARMISD::VSHLLu);
4333 case Intrinsic::arm_neon_vshiftn:
4334 VShiftOpc = ARMISD::VSHRN; break;
4335 case Intrinsic::arm_neon_vrshifts:
4336 VShiftOpc = ARMISD::VRSHRs; break;
4337 case Intrinsic::arm_neon_vrshiftu:
4338 VShiftOpc = ARMISD::VRSHRu; break;
4339 case Intrinsic::arm_neon_vrshiftn:
4340 VShiftOpc = ARMISD::VRSHRN; break;
4341 case Intrinsic::arm_neon_vqshifts:
4342 VShiftOpc = ARMISD::VQSHLs; break;
4343 case Intrinsic::arm_neon_vqshiftu:
4344 VShiftOpc = ARMISD::VQSHLu; break;
4345 case Intrinsic::arm_neon_vqshiftsu:
4346 VShiftOpc = ARMISD::VQSHLsu; break;
4347 case Intrinsic::arm_neon_vqshiftns:
4348 VShiftOpc = ARMISD::VQSHRNs; break;
4349 case Intrinsic::arm_neon_vqshiftnu:
4350 VShiftOpc = ARMISD::VQSHRNu; break;
4351 case Intrinsic::arm_neon_vqshiftnsu:
4352 VShiftOpc = ARMISD::VQSHRNsu; break;
4353 case Intrinsic::arm_neon_vqrshiftns:
4354 VShiftOpc = ARMISD::VQRSHRNs; break;
4355 case Intrinsic::arm_neon_vqrshiftnu:
4356 VShiftOpc = ARMISD::VQRSHRNu; break;
4357 case Intrinsic::arm_neon_vqrshiftnsu:
4358 VShiftOpc = ARMISD::VQRSHRNsu; break;
4361 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4362 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4365 case Intrinsic::arm_neon_vshiftins: {
4366 EVT VT = N->getOperand(1).getValueType();
4368 unsigned VShiftOpc = 0;
4370 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4371 VShiftOpc = ARMISD::VSLI;
4372 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4373 VShiftOpc = ARMISD::VSRI;
4375 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4378 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4379 N->getOperand(1), N->getOperand(2),
4380 DAG.getConstant(Cnt, MVT::i32));
4383 case Intrinsic::arm_neon_vqrshifts:
4384 case Intrinsic::arm_neon_vqrshiftu:
4385 // No immediate versions of these to check for.
4392 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4393 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4394 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4395 /// vector element shift counts are generally not legal, and it is hard to see
4396 /// their values after they get legalized to loads from a constant pool.
4397 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4398 const ARMSubtarget *ST) {
4399 EVT VT = N->getValueType(0);
4401 // Nothing to be done for scalar shifts.
4402 if (! VT.isVector())
4405 assert(ST->hasNEON() && "unexpected vector shift");
4408 switch (N->getOpcode()) {
4409 default: llvm_unreachable("unexpected shift opcode");
4412 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4413 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4414 DAG.getConstant(Cnt, MVT::i32));
4419 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4420 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4421 ARMISD::VSHRs : ARMISD::VSHRu);
4422 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4423 DAG.getConstant(Cnt, MVT::i32));
4429 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4430 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4431 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4432 const ARMSubtarget *ST) {
4433 SDValue N0 = N->getOperand(0);
4435 // Check for sign- and zero-extensions of vector extract operations of 8-
4436 // and 16-bit vector elements. NEON supports these directly. They are
4437 // handled during DAG combining because type legalization will promote them
4438 // to 32-bit types and it is messy to recognize the operations after that.
4439 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4440 SDValue Vec = N0.getOperand(0);
4441 SDValue Lane = N0.getOperand(1);
4442 EVT VT = N->getValueType(0);
4443 EVT EltVT = N0.getValueType();
4444 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4446 if (VT == MVT::i32 &&
4447 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4448 TLI.isTypeLegal(Vec.getValueType())) {
4451 switch (N->getOpcode()) {
4452 default: llvm_unreachable("unexpected opcode");
4453 case ISD::SIGN_EXTEND:
4454 Opc = ARMISD::VGETLANEs;
4456 case ISD::ZERO_EXTEND:
4457 case ISD::ANY_EXTEND:
4458 Opc = ARMISD::VGETLANEu;
4461 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4468 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4469 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4470 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4471 const ARMSubtarget *ST) {
4472 // If the target supports NEON, try to use vmax/vmin instructions for f32
4473 // selects like "x < y ? x : y". Unless the FiniteOnlyFPMath option is set,
4474 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4475 // a NaN; only do the transformation when it matches that behavior.
4477 // For now only do this when using NEON for FP operations; if using VFP, it
4478 // is not obvious that the benefit outweighs the cost of switching to the
4480 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4481 N->getValueType(0) != MVT::f32)
4484 SDValue CondLHS = N->getOperand(0);
4485 SDValue CondRHS = N->getOperand(1);
4486 SDValue LHS = N->getOperand(2);
4487 SDValue RHS = N->getOperand(3);
4488 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4490 unsigned Opcode = 0;
4492 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4493 IsReversed = false; // x CC y ? x : y
4494 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4495 IsReversed = true ; // x CC y ? y : x
4509 // If LHS is NaN, an ordered comparison will be false and the result will
4510 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4511 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4512 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4513 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4515 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4516 // will return -0, so vmin can only be used for unsafe math or if one of
4517 // the operands is known to be nonzero.
4518 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4520 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4522 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4531 // If LHS is NaN, an ordered comparison will be false and the result will
4532 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4533 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4534 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4535 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4537 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4538 // will return +0, so vmax can only be used for unsafe math or if one of
4539 // the operands is known to be nonzero.
4540 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4542 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4544 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4550 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
4553 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
4554 DAGCombinerInfo &DCI) const {
4555 switch (N->getOpcode()) {
4557 case ISD::ADD: return PerformADDCombine(N, DCI);
4558 case ISD::SUB: return PerformSUBCombine(N, DCI);
4559 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
4560 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
4561 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
4564 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
4565 case ISD::SIGN_EXTEND:
4566 case ISD::ZERO_EXTEND:
4567 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
4568 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
4573 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
4574 if (!Subtarget->hasV6Ops())
4575 // Pre-v6 does not support unaligned mem access.
4578 // v6+ may or may not support unaligned mem access depending on the system
4580 // FIXME: This is pretty conservative. Should we provide cmdline option to
4581 // control the behaviour?
4582 if (!Subtarget->isTargetDarwin())
4585 switch (VT.getSimpleVT().SimpleTy) {
4592 // FIXME: VLD1 etc with standard alignment is legal.
4596 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
4601 switch (VT.getSimpleVT().SimpleTy) {
4602 default: return false;
4617 if ((V & (Scale - 1)) != 0)
4620 return V == (V & ((1LL << 5) - 1));
4623 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
4624 const ARMSubtarget *Subtarget) {
4631 switch (VT.getSimpleVT().SimpleTy) {
4632 default: return false;
4637 // + imm12 or - imm8
4639 return V == (V & ((1LL << 8) - 1));
4640 return V == (V & ((1LL << 12) - 1));
4643 // Same as ARM mode. FIXME: NEON?
4644 if (!Subtarget->hasVFP2())
4649 return V == (V & ((1LL << 8) - 1));
4653 /// isLegalAddressImmediate - Return true if the integer value can be used
4654 /// as the offset of the target addressing mode for load / store of the
4656 static bool isLegalAddressImmediate(int64_t V, EVT VT,
4657 const ARMSubtarget *Subtarget) {
4664 if (Subtarget->isThumb1Only())
4665 return isLegalT1AddressImmediate(V, VT);
4666 else if (Subtarget->isThumb2())
4667 return isLegalT2AddressImmediate(V, VT, Subtarget);
4672 switch (VT.getSimpleVT().SimpleTy) {
4673 default: return false;
4678 return V == (V & ((1LL << 12) - 1));
4681 return V == (V & ((1LL << 8) - 1));
4684 if (!Subtarget->hasVFP2()) // FIXME: NEON?
4689 return V == (V & ((1LL << 8) - 1));
4693 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
4695 int Scale = AM.Scale;
4699 switch (VT.getSimpleVT().SimpleTy) {
4700 default: return false;
4709 return Scale == 2 || Scale == 4 || Scale == 8;
4712 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4716 // Note, we allow "void" uses (basically, uses that aren't loads or
4717 // stores), because arm allows folding a scale into many arithmetic
4718 // operations. This should be made more precise and revisited later.
4720 // Allow r << imm, but the imm has to be a multiple of two.
4721 if (Scale & 1) return false;
4722 return isPowerOf2_32(Scale);
4726 /// isLegalAddressingMode - Return true if the addressing mode represented
4727 /// by AM is legal for this target, for a load/store of the specified type.
4728 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4729 const Type *Ty) const {
4730 EVT VT = getValueType(Ty, true);
4731 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
4734 // Can never fold addr of global into load/store.
4739 case 0: // no scale reg, must be "r+i" or "r", or "i".
4742 if (Subtarget->isThumb1Only())
4746 // ARM doesn't support any R+R*scale+imm addr modes.
4753 if (Subtarget->isThumb2())
4754 return isLegalT2ScaledAddressingMode(AM, VT);
4756 int Scale = AM.Scale;
4757 switch (VT.getSimpleVT().SimpleTy) {
4758 default: return false;
4762 if (Scale < 0) Scale = -Scale;
4766 return isPowerOf2_32(Scale & ~1);
4770 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4775 // Note, we allow "void" uses (basically, uses that aren't loads or
4776 // stores), because arm allows folding a scale into many arithmetic
4777 // operations. This should be made more precise and revisited later.
4779 // Allow r << imm, but the imm has to be a multiple of two.
4780 if (Scale & 1) return false;
4781 return isPowerOf2_32(Scale);
4788 /// isLegalICmpImmediate - Return true if the specified immediate is legal
4789 /// icmp immediate, that is the target has icmp instructions which can compare
4790 /// a register against the immediate without having to materialize the
4791 /// immediate into a register.
4792 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
4793 if (!Subtarget->isThumb())
4794 return ARM_AM::getSOImmVal(Imm) != -1;
4795 if (Subtarget->isThumb2())
4796 return ARM_AM::getT2SOImmVal(Imm) != -1;
4797 return Imm >= 0 && Imm <= 255;
4800 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
4801 bool isSEXTLoad, SDValue &Base,
4802 SDValue &Offset, bool &isInc,
4803 SelectionDAG &DAG) {
4804 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4807 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
4809 Base = Ptr->getOperand(0);
4810 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4811 int RHSC = (int)RHS->getZExtValue();
4812 if (RHSC < 0 && RHSC > -256) {
4813 assert(Ptr->getOpcode() == ISD::ADD);
4815 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4819 isInc = (Ptr->getOpcode() == ISD::ADD);
4820 Offset = Ptr->getOperand(1);
4822 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
4824 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4825 int RHSC = (int)RHS->getZExtValue();
4826 if (RHSC < 0 && RHSC > -0x1000) {
4827 assert(Ptr->getOpcode() == ISD::ADD);
4829 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4830 Base = Ptr->getOperand(0);
4835 if (Ptr->getOpcode() == ISD::ADD) {
4837 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
4838 if (ShOpcVal != ARM_AM::no_shift) {
4839 Base = Ptr->getOperand(1);
4840 Offset = Ptr->getOperand(0);
4842 Base = Ptr->getOperand(0);
4843 Offset = Ptr->getOperand(1);
4848 isInc = (Ptr->getOpcode() == ISD::ADD);
4849 Base = Ptr->getOperand(0);
4850 Offset = Ptr->getOperand(1);
4854 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
4858 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
4859 bool isSEXTLoad, SDValue &Base,
4860 SDValue &Offset, bool &isInc,
4861 SelectionDAG &DAG) {
4862 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4865 Base = Ptr->getOperand(0);
4866 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4867 int RHSC = (int)RHS->getZExtValue();
4868 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
4869 assert(Ptr->getOpcode() == ISD::ADD);
4871 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4873 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
4874 isInc = Ptr->getOpcode() == ISD::ADD;
4875 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
4883 /// getPreIndexedAddressParts - returns true by value, base pointer and
4884 /// offset pointer and addressing mode by reference if the node's address
4885 /// can be legally represented as pre-indexed load / store address.
4887 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
4889 ISD::MemIndexedMode &AM,
4890 SelectionDAG &DAG) const {
4891 if (Subtarget->isThumb1Only())
4896 bool isSEXTLoad = false;
4897 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4898 Ptr = LD->getBasePtr();
4899 VT = LD->getMemoryVT();
4900 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4901 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4902 Ptr = ST->getBasePtr();
4903 VT = ST->getMemoryVT();
4908 bool isLegal = false;
4909 if (Subtarget->isThumb2())
4910 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4911 Offset, isInc, DAG);
4913 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4914 Offset, isInc, DAG);
4918 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
4922 /// getPostIndexedAddressParts - returns true by value, base pointer and
4923 /// offset pointer and addressing mode by reference if this node can be
4924 /// combined with a load / store to form a post-indexed load / store.
4925 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
4928 ISD::MemIndexedMode &AM,
4929 SelectionDAG &DAG) const {
4930 if (Subtarget->isThumb1Only())
4935 bool isSEXTLoad = false;
4936 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4937 VT = LD->getMemoryVT();
4938 Ptr = LD->getBasePtr();
4939 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4940 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4941 VT = ST->getMemoryVT();
4942 Ptr = ST->getBasePtr();
4947 bool isLegal = false;
4948 if (Subtarget->isThumb2())
4949 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4952 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4958 // Swap base ptr and offset to catch more post-index load / store when
4959 // it's legal. In Thumb2 mode, offset must be an immediate.
4960 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
4961 !Subtarget->isThumb2())
4962 std::swap(Base, Offset);
4964 // Post-indexed load / store update the base pointer.
4969 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
4973 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
4977 const SelectionDAG &DAG,
4978 unsigned Depth) const {
4979 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4980 switch (Op.getOpcode()) {
4982 case ARMISD::CMOV: {
4983 // Bits are known zero/one if known on the LHS and RHS.
4984 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
4985 if (KnownZero == 0 && KnownOne == 0) return;
4987 APInt KnownZeroRHS, KnownOneRHS;
4988 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
4989 KnownZeroRHS, KnownOneRHS, Depth+1);
4990 KnownZero &= KnownZeroRHS;
4991 KnownOne &= KnownOneRHS;
4997 //===----------------------------------------------------------------------===//
4998 // ARM Inline Assembly Support
4999 //===----------------------------------------------------------------------===//
5001 /// getConstraintType - Given a constraint letter, return the type of
5002 /// constraint it is for this target.
5003 ARMTargetLowering::ConstraintType
5004 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5005 if (Constraint.size() == 1) {
5006 switch (Constraint[0]) {
5008 case 'l': return C_RegisterClass;
5009 case 'w': return C_RegisterClass;
5012 return TargetLowering::getConstraintType(Constraint);
5015 std::pair<unsigned, const TargetRegisterClass*>
5016 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5018 if (Constraint.size() == 1) {
5019 // GCC ARM Constraint Letters
5020 switch (Constraint[0]) {
5022 if (Subtarget->isThumb())
5023 return std::make_pair(0U, ARM::tGPRRegisterClass);
5025 return std::make_pair(0U, ARM::GPRRegisterClass);
5027 return std::make_pair(0U, ARM::GPRRegisterClass);
5030 return std::make_pair(0U, ARM::SPRRegisterClass);
5031 if (VT.getSizeInBits() == 64)
5032 return std::make_pair(0U, ARM::DPRRegisterClass);
5033 if (VT.getSizeInBits() == 128)
5034 return std::make_pair(0U, ARM::QPRRegisterClass);
5038 if (StringRef("{cc}").equals_lower(Constraint))
5039 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5041 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5044 std::vector<unsigned> ARMTargetLowering::
5045 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5047 if (Constraint.size() != 1)
5048 return std::vector<unsigned>();
5050 switch (Constraint[0]) { // GCC ARM Constraint Letters
5053 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5054 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5057 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5058 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5059 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5060 ARM::R12, ARM::LR, 0);
5063 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5064 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5065 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5066 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5067 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5068 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5069 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5070 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5071 if (VT.getSizeInBits() == 64)
5072 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5073 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5074 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5075 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5076 if (VT.getSizeInBits() == 128)
5077 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5078 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5082 return std::vector<unsigned>();
5085 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5086 /// vector. If it is invalid, don't add anything to Ops.
5087 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5089 std::vector<SDValue>&Ops,
5090 SelectionDAG &DAG) const {
5091 SDValue Result(0, 0);
5093 switch (Constraint) {
5095 case 'I': case 'J': case 'K': case 'L':
5096 case 'M': case 'N': case 'O':
5097 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5101 int64_t CVal64 = C->getSExtValue();
5102 int CVal = (int) CVal64;
5103 // None of these constraints allow values larger than 32 bits. Check
5104 // that the value fits in an int.
5108 switch (Constraint) {
5110 if (Subtarget->isThumb1Only()) {
5111 // This must be a constant between 0 and 255, for ADD
5113 if (CVal >= 0 && CVal <= 255)
5115 } else if (Subtarget->isThumb2()) {
5116 // A constant that can be used as an immediate value in a
5117 // data-processing instruction.
5118 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5121 // A constant that can be used as an immediate value in a
5122 // data-processing instruction.
5123 if (ARM_AM::getSOImmVal(CVal) != -1)
5129 if (Subtarget->isThumb()) { // FIXME thumb2
5130 // This must be a constant between -255 and -1, for negated ADD
5131 // immediates. This can be used in GCC with an "n" modifier that
5132 // prints the negated value, for use with SUB instructions. It is
5133 // not useful otherwise but is implemented for compatibility.
5134 if (CVal >= -255 && CVal <= -1)
5137 // This must be a constant between -4095 and 4095. It is not clear
5138 // what this constraint is intended for. Implemented for
5139 // compatibility with GCC.
5140 if (CVal >= -4095 && CVal <= 4095)
5146 if (Subtarget->isThumb1Only()) {
5147 // A 32-bit value where only one byte has a nonzero value. Exclude
5148 // zero to match GCC. This constraint is used by GCC internally for
5149 // constants that can be loaded with a move/shift combination.
5150 // It is not useful otherwise but is implemented for compatibility.
5151 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5153 } else if (Subtarget->isThumb2()) {
5154 // A constant whose bitwise inverse can be used as an immediate
5155 // value in a data-processing instruction. This can be used in GCC
5156 // with a "B" modifier that prints the inverted value, for use with
5157 // BIC and MVN instructions. It is not useful otherwise but is
5158 // implemented for compatibility.
5159 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5162 // A constant whose bitwise inverse can be used as an immediate
5163 // value in a data-processing instruction. This can be used in GCC
5164 // with a "B" modifier that prints the inverted value, for use with
5165 // BIC and MVN instructions. It is not useful otherwise but is
5166 // implemented for compatibility.
5167 if (ARM_AM::getSOImmVal(~CVal) != -1)
5173 if (Subtarget->isThumb1Only()) {
5174 // This must be a constant between -7 and 7,
5175 // for 3-operand ADD/SUB immediate instructions.
5176 if (CVal >= -7 && CVal < 7)
5178 } else if (Subtarget->isThumb2()) {
5179 // A constant whose negation can be used as an immediate value in a
5180 // data-processing instruction. This can be used in GCC with an "n"
5181 // modifier that prints the negated value, for use with SUB
5182 // instructions. It is not useful otherwise but is implemented for
5184 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5187 // A constant whose negation can be used as an immediate value in a
5188 // data-processing instruction. This can be used in GCC with an "n"
5189 // modifier that prints the negated value, for use with SUB
5190 // instructions. It is not useful otherwise but is implemented for
5192 if (ARM_AM::getSOImmVal(-CVal) != -1)
5198 if (Subtarget->isThumb()) { // FIXME thumb2
5199 // This must be a multiple of 4 between 0 and 1020, for
5200 // ADD sp + immediate.
5201 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5204 // A power of two or a constant between 0 and 32. This is used in
5205 // GCC for the shift amount on shifted register operands, but it is
5206 // useful in general for any shift amounts.
5207 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5213 if (Subtarget->isThumb()) { // FIXME thumb2
5214 // This must be a constant between 0 and 31, for shift amounts.
5215 if (CVal >= 0 && CVal <= 31)
5221 if (Subtarget->isThumb()) { // FIXME thumb2
5222 // This must be a multiple of 4 between -508 and 508, for
5223 // ADD/SUB sp = sp + immediate.
5224 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5229 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5233 if (Result.getNode()) {
5234 Ops.push_back(Result);
5237 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5241 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5242 // The ARM target isn't yet aware of offsets.
5246 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5247 APInt Imm = FPImm.bitcastToAPInt();
5248 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5249 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5250 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5252 // We can handle 4 bits of mantissa.
5253 // mantissa = (16+UInt(e:f:g:h))/16.
5254 if (Mantissa & 0x7ffff)
5257 if ((Mantissa & 0xf) != Mantissa)
5260 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5261 if (Exp < -3 || Exp > 4)
5263 Exp = ((Exp+3) & 0x7) ^ 4;
5265 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5268 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5269 APInt Imm = FPImm.bitcastToAPInt();
5270 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5271 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5272 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5274 // We can handle 4 bits of mantissa.
5275 // mantissa = (16+UInt(e:f:g:h))/16.
5276 if (Mantissa & 0xffffffffffffLL)
5279 if ((Mantissa & 0xf) != Mantissa)
5282 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5283 if (Exp < -3 || Exp > 4)
5285 Exp = ((Exp+3) & 0x7) ^ 4;
5287 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5290 /// isFPImmLegal - Returns true if the target can instruction select the
5291 /// specified FP immediate natively. If false, the legalizer will
5292 /// materialize the FP immediate as a load from a constant pool.
5293 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5294 if (!Subtarget->hasVFP3())
5297 return ARM::getVFPf32Imm(Imm) != -1;
5299 return ARM::getVFPf64Imm(Imm) != -1;