1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
16 #include "ARMISelLowering.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/IntrinsicLowering.h"
31 #include "llvm/CodeGen/MachineBasicBlock.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Constants.h"
39 #include "llvm/Function.h"
40 #include "llvm/GlobalValue.h"
41 #include "llvm/Instruction.h"
42 #include "llvm/Instructions.h"
43 #include "llvm/Intrinsics.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Type.h"
53 STATISTIC(NumTailCalls, "Number of tail calls");
54 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
55 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
57 // This option should go away when tail calls fully work.
59 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
60 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
64 EnableARMLongCalls("arm-long-calls", cl::Hidden,
65 cl::desc("Generate calls via indirect call instructions"),
69 ARMInterworking("arm-interworking", cl::Hidden,
70 cl::desc("Enable / disable ARM interworking (for debugging only)"),
74 class ARMCCState : public CCState {
76 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
77 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,
78 LLVMContext &C, ParmContext PC)
79 : CCState(CC, isVarArg, MF, TM, locs, C) {
80 assert(((PC == Call) || (PC == Prologue)) &&
81 "ARMCCState users must specify whether their context is call"
82 "or prologue generation.");
88 // The APCS parameter registers.
89 static const uint16_t GPRArgRegs[] = {
90 ARM::R0, ARM::R1, ARM::R2, ARM::R3
93 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
94 MVT PromotedBitwiseVT) {
95 if (VT != PromotedLdStVT) {
96 setOperationAction(ISD::LOAD, VT, Promote);
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
99 setOperationAction(ISD::STORE, VT, Promote);
100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
103 MVT ElemTy = VT.getVectorElementType();
104 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
105 setOperationAction(ISD::SETCC, VT, Custom);
106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
108 if (ElemTy == MVT::i32) {
109 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
110 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
111 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
112 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
114 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
115 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
116 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
117 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
119 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
120 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
121 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
122 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
123 setOperationAction(ISD::SELECT, VT, Expand);
124 setOperationAction(ISD::SELECT_CC, VT, Expand);
125 setOperationAction(ISD::VSELECT, VT, Expand);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
127 if (VT.isInteger()) {
128 setOperationAction(ISD::SHL, VT, Custom);
129 setOperationAction(ISD::SRA, VT, Custom);
130 setOperationAction(ISD::SRL, VT, Custom);
133 // Promote all bit-wise operations.
134 if (VT.isInteger() && VT != PromotedBitwiseVT) {
135 setOperationAction(ISD::AND, VT, Promote);
136 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
137 setOperationAction(ISD::OR, VT, Promote);
138 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
139 setOperationAction(ISD::XOR, VT, Promote);
140 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
143 // Neon does not support vector divide/remainder operations.
144 setOperationAction(ISD::SDIV, VT, Expand);
145 setOperationAction(ISD::UDIV, VT, Expand);
146 setOperationAction(ISD::FDIV, VT, Expand);
147 setOperationAction(ISD::SREM, VT, Expand);
148 setOperationAction(ISD::UREM, VT, Expand);
149 setOperationAction(ISD::FREM, VT, Expand);
152 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
153 addRegisterClass(VT, &ARM::DPRRegClass);
154 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
157 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
158 addRegisterClass(VT, &ARM::QPRRegClass);
159 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
162 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
163 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
164 return new TargetLoweringObjectFileMachO();
166 return new ARMElfTargetObjectFile();
169 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
170 : TargetLowering(TM, createTLOF(TM)) {
171 Subtarget = &TM.getSubtarget<ARMSubtarget>();
172 RegInfo = TM.getRegisterInfo();
173 Itins = TM.getInstrItineraryData();
175 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
177 if (Subtarget->isTargetDarwin()) {
178 // Uses VFP for Thumb libfuncs if available.
179 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
180 // Single-precision floating-point arithmetic.
181 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
182 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
183 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
184 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
186 // Double-precision floating-point arithmetic.
187 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
188 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
189 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
190 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
192 // Single-precision comparisons.
193 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
194 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
195 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
196 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
197 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
198 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
199 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
200 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
202 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
205 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
211 // Double-precision comparisons.
212 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
213 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
214 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
215 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
216 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
217 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
218 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
219 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
221 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
222 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
223 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
224 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
225 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
226 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
227 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
228 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
230 // Floating-point to integer conversions.
231 // i64 conversions are done via library routines even when generating VFP
232 // instructions, so use the same ones.
233 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
234 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
235 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
236 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
238 // Conversions between floating types.
239 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
240 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
242 // Integer to floating-point conversions.
243 // i64 conversions are done via library routines even when generating VFP
244 // instructions, so use the same ones.
245 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
246 // e.g., __floatunsidf vs. __floatunssidfvfp.
247 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
248 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
249 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
250 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
254 // These libcalls are not available in 32-bit.
255 setLibcallName(RTLIB::SHL_I128, 0);
256 setLibcallName(RTLIB::SRL_I128, 0);
257 setLibcallName(RTLIB::SRA_I128, 0);
259 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetDarwin()) {
260 // Double-precision floating-point arithmetic helper functions
261 // RTABI chapter 4.1.2, Table 2
262 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
263 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
264 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
265 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
266 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
267 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
268 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
269 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
271 // Double-precision floating-point comparison helper functions
272 // RTABI chapter 4.1.2, Table 3
273 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
274 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
275 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
276 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
277 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
278 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
279 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
280 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
281 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
282 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
283 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
284 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
285 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
286 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
287 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
288 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
289 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
290 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
291 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
292 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
293 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
294 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
295 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
296 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
298 // Single-precision floating-point arithmetic helper functions
299 // RTABI chapter 4.1.2, Table 4
300 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
301 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
302 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
303 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
304 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
305 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
306 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
307 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
309 // Single-precision floating-point comparison helper functions
310 // RTABI chapter 4.1.2, Table 5
311 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
312 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
313 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
314 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
315 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
316 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
317 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
318 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
319 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
320 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
321 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
322 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
323 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
324 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
325 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
326 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
327 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
328 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
329 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
330 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
336 // Floating-point to integer conversions.
337 // RTABI chapter 4.1.2, Table 6
338 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
339 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
340 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
341 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
342 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
343 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
344 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
345 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
346 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
347 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
348 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
349 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
350 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
351 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
352 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
353 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
355 // Conversions between floating types.
356 // RTABI chapter 4.1.2, Table 7
357 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
358 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
359 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
362 // Integer to floating-point conversions.
363 // RTABI chapter 4.1.2, Table 8
364 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
365 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
366 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
367 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
368 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
369 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
370 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
371 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
372 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
373 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
376 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
377 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
378 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
379 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
381 // Long long helper functions
382 // RTABI chapter 4.2, Table 9
383 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
384 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
385 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
386 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
387 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
388 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
391 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
394 // Integer division functions
395 // RTABI chapter 4.3.1
396 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
397 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
398 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
399 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
400 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
401 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
402 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
403 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
404 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
405 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
406 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
407 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
408 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
409 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
410 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
411 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
414 // RTABI chapter 4.3.4
415 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
416 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
417 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
418 setLibcallCallingConv(RTLIB::MEMCPY, CallingConv::ARM_AAPCS);
419 setLibcallCallingConv(RTLIB::MEMMOVE, CallingConv::ARM_AAPCS);
420 setLibcallCallingConv(RTLIB::MEMSET, CallingConv::ARM_AAPCS);
423 // Use divmod compiler-rt calls for iOS 5.0 and later.
424 if (Subtarget->getTargetTriple().getOS() == Triple::IOS &&
425 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
426 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
427 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
430 if (Subtarget->isThumb1Only())
431 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
433 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
434 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
435 !Subtarget->isThumb1Only()) {
436 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
437 if (!Subtarget->isFPOnlySP())
438 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
440 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
443 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
444 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
445 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
446 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
447 setTruncStoreAction((MVT::SimpleValueType)VT,
448 (MVT::SimpleValueType)InnerVT, Expand);
449 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
450 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
451 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
454 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
456 if (Subtarget->hasNEON()) {
457 addDRTypeForNEON(MVT::v2f32);
458 addDRTypeForNEON(MVT::v8i8);
459 addDRTypeForNEON(MVT::v4i16);
460 addDRTypeForNEON(MVT::v2i32);
461 addDRTypeForNEON(MVT::v1i64);
463 addQRTypeForNEON(MVT::v4f32);
464 addQRTypeForNEON(MVT::v2f64);
465 addQRTypeForNEON(MVT::v16i8);
466 addQRTypeForNEON(MVT::v8i16);
467 addQRTypeForNEON(MVT::v4i32);
468 addQRTypeForNEON(MVT::v2i64);
470 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
471 // neither Neon nor VFP support any arithmetic operations on it.
472 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
473 // supported for v4f32.
474 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
475 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
476 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
477 // FIXME: Code duplication: FDIV and FREM are expanded always, see
478 // ARMTargetLowering::addTypeForNEON method for details.
479 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
480 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
481 // FIXME: Create unittest.
482 // In another words, find a way when "copysign" appears in DAG with vector
484 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
485 // FIXME: Code duplication: SETCC has custom operation action, see
486 // ARMTargetLowering::addTypeForNEON method for details.
487 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
488 // FIXME: Create unittest for FNEG and for FABS.
489 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
490 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
491 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
492 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
493 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
494 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
495 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
496 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
497 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
498 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
499 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
500 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
501 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
502 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
503 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
504 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
505 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
506 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
508 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
509 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
510 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
511 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
512 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
513 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
514 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
515 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
516 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
517 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
518 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
519 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
520 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
521 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
522 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
524 // Neon does not support some operations on v1i64 and v2i64 types.
525 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
526 // Custom handling for some quad-vector types to detect VMULL.
527 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
528 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
529 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
530 // Custom handling for some vector types to avoid expensive expansions
531 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
532 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
533 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
534 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
535 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
536 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
537 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
538 // a destination type that is wider than the source, and nor does
539 // it have a FP_TO_[SU]INT instruction with a narrower destination than
541 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
542 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
543 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
544 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
546 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
547 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
549 // NEON does not have single instruction CTPOP for vectors with element
550 // types wider than 8-bits. However, custom lowering can leverage the
551 // v8i8/v16i8 vcnt instruction.
552 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
553 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
554 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
555 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
557 setTargetDAGCombine(ISD::INTRINSIC_VOID);
558 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
559 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
560 setTargetDAGCombine(ISD::SHL);
561 setTargetDAGCombine(ISD::SRL);
562 setTargetDAGCombine(ISD::SRA);
563 setTargetDAGCombine(ISD::SIGN_EXTEND);
564 setTargetDAGCombine(ISD::ZERO_EXTEND);
565 setTargetDAGCombine(ISD::ANY_EXTEND);
566 setTargetDAGCombine(ISD::SELECT_CC);
567 setTargetDAGCombine(ISD::BUILD_VECTOR);
568 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
569 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
570 setTargetDAGCombine(ISD::STORE);
571 setTargetDAGCombine(ISD::FP_TO_SINT);
572 setTargetDAGCombine(ISD::FP_TO_UINT);
573 setTargetDAGCombine(ISD::FDIV);
575 // It is legal to extload from v4i8 to v4i16 or v4i32.
576 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
577 MVT::v4i16, MVT::v2i16,
579 for (unsigned i = 0; i < 6; ++i) {
580 setLoadExtAction(ISD::EXTLOAD, Tys[i], Legal);
581 setLoadExtAction(ISD::ZEXTLOAD, Tys[i], Legal);
582 setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal);
586 // ARM and Thumb2 support UMLAL/SMLAL.
587 if (!Subtarget->isThumb1Only())
588 setTargetDAGCombine(ISD::ADDC);
591 computeRegisterProperties();
593 // ARM does not have f32 extending load.
594 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
596 // ARM does not have i1 sign extending load.
597 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
599 // ARM supports all 4 flavors of integer indexed load / store.
600 if (!Subtarget->isThumb1Only()) {
601 for (unsigned im = (unsigned)ISD::PRE_INC;
602 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
603 setIndexedLoadAction(im, MVT::i1, Legal);
604 setIndexedLoadAction(im, MVT::i8, Legal);
605 setIndexedLoadAction(im, MVT::i16, Legal);
606 setIndexedLoadAction(im, MVT::i32, Legal);
607 setIndexedStoreAction(im, MVT::i1, Legal);
608 setIndexedStoreAction(im, MVT::i8, Legal);
609 setIndexedStoreAction(im, MVT::i16, Legal);
610 setIndexedStoreAction(im, MVT::i32, Legal);
614 // i64 operation support.
615 setOperationAction(ISD::MUL, MVT::i64, Expand);
616 setOperationAction(ISD::MULHU, MVT::i32, Expand);
617 if (Subtarget->isThumb1Only()) {
618 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
619 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
621 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
622 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
623 setOperationAction(ISD::MULHS, MVT::i32, Expand);
625 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
626 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
627 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
628 setOperationAction(ISD::SRL, MVT::i64, Custom);
629 setOperationAction(ISD::SRA, MVT::i64, Custom);
631 if (!Subtarget->isThumb1Only()) {
632 // FIXME: We should do this for Thumb1 as well.
633 setOperationAction(ISD::ADDC, MVT::i32, Custom);
634 setOperationAction(ISD::ADDE, MVT::i32, Custom);
635 setOperationAction(ISD::SUBC, MVT::i32, Custom);
636 setOperationAction(ISD::SUBE, MVT::i32, Custom);
639 // ARM does not have ROTL.
640 setOperationAction(ISD::ROTL, MVT::i32, Expand);
641 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
642 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
643 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
644 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
646 // These just redirect to CTTZ and CTLZ on ARM.
647 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
648 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
650 // Only ARMv6 has BSWAP.
651 if (!Subtarget->hasV6Ops())
652 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
654 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
655 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
656 // These are expanded into libcalls if the cpu doesn't have HW divider.
657 setOperationAction(ISD::SDIV, MVT::i32, Expand);
658 setOperationAction(ISD::UDIV, MVT::i32, Expand);
660 setOperationAction(ISD::SREM, MVT::i32, Expand);
661 setOperationAction(ISD::UREM, MVT::i32, Expand);
662 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
663 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
665 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
666 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
667 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
668 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
669 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
671 setOperationAction(ISD::TRAP, MVT::Other, Legal);
673 // Use the default implementation.
674 setOperationAction(ISD::VASTART, MVT::Other, Custom);
675 setOperationAction(ISD::VAARG, MVT::Other, Expand);
676 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
677 setOperationAction(ISD::VAEND, MVT::Other, Expand);
678 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
679 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
681 if (!Subtarget->isTargetDarwin()) {
682 // Non-Darwin platforms may return values in these registers via the
683 // personality function.
684 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
685 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
686 setExceptionPointerRegister(ARM::R0);
687 setExceptionSelectorRegister(ARM::R1);
690 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
691 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
692 // the default expansion.
693 // FIXME: This should be checking for v6k, not just v6.
694 if (Subtarget->hasDataBarrier() ||
695 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
696 // membarrier needs custom lowering; the rest are legal and handled
698 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
699 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
700 // Custom lowering for 64-bit ops
701 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
702 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
703 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
704 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
705 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
706 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
707 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
708 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
709 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
710 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
711 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
712 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
713 setInsertFencesForAtomic(true);
715 // Set them all for expansion, which will force libcalls.
716 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
717 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
718 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
719 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
720 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
721 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
722 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
723 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
724 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
725 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
726 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
727 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
728 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
729 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
730 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
731 // Unordered/Monotonic case.
732 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
733 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
734 // Since the libcalls include locking, fold in the fences
735 setShouldFoldAtomicFences(true);
738 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
740 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
741 if (!Subtarget->hasV6Ops()) {
742 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
743 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
745 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
747 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
748 !Subtarget->isThumb1Only()) {
749 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
750 // iff target supports vfp2.
751 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
752 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
755 // We want to custom lower some of our intrinsics.
756 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
757 if (Subtarget->isTargetDarwin()) {
758 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
759 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
760 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
763 setOperationAction(ISD::SETCC, MVT::i32, Expand);
764 setOperationAction(ISD::SETCC, MVT::f32, Expand);
765 setOperationAction(ISD::SETCC, MVT::f64, Expand);
766 setOperationAction(ISD::SELECT, MVT::i32, Custom);
767 setOperationAction(ISD::SELECT, MVT::f32, Custom);
768 setOperationAction(ISD::SELECT, MVT::f64, Custom);
769 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
770 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
771 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
773 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
774 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
775 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
776 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
777 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
779 // We don't support sin/cos/fmod/copysign/pow
780 setOperationAction(ISD::FSIN, MVT::f64, Expand);
781 setOperationAction(ISD::FSIN, MVT::f32, Expand);
782 setOperationAction(ISD::FCOS, MVT::f32, Expand);
783 setOperationAction(ISD::FCOS, MVT::f64, Expand);
784 setOperationAction(ISD::FREM, MVT::f64, Expand);
785 setOperationAction(ISD::FREM, MVT::f32, Expand);
786 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
787 !Subtarget->isThumb1Only()) {
788 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
789 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
791 setOperationAction(ISD::FPOW, MVT::f64, Expand);
792 setOperationAction(ISD::FPOW, MVT::f32, Expand);
794 if (!Subtarget->hasVFP4()) {
795 setOperationAction(ISD::FMA, MVT::f64, Expand);
796 setOperationAction(ISD::FMA, MVT::f32, Expand);
799 // Various VFP goodness
800 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
801 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
802 if (Subtarget->hasVFP2()) {
803 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
804 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
805 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
806 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
808 // Special handling for half-precision FP.
809 if (!Subtarget->hasFP16()) {
810 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
811 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
815 // We have target-specific dag combine patterns for the following nodes:
816 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
817 setTargetDAGCombine(ISD::ADD);
818 setTargetDAGCombine(ISD::SUB);
819 setTargetDAGCombine(ISD::MUL);
820 setTargetDAGCombine(ISD::AND);
821 setTargetDAGCombine(ISD::OR);
822 setTargetDAGCombine(ISD::XOR);
824 if (Subtarget->hasV6Ops())
825 setTargetDAGCombine(ISD::SRL);
827 setStackPointerRegisterToSaveRestore(ARM::SP);
829 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
830 !Subtarget->hasVFP2())
831 setSchedulingPreference(Sched::RegPressure);
833 setSchedulingPreference(Sched::Hybrid);
835 //// temporary - rewrite interface to use type
836 maxStoresPerMemset = 8;
837 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
838 maxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
839 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
840 maxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
841 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
843 // On ARM arguments smaller than 4 bytes are extended, so all arguments
844 // are at least 4 bytes aligned.
845 setMinStackArgumentAlignment(4);
847 benefitFromCodePlacementOpt = true;
849 // Prefer likely predicted branches to selects on out-of-order cores.
850 predictableSelectIsExpensive = Subtarget->isLikeA9();
852 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
855 // FIXME: It might make sense to define the representative register class as the
856 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
857 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
858 // SPR's representative would be DPR_VFP2. This should work well if register
859 // pressure tracking were modified such that a register use would increment the
860 // pressure of the register class's representative and all of it's super
861 // classes' representatives transitively. We have not implemented this because
862 // of the difficulty prior to coalescing of modeling operand register classes
863 // due to the common occurrence of cross class copies and subregister insertions
865 std::pair<const TargetRegisterClass*, uint8_t>
866 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
867 const TargetRegisterClass *RRC = 0;
869 switch (VT.getSimpleVT().SimpleTy) {
871 return TargetLowering::findRepresentativeClass(VT);
872 // Use DPR as representative register class for all floating point
873 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
874 // the cost is 1 for both f32 and f64.
875 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
876 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
877 RRC = &ARM::DPRRegClass;
878 // When NEON is used for SP, only half of the register file is available
879 // because operations that define both SP and DP results will be constrained
880 // to the VFP2 class (D0-D15). We currently model this constraint prior to
881 // coalescing by double-counting the SP regs. See the FIXME above.
882 if (Subtarget->useNEONForSinglePrecisionFP())
885 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
886 case MVT::v4f32: case MVT::v2f64:
887 RRC = &ARM::DPRRegClass;
891 RRC = &ARM::DPRRegClass;
895 RRC = &ARM::DPRRegClass;
899 return std::make_pair(RRC, Cost);
902 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
905 case ARMISD::Wrapper: return "ARMISD::Wrapper";
906 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
907 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
908 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
909 case ARMISD::CALL: return "ARMISD::CALL";
910 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
911 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
912 case ARMISD::tCALL: return "ARMISD::tCALL";
913 case ARMISD::BRCOND: return "ARMISD::BRCOND";
914 case ARMISD::BR_JT: return "ARMISD::BR_JT";
915 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
916 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
917 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
918 case ARMISD::CMP: return "ARMISD::CMP";
919 case ARMISD::CMN: return "ARMISD::CMN";
920 case ARMISD::CMPZ: return "ARMISD::CMPZ";
921 case ARMISD::CMPFP: return "ARMISD::CMPFP";
922 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
923 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
924 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
926 case ARMISD::CMOV: return "ARMISD::CMOV";
928 case ARMISD::RBIT: return "ARMISD::RBIT";
930 case ARMISD::FTOSI: return "ARMISD::FTOSI";
931 case ARMISD::FTOUI: return "ARMISD::FTOUI";
932 case ARMISD::SITOF: return "ARMISD::SITOF";
933 case ARMISD::UITOF: return "ARMISD::UITOF";
935 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
936 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
937 case ARMISD::RRX: return "ARMISD::RRX";
939 case ARMISD::ADDC: return "ARMISD::ADDC";
940 case ARMISD::ADDE: return "ARMISD::ADDE";
941 case ARMISD::SUBC: return "ARMISD::SUBC";
942 case ARMISD::SUBE: return "ARMISD::SUBE";
944 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
945 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
947 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
948 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
950 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
952 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
954 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
956 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
957 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
959 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
961 case ARMISD::VCEQ: return "ARMISD::VCEQ";
962 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
963 case ARMISD::VCGE: return "ARMISD::VCGE";
964 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
965 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
966 case ARMISD::VCGEU: return "ARMISD::VCGEU";
967 case ARMISD::VCGT: return "ARMISD::VCGT";
968 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
969 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
970 case ARMISD::VCGTU: return "ARMISD::VCGTU";
971 case ARMISD::VTST: return "ARMISD::VTST";
973 case ARMISD::VSHL: return "ARMISD::VSHL";
974 case ARMISD::VSHRs: return "ARMISD::VSHRs";
975 case ARMISD::VSHRu: return "ARMISD::VSHRu";
976 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
977 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
978 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
979 case ARMISD::VSHRN: return "ARMISD::VSHRN";
980 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
981 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
982 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
983 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
984 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
985 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
986 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
987 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
988 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
989 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
990 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
991 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
992 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
993 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
994 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
995 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
996 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
997 case ARMISD::VDUP: return "ARMISD::VDUP";
998 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
999 case ARMISD::VEXT: return "ARMISD::VEXT";
1000 case ARMISD::VREV64: return "ARMISD::VREV64";
1001 case ARMISD::VREV32: return "ARMISD::VREV32";
1002 case ARMISD::VREV16: return "ARMISD::VREV16";
1003 case ARMISD::VZIP: return "ARMISD::VZIP";
1004 case ARMISD::VUZP: return "ARMISD::VUZP";
1005 case ARMISD::VTRN: return "ARMISD::VTRN";
1006 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1007 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1008 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1009 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1010 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1011 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1012 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1013 case ARMISD::FMAX: return "ARMISD::FMAX";
1014 case ARMISD::FMIN: return "ARMISD::FMIN";
1015 case ARMISD::BFI: return "ARMISD::BFI";
1016 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1017 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1018 case ARMISD::VBSL: return "ARMISD::VBSL";
1019 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1020 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1021 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1022 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1023 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1024 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1025 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1026 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1027 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1028 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1029 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1030 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1031 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1032 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1033 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1034 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1035 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1036 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1037 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1038 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1042 EVT ARMTargetLowering::getSetCCResultType(EVT VT) const {
1043 if (!VT.isVector()) return getPointerTy();
1044 return VT.changeVectorElementTypeToInteger();
1047 /// getRegClassFor - Return the register class that should be used for the
1048 /// specified value type.
1049 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
1050 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1051 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1052 // load / store 4 to 8 consecutive D registers.
1053 if (Subtarget->hasNEON()) {
1054 if (VT == MVT::v4i64)
1055 return &ARM::QQPRRegClass;
1056 if (VT == MVT::v8i64)
1057 return &ARM::QQQQPRRegClass;
1059 return TargetLowering::getRegClassFor(VT);
1062 // Create a fast isel object.
1064 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1065 const TargetLibraryInfo *libInfo) const {
1066 return ARM::createFastISel(funcInfo, libInfo);
1069 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
1070 /// be used for loads / stores from the global.
1071 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1072 return (Subtarget->isThumb1Only() ? 127 : 4095);
1075 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1076 unsigned NumVals = N->getNumValues();
1078 return Sched::RegPressure;
1080 for (unsigned i = 0; i != NumVals; ++i) {
1081 EVT VT = N->getValueType(i);
1082 if (VT == MVT::Glue || VT == MVT::Other)
1084 if (VT.isFloatingPoint() || VT.isVector())
1088 if (!N->isMachineOpcode())
1089 return Sched::RegPressure;
1091 // Load are scheduled for latency even if there instruction itinerary
1092 // is not available.
1093 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1094 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1096 if (MCID.getNumDefs() == 0)
1097 return Sched::RegPressure;
1098 if (!Itins->isEmpty() &&
1099 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1102 return Sched::RegPressure;
1105 //===----------------------------------------------------------------------===//
1107 //===----------------------------------------------------------------------===//
1109 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1110 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1112 default: llvm_unreachable("Unknown condition code!");
1113 case ISD::SETNE: return ARMCC::NE;
1114 case ISD::SETEQ: return ARMCC::EQ;
1115 case ISD::SETGT: return ARMCC::GT;
1116 case ISD::SETGE: return ARMCC::GE;
1117 case ISD::SETLT: return ARMCC::LT;
1118 case ISD::SETLE: return ARMCC::LE;
1119 case ISD::SETUGT: return ARMCC::HI;
1120 case ISD::SETUGE: return ARMCC::HS;
1121 case ISD::SETULT: return ARMCC::LO;
1122 case ISD::SETULE: return ARMCC::LS;
1126 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1127 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1128 ARMCC::CondCodes &CondCode2) {
1129 CondCode2 = ARMCC::AL;
1131 default: llvm_unreachable("Unknown FP condition!");
1133 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1135 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1137 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1138 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1139 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1140 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1141 case ISD::SETO: CondCode = ARMCC::VC; break;
1142 case ISD::SETUO: CondCode = ARMCC::VS; break;
1143 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1144 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1145 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1147 case ISD::SETULT: CondCode = ARMCC::LT; break;
1149 case ISD::SETULE: CondCode = ARMCC::LE; break;
1151 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1155 //===----------------------------------------------------------------------===//
1156 // Calling Convention Implementation
1157 //===----------------------------------------------------------------------===//
1159 #include "ARMGenCallingConv.inc"
1161 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1162 /// given CallingConvention value.
1163 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1165 bool isVarArg) const {
1168 llvm_unreachable("Unsupported calling convention");
1169 case CallingConv::Fast:
1170 if (Subtarget->hasVFP2() && !isVarArg) {
1171 if (!Subtarget->isAAPCS_ABI())
1172 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1173 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1174 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1177 case CallingConv::C: {
1178 // Use target triple & subtarget features to do actual dispatch.
1179 if (!Subtarget->isAAPCS_ABI())
1180 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1181 else if (Subtarget->hasVFP2() &&
1182 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1184 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1185 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1187 case CallingConv::ARM_AAPCS_VFP:
1189 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1191 case CallingConv::ARM_AAPCS:
1192 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1193 case CallingConv::ARM_APCS:
1194 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1195 case CallingConv::GHC:
1196 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1200 /// LowerCallResult - Lower the result values of a call into the
1201 /// appropriate copies out of appropriate physical registers.
1203 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1204 CallingConv::ID CallConv, bool isVarArg,
1205 const SmallVectorImpl<ISD::InputArg> &Ins,
1206 DebugLoc dl, SelectionDAG &DAG,
1207 SmallVectorImpl<SDValue> &InVals) const {
1209 // Assign locations to each value returned by this call.
1210 SmallVector<CCValAssign, 16> RVLocs;
1211 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1212 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1213 CCInfo.AnalyzeCallResult(Ins,
1214 CCAssignFnForNode(CallConv, /* Return*/ true,
1217 // Copy all of the result registers out of their specified physreg.
1218 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1219 CCValAssign VA = RVLocs[i];
1222 if (VA.needsCustom()) {
1223 // Handle f64 or half of a v2f64.
1224 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1226 Chain = Lo.getValue(1);
1227 InFlag = Lo.getValue(2);
1228 VA = RVLocs[++i]; // skip ahead to next loc
1229 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1231 Chain = Hi.getValue(1);
1232 InFlag = Hi.getValue(2);
1233 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1235 if (VA.getLocVT() == MVT::v2f64) {
1236 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1237 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1238 DAG.getConstant(0, MVT::i32));
1240 VA = RVLocs[++i]; // skip ahead to next loc
1241 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1242 Chain = Lo.getValue(1);
1243 InFlag = Lo.getValue(2);
1244 VA = RVLocs[++i]; // skip ahead to next loc
1245 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1246 Chain = Hi.getValue(1);
1247 InFlag = Hi.getValue(2);
1248 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1249 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1250 DAG.getConstant(1, MVT::i32));
1253 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1255 Chain = Val.getValue(1);
1256 InFlag = Val.getValue(2);
1259 switch (VA.getLocInfo()) {
1260 default: llvm_unreachable("Unknown loc info!");
1261 case CCValAssign::Full: break;
1262 case CCValAssign::BCvt:
1263 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1267 InVals.push_back(Val);
1273 /// LowerMemOpCallTo - Store the argument to the stack.
1275 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1276 SDValue StackPtr, SDValue Arg,
1277 DebugLoc dl, SelectionDAG &DAG,
1278 const CCValAssign &VA,
1279 ISD::ArgFlagsTy Flags) const {
1280 unsigned LocMemOffset = VA.getLocMemOffset();
1281 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1282 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1283 return DAG.getStore(Chain, dl, Arg, PtrOff,
1284 MachinePointerInfo::getStack(LocMemOffset),
1288 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1289 SDValue Chain, SDValue &Arg,
1290 RegsToPassVector &RegsToPass,
1291 CCValAssign &VA, CCValAssign &NextVA,
1293 SmallVector<SDValue, 8> &MemOpChains,
1294 ISD::ArgFlagsTy Flags) const {
1296 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1297 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1298 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1300 if (NextVA.isRegLoc())
1301 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1303 assert(NextVA.isMemLoc());
1304 if (StackPtr.getNode() == 0)
1305 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1307 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1313 /// LowerCall - Lowering a call into a callseq_start <-
1314 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1317 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1318 SmallVectorImpl<SDValue> &InVals) const {
1319 SelectionDAG &DAG = CLI.DAG;
1320 DebugLoc &dl = CLI.DL;
1321 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
1322 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
1323 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
1324 SDValue Chain = CLI.Chain;
1325 SDValue Callee = CLI.Callee;
1326 bool &isTailCall = CLI.IsTailCall;
1327 CallingConv::ID CallConv = CLI.CallConv;
1328 bool doesNotRet = CLI.DoesNotReturn;
1329 bool isVarArg = CLI.IsVarArg;
1331 MachineFunction &MF = DAG.getMachineFunction();
1332 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1333 bool IsSibCall = false;
1334 // Disable tail calls if they're not supported.
1335 if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
1338 // Check if it's really possible to do a tail call.
1339 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1340 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1341 Outs, OutVals, Ins, DAG);
1342 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1343 // detected sibcalls.
1350 // Analyze operands of the call, assigning locations to each operand.
1351 SmallVector<CCValAssign, 16> ArgLocs;
1352 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1353 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1354 CCInfo.AnalyzeCallOperands(Outs,
1355 CCAssignFnForNode(CallConv, /* Return*/ false,
1358 // Get a count of how many bytes are to be pushed on the stack.
1359 unsigned NumBytes = CCInfo.getNextStackOffset();
1361 // For tail calls, memory operands are available in our caller's stack.
1365 // Adjust the stack pointer for the new arguments...
1366 // These operations are automatically eliminated by the prolog/epilog pass
1368 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1370 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1372 RegsToPassVector RegsToPass;
1373 SmallVector<SDValue, 8> MemOpChains;
1375 // Walk the register/memloc assignments, inserting copies/loads. In the case
1376 // of tail call optimization, arguments are handled later.
1377 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1379 ++i, ++realArgIdx) {
1380 CCValAssign &VA = ArgLocs[i];
1381 SDValue Arg = OutVals[realArgIdx];
1382 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1383 bool isByVal = Flags.isByVal();
1385 // Promote the value if needed.
1386 switch (VA.getLocInfo()) {
1387 default: llvm_unreachable("Unknown loc info!");
1388 case CCValAssign::Full: break;
1389 case CCValAssign::SExt:
1390 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1392 case CCValAssign::ZExt:
1393 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1395 case CCValAssign::AExt:
1396 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1398 case CCValAssign::BCvt:
1399 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1403 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1404 if (VA.needsCustom()) {
1405 if (VA.getLocVT() == MVT::v2f64) {
1406 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1407 DAG.getConstant(0, MVT::i32));
1408 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1409 DAG.getConstant(1, MVT::i32));
1411 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1412 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1414 VA = ArgLocs[++i]; // skip ahead to next loc
1415 if (VA.isRegLoc()) {
1416 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1417 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1419 assert(VA.isMemLoc());
1421 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1422 dl, DAG, VA, Flags));
1425 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1426 StackPtr, MemOpChains, Flags);
1428 } else if (VA.isRegLoc()) {
1429 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1430 } else if (isByVal) {
1431 assert(VA.isMemLoc());
1432 unsigned offset = 0;
1434 // True if this byval aggregate will be split between registers
1436 if (CCInfo.isFirstByValRegValid()) {
1437 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1439 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) {
1440 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1441 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1442 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1443 MachinePointerInfo(),
1444 false, false, false, 0);
1445 MemOpChains.push_back(Load.getValue(1));
1446 RegsToPass.push_back(std::make_pair(j, Load));
1448 offset = ARM::R4 - CCInfo.getFirstByValReg();
1449 CCInfo.clearFirstByValReg();
1452 if (Flags.getByValSize() - 4*offset > 0) {
1453 unsigned LocMemOffset = VA.getLocMemOffset();
1454 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1455 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1457 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1458 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1459 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1461 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
1463 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1464 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1465 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1466 Ops, array_lengthof(Ops)));
1468 } else if (!IsSibCall) {
1469 assert(VA.isMemLoc());
1471 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1472 dl, DAG, VA, Flags));
1476 if (!MemOpChains.empty())
1477 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1478 &MemOpChains[0], MemOpChains.size());
1480 // Build a sequence of copy-to-reg nodes chained together with token chain
1481 // and flag operands which copy the outgoing args into the appropriate regs.
1483 // Tail call byval lowering might overwrite argument registers so in case of
1484 // tail call optimization the copies to registers are lowered later.
1486 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1487 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1488 RegsToPass[i].second, InFlag);
1489 InFlag = Chain.getValue(1);
1492 // For tail calls lower the arguments to the 'real' stack slot.
1494 // Force all the incoming stack arguments to be loaded from the stack
1495 // before any new outgoing arguments are stored to the stack, because the
1496 // outgoing stack slots may alias the incoming argument stack slots, and
1497 // the alias isn't otherwise explicit. This is slightly more conservative
1498 // than necessary, because it means that each store effectively depends
1499 // on every argument instead of just those arguments it would clobber.
1501 // Do not flag preceding copytoreg stuff together with the following stuff.
1503 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1504 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1505 RegsToPass[i].second, InFlag);
1506 InFlag = Chain.getValue(1);
1511 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1512 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1513 // node so that legalize doesn't hack it.
1514 bool isDirect = false;
1515 bool isARMFunc = false;
1516 bool isLocalARMFunc = false;
1517 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1519 if (EnableARMLongCalls) {
1520 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1521 && "long-calls with non-static relocation model!");
1522 // Handle a global address or an external symbol. If it's not one of
1523 // those, the target's already in a register, so we don't need to do
1525 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1526 const GlobalValue *GV = G->getGlobal();
1527 // Create a constant pool entry for the callee address
1528 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1529 ARMConstantPoolValue *CPV =
1530 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1532 // Get the address of the callee into a register
1533 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1534 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1535 Callee = DAG.getLoad(getPointerTy(), dl,
1536 DAG.getEntryNode(), CPAddr,
1537 MachinePointerInfo::getConstantPool(),
1538 false, false, false, 0);
1539 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1540 const char *Sym = S->getSymbol();
1542 // Create a constant pool entry for the callee address
1543 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1544 ARMConstantPoolValue *CPV =
1545 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1546 ARMPCLabelIndex, 0);
1547 // Get the address of the callee into a register
1548 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1549 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1550 Callee = DAG.getLoad(getPointerTy(), dl,
1551 DAG.getEntryNode(), CPAddr,
1552 MachinePointerInfo::getConstantPool(),
1553 false, false, false, 0);
1555 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1556 const GlobalValue *GV = G->getGlobal();
1558 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1559 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1560 getTargetMachine().getRelocationModel() != Reloc::Static;
1561 isARMFunc = !Subtarget->isThumb() || isStub;
1562 // ARM call to a local ARM function is predicable.
1563 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1564 // tBX takes a register source operand.
1565 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1566 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1567 ARMConstantPoolValue *CPV =
1568 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4);
1569 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1570 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1571 Callee = DAG.getLoad(getPointerTy(), dl,
1572 DAG.getEntryNode(), CPAddr,
1573 MachinePointerInfo::getConstantPool(),
1574 false, false, false, 0);
1575 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1576 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1577 getPointerTy(), Callee, PICLabel);
1579 // On ELF targets for PIC code, direct calls should go through the PLT
1580 unsigned OpFlags = 0;
1581 if (Subtarget->isTargetELF() &&
1582 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1583 OpFlags = ARMII::MO_PLT;
1584 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1586 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1588 bool isStub = Subtarget->isTargetDarwin() &&
1589 getTargetMachine().getRelocationModel() != Reloc::Static;
1590 isARMFunc = !Subtarget->isThumb() || isStub;
1591 // tBX takes a register source operand.
1592 const char *Sym = S->getSymbol();
1593 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1594 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1595 ARMConstantPoolValue *CPV =
1596 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1597 ARMPCLabelIndex, 4);
1598 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1599 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1600 Callee = DAG.getLoad(getPointerTy(), dl,
1601 DAG.getEntryNode(), CPAddr,
1602 MachinePointerInfo::getConstantPool(),
1603 false, false, false, 0);
1604 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1605 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1606 getPointerTy(), Callee, PICLabel);
1608 unsigned OpFlags = 0;
1609 // On ELF targets for PIC code, direct calls should go through the PLT
1610 if (Subtarget->isTargetELF() &&
1611 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1612 OpFlags = ARMII::MO_PLT;
1613 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1617 // FIXME: handle tail calls differently.
1619 bool HasMinSizeAttr = MF.getFunction()->getFnAttributes().
1620 hasAttribute(Attributes::MinSize);
1621 if (Subtarget->isThumb()) {
1622 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1623 CallOpc = ARMISD::CALL_NOLINK;
1625 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1627 if (!isDirect && !Subtarget->hasV5TOps())
1628 CallOpc = ARMISD::CALL_NOLINK;
1629 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1630 // Emit regular call when code size is the priority
1632 // "mov lr, pc; b _foo" to avoid confusing the RSP
1633 CallOpc = ARMISD::CALL_NOLINK;
1635 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1638 std::vector<SDValue> Ops;
1639 Ops.push_back(Chain);
1640 Ops.push_back(Callee);
1642 // Add argument registers to the end of the list so that they are known live
1644 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1645 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1646 RegsToPass[i].second.getValueType()));
1648 // Add a register mask operand representing the call-preserved registers.
1649 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1650 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
1651 assert(Mask && "Missing call preserved mask for calling convention");
1652 Ops.push_back(DAG.getRegisterMask(Mask));
1654 if (InFlag.getNode())
1655 Ops.push_back(InFlag);
1657 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1659 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1661 // Returns a chain and a flag for retval copy to use.
1662 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1663 InFlag = Chain.getValue(1);
1665 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1666 DAG.getIntPtrConstant(0, true), InFlag);
1668 InFlag = Chain.getValue(1);
1670 // Handle result values, copying them out of physregs into vregs that we
1672 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1676 /// HandleByVal - Every parameter *after* a byval parameter is passed
1677 /// on the stack. Remember the next parameter register to allocate,
1678 /// and then confiscate the rest of the parameter registers to insure
1681 ARMTargetLowering::HandleByVal(
1682 CCState *State, unsigned &size, unsigned Align) const {
1683 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1684 assert((State->getCallOrPrologue() == Prologue ||
1685 State->getCallOrPrologue() == Call) &&
1686 "unhandled ParmContext");
1687 if ((!State->isFirstByValRegValid()) &&
1688 (ARM::R0 <= reg) && (reg <= ARM::R3)) {
1689 if (Subtarget->isAAPCS_ABI() && Align > 4) {
1690 unsigned AlignInRegs = Align / 4;
1691 unsigned Waste = (ARM::R4 - reg) % AlignInRegs;
1692 for (unsigned i = 0; i < Waste; ++i)
1693 reg = State->AllocateReg(GPRArgRegs, 4);
1696 State->setFirstByValReg(reg);
1697 // At a call site, a byval parameter that is split between
1698 // registers and memory needs its size truncated here. In a
1699 // function prologue, such byval parameters are reassembled in
1700 // memory, and are not truncated.
1701 if (State->getCallOrPrologue() == Call) {
1702 unsigned excess = 4 * (ARM::R4 - reg);
1703 assert(size >= excess && "expected larger existing stack allocation");
1708 // Confiscate any remaining parameter registers to preclude their
1709 // assignment to subsequent parameters.
1710 while (State->AllocateReg(GPRArgRegs, 4))
1714 /// MatchingStackOffset - Return true if the given stack call argument is
1715 /// already available in the same position (relatively) of the caller's
1716 /// incoming argument stack.
1718 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1719 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1720 const TargetInstrInfo *TII) {
1721 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1723 if (Arg.getOpcode() == ISD::CopyFromReg) {
1724 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1725 if (!TargetRegisterInfo::isVirtualRegister(VR))
1727 MachineInstr *Def = MRI->getVRegDef(VR);
1730 if (!Flags.isByVal()) {
1731 if (!TII->isLoadFromStackSlot(Def, FI))
1736 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1737 if (Flags.isByVal())
1738 // ByVal argument is passed in as a pointer but it's now being
1739 // dereferenced. e.g.
1740 // define @foo(%struct.X* %A) {
1741 // tail call @bar(%struct.X* byval %A)
1744 SDValue Ptr = Ld->getBasePtr();
1745 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1748 FI = FINode->getIndex();
1752 assert(FI != INT_MAX);
1753 if (!MFI->isFixedObjectIndex(FI))
1755 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1758 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1759 /// for tail call optimization. Targets which want to do tail call
1760 /// optimization should implement this function.
1762 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1763 CallingConv::ID CalleeCC,
1765 bool isCalleeStructRet,
1766 bool isCallerStructRet,
1767 const SmallVectorImpl<ISD::OutputArg> &Outs,
1768 const SmallVectorImpl<SDValue> &OutVals,
1769 const SmallVectorImpl<ISD::InputArg> &Ins,
1770 SelectionDAG& DAG) const {
1771 const Function *CallerF = DAG.getMachineFunction().getFunction();
1772 CallingConv::ID CallerCC = CallerF->getCallingConv();
1773 bool CCMatch = CallerCC == CalleeCC;
1775 // Look for obvious safe cases to perform tail call optimization that do not
1776 // require ABI changes. This is what gcc calls sibcall.
1778 // Do not sibcall optimize vararg calls unless the call site is not passing
1780 if (isVarArg && !Outs.empty())
1783 // Also avoid sibcall optimization if either caller or callee uses struct
1784 // return semantics.
1785 if (isCalleeStructRet || isCallerStructRet)
1788 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1789 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1790 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1791 // support in the assembler and linker to be used. This would need to be
1792 // fixed to fully support tail calls in Thumb1.
1794 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1795 // LR. This means if we need to reload LR, it takes an extra instructions,
1796 // which outweighs the value of the tail call; but here we don't know yet
1797 // whether LR is going to be used. Probably the right approach is to
1798 // generate the tail call here and turn it back into CALL/RET in
1799 // emitEpilogue if LR is used.
1801 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1802 // but we need to make sure there are enough registers; the only valid
1803 // registers are the 4 used for parameters. We don't currently do this
1805 if (Subtarget->isThumb1Only())
1808 // If the calling conventions do not match, then we'd better make sure the
1809 // results are returned in the same way as what the caller expects.
1811 SmallVector<CCValAssign, 16> RVLocs1;
1812 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1813 getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
1814 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1816 SmallVector<CCValAssign, 16> RVLocs2;
1817 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1818 getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
1819 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1821 if (RVLocs1.size() != RVLocs2.size())
1823 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1824 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1826 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1828 if (RVLocs1[i].isRegLoc()) {
1829 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1832 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1838 // If Caller's vararg or byval argument has been split between registers and
1839 // stack, do not perform tail call, since part of the argument is in caller's
1841 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
1842 getInfo<ARMFunctionInfo>();
1843 if (AFI_Caller->getVarArgsRegSaveSize())
1846 // If the callee takes no arguments then go on to check the results of the
1848 if (!Outs.empty()) {
1849 // Check if stack adjustment is needed. For now, do not do this if any
1850 // argument is passed on the stack.
1851 SmallVector<CCValAssign, 16> ArgLocs;
1852 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
1853 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1854 CCInfo.AnalyzeCallOperands(Outs,
1855 CCAssignFnForNode(CalleeCC, false, isVarArg));
1856 if (CCInfo.getNextStackOffset()) {
1857 MachineFunction &MF = DAG.getMachineFunction();
1859 // Check if the arguments are already laid out in the right way as
1860 // the caller's fixed stack objects.
1861 MachineFrameInfo *MFI = MF.getFrameInfo();
1862 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1863 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1864 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1866 ++i, ++realArgIdx) {
1867 CCValAssign &VA = ArgLocs[i];
1868 EVT RegVT = VA.getLocVT();
1869 SDValue Arg = OutVals[realArgIdx];
1870 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1871 if (VA.getLocInfo() == CCValAssign::Indirect)
1873 if (VA.needsCustom()) {
1874 // f64 and vector types are split into multiple registers or
1875 // register/stack-slot combinations. The types will not match
1876 // the registers; give up on memory f64 refs until we figure
1877 // out what to do about this.
1880 if (!ArgLocs[++i].isRegLoc())
1882 if (RegVT == MVT::v2f64) {
1883 if (!ArgLocs[++i].isRegLoc())
1885 if (!ArgLocs[++i].isRegLoc())
1888 } else if (!VA.isRegLoc()) {
1889 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1901 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1902 MachineFunction &MF, bool isVarArg,
1903 const SmallVectorImpl<ISD::OutputArg> &Outs,
1904 LLVMContext &Context) const {
1905 SmallVector<CCValAssign, 16> RVLocs;
1906 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
1907 return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
1912 ARMTargetLowering::LowerReturn(SDValue Chain,
1913 CallingConv::ID CallConv, bool isVarArg,
1914 const SmallVectorImpl<ISD::OutputArg> &Outs,
1915 const SmallVectorImpl<SDValue> &OutVals,
1916 DebugLoc dl, SelectionDAG &DAG) const {
1918 // CCValAssign - represent the assignment of the return value to a location.
1919 SmallVector<CCValAssign, 16> RVLocs;
1921 // CCState - Info about the registers and stack slots.
1922 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1923 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1925 // Analyze outgoing return values.
1926 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1929 // If this is the first return lowered for this function, add
1930 // the regs to the liveout set for the function.
1931 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1932 for (unsigned i = 0; i != RVLocs.size(); ++i)
1933 if (RVLocs[i].isRegLoc())
1934 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1939 // Copy the result values into the output registers.
1940 for (unsigned i = 0, realRVLocIdx = 0;
1942 ++i, ++realRVLocIdx) {
1943 CCValAssign &VA = RVLocs[i];
1944 assert(VA.isRegLoc() && "Can only return in registers!");
1946 SDValue Arg = OutVals[realRVLocIdx];
1948 switch (VA.getLocInfo()) {
1949 default: llvm_unreachable("Unknown loc info!");
1950 case CCValAssign::Full: break;
1951 case CCValAssign::BCvt:
1952 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1956 if (VA.needsCustom()) {
1957 if (VA.getLocVT() == MVT::v2f64) {
1958 // Extract the first half and return it in two registers.
1959 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1960 DAG.getConstant(0, MVT::i32));
1961 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1962 DAG.getVTList(MVT::i32, MVT::i32), Half);
1964 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1965 Flag = Chain.getValue(1);
1966 VA = RVLocs[++i]; // skip ahead to next loc
1967 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1968 HalfGPRs.getValue(1), Flag);
1969 Flag = Chain.getValue(1);
1970 VA = RVLocs[++i]; // skip ahead to next loc
1972 // Extract the 2nd half and fall through to handle it as an f64 value.
1973 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1974 DAG.getConstant(1, MVT::i32));
1976 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1978 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1979 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1980 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1981 Flag = Chain.getValue(1);
1982 VA = RVLocs[++i]; // skip ahead to next loc
1983 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1986 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1988 // Guarantee that all emitted copies are
1989 // stuck together, avoiding something bad.
1990 Flag = Chain.getValue(1);
1995 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1997 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
2002 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2003 if (N->getNumValues() != 1)
2005 if (!N->hasNUsesOfValue(1, 0))
2008 SDValue TCChain = Chain;
2009 SDNode *Copy = *N->use_begin();
2010 if (Copy->getOpcode() == ISD::CopyToReg) {
2011 // If the copy has a glue operand, we conservatively assume it isn't safe to
2012 // perform a tail call.
2013 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2015 TCChain = Copy->getOperand(0);
2016 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2017 SDNode *VMov = Copy;
2018 // f64 returned in a pair of GPRs.
2019 SmallPtrSet<SDNode*, 2> Copies;
2020 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2022 if (UI->getOpcode() != ISD::CopyToReg)
2026 if (Copies.size() > 2)
2029 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2031 SDValue UseChain = UI->getOperand(0);
2032 if (Copies.count(UseChain.getNode()))
2039 } else if (Copy->getOpcode() == ISD::BITCAST) {
2040 // f32 returned in a single GPR.
2041 if (!Copy->hasOneUse())
2043 Copy = *Copy->use_begin();
2044 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2046 Chain = Copy->getOperand(0);
2051 bool HasRet = false;
2052 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2054 if (UI->getOpcode() != ARMISD::RET_FLAG)
2066 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2067 if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
2070 if (!CI->isTailCall())
2073 return !Subtarget->isThumb1Only();
2076 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2077 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2078 // one of the above mentioned nodes. It has to be wrapped because otherwise
2079 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2080 // be used to form addressing mode. These wrapped nodes will be selected
2082 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2083 EVT PtrVT = Op.getValueType();
2084 // FIXME there is no actual debug info here
2085 DebugLoc dl = Op.getDebugLoc();
2086 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2088 if (CP->isMachineConstantPoolEntry())
2089 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2090 CP->getAlignment());
2092 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2093 CP->getAlignment());
2094 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2097 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2098 return MachineJumpTableInfo::EK_Inline;
2101 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2102 SelectionDAG &DAG) const {
2103 MachineFunction &MF = DAG.getMachineFunction();
2104 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2105 unsigned ARMPCLabelIndex = 0;
2106 DebugLoc DL = Op.getDebugLoc();
2107 EVT PtrVT = getPointerTy();
2108 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2109 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2111 if (RelocM == Reloc::Static) {
2112 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2114 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2115 ARMPCLabelIndex = AFI->createPICLabelUId();
2116 ARMConstantPoolValue *CPV =
2117 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2118 ARMCP::CPBlockAddress, PCAdj);
2119 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2121 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2122 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2123 MachinePointerInfo::getConstantPool(),
2124 false, false, false, 0);
2125 if (RelocM == Reloc::Static)
2127 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2128 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2131 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2133 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2134 SelectionDAG &DAG) const {
2135 DebugLoc dl = GA->getDebugLoc();
2136 EVT PtrVT = getPointerTy();
2137 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2138 MachineFunction &MF = DAG.getMachineFunction();
2139 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2140 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2141 ARMConstantPoolValue *CPV =
2142 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2143 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2144 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2145 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2146 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2147 MachinePointerInfo::getConstantPool(),
2148 false, false, false, 0);
2149 SDValue Chain = Argument.getValue(1);
2151 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2152 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2154 // call __tls_get_addr.
2157 Entry.Node = Argument;
2158 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2159 Args.push_back(Entry);
2160 // FIXME: is there useful debug info available here?
2161 TargetLowering::CallLoweringInfo CLI(Chain,
2162 (Type *) Type::getInt32Ty(*DAG.getContext()),
2163 false, false, false, false,
2164 0, CallingConv::C, /*isTailCall=*/false,
2165 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
2166 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
2167 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2168 return CallResult.first;
2171 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2172 // "local exec" model.
2174 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2176 TLSModel::Model model) const {
2177 const GlobalValue *GV = GA->getGlobal();
2178 DebugLoc dl = GA->getDebugLoc();
2180 SDValue Chain = DAG.getEntryNode();
2181 EVT PtrVT = getPointerTy();
2182 // Get the Thread Pointer
2183 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2185 if (model == TLSModel::InitialExec) {
2186 MachineFunction &MF = DAG.getMachineFunction();
2187 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2188 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2189 // Initial exec model.
2190 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2191 ARMConstantPoolValue *CPV =
2192 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2193 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2195 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2196 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2197 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2198 MachinePointerInfo::getConstantPool(),
2199 false, false, false, 0);
2200 Chain = Offset.getValue(1);
2202 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2203 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2205 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2206 MachinePointerInfo::getConstantPool(),
2207 false, false, false, 0);
2210 assert(model == TLSModel::LocalExec);
2211 ARMConstantPoolValue *CPV =
2212 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2213 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2214 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2215 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2216 MachinePointerInfo::getConstantPool(),
2217 false, false, false, 0);
2220 // The address of the thread local variable is the add of the thread
2221 // pointer with the offset of the variable.
2222 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2226 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2227 // TODO: implement the "local dynamic" model
2228 assert(Subtarget->isTargetELF() &&
2229 "TLS not implemented for non-ELF targets");
2230 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2232 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2235 case TLSModel::GeneralDynamic:
2236 case TLSModel::LocalDynamic:
2237 return LowerToTLSGeneralDynamicModel(GA, DAG);
2238 case TLSModel::InitialExec:
2239 case TLSModel::LocalExec:
2240 return LowerToTLSExecModels(GA, DAG, model);
2242 llvm_unreachable("bogus TLS model");
2245 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2246 SelectionDAG &DAG) const {
2247 EVT PtrVT = getPointerTy();
2248 DebugLoc dl = Op.getDebugLoc();
2249 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2250 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2251 if (RelocM == Reloc::PIC_) {
2252 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2253 ARMConstantPoolValue *CPV =
2254 ARMConstantPoolConstant::Create(GV,
2255 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2256 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2257 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2258 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2260 MachinePointerInfo::getConstantPool(),
2261 false, false, false, 0);
2262 SDValue Chain = Result.getValue(1);
2263 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2264 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2266 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2267 MachinePointerInfo::getGOT(),
2268 false, false, false, 0);
2272 // If we have T2 ops, we can materialize the address directly via movt/movw
2273 // pair. This is always cheaper.
2274 if (Subtarget->useMovt()) {
2276 // FIXME: Once remat is capable of dealing with instructions with register
2277 // operands, expand this into two nodes.
2278 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2279 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2281 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2282 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2283 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2284 MachinePointerInfo::getConstantPool(),
2285 false, false, false, 0);
2289 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2290 SelectionDAG &DAG) const {
2291 EVT PtrVT = getPointerTy();
2292 DebugLoc dl = Op.getDebugLoc();
2293 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2294 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2295 MachineFunction &MF = DAG.getMachineFunction();
2296 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2298 // FIXME: Enable this for static codegen when tool issues are fixed. Also
2299 // update ARMFastISel::ARMMaterializeGV.
2300 if (Subtarget->useMovt() && RelocM != Reloc::Static) {
2302 // FIXME: Once remat is capable of dealing with instructions with register
2303 // operands, expand this into two nodes.
2304 if (RelocM == Reloc::Static)
2305 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2306 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2308 unsigned Wrapper = (RelocM == Reloc::PIC_)
2309 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2310 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2311 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2312 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2313 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2314 MachinePointerInfo::getGOT(),
2315 false, false, false, 0);
2319 unsigned ARMPCLabelIndex = 0;
2321 if (RelocM == Reloc::Static) {
2322 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2324 ARMPCLabelIndex = AFI->createPICLabelUId();
2325 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2326 ARMConstantPoolValue *CPV =
2327 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue,
2329 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2331 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2333 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2334 MachinePointerInfo::getConstantPool(),
2335 false, false, false, 0);
2336 SDValue Chain = Result.getValue(1);
2338 if (RelocM == Reloc::PIC_) {
2339 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2340 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2343 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2344 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2345 false, false, false, 0);
2350 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2351 SelectionDAG &DAG) const {
2352 assert(Subtarget->isTargetELF() &&
2353 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2354 MachineFunction &MF = DAG.getMachineFunction();
2355 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2356 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2357 EVT PtrVT = getPointerTy();
2358 DebugLoc dl = Op.getDebugLoc();
2359 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2360 ARMConstantPoolValue *CPV =
2361 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2362 ARMPCLabelIndex, PCAdj);
2363 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2364 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2365 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2366 MachinePointerInfo::getConstantPool(),
2367 false, false, false, 0);
2368 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2369 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2373 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2374 DebugLoc dl = Op.getDebugLoc();
2375 SDValue Val = DAG.getConstant(0, MVT::i32);
2376 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2377 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2378 Op.getOperand(1), Val);
2382 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2383 DebugLoc dl = Op.getDebugLoc();
2384 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2385 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2389 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2390 const ARMSubtarget *Subtarget) const {
2391 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2392 DebugLoc dl = Op.getDebugLoc();
2394 default: return SDValue(); // Don't custom lower most intrinsics.
2395 case Intrinsic::arm_thread_pointer: {
2396 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2397 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2399 case Intrinsic::eh_sjlj_lsda: {
2400 MachineFunction &MF = DAG.getMachineFunction();
2401 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2402 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2403 EVT PtrVT = getPointerTy();
2404 DebugLoc dl = Op.getDebugLoc();
2405 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2407 unsigned PCAdj = (RelocM != Reloc::PIC_)
2408 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2409 ARMConstantPoolValue *CPV =
2410 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2411 ARMCP::CPLSDA, PCAdj);
2412 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2413 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2415 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2416 MachinePointerInfo::getConstantPool(),
2417 false, false, false, 0);
2419 if (RelocM == Reloc::PIC_) {
2420 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2421 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2425 case Intrinsic::arm_neon_vmulls:
2426 case Intrinsic::arm_neon_vmullu: {
2427 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2428 ? ARMISD::VMULLs : ARMISD::VMULLu;
2429 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2430 Op.getOperand(1), Op.getOperand(2));
2435 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2436 const ARMSubtarget *Subtarget) {
2437 DebugLoc dl = Op.getDebugLoc();
2438 if (!Subtarget->hasDataBarrier()) {
2439 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2440 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2442 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2443 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2444 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2445 DAG.getConstant(0, MVT::i32));
2448 SDValue Op5 = Op.getOperand(5);
2449 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2450 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2451 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2452 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2454 ARM_MB::MemBOpt DMBOpt;
2455 if (isDeviceBarrier)
2456 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2458 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2459 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2460 DAG.getConstant(DMBOpt, MVT::i32));
2464 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2465 const ARMSubtarget *Subtarget) {
2466 // FIXME: handle "fence singlethread" more efficiently.
2467 DebugLoc dl = Op.getDebugLoc();
2468 if (!Subtarget->hasDataBarrier()) {
2469 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2470 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2472 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2473 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2474 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2475 DAG.getConstant(0, MVT::i32));
2478 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2479 DAG.getConstant(ARM_MB::ISH, MVT::i32));
2482 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2483 const ARMSubtarget *Subtarget) {
2484 // ARM pre v5TE and Thumb1 does not have preload instructions.
2485 if (!(Subtarget->isThumb2() ||
2486 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2487 // Just preserve the chain.
2488 return Op.getOperand(0);
2490 DebugLoc dl = Op.getDebugLoc();
2491 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2493 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2494 // ARMv7 with MP extension has PLDW.
2495 return Op.getOperand(0);
2497 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2498 if (Subtarget->isThumb()) {
2500 isRead = ~isRead & 1;
2501 isData = ~isData & 1;
2504 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2505 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2506 DAG.getConstant(isData, MVT::i32));
2509 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2510 MachineFunction &MF = DAG.getMachineFunction();
2511 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2513 // vastart just stores the address of the VarArgsFrameIndex slot into the
2514 // memory location argument.
2515 DebugLoc dl = Op.getDebugLoc();
2516 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2517 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2518 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2519 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2520 MachinePointerInfo(SV), false, false, 0);
2524 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2525 SDValue &Root, SelectionDAG &DAG,
2526 DebugLoc dl) const {
2527 MachineFunction &MF = DAG.getMachineFunction();
2528 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2530 const TargetRegisterClass *RC;
2531 if (AFI->isThumb1OnlyFunction())
2532 RC = &ARM::tGPRRegClass;
2534 RC = &ARM::GPRRegClass;
2536 // Transform the arguments stored in physical registers into virtual ones.
2537 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2538 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2541 if (NextVA.isMemLoc()) {
2542 MachineFrameInfo *MFI = MF.getFrameInfo();
2543 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2545 // Create load node to retrieve arguments from the stack.
2546 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2547 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2548 MachinePointerInfo::getFixedStack(FI),
2549 false, false, false, 0);
2551 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2552 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2555 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2559 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2560 unsigned &VARegSize, unsigned &VARegSaveSize)
2563 if (CCInfo.isFirstByValRegValid())
2564 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
2566 unsigned int firstUnalloced;
2567 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2568 sizeof(GPRArgRegs) /
2569 sizeof(GPRArgRegs[0]));
2570 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2573 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2574 VARegSize = NumGPRs * 4;
2575 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2578 // The remaining GPRs hold either the beginning of variable-argument
2579 // data, or the beginning of an aggregate passed by value (usuall
2580 // byval). Either way, we allocate stack slots adjacent to the data
2581 // provided by our caller, and store the unallocated registers there.
2582 // If this is a variadic function, the va_list pointer will begin with
2583 // these values; otherwise, this reassembles a (byval) structure that
2584 // was split between registers and memory.
2586 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2587 DebugLoc dl, SDValue &Chain,
2588 const Value *OrigArg,
2589 unsigned OffsetFromOrigArg,
2591 bool ForceMutable) const {
2592 MachineFunction &MF = DAG.getMachineFunction();
2593 MachineFrameInfo *MFI = MF.getFrameInfo();
2594 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2595 unsigned firstRegToSaveIndex;
2596 if (CCInfo.isFirstByValRegValid())
2597 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
2599 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2600 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2603 unsigned VARegSize, VARegSaveSize;
2604 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2605 if (VARegSaveSize) {
2606 // If this function is vararg, store any remaining integer argument regs
2607 // to their spots on the stack so that they may be loaded by deferencing
2608 // the result of va_next.
2609 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2610 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize,
2611 ArgOffset + VARegSaveSize
2614 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2617 SmallVector<SDValue, 4> MemOps;
2618 for (unsigned i = 0; firstRegToSaveIndex < 4; ++firstRegToSaveIndex, ++i) {
2619 const TargetRegisterClass *RC;
2620 if (AFI->isThumb1OnlyFunction())
2621 RC = &ARM::tGPRRegClass;
2623 RC = &ARM::GPRRegClass;
2625 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2626 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2628 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2629 MachinePointerInfo(OrigArg, OffsetFromOrigArg + 4*i),
2631 MemOps.push_back(Store);
2632 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2633 DAG.getConstant(4, getPointerTy()));
2635 if (!MemOps.empty())
2636 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2637 &MemOps[0], MemOps.size());
2639 // This will point to the next argument passed via stack.
2640 AFI->setVarArgsFrameIndex(
2641 MFI->CreateFixedObject(4, ArgOffset, !ForceMutable));
2645 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2646 CallingConv::ID CallConv, bool isVarArg,
2647 const SmallVectorImpl<ISD::InputArg>
2649 DebugLoc dl, SelectionDAG &DAG,
2650 SmallVectorImpl<SDValue> &InVals)
2652 MachineFunction &MF = DAG.getMachineFunction();
2653 MachineFrameInfo *MFI = MF.getFrameInfo();
2655 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2657 // Assign locations to all of the incoming arguments.
2658 SmallVector<CCValAssign, 16> ArgLocs;
2659 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2660 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2661 CCInfo.AnalyzeFormalArguments(Ins,
2662 CCAssignFnForNode(CallConv, /* Return*/ false,
2665 SmallVector<SDValue, 16> ArgValues;
2666 int lastInsIndex = -1;
2668 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2669 unsigned CurArgIdx = 0;
2670 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2671 CCValAssign &VA = ArgLocs[i];
2672 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
2673 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
2674 // Arguments stored in registers.
2675 if (VA.isRegLoc()) {
2676 EVT RegVT = VA.getLocVT();
2678 if (VA.needsCustom()) {
2679 // f64 and vector types are split up into multiple registers or
2680 // combinations of registers and stack slots.
2681 if (VA.getLocVT() == MVT::v2f64) {
2682 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2684 VA = ArgLocs[++i]; // skip ahead to next loc
2686 if (VA.isMemLoc()) {
2687 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2688 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2689 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2690 MachinePointerInfo::getFixedStack(FI),
2691 false, false, false, 0);
2693 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2696 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2697 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2698 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2699 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2700 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2702 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2705 const TargetRegisterClass *RC;
2707 if (RegVT == MVT::f32)
2708 RC = &ARM::SPRRegClass;
2709 else if (RegVT == MVT::f64)
2710 RC = &ARM::DPRRegClass;
2711 else if (RegVT == MVT::v2f64)
2712 RC = &ARM::QPRRegClass;
2713 else if (RegVT == MVT::i32)
2714 RC = AFI->isThumb1OnlyFunction() ?
2715 (const TargetRegisterClass*)&ARM::tGPRRegClass :
2716 (const TargetRegisterClass*)&ARM::GPRRegClass;
2718 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2720 // Transform the arguments in physical registers into virtual ones.
2721 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2722 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2725 // If this is an 8 or 16-bit value, it is really passed promoted
2726 // to 32 bits. Insert an assert[sz]ext to capture this, then
2727 // truncate to the right size.
2728 switch (VA.getLocInfo()) {
2729 default: llvm_unreachable("Unknown loc info!");
2730 case CCValAssign::Full: break;
2731 case CCValAssign::BCvt:
2732 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2734 case CCValAssign::SExt:
2735 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2736 DAG.getValueType(VA.getValVT()));
2737 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2739 case CCValAssign::ZExt:
2740 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2741 DAG.getValueType(VA.getValVT()));
2742 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2746 InVals.push_back(ArgValue);
2748 } else { // VA.isRegLoc()
2751 assert(VA.isMemLoc());
2752 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2754 int index = ArgLocs[i].getValNo();
2756 // Some Ins[] entries become multiple ArgLoc[] entries.
2757 // Process them only once.
2758 if (index != lastInsIndex)
2760 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2761 // FIXME: For now, all byval parameter objects are marked mutable.
2762 // This can be changed with more analysis.
2763 // In case of tail call optimization mark all arguments mutable.
2764 // Since they could be overwritten by lowering of arguments in case of
2766 if (Flags.isByVal()) {
2767 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2768 if (!AFI->getVarArgsFrameIndex()) {
2769 VarArgStyleRegisters(CCInfo, DAG,
2770 dl, Chain, CurOrigArg,
2771 Ins[VA.getValNo()].PartOffset,
2772 VA.getLocMemOffset(),
2773 true /*force mutable frames*/);
2774 int VAFrameIndex = AFI->getVarArgsFrameIndex();
2775 InVals.push_back(DAG.getFrameIndex(VAFrameIndex, getPointerTy()));
2777 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
2778 VA.getLocMemOffset(), false);
2779 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2782 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2783 VA.getLocMemOffset(), true);
2785 // Create load nodes to retrieve arguments from the stack.
2786 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2787 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2788 MachinePointerInfo::getFixedStack(FI),
2789 false, false, false, 0));
2791 lastInsIndex = index;
2798 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0, 0,
2799 CCInfo.getNextStackOffset());
2804 /// isFloatingPointZero - Return true if this is +0.0.
2805 static bool isFloatingPointZero(SDValue Op) {
2806 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2807 return CFP->getValueAPF().isPosZero();
2808 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2809 // Maybe this has already been legalized into the constant pool?
2810 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2811 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2812 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2813 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2814 return CFP->getValueAPF().isPosZero();
2820 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2821 /// the given operands.
2823 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2824 SDValue &ARMcc, SelectionDAG &DAG,
2825 DebugLoc dl) const {
2826 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2827 unsigned C = RHSC->getZExtValue();
2828 if (!isLegalICmpImmediate(C)) {
2829 // Constant does not fit, try adjusting it by one?
2834 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2835 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2836 RHS = DAG.getConstant(C-1, MVT::i32);
2841 if (C != 0 && isLegalICmpImmediate(C-1)) {
2842 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2843 RHS = DAG.getConstant(C-1, MVT::i32);
2848 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2849 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2850 RHS = DAG.getConstant(C+1, MVT::i32);
2855 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2856 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2857 RHS = DAG.getConstant(C+1, MVT::i32);
2864 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2865 ARMISD::NodeType CompareType;
2868 CompareType = ARMISD::CMP;
2873 CompareType = ARMISD::CMPZ;
2876 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2877 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2880 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2882 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2883 DebugLoc dl) const {
2885 if (!isFloatingPointZero(RHS))
2886 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2888 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2889 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2892 /// duplicateCmp - Glue values can have only one use, so this function
2893 /// duplicates a comparison node.
2895 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2896 unsigned Opc = Cmp.getOpcode();
2897 DebugLoc DL = Cmp.getDebugLoc();
2898 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2899 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2901 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2902 Cmp = Cmp.getOperand(0);
2903 Opc = Cmp.getOpcode();
2904 if (Opc == ARMISD::CMPFP)
2905 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2907 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2908 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2910 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2913 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2914 SDValue Cond = Op.getOperand(0);
2915 SDValue SelectTrue = Op.getOperand(1);
2916 SDValue SelectFalse = Op.getOperand(2);
2917 DebugLoc dl = Op.getDebugLoc();
2921 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2922 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2924 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2925 const ConstantSDNode *CMOVTrue =
2926 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2927 const ConstantSDNode *CMOVFalse =
2928 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2930 if (CMOVTrue && CMOVFalse) {
2931 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2932 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2936 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2938 False = SelectFalse;
2939 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2944 if (True.getNode() && False.getNode()) {
2945 EVT VT = Op.getValueType();
2946 SDValue ARMcc = Cond.getOperand(2);
2947 SDValue CCR = Cond.getOperand(3);
2948 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2949 assert(True.getValueType() == VT);
2950 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2955 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
2956 // undefined bits before doing a full-word comparison with zero.
2957 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
2958 DAG.getConstant(1, Cond.getValueType()));
2960 return DAG.getSelectCC(dl, Cond,
2961 DAG.getConstant(0, Cond.getValueType()),
2962 SelectTrue, SelectFalse, ISD::SETNE);
2965 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2966 EVT VT = Op.getValueType();
2967 SDValue LHS = Op.getOperand(0);
2968 SDValue RHS = Op.getOperand(1);
2969 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2970 SDValue TrueVal = Op.getOperand(2);
2971 SDValue FalseVal = Op.getOperand(3);
2972 DebugLoc dl = Op.getDebugLoc();
2974 if (LHS.getValueType() == MVT::i32) {
2976 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2977 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2978 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2981 ARMCC::CondCodes CondCode, CondCode2;
2982 FPCCToARMCC(CC, CondCode, CondCode2);
2984 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2985 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2986 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2987 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2989 if (CondCode2 != ARMCC::AL) {
2990 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2991 // FIXME: Needs another CMP because flag can have but one use.
2992 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2993 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2994 Result, TrueVal, ARMcc2, CCR, Cmp2);
2999 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
3000 /// to morph to an integer compare sequence.
3001 static bool canChangeToInt(SDValue Op, bool &SeenZero,
3002 const ARMSubtarget *Subtarget) {
3003 SDNode *N = Op.getNode();
3004 if (!N->hasOneUse())
3005 // Otherwise it requires moving the value from fp to integer registers.
3007 if (!N->getNumValues())
3009 EVT VT = Op.getValueType();
3010 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3011 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3012 // vmrs are very slow, e.g. cortex-a8.
3015 if (isFloatingPointZero(Op)) {
3019 return ISD::isNormalLoad(N);
3022 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3023 if (isFloatingPointZero(Op))
3024 return DAG.getConstant(0, MVT::i32);
3026 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3027 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
3028 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3029 Ld->isVolatile(), Ld->isNonTemporal(),
3030 Ld->isInvariant(), Ld->getAlignment());
3032 llvm_unreachable("Unknown VFP cmp argument!");
3035 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3036 SDValue &RetVal1, SDValue &RetVal2) {
3037 if (isFloatingPointZero(Op)) {
3038 RetVal1 = DAG.getConstant(0, MVT::i32);
3039 RetVal2 = DAG.getConstant(0, MVT::i32);
3043 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3044 SDValue Ptr = Ld->getBasePtr();
3045 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
3046 Ld->getChain(), Ptr,
3047 Ld->getPointerInfo(),
3048 Ld->isVolatile(), Ld->isNonTemporal(),
3049 Ld->isInvariant(), Ld->getAlignment());
3051 EVT PtrType = Ptr.getValueType();
3052 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3053 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
3054 PtrType, Ptr, DAG.getConstant(4, PtrType));
3055 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
3056 Ld->getChain(), NewPtr,
3057 Ld->getPointerInfo().getWithOffset(4),
3058 Ld->isVolatile(), Ld->isNonTemporal(),
3059 Ld->isInvariant(), NewAlign);
3063 llvm_unreachable("Unknown VFP cmp argument!");
3066 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3067 /// f32 and even f64 comparisons to integer ones.
3069 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3070 SDValue Chain = Op.getOperand(0);
3071 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3072 SDValue LHS = Op.getOperand(2);
3073 SDValue RHS = Op.getOperand(3);
3074 SDValue Dest = Op.getOperand(4);
3075 DebugLoc dl = Op.getDebugLoc();
3077 bool LHSSeenZero = false;
3078 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3079 bool RHSSeenZero = false;
3080 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3081 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3082 // If unsafe fp math optimization is enabled and there are no other uses of
3083 // the CMP operands, and the condition code is EQ or NE, we can optimize it
3084 // to an integer comparison.
3085 if (CC == ISD::SETOEQ)
3087 else if (CC == ISD::SETUNE)
3090 SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
3092 if (LHS.getValueType() == MVT::f32) {
3093 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3094 bitcastf32Toi32(LHS, DAG), Mask);
3095 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3096 bitcastf32Toi32(RHS, DAG), Mask);
3097 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3098 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3099 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3100 Chain, Dest, ARMcc, CCR, Cmp);
3105 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3106 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3107 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3108 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3109 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3110 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3111 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3112 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3113 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
3119 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3120 SDValue Chain = Op.getOperand(0);
3121 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3122 SDValue LHS = Op.getOperand(2);
3123 SDValue RHS = Op.getOperand(3);
3124 SDValue Dest = Op.getOperand(4);
3125 DebugLoc dl = Op.getDebugLoc();
3127 if (LHS.getValueType() == MVT::i32) {
3129 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3130 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3131 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3132 Chain, Dest, ARMcc, CCR, Cmp);
3135 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3137 if (getTargetMachine().Options.UnsafeFPMath &&
3138 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3139 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3140 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3141 if (Result.getNode())
3145 ARMCC::CondCodes CondCode, CondCode2;
3146 FPCCToARMCC(CC, CondCode, CondCode2);
3148 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3149 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3150 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3151 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3152 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3153 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3154 if (CondCode2 != ARMCC::AL) {
3155 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3156 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3157 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3162 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3163 SDValue Chain = Op.getOperand(0);
3164 SDValue Table = Op.getOperand(1);
3165 SDValue Index = Op.getOperand(2);
3166 DebugLoc dl = Op.getDebugLoc();
3168 EVT PTy = getPointerTy();
3169 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3170 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3171 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
3172 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3173 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3174 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
3175 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3176 if (Subtarget->isThumb2()) {
3177 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3178 // which does another jump to the destination. This also makes it easier
3179 // to translate it to TBB / TBH later.
3180 // FIXME: This might not work if the function is extremely large.
3181 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3182 Addr, Op.getOperand(2), JTI, UId);
3184 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3185 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3186 MachinePointerInfo::getJumpTable(),
3187 false, false, false, 0);
3188 Chain = Addr.getValue(1);
3189 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3190 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3192 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3193 MachinePointerInfo::getJumpTable(),
3194 false, false, false, 0);
3195 Chain = Addr.getValue(1);
3196 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3200 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3201 EVT VT = Op.getValueType();
3202 DebugLoc dl = Op.getDebugLoc();
3204 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3205 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3207 return DAG.UnrollVectorOp(Op.getNode());
3210 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3211 "Invalid type for custom lowering!");
3212 if (VT != MVT::v4i16)
3213 return DAG.UnrollVectorOp(Op.getNode());
3215 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3216 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3219 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3220 EVT VT = Op.getValueType();
3222 return LowerVectorFP_TO_INT(Op, DAG);
3224 DebugLoc dl = Op.getDebugLoc();
3227 switch (Op.getOpcode()) {
3228 default: llvm_unreachable("Invalid opcode!");
3229 case ISD::FP_TO_SINT:
3230 Opc = ARMISD::FTOSI;
3232 case ISD::FP_TO_UINT:
3233 Opc = ARMISD::FTOUI;
3236 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3237 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3240 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3241 EVT VT = Op.getValueType();
3242 DebugLoc dl = Op.getDebugLoc();
3244 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3245 if (VT.getVectorElementType() == MVT::f32)
3247 return DAG.UnrollVectorOp(Op.getNode());
3250 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3251 "Invalid type for custom lowering!");
3252 if (VT != MVT::v4f32)
3253 return DAG.UnrollVectorOp(Op.getNode());
3257 switch (Op.getOpcode()) {
3258 default: llvm_unreachable("Invalid opcode!");
3259 case ISD::SINT_TO_FP:
3260 CastOpc = ISD::SIGN_EXTEND;
3261 Opc = ISD::SINT_TO_FP;
3263 case ISD::UINT_TO_FP:
3264 CastOpc = ISD::ZERO_EXTEND;
3265 Opc = ISD::UINT_TO_FP;
3269 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3270 return DAG.getNode(Opc, dl, VT, Op);
3273 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3274 EVT VT = Op.getValueType();
3276 return LowerVectorINT_TO_FP(Op, DAG);
3278 DebugLoc dl = Op.getDebugLoc();
3281 switch (Op.getOpcode()) {
3282 default: llvm_unreachable("Invalid opcode!");
3283 case ISD::SINT_TO_FP:
3284 Opc = ARMISD::SITOF;
3286 case ISD::UINT_TO_FP:
3287 Opc = ARMISD::UITOF;
3291 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3292 return DAG.getNode(Opc, dl, VT, Op);
3295 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3296 // Implement fcopysign with a fabs and a conditional fneg.
3297 SDValue Tmp0 = Op.getOperand(0);
3298 SDValue Tmp1 = Op.getOperand(1);
3299 DebugLoc dl = Op.getDebugLoc();
3300 EVT VT = Op.getValueType();
3301 EVT SrcVT = Tmp1.getValueType();
3302 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3303 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3304 bool UseNEON = !InGPR && Subtarget->hasNEON();
3307 // Use VBSL to copy the sign bit.
3308 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3309 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3310 DAG.getTargetConstant(EncodedVal, MVT::i32));
3311 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3313 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3314 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3315 DAG.getConstant(32, MVT::i32));
3316 else /*if (VT == MVT::f32)*/
3317 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3318 if (SrcVT == MVT::f32) {
3319 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3321 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3322 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3323 DAG.getConstant(32, MVT::i32));
3324 } else if (VT == MVT::f32)
3325 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3326 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3327 DAG.getConstant(32, MVT::i32));
3328 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3329 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3331 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3333 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3334 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3335 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3337 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3338 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3339 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3340 if (VT == MVT::f32) {
3341 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3342 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3343 DAG.getConstant(0, MVT::i32));
3345 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3351 // Bitcast operand 1 to i32.
3352 if (SrcVT == MVT::f64)
3353 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3354 &Tmp1, 1).getValue(1);
3355 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3357 // Or in the signbit with integer operations.
3358 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3359 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3360 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3361 if (VT == MVT::f32) {
3362 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3363 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3364 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3365 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3368 // f64: Or the high part with signbit and then combine two parts.
3369 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3371 SDValue Lo = Tmp0.getValue(0);
3372 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3373 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3374 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3377 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3378 MachineFunction &MF = DAG.getMachineFunction();
3379 MachineFrameInfo *MFI = MF.getFrameInfo();
3380 MFI->setReturnAddressIsTaken(true);
3382 EVT VT = Op.getValueType();
3383 DebugLoc dl = Op.getDebugLoc();
3384 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3386 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3387 SDValue Offset = DAG.getConstant(4, MVT::i32);
3388 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3389 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3390 MachinePointerInfo(), false, false, false, 0);
3393 // Return LR, which contains the return address. Mark it an implicit live-in.
3394 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3395 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3398 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3399 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3400 MFI->setFrameAddressIsTaken(true);
3402 EVT VT = Op.getValueType();
3403 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3404 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3405 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3406 ? ARM::R7 : ARM::R11;
3407 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3409 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3410 MachinePointerInfo(),
3411 false, false, false, 0);
3415 /// ExpandBITCAST - If the target supports VFP, this function is called to
3416 /// expand a bit convert where either the source or destination type is i64 to
3417 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3418 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3419 /// vectors), since the legalizer won't know what to do with that.
3420 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3421 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3422 DebugLoc dl = N->getDebugLoc();
3423 SDValue Op = N->getOperand(0);
3425 // This function is only supposed to be called for i64 types, either as the
3426 // source or destination of the bit convert.
3427 EVT SrcVT = Op.getValueType();
3428 EVT DstVT = N->getValueType(0);
3429 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3430 "ExpandBITCAST called for non-i64 type");
3432 // Turn i64->f64 into VMOVDRR.
3433 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3434 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3435 DAG.getConstant(0, MVT::i32));
3436 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3437 DAG.getConstant(1, MVT::i32));
3438 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3439 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3442 // Turn f64->i64 into VMOVRRD.
3443 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3444 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3445 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3446 // Merge the pieces into a single i64 value.
3447 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3453 /// getZeroVector - Returns a vector of specified type with all zero elements.
3454 /// Zero vectors are used to represent vector negation and in those cases
3455 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3456 /// not support i64 elements, so sometimes the zero vectors will need to be
3457 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3459 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3460 assert(VT.isVector() && "Expected a vector type");
3461 // The canonical modified immediate encoding of a zero vector is....0!
3462 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3463 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3464 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3465 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3468 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3469 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3470 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3471 SelectionDAG &DAG) const {
3472 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3473 EVT VT = Op.getValueType();
3474 unsigned VTBits = VT.getSizeInBits();
3475 DebugLoc dl = Op.getDebugLoc();
3476 SDValue ShOpLo = Op.getOperand(0);
3477 SDValue ShOpHi = Op.getOperand(1);
3478 SDValue ShAmt = Op.getOperand(2);
3480 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3482 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3484 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3485 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3486 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3487 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3488 DAG.getConstant(VTBits, MVT::i32));
3489 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3490 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3491 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3493 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3494 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3496 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3497 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3500 SDValue Ops[2] = { Lo, Hi };
3501 return DAG.getMergeValues(Ops, 2, dl);
3504 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3505 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3506 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3507 SelectionDAG &DAG) const {
3508 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3509 EVT VT = Op.getValueType();
3510 unsigned VTBits = VT.getSizeInBits();
3511 DebugLoc dl = Op.getDebugLoc();
3512 SDValue ShOpLo = Op.getOperand(0);
3513 SDValue ShOpHi = Op.getOperand(1);
3514 SDValue ShAmt = Op.getOperand(2);
3517 assert(Op.getOpcode() == ISD::SHL_PARTS);
3518 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3519 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3520 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3521 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3522 DAG.getConstant(VTBits, MVT::i32));
3523 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3524 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3526 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3527 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3528 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3530 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3531 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3534 SDValue Ops[2] = { Lo, Hi };
3535 return DAG.getMergeValues(Ops, 2, dl);
3538 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3539 SelectionDAG &DAG) const {
3540 // The rounding mode is in bits 23:22 of the FPSCR.
3541 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3542 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3543 // so that the shift + and get folded into a bitfield extract.
3544 DebugLoc dl = Op.getDebugLoc();
3545 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3546 DAG.getConstant(Intrinsic::arm_get_fpscr,
3548 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3549 DAG.getConstant(1U << 22, MVT::i32));
3550 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3551 DAG.getConstant(22, MVT::i32));
3552 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3553 DAG.getConstant(3, MVT::i32));
3556 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3557 const ARMSubtarget *ST) {
3558 EVT VT = N->getValueType(0);
3559 DebugLoc dl = N->getDebugLoc();
3561 if (!ST->hasV6T2Ops())
3564 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3565 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3568 /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
3569 /// for each 16-bit element from operand, repeated. The basic idea is to
3570 /// leverage vcnt to get the 8-bit counts, gather and add the results.
3572 /// Trace for v4i16:
3573 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
3574 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
3575 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
3576 /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
3577 /// [b0 b1 b2 b3 b4 b5 b6 b7]
3578 /// +[b1 b0 b3 b2 b5 b4 b7 b6]
3579 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
3580 /// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
3581 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
3582 EVT VT = N->getValueType(0);
3583 DebugLoc DL = N->getDebugLoc();
3585 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
3586 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
3587 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
3588 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
3589 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
3590 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
3593 /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
3594 /// bit-count for each 16-bit element from the operand. We need slightly
3595 /// different sequencing for v4i16 and v8i16 to stay within NEON's available
3596 /// 64/128-bit registers.
3598 /// Trace for v4i16:
3599 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
3600 /// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
3601 /// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
3602 /// v4i16:Extracted = [k0 k1 k2 k3 ]
3603 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
3604 EVT VT = N->getValueType(0);
3605 DebugLoc DL = N->getDebugLoc();
3607 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
3608 if (VT.is64BitVector()) {
3609 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
3610 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
3611 DAG.getIntPtrConstant(0));
3613 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
3614 BitCounts, DAG.getIntPtrConstant(0));
3615 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
3619 /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
3620 /// bit-count for each 32-bit element from the operand. The idea here is
3621 /// to split the vector into 16-bit elements, leverage the 16-bit count
3622 /// routine, and then combine the results.
3624 /// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
3625 /// input = [v0 v1 ] (vi: 32-bit elements)
3626 /// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
3627 /// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
3628 /// vrev: N0 = [k1 k0 k3 k2 ]
3630 /// N1 =+[k1 k0 k3 k2 ]
3632 /// N2 =+[k1 k3 k0 k2 ]
3634 /// Extended =+[k1 k3 k0 k2 ]
3636 /// Extracted=+[k1 k3 ]
3638 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
3639 EVT VT = N->getValueType(0);
3640 DebugLoc DL = N->getDebugLoc();
3642 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
3644 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
3645 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
3646 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
3647 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
3648 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
3650 if (VT.is64BitVector()) {
3651 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
3652 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
3653 DAG.getIntPtrConstant(0));
3655 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
3656 DAG.getIntPtrConstant(0));
3657 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
3661 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
3662 const ARMSubtarget *ST) {
3663 EVT VT = N->getValueType(0);
3665 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
3666 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
3667 VT == MVT::v4i16 || VT == MVT::v8i16) &&
3668 "Unexpected type for custom ctpop lowering");
3670 if (VT.getVectorElementType() == MVT::i32)
3671 return lowerCTPOP32BitElements(N, DAG);
3673 return lowerCTPOP16BitElements(N, DAG);
3676 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3677 const ARMSubtarget *ST) {
3678 EVT VT = N->getValueType(0);
3679 DebugLoc dl = N->getDebugLoc();
3684 // Lower vector shifts on NEON to use VSHL.
3685 assert(ST->hasNEON() && "unexpected vector shift");
3687 // Left shifts translate directly to the vshiftu intrinsic.
3688 if (N->getOpcode() == ISD::SHL)
3689 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3690 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3691 N->getOperand(0), N->getOperand(1));
3693 assert((N->getOpcode() == ISD::SRA ||
3694 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3696 // NEON uses the same intrinsics for both left and right shifts. For
3697 // right shifts, the shift amounts are negative, so negate the vector of
3699 EVT ShiftVT = N->getOperand(1).getValueType();
3700 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3701 getZeroVector(ShiftVT, DAG, dl),
3703 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3704 Intrinsic::arm_neon_vshifts :
3705 Intrinsic::arm_neon_vshiftu);
3706 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3707 DAG.getConstant(vshiftInt, MVT::i32),
3708 N->getOperand(0), NegatedCount);
3711 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3712 const ARMSubtarget *ST) {
3713 EVT VT = N->getValueType(0);
3714 DebugLoc dl = N->getDebugLoc();
3716 // We can get here for a node like i32 = ISD::SHL i32, i64
3720 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3721 "Unknown shift to lower!");
3723 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3724 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3725 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3728 // If we are in thumb mode, we don't have RRX.
3729 if (ST->isThumb1Only()) return SDValue();
3731 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3732 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3733 DAG.getConstant(0, MVT::i32));
3734 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3735 DAG.getConstant(1, MVT::i32));
3737 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3738 // captures the result into a carry flag.
3739 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3740 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3742 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3743 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3745 // Merge the pieces into a single i64 value.
3746 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3749 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3750 SDValue TmpOp0, TmpOp1;
3751 bool Invert = false;
3755 SDValue Op0 = Op.getOperand(0);
3756 SDValue Op1 = Op.getOperand(1);
3757 SDValue CC = Op.getOperand(2);
3758 EVT VT = Op.getValueType();
3759 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3760 DebugLoc dl = Op.getDebugLoc();
3762 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3763 switch (SetCCOpcode) {
3764 default: llvm_unreachable("Illegal FP comparison");
3766 case ISD::SETNE: Invert = true; // Fallthrough
3768 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3770 case ISD::SETLT: Swap = true; // Fallthrough
3772 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3774 case ISD::SETLE: Swap = true; // Fallthrough
3776 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3777 case ISD::SETUGE: Swap = true; // Fallthrough
3778 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3779 case ISD::SETUGT: Swap = true; // Fallthrough
3780 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3781 case ISD::SETUEQ: Invert = true; // Fallthrough
3783 // Expand this to (OLT | OGT).
3787 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3788 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3790 case ISD::SETUO: Invert = true; // Fallthrough
3792 // Expand this to (OLT | OGE).
3796 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3797 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3801 // Integer comparisons.
3802 switch (SetCCOpcode) {
3803 default: llvm_unreachable("Illegal integer comparison");
3804 case ISD::SETNE: Invert = true;
3805 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3806 case ISD::SETLT: Swap = true;
3807 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3808 case ISD::SETLE: Swap = true;
3809 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3810 case ISD::SETULT: Swap = true;
3811 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3812 case ISD::SETULE: Swap = true;
3813 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3816 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3817 if (Opc == ARMISD::VCEQ) {
3820 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3822 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3825 // Ignore bitconvert.
3826 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3827 AndOp = AndOp.getOperand(0);
3829 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3831 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3832 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3839 std::swap(Op0, Op1);
3841 // If one of the operands is a constant vector zero, attempt to fold the
3842 // comparison to a specialized compare-against-zero form.
3844 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3846 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3847 if (Opc == ARMISD::VCGE)
3848 Opc = ARMISD::VCLEZ;
3849 else if (Opc == ARMISD::VCGT)
3850 Opc = ARMISD::VCLTZ;
3855 if (SingleOp.getNode()) {
3858 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3860 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3862 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3864 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3866 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3868 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3871 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3875 Result = DAG.getNOT(dl, Result, VT);
3880 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3881 /// valid vector constant for a NEON instruction with a "modified immediate"
3882 /// operand (e.g., VMOV). If so, return the encoded value.
3883 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3884 unsigned SplatBitSize, SelectionDAG &DAG,
3885 EVT &VT, bool is128Bits, NEONModImmType type) {
3886 unsigned OpCmode, Imm;
3888 // SplatBitSize is set to the smallest size that splats the vector, so a
3889 // zero vector will always have SplatBitSize == 8. However, NEON modified
3890 // immediate instructions others than VMOV do not support the 8-bit encoding
3891 // of a zero vector, and the default encoding of zero is supposed to be the
3896 switch (SplatBitSize) {
3898 if (type != VMOVModImm)
3900 // Any 1-byte value is OK. Op=0, Cmode=1110.
3901 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3904 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3908 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3909 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3910 if ((SplatBits & ~0xff) == 0) {
3911 // Value = 0x00nn: Op=x, Cmode=100x.
3916 if ((SplatBits & ~0xff00) == 0) {
3917 // Value = 0xnn00: Op=x, Cmode=101x.
3919 Imm = SplatBits >> 8;
3925 // NEON's 32-bit VMOV supports splat values where:
3926 // * only one byte is nonzero, or
3927 // * the least significant byte is 0xff and the second byte is nonzero, or
3928 // * the least significant 2 bytes are 0xff and the third is nonzero.
3929 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3930 if ((SplatBits & ~0xff) == 0) {
3931 // Value = 0x000000nn: Op=x, Cmode=000x.
3936 if ((SplatBits & ~0xff00) == 0) {
3937 // Value = 0x0000nn00: Op=x, Cmode=001x.
3939 Imm = SplatBits >> 8;
3942 if ((SplatBits & ~0xff0000) == 0) {
3943 // Value = 0x00nn0000: Op=x, Cmode=010x.
3945 Imm = SplatBits >> 16;
3948 if ((SplatBits & ~0xff000000) == 0) {
3949 // Value = 0xnn000000: Op=x, Cmode=011x.
3951 Imm = SplatBits >> 24;
3955 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3956 if (type == OtherModImm) return SDValue();
3958 if ((SplatBits & ~0xffff) == 0 &&
3959 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3960 // Value = 0x0000nnff: Op=x, Cmode=1100.
3962 Imm = SplatBits >> 8;
3967 if ((SplatBits & ~0xffffff) == 0 &&
3968 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3969 // Value = 0x00nnffff: Op=x, Cmode=1101.
3971 Imm = SplatBits >> 16;
3972 SplatBits |= 0xffff;
3976 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3977 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3978 // VMOV.I32. A (very) minor optimization would be to replicate the value
3979 // and fall through here to test for a valid 64-bit splat. But, then the
3980 // caller would also need to check and handle the change in size.
3984 if (type != VMOVModImm)
3986 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3987 uint64_t BitMask = 0xff;
3989 unsigned ImmMask = 1;
3991 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3992 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3995 } else if ((SplatBits & BitMask) != 0) {
4001 // Op=1, Cmode=1110.
4004 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4009 llvm_unreachable("unexpected size for isNEONModifiedImm");
4012 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4013 return DAG.getTargetConstant(EncodedVal, MVT::i32);
4016 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4017 const ARMSubtarget *ST) const {
4018 if (!ST->useNEONForSinglePrecisionFP() || !ST->hasVFP3() || ST->hasD16())
4021 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4022 assert(Op.getValueType() == MVT::f32 &&
4023 "ConstantFP custom lowering should only occur for f32.");
4025 // Try splatting with a VMOV.f32...
4026 APFloat FPVal = CFP->getValueAPF();
4027 int ImmVal = ARM_AM::getFP32Imm(FPVal);
4029 DebugLoc DL = Op.getDebugLoc();
4030 SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
4031 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4033 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4034 DAG.getConstant(0, MVT::i32));
4037 // If that fails, try a VMOV.i32
4039 unsigned iVal = FPVal.bitcastToAPInt().getZExtValue();
4040 SDValue NewVal = isNEONModifiedImm(iVal, 0, 32, DAG, VMovVT, false,
4042 if (NewVal != SDValue()) {
4043 DebugLoc DL = Op.getDebugLoc();
4044 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4046 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4048 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4049 DAG.getConstant(0, MVT::i32));
4052 // Finally, try a VMVN.i32
4053 NewVal = isNEONModifiedImm(~iVal & 0xffffffff, 0, 32, DAG, VMovVT, false,
4055 if (NewVal != SDValue()) {
4056 DebugLoc DL = Op.getDebugLoc();
4057 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4058 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4060 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4061 DAG.getConstant(0, MVT::i32));
4067 // check if an VEXT instruction can handle the shuffle mask when the
4068 // vector sources of the shuffle are the same.
4069 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4070 unsigned NumElts = VT.getVectorNumElements();
4072 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4078 // If this is a VEXT shuffle, the immediate value is the index of the first
4079 // element. The other shuffle indices must be the successive elements after
4081 unsigned ExpectedElt = Imm;
4082 for (unsigned i = 1; i < NumElts; ++i) {
4083 // Increment the expected index. If it wraps around, just follow it
4084 // back to index zero and keep going.
4086 if (ExpectedElt == NumElts)
4089 if (M[i] < 0) continue; // ignore UNDEF indices
4090 if (ExpectedElt != static_cast<unsigned>(M[i]))
4098 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
4099 bool &ReverseVEXT, unsigned &Imm) {
4100 unsigned NumElts = VT.getVectorNumElements();
4101 ReverseVEXT = false;
4103 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4109 // If this is a VEXT shuffle, the immediate value is the index of the first
4110 // element. The other shuffle indices must be the successive elements after
4112 unsigned ExpectedElt = Imm;
4113 for (unsigned i = 1; i < NumElts; ++i) {
4114 // Increment the expected index. If it wraps around, it may still be
4115 // a VEXT but the source vectors must be swapped.
4117 if (ExpectedElt == NumElts * 2) {
4122 if (M[i] < 0) continue; // ignore UNDEF indices
4123 if (ExpectedElt != static_cast<unsigned>(M[i]))
4127 // Adjust the index value if the source operands will be swapped.
4134 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
4135 /// instruction with the specified blocksize. (The order of the elements
4136 /// within each block of the vector is reversed.)
4137 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4138 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
4139 "Only possible block sizes for VREV are: 16, 32, 64");
4141 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4145 unsigned NumElts = VT.getVectorNumElements();
4146 unsigned BlockElts = M[0] + 1;
4147 // If the first shuffle index is UNDEF, be optimistic.
4149 BlockElts = BlockSize / EltSz;
4151 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4154 for (unsigned i = 0; i < NumElts; ++i) {
4155 if (M[i] < 0) continue; // ignore UNDEF indices
4156 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
4163 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
4164 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
4165 // range, then 0 is placed into the resulting vector. So pretty much any mask
4166 // of 8 elements can work here.
4167 return VT == MVT::v8i8 && M.size() == 8;
4170 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4171 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4175 unsigned NumElts = VT.getVectorNumElements();
4176 WhichResult = (M[0] == 0 ? 0 : 1);
4177 for (unsigned i = 0; i < NumElts; i += 2) {
4178 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4179 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
4185 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
4186 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4187 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4188 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4189 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4193 unsigned NumElts = VT.getVectorNumElements();
4194 WhichResult = (M[0] == 0 ? 0 : 1);
4195 for (unsigned i = 0; i < NumElts; i += 2) {
4196 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4197 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
4203 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4204 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4208 unsigned NumElts = VT.getVectorNumElements();
4209 WhichResult = (M[0] == 0 ? 0 : 1);
4210 for (unsigned i = 0; i != NumElts; ++i) {
4211 if (M[i] < 0) continue; // ignore UNDEF indices
4212 if ((unsigned) M[i] != 2 * i + WhichResult)
4216 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4217 if (VT.is64BitVector() && EltSz == 32)
4223 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
4224 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4225 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4226 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4227 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4231 unsigned Half = VT.getVectorNumElements() / 2;
4232 WhichResult = (M[0] == 0 ? 0 : 1);
4233 for (unsigned j = 0; j != 2; ++j) {
4234 unsigned Idx = WhichResult;
4235 for (unsigned i = 0; i != Half; ++i) {
4236 int MIdx = M[i + j * Half];
4237 if (MIdx >= 0 && (unsigned) MIdx != Idx)
4243 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4244 if (VT.is64BitVector() && EltSz == 32)
4250 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4251 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4255 unsigned NumElts = VT.getVectorNumElements();
4256 WhichResult = (M[0] == 0 ? 0 : 1);
4257 unsigned Idx = WhichResult * NumElts / 2;
4258 for (unsigned i = 0; i != NumElts; i += 2) {
4259 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4260 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
4265 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4266 if (VT.is64BitVector() && EltSz == 32)
4272 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
4273 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4274 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4275 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4276 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4280 unsigned NumElts = VT.getVectorNumElements();
4281 WhichResult = (M[0] == 0 ? 0 : 1);
4282 unsigned Idx = WhichResult * NumElts / 2;
4283 for (unsigned i = 0; i != NumElts; i += 2) {
4284 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4285 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
4290 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4291 if (VT.is64BitVector() && EltSz == 32)
4297 // If N is an integer constant that can be moved into a register in one
4298 // instruction, return an SDValue of such a constant (will become a MOV
4299 // instruction). Otherwise return null.
4300 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
4301 const ARMSubtarget *ST, DebugLoc dl) {
4303 if (!isa<ConstantSDNode>(N))
4305 Val = cast<ConstantSDNode>(N)->getZExtValue();
4307 if (ST->isThumb1Only()) {
4308 if (Val <= 255 || ~Val <= 255)
4309 return DAG.getConstant(Val, MVT::i32);
4311 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
4312 return DAG.getConstant(Val, MVT::i32);
4317 // If this is a case we can't handle, return null and let the default
4318 // expansion code take care of it.
4319 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
4320 const ARMSubtarget *ST) const {
4321 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
4322 DebugLoc dl = Op.getDebugLoc();
4323 EVT VT = Op.getValueType();
4325 APInt SplatBits, SplatUndef;
4326 unsigned SplatBitSize;
4328 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4329 if (SplatBitSize <= 64) {
4330 // Check if an immediate VMOV works.
4332 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
4333 SplatUndef.getZExtValue(), SplatBitSize,
4334 DAG, VmovVT, VT.is128BitVector(),
4336 if (Val.getNode()) {
4337 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
4338 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4341 // Try an immediate VMVN.
4342 uint64_t NegatedImm = (~SplatBits).getZExtValue();
4343 Val = isNEONModifiedImm(NegatedImm,
4344 SplatUndef.getZExtValue(), SplatBitSize,
4345 DAG, VmovVT, VT.is128BitVector(),
4347 if (Val.getNode()) {
4348 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
4349 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4352 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
4353 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
4354 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
4356 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4357 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
4363 // Scan through the operands to see if only one value is used.
4365 // As an optimisation, even if more than one value is used it may be more
4366 // profitable to splat with one value then change some lanes.
4368 // Heuristically we decide to do this if the vector has a "dominant" value,
4369 // defined as splatted to more than half of the lanes.
4370 unsigned NumElts = VT.getVectorNumElements();
4371 bool isOnlyLowElement = true;
4372 bool usesOnlyOneValue = true;
4373 bool hasDominantValue = false;
4374 bool isConstant = true;
4376 // Map of the number of times a particular SDValue appears in the
4378 DenseMap<SDValue, unsigned> ValueCounts;
4380 for (unsigned i = 0; i < NumElts; ++i) {
4381 SDValue V = Op.getOperand(i);
4382 if (V.getOpcode() == ISD::UNDEF)
4385 isOnlyLowElement = false;
4386 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
4389 ValueCounts.insert(std::make_pair(V, 0));
4390 unsigned &Count = ValueCounts[V];
4392 // Is this value dominant? (takes up more than half of the lanes)
4393 if (++Count > (NumElts / 2)) {
4394 hasDominantValue = true;
4398 if (ValueCounts.size() != 1)
4399 usesOnlyOneValue = false;
4400 if (!Value.getNode() && ValueCounts.size() > 0)
4401 Value = ValueCounts.begin()->first;
4403 if (ValueCounts.size() == 0)
4404 return DAG.getUNDEF(VT);
4406 if (isOnlyLowElement)
4407 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
4409 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4411 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
4412 // i32 and try again.
4413 if (hasDominantValue && EltSize <= 32) {
4417 // If we are VDUPing a value that comes directly from a vector, that will
4418 // cause an unnecessary move to and from a GPR, where instead we could
4419 // just use VDUPLANE.
4420 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4421 // We need to create a new undef vector to use for the VDUPLANE if the
4422 // size of the vector from which we get the value is different than the
4423 // size of the vector that we need to create. We will insert the element
4424 // such that the register coalescer will remove unnecessary copies.
4425 if (VT != Value->getOperand(0).getValueType()) {
4426 ConstantSDNode *constIndex;
4427 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
4428 assert(constIndex && "The index is not a constant!");
4429 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
4430 VT.getVectorNumElements();
4431 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4432 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
4433 Value, DAG.getConstant(index, MVT::i32)),
4434 DAG.getConstant(index, MVT::i32));
4436 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4437 Value->getOperand(0), Value->getOperand(1));
4441 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
4443 if (!usesOnlyOneValue) {
4444 // The dominant value was splatted as 'N', but we now have to insert
4445 // all differing elements.
4446 for (unsigned I = 0; I < NumElts; ++I) {
4447 if (Op.getOperand(I) == Value)
4449 SmallVector<SDValue, 3> Ops;
4451 Ops.push_back(Op.getOperand(I));
4452 Ops.push_back(DAG.getConstant(I, MVT::i32));
4453 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, &Ops[0], 3);
4458 if (VT.getVectorElementType().isFloatingPoint()) {
4459 SmallVector<SDValue, 8> Ops;
4460 for (unsigned i = 0; i < NumElts; ++i)
4461 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4463 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
4464 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
4465 Val = LowerBUILD_VECTOR(Val, DAG, ST);
4467 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4469 if (usesOnlyOneValue) {
4470 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
4471 if (isConstant && Val.getNode())
4472 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
4476 // If all elements are constants and the case above didn't get hit, fall back
4477 // to the default expansion, which will generate a load from the constant
4482 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
4484 SDValue shuffle = ReconstructShuffle(Op, DAG);
4485 if (shuffle != SDValue())
4489 // Vectors with 32- or 64-bit elements can be built by directly assigning
4490 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
4491 // will be legalized.
4492 if (EltSize >= 32) {
4493 // Do the expansion with floating-point types, since that is what the VFP
4494 // registers are defined to use, and since i64 is not legal.
4495 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4496 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4497 SmallVector<SDValue, 8> Ops;
4498 for (unsigned i = 0; i < NumElts; ++i)
4499 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
4500 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4501 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4507 // Gather data to see if the operation can be modelled as a
4508 // shuffle in combination with VEXTs.
4509 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
4510 SelectionDAG &DAG) const {
4511 DebugLoc dl = Op.getDebugLoc();
4512 EVT VT = Op.getValueType();
4513 unsigned NumElts = VT.getVectorNumElements();
4515 SmallVector<SDValue, 2> SourceVecs;
4516 SmallVector<unsigned, 2> MinElts;
4517 SmallVector<unsigned, 2> MaxElts;
4519 for (unsigned i = 0; i < NumElts; ++i) {
4520 SDValue V = Op.getOperand(i);
4521 if (V.getOpcode() == ISD::UNDEF)
4523 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4524 // A shuffle can only come from building a vector from various
4525 // elements of other vectors.
4527 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
4528 VT.getVectorElementType()) {
4529 // This code doesn't know how to handle shuffles where the vector
4530 // element types do not match (this happens because type legalization
4531 // promotes the return type of EXTRACT_VECTOR_ELT).
4532 // FIXME: It might be appropriate to extend this code to handle
4533 // mismatched types.
4537 // Record this extraction against the appropriate vector if possible...
4538 SDValue SourceVec = V.getOperand(0);
4539 // If the element number isn't a constant, we can't effectively
4540 // analyze what's going on.
4541 if (!isa<ConstantSDNode>(V.getOperand(1)))
4543 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4544 bool FoundSource = false;
4545 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4546 if (SourceVecs[j] == SourceVec) {
4547 if (MinElts[j] > EltNo)
4549 if (MaxElts[j] < EltNo)
4556 // Or record a new source if not...
4558 SourceVecs.push_back(SourceVec);
4559 MinElts.push_back(EltNo);
4560 MaxElts.push_back(EltNo);
4564 // Currently only do something sane when at most two source vectors
4566 if (SourceVecs.size() > 2)
4569 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4570 int VEXTOffsets[2] = {0, 0};
4572 // This loop extracts the usage patterns of the source vectors
4573 // and prepares appropriate SDValues for a shuffle if possible.
4574 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4575 if (SourceVecs[i].getValueType() == VT) {
4576 // No VEXT necessary
4577 ShuffleSrcs[i] = SourceVecs[i];
4580 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4581 // It probably isn't worth padding out a smaller vector just to
4582 // break it down again in a shuffle.
4586 // Since only 64-bit and 128-bit vectors are legal on ARM and
4587 // we've eliminated the other cases...
4588 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
4589 "unexpected vector sizes in ReconstructShuffle");
4591 if (MaxElts[i] - MinElts[i] >= NumElts) {
4592 // Span too large for a VEXT to cope
4596 if (MinElts[i] >= NumElts) {
4597 // The extraction can just take the second half
4598 VEXTOffsets[i] = NumElts;
4599 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4601 DAG.getIntPtrConstant(NumElts));
4602 } else if (MaxElts[i] < NumElts) {
4603 // The extraction can just take the first half
4605 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4607 DAG.getIntPtrConstant(0));
4609 // An actual VEXT is needed
4610 VEXTOffsets[i] = MinElts[i];
4611 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4613 DAG.getIntPtrConstant(0));
4614 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4616 DAG.getIntPtrConstant(NumElts));
4617 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4618 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4622 SmallVector<int, 8> Mask;
4624 for (unsigned i = 0; i < NumElts; ++i) {
4625 SDValue Entry = Op.getOperand(i);
4626 if (Entry.getOpcode() == ISD::UNDEF) {
4631 SDValue ExtractVec = Entry.getOperand(0);
4632 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
4633 .getOperand(1))->getSExtValue();
4634 if (ExtractVec == SourceVecs[0]) {
4635 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4637 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4641 // Final check before we try to produce nonsense...
4642 if (isShuffleMaskLegal(Mask, VT))
4643 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4649 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4650 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4651 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4652 /// are assumed to be legal.
4654 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4656 if (VT.getVectorNumElements() == 4 &&
4657 (VT.is128BitVector() || VT.is64BitVector())) {
4658 unsigned PFIndexes[4];
4659 for (unsigned i = 0; i != 4; ++i) {
4663 PFIndexes[i] = M[i];
4666 // Compute the index in the perfect shuffle table.
4667 unsigned PFTableIndex =
4668 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4669 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4670 unsigned Cost = (PFEntry >> 30);
4677 unsigned Imm, WhichResult;
4679 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4680 return (EltSize >= 32 ||
4681 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4682 isVREVMask(M, VT, 64) ||
4683 isVREVMask(M, VT, 32) ||
4684 isVREVMask(M, VT, 16) ||
4685 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4686 isVTBLMask(M, VT) ||
4687 isVTRNMask(M, VT, WhichResult) ||
4688 isVUZPMask(M, VT, WhichResult) ||
4689 isVZIPMask(M, VT, WhichResult) ||
4690 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4691 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4692 isVZIP_v_undef_Mask(M, VT, WhichResult));
4695 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4696 /// the specified operations to build the shuffle.
4697 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4698 SDValue RHS, SelectionDAG &DAG,
4700 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4701 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4702 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4705 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4714 OP_VUZPL, // VUZP, left result
4715 OP_VUZPR, // VUZP, right result
4716 OP_VZIPL, // VZIP, left result
4717 OP_VZIPR, // VZIP, right result
4718 OP_VTRNL, // VTRN, left result
4719 OP_VTRNR // VTRN, right result
4722 if (OpNum == OP_COPY) {
4723 if (LHSID == (1*9+2)*9+3) return LHS;
4724 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4728 SDValue OpLHS, OpRHS;
4729 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4730 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4731 EVT VT = OpLHS.getValueType();
4734 default: llvm_unreachable("Unknown shuffle opcode!");
4736 // VREV divides the vector in half and swaps within the half.
4737 if (VT.getVectorElementType() == MVT::i32 ||
4738 VT.getVectorElementType() == MVT::f32)
4739 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4740 // vrev <4 x i16> -> VREV32
4741 if (VT.getVectorElementType() == MVT::i16)
4742 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4743 // vrev <4 x i8> -> VREV16
4744 assert(VT.getVectorElementType() == MVT::i8);
4745 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4750 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4751 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4755 return DAG.getNode(ARMISD::VEXT, dl, VT,
4757 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4760 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4761 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4764 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4765 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4768 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4769 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4773 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4774 ArrayRef<int> ShuffleMask,
4775 SelectionDAG &DAG) {
4776 // Check to see if we can use the VTBL instruction.
4777 SDValue V1 = Op.getOperand(0);
4778 SDValue V2 = Op.getOperand(1);
4779 DebugLoc DL = Op.getDebugLoc();
4781 SmallVector<SDValue, 8> VTBLMask;
4782 for (ArrayRef<int>::iterator
4783 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4784 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4786 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4787 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4788 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4791 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4792 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4796 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4797 SDValue V1 = Op.getOperand(0);
4798 SDValue V2 = Op.getOperand(1);
4799 DebugLoc dl = Op.getDebugLoc();
4800 EVT VT = Op.getValueType();
4801 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4803 // Convert shuffles that are directly supported on NEON to target-specific
4804 // DAG nodes, instead of keeping them as shuffles and matching them again
4805 // during code selection. This is more efficient and avoids the possibility
4806 // of inconsistencies between legalization and selection.
4807 // FIXME: floating-point vectors should be canonicalized to integer vectors
4808 // of the same time so that they get CSEd properly.
4809 ArrayRef<int> ShuffleMask = SVN->getMask();
4811 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4812 if (EltSize <= 32) {
4813 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4814 int Lane = SVN->getSplatIndex();
4815 // If this is undef splat, generate it via "just" vdup, if possible.
4816 if (Lane == -1) Lane = 0;
4818 // Test if V1 is a SCALAR_TO_VECTOR.
4819 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4820 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4822 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
4823 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
4825 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
4826 !isa<ConstantSDNode>(V1.getOperand(0))) {
4827 bool IsScalarToVector = true;
4828 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
4829 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
4830 IsScalarToVector = false;
4833 if (IsScalarToVector)
4834 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4836 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4837 DAG.getConstant(Lane, MVT::i32));
4842 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4845 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4846 DAG.getConstant(Imm, MVT::i32));
4849 if (isVREVMask(ShuffleMask, VT, 64))
4850 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4851 if (isVREVMask(ShuffleMask, VT, 32))
4852 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4853 if (isVREVMask(ShuffleMask, VT, 16))
4854 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4856 if (V2->getOpcode() == ISD::UNDEF &&
4857 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
4858 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
4859 DAG.getConstant(Imm, MVT::i32));
4862 // Check for Neon shuffles that modify both input vectors in place.
4863 // If both results are used, i.e., if there are two shuffles with the same
4864 // source operands and with masks corresponding to both results of one of
4865 // these operations, DAG memoization will ensure that a single node is
4866 // used for both shuffles.
4867 unsigned WhichResult;
4868 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4869 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4870 V1, V2).getValue(WhichResult);
4871 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4872 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4873 V1, V2).getValue(WhichResult);
4874 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4875 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4876 V1, V2).getValue(WhichResult);
4878 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4879 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4880 V1, V1).getValue(WhichResult);
4881 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4882 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4883 V1, V1).getValue(WhichResult);
4884 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4885 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4886 V1, V1).getValue(WhichResult);
4889 // If the shuffle is not directly supported and it has 4 elements, use
4890 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4891 unsigned NumElts = VT.getVectorNumElements();
4893 unsigned PFIndexes[4];
4894 for (unsigned i = 0; i != 4; ++i) {
4895 if (ShuffleMask[i] < 0)
4898 PFIndexes[i] = ShuffleMask[i];
4901 // Compute the index in the perfect shuffle table.
4902 unsigned PFTableIndex =
4903 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4904 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4905 unsigned Cost = (PFEntry >> 30);
4908 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4911 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4912 if (EltSize >= 32) {
4913 // Do the expansion with floating-point types, since that is what the VFP
4914 // registers are defined to use, and since i64 is not legal.
4915 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4916 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4917 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4918 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4919 SmallVector<SDValue, 8> Ops;
4920 for (unsigned i = 0; i < NumElts; ++i) {
4921 if (ShuffleMask[i] < 0)
4922 Ops.push_back(DAG.getUNDEF(EltVT));
4924 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4925 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4926 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4929 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4930 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4933 if (VT == MVT::v8i8) {
4934 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4935 if (NewOp.getNode())
4942 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4943 // INSERT_VECTOR_ELT is legal only for immediate indexes.
4944 SDValue Lane = Op.getOperand(2);
4945 if (!isa<ConstantSDNode>(Lane))
4951 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4952 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4953 SDValue Lane = Op.getOperand(1);
4954 if (!isa<ConstantSDNode>(Lane))
4957 SDValue Vec = Op.getOperand(0);
4958 if (Op.getValueType() == MVT::i32 &&
4959 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4960 DebugLoc dl = Op.getDebugLoc();
4961 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4967 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4968 // The only time a CONCAT_VECTORS operation can have legal types is when
4969 // two 64-bit vectors are concatenated to a 128-bit vector.
4970 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4971 "unexpected CONCAT_VECTORS");
4972 DebugLoc dl = Op.getDebugLoc();
4973 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4974 SDValue Op0 = Op.getOperand(0);
4975 SDValue Op1 = Op.getOperand(1);
4976 if (Op0.getOpcode() != ISD::UNDEF)
4977 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4978 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4979 DAG.getIntPtrConstant(0));
4980 if (Op1.getOpcode() != ISD::UNDEF)
4981 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4982 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4983 DAG.getIntPtrConstant(1));
4984 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4987 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4988 /// element has been zero/sign-extended, depending on the isSigned parameter,
4989 /// from an integer type half its size.
4990 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4992 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4993 EVT VT = N->getValueType(0);
4994 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4995 SDNode *BVN = N->getOperand(0).getNode();
4996 if (BVN->getValueType(0) != MVT::v4i32 ||
4997 BVN->getOpcode() != ISD::BUILD_VECTOR)
4999 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5000 unsigned HiElt = 1 - LoElt;
5001 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
5002 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
5003 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
5004 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
5005 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
5008 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
5009 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
5012 if (Hi0->isNullValue() && Hi1->isNullValue())
5018 if (N->getOpcode() != ISD::BUILD_VECTOR)
5021 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5022 SDNode *Elt = N->getOperand(i).getNode();
5023 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
5024 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5025 unsigned HalfSize = EltSize / 2;
5027 if (!isIntN(HalfSize, C->getSExtValue()))
5030 if (!isUIntN(HalfSize, C->getZExtValue()))
5041 /// isSignExtended - Check if a node is a vector value that is sign-extended
5042 /// or a constant BUILD_VECTOR with sign-extended elements.
5043 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
5044 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
5046 if (isExtendedBUILD_VECTOR(N, DAG, true))
5051 /// isZeroExtended - Check if a node is a vector value that is zero-extended
5052 /// or a constant BUILD_VECTOR with zero-extended elements.
5053 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
5054 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
5056 if (isExtendedBUILD_VECTOR(N, DAG, false))
5061 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
5062 /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
5063 /// We insert the required extension here to get the vector to fill a D register.
5064 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
5067 unsigned ExtOpcode) {
5068 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
5069 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
5070 // 64-bits we need to insert a new extension so that it will be 64-bits.
5071 assert(ExtTy.is128BitVector() && "Unexpected extension size");
5072 if (OrigTy.getSizeInBits() >= 64)
5075 // Must extend size to at least 64 bits to be used as an operand for VMULL.
5076 MVT::SimpleValueType OrigSimpleTy = OrigTy.getSimpleVT().SimpleTy;
5078 switch (OrigSimpleTy) {
5079 default: llvm_unreachable("Unexpected Orig Vector Type");
5088 return DAG.getNode(ExtOpcode, N->getDebugLoc(), NewVT, N);
5091 /// SkipLoadExtensionForVMULL - return a load of the original vector size that
5092 /// does not do any sign/zero extension. If the original vector is less
5093 /// than 64 bits, an appropriate extension will be added after the load to
5094 /// reach a total size of 64 bits. We have to add the extension separately
5095 /// because ARM does not have a sign/zero extending load for vectors.
5096 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
5097 SDValue NonExtendingLoad =
5098 DAG.getLoad(LD->getMemoryVT(), LD->getDebugLoc(), LD->getChain(),
5099 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
5100 LD->isNonTemporal(), LD->isInvariant(),
5101 LD->getAlignment());
5103 switch (LD->getExtensionType()) {
5104 default: llvm_unreachable("Unexpected LoadExtType");
5106 case ISD::SEXTLOAD: ExtOp = ISD::SIGN_EXTEND; break;
5107 case ISD::ZEXTLOAD: ExtOp = ISD::ZERO_EXTEND; break;
5109 MVT::SimpleValueType MemType = LD->getMemoryVT().getSimpleVT().SimpleTy;
5110 MVT::SimpleValueType ExtType = LD->getValueType(0).getSimpleVT().SimpleTy;
5111 return AddRequiredExtensionForVMULL(NonExtendingLoad, DAG,
5112 MemType, ExtType, ExtOp);
5115 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
5116 /// extending load, or BUILD_VECTOR with extended elements, return the
5117 /// unextended value. The unextended vector should be 64 bits so that it can
5118 /// be used as an operand to a VMULL instruction. If the original vector size
5119 /// before extension is less than 64 bits we add a an extension to resize
5120 /// the vector to 64 bits.
5121 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
5122 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
5123 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
5124 N->getOperand(0)->getValueType(0),
5128 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
5129 return SkipLoadExtensionForVMULL(LD, DAG);
5131 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
5132 // have been legalized as a BITCAST from v4i32.
5133 if (N->getOpcode() == ISD::BITCAST) {
5134 SDNode *BVN = N->getOperand(0).getNode();
5135 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
5136 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
5137 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5138 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
5139 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
5141 // Construct a new BUILD_VECTOR with elements truncated to half the size.
5142 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
5143 EVT VT = N->getValueType(0);
5144 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
5145 unsigned NumElts = VT.getVectorNumElements();
5146 MVT TruncVT = MVT::getIntegerVT(EltSize);
5147 SmallVector<SDValue, 8> Ops;
5148 for (unsigned i = 0; i != NumElts; ++i) {
5149 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
5150 const APInt &CInt = C->getAPIntValue();
5151 // Element types smaller than 32 bits are not legal, so use i32 elements.
5152 // The values are implicitly truncated so sext vs. zext doesn't matter.
5153 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
5155 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5156 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
5159 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
5160 unsigned Opcode = N->getOpcode();
5161 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5162 SDNode *N0 = N->getOperand(0).getNode();
5163 SDNode *N1 = N->getOperand(1).getNode();
5164 return N0->hasOneUse() && N1->hasOneUse() &&
5165 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5170 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
5171 unsigned Opcode = N->getOpcode();
5172 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5173 SDNode *N0 = N->getOperand(0).getNode();
5174 SDNode *N1 = N->getOperand(1).getNode();
5175 return N0->hasOneUse() && N1->hasOneUse() &&
5176 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
5181 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
5182 // Multiplications are only custom-lowered for 128-bit vectors so that
5183 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
5184 EVT VT = Op.getValueType();
5185 assert(VT.is128BitVector() && VT.isInteger() &&
5186 "unexpected type for custom-lowering ISD::MUL");
5187 SDNode *N0 = Op.getOperand(0).getNode();
5188 SDNode *N1 = Op.getOperand(1).getNode();
5189 unsigned NewOpc = 0;
5191 bool isN0SExt = isSignExtended(N0, DAG);
5192 bool isN1SExt = isSignExtended(N1, DAG);
5193 if (isN0SExt && isN1SExt)
5194 NewOpc = ARMISD::VMULLs;
5196 bool isN0ZExt = isZeroExtended(N0, DAG);
5197 bool isN1ZExt = isZeroExtended(N1, DAG);
5198 if (isN0ZExt && isN1ZExt)
5199 NewOpc = ARMISD::VMULLu;
5200 else if (isN1SExt || isN1ZExt) {
5201 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
5202 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
5203 if (isN1SExt && isAddSubSExt(N0, DAG)) {
5204 NewOpc = ARMISD::VMULLs;
5206 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
5207 NewOpc = ARMISD::VMULLu;
5209 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
5211 NewOpc = ARMISD::VMULLu;
5217 if (VT == MVT::v2i64)
5218 // Fall through to expand this. It is not legal.
5221 // Other vector multiplications are legal.
5226 // Legalize to a VMULL instruction.
5227 DebugLoc DL = Op.getDebugLoc();
5229 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
5231 Op0 = SkipExtensionForVMULL(N0, DAG);
5232 assert(Op0.getValueType().is64BitVector() &&
5233 Op1.getValueType().is64BitVector() &&
5234 "unexpected types for extended operands to VMULL");
5235 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
5238 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
5239 // isel lowering to take advantage of no-stall back to back vmul + vmla.
5246 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
5247 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
5248 EVT Op1VT = Op1.getValueType();
5249 return DAG.getNode(N0->getOpcode(), DL, VT,
5250 DAG.getNode(NewOpc, DL, VT,
5251 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
5252 DAG.getNode(NewOpc, DL, VT,
5253 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
5257 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
5259 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
5260 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
5261 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
5262 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
5263 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
5264 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
5265 // Get reciprocal estimate.
5266 // float4 recip = vrecpeq_f32(yf);
5267 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5268 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
5269 // Because char has a smaller range than uchar, we can actually get away
5270 // without any newton steps. This requires that we use a weird bias
5271 // of 0xb000, however (again, this has been exhaustively tested).
5272 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
5273 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
5274 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
5275 Y = DAG.getConstant(0xb000, MVT::i32);
5276 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
5277 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
5278 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
5279 // Convert back to short.
5280 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
5281 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
5286 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
5288 // Convert to float.
5289 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
5290 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
5291 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
5292 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
5293 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5294 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5296 // Use reciprocal estimate and one refinement step.
5297 // float4 recip = vrecpeq_f32(yf);
5298 // recip *= vrecpsq_f32(yf, recip);
5299 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5300 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
5301 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5302 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5304 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5305 // Because short has a smaller range than ushort, we can actually get away
5306 // with only a single newton step. This requires that we use a weird bias
5307 // of 89, however (again, this has been exhaustively tested).
5308 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
5309 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5310 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5311 N1 = DAG.getConstant(0x89, MVT::i32);
5312 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5313 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5314 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5315 // Convert back to integer and return.
5316 // return vmovn_s32(vcvt_s32_f32(result));
5317 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5318 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5322 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
5323 EVT VT = Op.getValueType();
5324 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5325 "unexpected type for custom-lowering ISD::SDIV");
5327 DebugLoc dl = Op.getDebugLoc();
5328 SDValue N0 = Op.getOperand(0);
5329 SDValue N1 = Op.getOperand(1);
5332 if (VT == MVT::v8i8) {
5333 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
5334 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
5336 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5337 DAG.getIntPtrConstant(4));
5338 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5339 DAG.getIntPtrConstant(4));
5340 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5341 DAG.getIntPtrConstant(0));
5342 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5343 DAG.getIntPtrConstant(0));
5345 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
5346 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
5348 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5349 N0 = LowerCONCAT_VECTORS(N0, DAG);
5351 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
5354 return LowerSDIV_v4i16(N0, N1, dl, DAG);
5357 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
5358 EVT VT = Op.getValueType();
5359 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5360 "unexpected type for custom-lowering ISD::UDIV");
5362 DebugLoc dl = Op.getDebugLoc();
5363 SDValue N0 = Op.getOperand(0);
5364 SDValue N1 = Op.getOperand(1);
5367 if (VT == MVT::v8i8) {
5368 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
5369 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
5371 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5372 DAG.getIntPtrConstant(4));
5373 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5374 DAG.getIntPtrConstant(4));
5375 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5376 DAG.getIntPtrConstant(0));
5377 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5378 DAG.getIntPtrConstant(0));
5380 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
5381 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
5383 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5384 N0 = LowerCONCAT_VECTORS(N0, DAG);
5386 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
5387 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
5392 // v4i16 sdiv ... Convert to float.
5393 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
5394 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
5395 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
5396 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
5397 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5398 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5400 // Use reciprocal estimate and two refinement steps.
5401 // float4 recip = vrecpeq_f32(yf);
5402 // recip *= vrecpsq_f32(yf, recip);
5403 // recip *= vrecpsq_f32(yf, recip);
5404 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5405 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
5406 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5407 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5409 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5410 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5411 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5413 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5414 // Simply multiplying by the reciprocal estimate can leave us a few ulps
5415 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
5416 // and that it will never cause us to return an answer too large).
5417 // float4 result = as_float4(as_int4(xf*recip) + 2);
5418 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5419 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5420 N1 = DAG.getConstant(2, MVT::i32);
5421 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5422 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5423 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5424 // Convert back to integer and return.
5425 // return vmovn_u32(vcvt_s32_f32(result));
5426 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5427 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5431 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
5432 EVT VT = Op.getNode()->getValueType(0);
5433 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
5436 bool ExtraOp = false;
5437 switch (Op.getOpcode()) {
5438 default: llvm_unreachable("Invalid code");
5439 case ISD::ADDC: Opc = ARMISD::ADDC; break;
5440 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
5441 case ISD::SUBC: Opc = ARMISD::SUBC; break;
5442 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
5446 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
5448 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
5449 Op.getOperand(1), Op.getOperand(2));
5452 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
5453 // Monotonic load/store is legal for all targets
5454 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
5457 // Aquire/Release load/store is not legal for targets without a
5458 // dmb or equivalent available.
5464 ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results,
5465 SelectionDAG &DAG, unsigned NewOp) {
5466 DebugLoc dl = Node->getDebugLoc();
5467 assert (Node->getValueType(0) == MVT::i64 &&
5468 "Only know how to expand i64 atomics");
5470 SmallVector<SDValue, 6> Ops;
5471 Ops.push_back(Node->getOperand(0)); // Chain
5472 Ops.push_back(Node->getOperand(1)); // Ptr
5474 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5475 Node->getOperand(2), DAG.getIntPtrConstant(0)));
5476 // High part of Val1
5477 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5478 Node->getOperand(2), DAG.getIntPtrConstant(1)));
5479 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) {
5480 // High part of Val1
5481 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5482 Node->getOperand(3), DAG.getIntPtrConstant(0)));
5483 // High part of Val2
5484 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5485 Node->getOperand(3), DAG.getIntPtrConstant(1)));
5487 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
5489 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64,
5490 cast<MemSDNode>(Node)->getMemOperand());
5491 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) };
5492 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
5493 Results.push_back(Result.getValue(2));
5496 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5497 switch (Op.getOpcode()) {
5498 default: llvm_unreachable("Don't know how to custom lower this!");
5499 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5500 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5501 case ISD::GlobalAddress:
5502 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
5503 LowerGlobalAddressELF(Op, DAG);
5504 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5505 case ISD::SELECT: return LowerSELECT(Op, DAG);
5506 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5507 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
5508 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
5509 case ISD::VASTART: return LowerVASTART(Op, DAG);
5510 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
5511 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
5512 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
5513 case ISD::SINT_TO_FP:
5514 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5515 case ISD::FP_TO_SINT:
5516 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
5517 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5518 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5519 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5520 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
5521 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
5522 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
5523 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
5525 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
5528 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
5529 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
5530 case ISD::SRL_PARTS:
5531 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
5532 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
5533 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
5534 case ISD::SETCC: return LowerVSETCC(Op, DAG);
5535 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
5536 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
5537 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5538 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5539 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5540 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
5541 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5542 case ISD::MUL: return LowerMUL(Op, DAG);
5543 case ISD::SDIV: return LowerSDIV(Op, DAG);
5544 case ISD::UDIV: return LowerUDIV(Op, DAG);
5548 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
5549 case ISD::ATOMIC_LOAD:
5550 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
5554 /// ReplaceNodeResults - Replace the results of node with an illegal result
5555 /// type with new values built out of custom code.
5556 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
5557 SmallVectorImpl<SDValue>&Results,
5558 SelectionDAG &DAG) const {
5560 switch (N->getOpcode()) {
5562 llvm_unreachable("Don't know how to custom expand this!");
5564 Res = ExpandBITCAST(N, DAG);
5568 Res = Expand64BitShift(N, DAG, Subtarget);
5570 case ISD::ATOMIC_LOAD_ADD:
5571 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG);
5573 case ISD::ATOMIC_LOAD_AND:
5574 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG);
5576 case ISD::ATOMIC_LOAD_NAND:
5577 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG);
5579 case ISD::ATOMIC_LOAD_OR:
5580 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG);
5582 case ISD::ATOMIC_LOAD_SUB:
5583 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG);
5585 case ISD::ATOMIC_LOAD_XOR:
5586 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG);
5588 case ISD::ATOMIC_SWAP:
5589 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG);
5591 case ISD::ATOMIC_CMP_SWAP:
5592 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG);
5594 case ISD::ATOMIC_LOAD_MIN:
5595 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMMIN64_DAG);
5597 case ISD::ATOMIC_LOAD_UMIN:
5598 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMUMIN64_DAG);
5600 case ISD::ATOMIC_LOAD_MAX:
5601 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMMAX64_DAG);
5603 case ISD::ATOMIC_LOAD_UMAX:
5604 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMUMAX64_DAG);
5608 Results.push_back(Res);
5611 //===----------------------------------------------------------------------===//
5612 // ARM Scheduler Hooks
5613 //===----------------------------------------------------------------------===//
5616 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
5617 MachineBasicBlock *BB,
5618 unsigned Size) const {
5619 unsigned dest = MI->getOperand(0).getReg();
5620 unsigned ptr = MI->getOperand(1).getReg();
5621 unsigned oldval = MI->getOperand(2).getReg();
5622 unsigned newval = MI->getOperand(3).getReg();
5623 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5624 DebugLoc dl = MI->getDebugLoc();
5625 bool isThumb2 = Subtarget->isThumb2();
5627 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5628 unsigned scratch = MRI.createVirtualRegister(isThumb2 ?
5629 (const TargetRegisterClass*)&ARM::rGPRRegClass :
5630 (const TargetRegisterClass*)&ARM::GPRRegClass);
5633 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
5634 MRI.constrainRegClass(oldval, &ARM::rGPRRegClass);
5635 MRI.constrainRegClass(newval, &ARM::rGPRRegClass);
5638 unsigned ldrOpc, strOpc;
5640 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5642 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5643 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5646 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5647 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5650 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5651 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5655 MachineFunction *MF = BB->getParent();
5656 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5657 MachineFunction::iterator It = BB;
5658 ++It; // insert the new blocks after the current block
5660 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5661 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5662 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5663 MF->insert(It, loop1MBB);
5664 MF->insert(It, loop2MBB);
5665 MF->insert(It, exitMBB);
5667 // Transfer the remainder of BB and its successor edges to exitMBB.
5668 exitMBB->splice(exitMBB->begin(), BB,
5669 llvm::next(MachineBasicBlock::iterator(MI)),
5671 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5675 // fallthrough --> loop1MBB
5676 BB->addSuccessor(loop1MBB);
5679 // ldrex dest, [ptr]
5683 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5684 if (ldrOpc == ARM::t2LDREX)
5686 AddDefaultPred(MIB);
5687 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5688 .addReg(dest).addReg(oldval));
5689 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5690 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5691 BB->addSuccessor(loop2MBB);
5692 BB->addSuccessor(exitMBB);
5695 // strex scratch, newval, [ptr]
5699 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr);
5700 if (strOpc == ARM::t2STREX)
5702 AddDefaultPred(MIB);
5703 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5704 .addReg(scratch).addImm(0));
5705 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5706 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5707 BB->addSuccessor(loop1MBB);
5708 BB->addSuccessor(exitMBB);
5714 MI->eraseFromParent(); // The instruction is gone now.
5720 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5721 unsigned Size, unsigned BinOpcode) const {
5722 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5723 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5725 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5726 MachineFunction *MF = BB->getParent();
5727 MachineFunction::iterator It = BB;
5730 unsigned dest = MI->getOperand(0).getReg();
5731 unsigned ptr = MI->getOperand(1).getReg();
5732 unsigned incr = MI->getOperand(2).getReg();
5733 DebugLoc dl = MI->getDebugLoc();
5734 bool isThumb2 = Subtarget->isThumb2();
5736 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5738 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
5739 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
5742 unsigned ldrOpc, strOpc;
5744 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5746 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5747 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5750 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5751 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5754 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5755 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5759 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5760 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5761 MF->insert(It, loopMBB);
5762 MF->insert(It, exitMBB);
5764 // Transfer the remainder of BB and its successor edges to exitMBB.
5765 exitMBB->splice(exitMBB->begin(), BB,
5766 llvm::next(MachineBasicBlock::iterator(MI)),
5768 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5770 const TargetRegisterClass *TRC = isThumb2 ?
5771 (const TargetRegisterClass*)&ARM::rGPRRegClass :
5772 (const TargetRegisterClass*)&ARM::GPRRegClass;
5773 unsigned scratch = MRI.createVirtualRegister(TRC);
5774 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
5778 // fallthrough --> loopMBB
5779 BB->addSuccessor(loopMBB);
5783 // <binop> scratch2, dest, incr
5784 // strex scratch, scratch2, ptr
5787 // fallthrough --> exitMBB
5789 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5790 if (ldrOpc == ARM::t2LDREX)
5792 AddDefaultPred(MIB);
5794 // operand order needs to go the other way for NAND
5795 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
5796 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5797 addReg(incr).addReg(dest)).addReg(0);
5799 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5800 addReg(dest).addReg(incr)).addReg(0);
5803 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5804 if (strOpc == ARM::t2STREX)
5806 AddDefaultPred(MIB);
5807 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5808 .addReg(scratch).addImm(0));
5809 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5810 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5812 BB->addSuccessor(loopMBB);
5813 BB->addSuccessor(exitMBB);
5819 MI->eraseFromParent(); // The instruction is gone now.
5825 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
5826 MachineBasicBlock *BB,
5829 ARMCC::CondCodes Cond) const {
5830 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5832 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5833 MachineFunction *MF = BB->getParent();
5834 MachineFunction::iterator It = BB;
5837 unsigned dest = MI->getOperand(0).getReg();
5838 unsigned ptr = MI->getOperand(1).getReg();
5839 unsigned incr = MI->getOperand(2).getReg();
5840 unsigned oldval = dest;
5841 DebugLoc dl = MI->getDebugLoc();
5842 bool isThumb2 = Subtarget->isThumb2();
5844 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5846 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
5847 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
5850 unsigned ldrOpc, strOpc, extendOpc;
5852 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5854 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5855 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5856 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
5859 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5860 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5861 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
5864 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5865 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5870 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5871 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5872 MF->insert(It, loopMBB);
5873 MF->insert(It, exitMBB);
5875 // Transfer the remainder of BB and its successor edges to exitMBB.
5876 exitMBB->splice(exitMBB->begin(), BB,
5877 llvm::next(MachineBasicBlock::iterator(MI)),
5879 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5881 const TargetRegisterClass *TRC = isThumb2 ?
5882 (const TargetRegisterClass*)&ARM::rGPRRegClass :
5883 (const TargetRegisterClass*)&ARM::GPRRegClass;
5884 unsigned scratch = MRI.createVirtualRegister(TRC);
5885 unsigned scratch2 = MRI.createVirtualRegister(TRC);
5889 // fallthrough --> loopMBB
5890 BB->addSuccessor(loopMBB);
5894 // (sign extend dest, if required)
5896 // cmov.cond scratch2, incr, dest
5897 // strex scratch, scratch2, ptr
5900 // fallthrough --> exitMBB
5902 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5903 if (ldrOpc == ARM::t2LDREX)
5905 AddDefaultPred(MIB);
5907 // Sign extend the value, if necessary.
5908 if (signExtend && extendOpc) {
5909 oldval = MRI.createVirtualRegister(&ARM::GPRRegClass);
5910 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
5915 // Build compare and cmov instructions.
5916 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5917 .addReg(oldval).addReg(incr));
5918 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
5919 .addReg(incr).addReg(oldval).addImm(Cond).addReg(ARM::CPSR);
5921 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5922 if (strOpc == ARM::t2STREX)
5924 AddDefaultPred(MIB);
5925 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5926 .addReg(scratch).addImm(0));
5927 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5928 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5930 BB->addSuccessor(loopMBB);
5931 BB->addSuccessor(exitMBB);
5937 MI->eraseFromParent(); // The instruction is gone now.
5943 ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
5944 unsigned Op1, unsigned Op2,
5945 bool NeedsCarry, bool IsCmpxchg,
5946 bool IsMinMax, ARMCC::CondCodes CC) const {
5947 // This also handles ATOMIC_SWAP, indicated by Op1==0.
5948 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5950 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5951 MachineFunction *MF = BB->getParent();
5952 MachineFunction::iterator It = BB;
5955 unsigned destlo = MI->getOperand(0).getReg();
5956 unsigned desthi = MI->getOperand(1).getReg();
5957 unsigned ptr = MI->getOperand(2).getReg();
5958 unsigned vallo = MI->getOperand(3).getReg();
5959 unsigned valhi = MI->getOperand(4).getReg();
5960 DebugLoc dl = MI->getDebugLoc();
5961 bool isThumb2 = Subtarget->isThumb2();
5963 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5965 MRI.constrainRegClass(destlo, &ARM::rGPRRegClass);
5966 MRI.constrainRegClass(desthi, &ARM::rGPRRegClass);
5967 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
5970 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD;
5971 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD;
5973 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5974 MachineBasicBlock *contBB = 0, *cont2BB = 0;
5975 if (IsCmpxchg || IsMinMax)
5976 contBB = MF->CreateMachineBasicBlock(LLVM_BB);
5978 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB);
5979 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5981 MF->insert(It, loopMBB);
5982 if (IsCmpxchg || IsMinMax) MF->insert(It, contBB);
5983 if (IsCmpxchg) MF->insert(It, cont2BB);
5984 MF->insert(It, exitMBB);
5986 // Transfer the remainder of BB and its successor edges to exitMBB.
5987 exitMBB->splice(exitMBB->begin(), BB,
5988 llvm::next(MachineBasicBlock::iterator(MI)),
5990 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5992 const TargetRegisterClass *TRC = isThumb2 ?
5993 (const TargetRegisterClass*)&ARM::tGPRRegClass :
5994 (const TargetRegisterClass*)&ARM::GPRRegClass;
5995 unsigned storesuccess = MRI.createVirtualRegister(TRC);
5999 // fallthrough --> loopMBB
6000 BB->addSuccessor(loopMBB);
6003 // ldrexd r2, r3, ptr
6004 // <binopa> r0, r2, incr
6005 // <binopb> r1, r3, incr
6006 // strexd storesuccess, r0, r1, ptr
6007 // cmp storesuccess, #0
6009 // fallthrough --> exitMBB
6011 // Note that the registers are explicitly specified because there is not any
6012 // way to force the register allocator to allocate a register pair.
6014 // FIXME: The hardcoded registers are not necessary for Thumb2, but we
6015 // need to properly enforce the restriction that the two output registers
6016 // for ldrexd must be different.
6019 unsigned GPRPair0 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6020 unsigned GPRPair1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6023 //We need an extra double register for doing min/max.
6024 unsigned undef = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6025 unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6026 GPRPair2 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6027 BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), undef);
6028 BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
6031 .addImm(ARM::gsub_0);
6032 BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), GPRPair2)
6035 .addImm(ARM::gsub_1);
6038 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
6039 .addReg(GPRPair0, RegState::Define).addReg(ptr));
6040 // Copy r2/r3 into dest. (This copy will normally be coalesced.)
6041 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo)
6042 .addReg(GPRPair0, 0, ARM::gsub_0);
6043 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi)
6044 .addReg(GPRPair0, 0, ARM::gsub_1);
6048 for (unsigned i = 0; i < 2; i++) {
6049 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr :
6051 .addReg(i == 0 ? destlo : desthi)
6052 .addReg(i == 0 ? vallo : valhi));
6053 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6054 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6055 BB->addSuccessor(exitMBB);
6056 BB->addSuccessor(i == 0 ? contBB : cont2BB);
6057 BB = (i == 0 ? contBB : cont2BB);
6060 // Copy to physregs for strexd
6061 unsigned setlo = MI->getOperand(5).getReg();
6062 unsigned sethi = MI->getOperand(6).getReg();
6063 unsigned undef = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6064 unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6065 BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), undef);
6066 BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
6069 .addImm(ARM::gsub_0);
6070 BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), GPRPair1)
6073 .addImm(ARM::gsub_1);
6075 // Perform binary operation
6076 unsigned tmpRegLo = MRI.createVirtualRegister(TRC);
6077 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), tmpRegLo)
6078 .addReg(destlo).addReg(vallo))
6079 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry));
6080 unsigned tmpRegHi = MRI.createVirtualRegister(TRC);
6081 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), tmpRegHi)
6082 .addReg(desthi).addReg(valhi))
6083 .addReg(IsMinMax ? ARM::CPSR : 0, getDefRegState(IsMinMax));
6085 unsigned UndefPair = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6086 BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), UndefPair);
6087 unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6088 BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
6091 .addImm(ARM::gsub_0);
6092 BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), GPRPair1)
6095 .addImm(ARM::gsub_1);
6097 // Copy to physregs for strexd
6098 unsigned UndefPair = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6099 unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6100 BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), UndefPair);
6101 BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
6104 .addImm(ARM::gsub_0);
6105 BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), GPRPair1)
6108 .addImm(ARM::gsub_1);
6110 unsigned GPRPairStore = GPRPair1;
6112 // Compare and branch to exit block.
6113 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6114 .addMBB(exitMBB).addImm(CC).addReg(ARM::CPSR);
6115 BB->addSuccessor(exitMBB);
6116 BB->addSuccessor(contBB);
6118 GPRPairStore = GPRPair2;
6122 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
6123 .addReg(GPRPairStore).addReg(ptr));
6125 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6126 .addReg(storesuccess).addImm(0));
6127 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6128 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6130 BB->addSuccessor(loopMBB);
6131 BB->addSuccessor(exitMBB);
6137 MI->eraseFromParent(); // The instruction is gone now.
6142 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
6143 /// registers the function context.
6144 void ARMTargetLowering::
6145 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
6146 MachineBasicBlock *DispatchBB, int FI) const {
6147 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6148 DebugLoc dl = MI->getDebugLoc();
6149 MachineFunction *MF = MBB->getParent();
6150 MachineRegisterInfo *MRI = &MF->getRegInfo();
6151 MachineConstantPool *MCP = MF->getConstantPool();
6152 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6153 const Function *F = MF->getFunction();
6155 bool isThumb = Subtarget->isThumb();
6156 bool isThumb2 = Subtarget->isThumb2();
6158 unsigned PCLabelId = AFI->createPICLabelUId();
6159 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
6160 ARMConstantPoolValue *CPV =
6161 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6162 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6164 const TargetRegisterClass *TRC = isThumb ?
6165 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6166 (const TargetRegisterClass*)&ARM::GPRRegClass;
6168 // Grab constant pool and fixed stack memory operands.
6169 MachineMemOperand *CPMMO =
6170 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
6171 MachineMemOperand::MOLoad, 4, 4);
6173 MachineMemOperand *FIMMOSt =
6174 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6175 MachineMemOperand::MOStore, 4, 4);
6177 // Load the address of the dispatch MBB into the jump buffer.
6179 // Incoming value: jbuf
6180 // ldr.n r5, LCPI1_1
6183 // str r5, [$jbuf, #+4] ; &jbuf[1]
6184 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6185 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6186 .addConstantPoolIndex(CPI)
6187 .addMemOperand(CPMMO));
6188 // Set the low bit because of thumb mode.
6189 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6191 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6192 .addReg(NewVReg1, RegState::Kill)
6194 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6195 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6196 .addReg(NewVReg2, RegState::Kill)
6198 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6199 .addReg(NewVReg3, RegState::Kill)
6201 .addImm(36) // &jbuf[1] :: pc
6202 .addMemOperand(FIMMOSt));
6203 } else if (isThumb) {
6204 // Incoming value: jbuf
6205 // ldr.n r1, LCPI1_4
6209 // add r2, $jbuf, #+4 ; &jbuf[1]
6211 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6212 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6213 .addConstantPoolIndex(CPI)
6214 .addMemOperand(CPMMO));
6215 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6216 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6217 .addReg(NewVReg1, RegState::Kill)
6219 // Set the low bit because of thumb mode.
6220 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6221 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6222 .addReg(ARM::CPSR, RegState::Define)
6224 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6225 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6226 .addReg(ARM::CPSR, RegState::Define)
6227 .addReg(NewVReg2, RegState::Kill)
6228 .addReg(NewVReg3, RegState::Kill));
6229 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6230 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
6232 .addImm(36)); // &jbuf[1] :: pc
6233 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6234 .addReg(NewVReg4, RegState::Kill)
6235 .addReg(NewVReg5, RegState::Kill)
6237 .addMemOperand(FIMMOSt));
6239 // Incoming value: jbuf
6242 // str r1, [$jbuf, #+4] ; &jbuf[1]
6243 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6244 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6245 .addConstantPoolIndex(CPI)
6247 .addMemOperand(CPMMO));
6248 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6249 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6250 .addReg(NewVReg1, RegState::Kill)
6251 .addImm(PCLabelId));
6252 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6253 .addReg(NewVReg2, RegState::Kill)
6255 .addImm(36) // &jbuf[1] :: pc
6256 .addMemOperand(FIMMOSt));
6260 MachineBasicBlock *ARMTargetLowering::
6261 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
6262 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6263 DebugLoc dl = MI->getDebugLoc();
6264 MachineFunction *MF = MBB->getParent();
6265 MachineRegisterInfo *MRI = &MF->getRegInfo();
6266 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6267 MachineFrameInfo *MFI = MF->getFrameInfo();
6268 int FI = MFI->getFunctionContextIndex();
6270 const TargetRegisterClass *TRC = Subtarget->isThumb() ?
6271 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6272 (const TargetRegisterClass*)&ARM::GPRnopcRegClass;
6274 // Get a mapping of the call site numbers to all of the landing pads they're
6276 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
6277 unsigned MaxCSNum = 0;
6278 MachineModuleInfo &MMI = MF->getMMI();
6279 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6281 if (!BB->isLandingPad()) continue;
6283 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6285 for (MachineBasicBlock::iterator
6286 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6287 if (!II->isEHLabel()) continue;
6289 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
6290 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
6292 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6293 for (SmallVectorImpl<unsigned>::iterator
6294 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6295 CSI != CSE; ++CSI) {
6296 CallSiteNumToLPad[*CSI].push_back(BB);
6297 MaxCSNum = std::max(MaxCSNum, *CSI);
6303 // Get an ordered list of the machine basic blocks for the jump table.
6304 std::vector<MachineBasicBlock*> LPadList;
6305 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
6306 LPadList.reserve(CallSiteNumToLPad.size());
6307 for (unsigned I = 1; I <= MaxCSNum; ++I) {
6308 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6309 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6310 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
6311 LPadList.push_back(*II);
6312 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6316 assert(!LPadList.empty() &&
6317 "No landing pad destinations for the dispatch jump table!");
6319 // Create the jump table and associated information.
6320 MachineJumpTableInfo *JTI =
6321 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6322 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6323 unsigned UId = AFI->createJumpTableUId();
6325 // Create the MBBs for the dispatch code.
6327 // Shove the dispatch's address into the return slot in the function context.
6328 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6329 DispatchBB->setIsLandingPad();
6331 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
6332 BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP));
6333 DispatchBB->addSuccessor(TrapBB);
6335 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6336 DispatchBB->addSuccessor(DispContBB);
6339 MF->insert(MF->end(), DispatchBB);
6340 MF->insert(MF->end(), DispContBB);
6341 MF->insert(MF->end(), TrapBB);
6343 // Insert code into the entry block that creates and registers the function
6345 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6347 MachineMemOperand *FIMMOLd =
6348 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6349 MachineMemOperand::MOLoad |
6350 MachineMemOperand::MOVolatile, 4, 4);
6352 MachineInstrBuilder MIB;
6353 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6355 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6356 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6358 // Add a register mask with no preserved registers. This results in all
6359 // registers being marked as clobbered.
6360 MIB.addRegMask(RI.getNoPreservedMask());
6362 unsigned NumLPads = LPadList.size();
6363 if (Subtarget->isThumb2()) {
6364 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6365 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6368 .addMemOperand(FIMMOLd));
6370 if (NumLPads < 256) {
6371 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6373 .addImm(LPadList.size()));
6375 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6376 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6377 .addImm(NumLPads & 0xFFFF));
6379 unsigned VReg2 = VReg1;
6380 if ((NumLPads & 0xFFFF0000) != 0) {
6381 VReg2 = MRI->createVirtualRegister(TRC);
6382 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6384 .addImm(NumLPads >> 16));
6387 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6392 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
6397 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6398 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6399 .addJumpTableIndex(MJTI)
6402 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6405 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
6406 .addReg(NewVReg3, RegState::Kill)
6408 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6410 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
6411 .addReg(NewVReg4, RegState::Kill)
6413 .addJumpTableIndex(MJTI)
6415 } else if (Subtarget->isThumb()) {
6416 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6417 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6420 .addMemOperand(FIMMOLd));
6422 if (NumLPads < 256) {
6423 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6427 MachineConstantPool *ConstantPool = MF->getConstantPool();
6428 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6429 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6431 // MachineConstantPool wants an explicit alignment.
6432 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6434 Align = getDataLayout()->getTypeAllocSize(C->getType());
6435 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6437 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6438 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
6439 .addReg(VReg1, RegState::Define)
6440 .addConstantPoolIndex(Idx));
6441 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
6446 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
6451 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6452 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
6453 .addReg(ARM::CPSR, RegState::Define)
6457 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6458 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
6459 .addJumpTableIndex(MJTI)
6462 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6463 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
6464 .addReg(ARM::CPSR, RegState::Define)
6465 .addReg(NewVReg2, RegState::Kill)
6468 MachineMemOperand *JTMMOLd =
6469 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6470 MachineMemOperand::MOLoad, 4, 4);
6472 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6473 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
6474 .addReg(NewVReg4, RegState::Kill)
6476 .addMemOperand(JTMMOLd));
6478 unsigned NewVReg6 = MRI->createVirtualRegister(TRC);
6479 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
6480 .addReg(ARM::CPSR, RegState::Define)
6481 .addReg(NewVReg5, RegState::Kill)
6484 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
6485 .addReg(NewVReg6, RegState::Kill)
6486 .addJumpTableIndex(MJTI)
6489 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6490 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
6493 .addMemOperand(FIMMOLd));
6495 if (NumLPads < 256) {
6496 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
6499 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
6500 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6501 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
6502 .addImm(NumLPads & 0xFFFF));
6504 unsigned VReg2 = VReg1;
6505 if ((NumLPads & 0xFFFF0000) != 0) {
6506 VReg2 = MRI->createVirtualRegister(TRC);
6507 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
6509 .addImm(NumLPads >> 16));
6512 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6516 MachineConstantPool *ConstantPool = MF->getConstantPool();
6517 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6518 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6520 // MachineConstantPool wants an explicit alignment.
6521 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6523 Align = getDataLayout()->getTypeAllocSize(C->getType());
6524 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6526 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6527 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
6528 .addReg(VReg1, RegState::Define)
6529 .addConstantPoolIndex(Idx)
6531 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6533 .addReg(VReg1, RegState::Kill));
6536 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
6541 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6543 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
6545 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6546 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6547 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
6548 .addJumpTableIndex(MJTI)
6551 MachineMemOperand *JTMMOLd =
6552 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6553 MachineMemOperand::MOLoad, 4, 4);
6554 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6556 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
6557 .addReg(NewVReg3, RegState::Kill)
6560 .addMemOperand(JTMMOLd));
6562 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
6563 .addReg(NewVReg5, RegState::Kill)
6565 .addJumpTableIndex(MJTI)
6569 // Add the jump table entries as successors to the MBB.
6570 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
6571 for (std::vector<MachineBasicBlock*>::iterator
6572 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
6573 MachineBasicBlock *CurMBB = *I;
6574 if (SeenMBBs.insert(CurMBB))
6575 DispContBB->addSuccessor(CurMBB);
6578 // N.B. the order the invoke BBs are processed in doesn't matter here.
6579 const uint16_t *SavedRegs = RI.getCalleeSavedRegs(MF);
6580 SmallVector<MachineBasicBlock*, 64> MBBLPads;
6581 for (SmallPtrSet<MachineBasicBlock*, 64>::iterator
6582 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) {
6583 MachineBasicBlock *BB = *I;
6585 // Remove the landing pad successor from the invoke block and replace it
6586 // with the new dispatch block.
6587 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
6589 while (!Successors.empty()) {
6590 MachineBasicBlock *SMBB = Successors.pop_back_val();
6591 if (SMBB->isLandingPad()) {
6592 BB->removeSuccessor(SMBB);
6593 MBBLPads.push_back(SMBB);
6597 BB->addSuccessor(DispatchBB);
6599 // Find the invoke call and mark all of the callee-saved registers as
6600 // 'implicit defined' so that they're spilled. This prevents code from
6601 // moving instructions to before the EH block, where they will never be
6603 for (MachineBasicBlock::reverse_iterator
6604 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
6605 if (!II->isCall()) continue;
6607 DenseMap<unsigned, bool> DefRegs;
6608 for (MachineInstr::mop_iterator
6609 OI = II->operands_begin(), OE = II->operands_end();
6611 if (!OI->isReg()) continue;
6612 DefRegs[OI->getReg()] = true;
6615 MachineInstrBuilder MIB(&*II);
6617 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
6618 unsigned Reg = SavedRegs[i];
6619 if (Subtarget->isThumb2() &&
6620 !ARM::tGPRRegClass.contains(Reg) &&
6621 !ARM::hGPRRegClass.contains(Reg))
6623 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
6625 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
6628 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
6635 // Mark all former landing pads as non-landing pads. The dispatch is the only
6637 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6638 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
6639 (*I)->setIsLandingPad(false);
6641 // The instruction is gone now.
6642 MI->eraseFromParent();
6648 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
6649 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
6650 E = MBB->succ_end(); I != E; ++I)
6653 llvm_unreachable("Expecting a BB with two successors!");
6656 MachineBasicBlock *ARMTargetLowering::
6657 EmitStructByval(MachineInstr *MI, MachineBasicBlock *BB) const {
6658 // This pseudo instruction has 3 operands: dst, src, size
6659 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
6660 // Otherwise, we will generate unrolled scalar copies.
6661 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6662 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6663 MachineFunction::iterator It = BB;
6666 unsigned dest = MI->getOperand(0).getReg();
6667 unsigned src = MI->getOperand(1).getReg();
6668 unsigned SizeVal = MI->getOperand(2).getImm();
6669 unsigned Align = MI->getOperand(3).getImm();
6670 DebugLoc dl = MI->getDebugLoc();
6672 bool isThumb2 = Subtarget->isThumb2();
6673 MachineFunction *MF = BB->getParent();
6674 MachineRegisterInfo &MRI = MF->getRegInfo();
6675 unsigned ldrOpc, strOpc, UnitSize = 0;
6677 const TargetRegisterClass *TRC = isThumb2 ?
6678 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6679 (const TargetRegisterClass*)&ARM::GPRRegClass;
6680 const TargetRegisterClass *TRC_Vec = 0;
6683 ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM;
6684 strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM;
6686 } else if (Align & 2) {
6687 ldrOpc = isThumb2 ? ARM::t2LDRH_POST : ARM::LDRH_POST;
6688 strOpc = isThumb2 ? ARM::t2STRH_POST : ARM::STRH_POST;
6691 // Check whether we can use NEON instructions.
6692 if (!MF->getFunction()->getFnAttributes().
6693 hasAttribute(Attributes::NoImplicitFloat) &&
6694 Subtarget->hasNEON()) {
6695 if ((Align % 16 == 0) && SizeVal >= 16) {
6696 ldrOpc = ARM::VLD1q32wb_fixed;
6697 strOpc = ARM::VST1q32wb_fixed;
6699 TRC_Vec = (const TargetRegisterClass*)&ARM::DPairRegClass;
6701 else if ((Align % 8 == 0) && SizeVal >= 8) {
6702 ldrOpc = ARM::VLD1d32wb_fixed;
6703 strOpc = ARM::VST1d32wb_fixed;
6705 TRC_Vec = (const TargetRegisterClass*)&ARM::DPRRegClass;
6708 // Can't use NEON instructions.
6709 if (UnitSize == 0) {
6710 ldrOpc = isThumb2 ? ARM::t2LDR_POST : ARM::LDR_POST_IMM;
6711 strOpc = isThumb2 ? ARM::t2STR_POST : ARM::STR_POST_IMM;
6716 unsigned BytesLeft = SizeVal % UnitSize;
6717 unsigned LoopSize = SizeVal - BytesLeft;
6719 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
6720 // Use LDR and STR to copy.
6721 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
6722 // [destOut] = STR_POST(scratch, destIn, UnitSize)
6723 unsigned srcIn = src;
6724 unsigned destIn = dest;
6725 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
6726 unsigned scratch = MRI.createVirtualRegister(UnitSize >= 8 ? TRC_Vec:TRC);
6727 unsigned srcOut = MRI.createVirtualRegister(TRC);
6728 unsigned destOut = MRI.createVirtualRegister(TRC);
6729 if (UnitSize >= 8) {
6730 AddDefaultPred(BuildMI(*BB, MI, dl,
6731 TII->get(ldrOpc), scratch)
6732 .addReg(srcOut, RegState::Define).addReg(srcIn).addImm(0));
6734 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6735 .addReg(destIn).addImm(0).addReg(scratch));
6736 } else if (isThumb2) {
6737 AddDefaultPred(BuildMI(*BB, MI, dl,
6738 TII->get(ldrOpc), scratch)
6739 .addReg(srcOut, RegState::Define).addReg(srcIn).addImm(UnitSize));
6741 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6742 .addReg(scratch).addReg(destIn)
6745 AddDefaultPred(BuildMI(*BB, MI, dl,
6746 TII->get(ldrOpc), scratch)
6747 .addReg(srcOut, RegState::Define).addReg(srcIn).addReg(0)
6750 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6751 .addReg(scratch).addReg(destIn)
6752 .addReg(0).addImm(UnitSize));
6758 // Handle the leftover bytes with LDRB and STRB.
6759 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
6760 // [destOut] = STRB_POST(scratch, destIn, 1)
6761 ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM;
6762 strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM;
6763 for (unsigned i = 0; i < BytesLeft; i++) {
6764 unsigned scratch = MRI.createVirtualRegister(TRC);
6765 unsigned srcOut = MRI.createVirtualRegister(TRC);
6766 unsigned destOut = MRI.createVirtualRegister(TRC);
6768 AddDefaultPred(BuildMI(*BB, MI, dl,
6769 TII->get(ldrOpc),scratch)
6770 .addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
6772 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6773 .addReg(scratch).addReg(destIn)
6774 .addReg(0).addImm(1));
6776 AddDefaultPred(BuildMI(*BB, MI, dl,
6777 TII->get(ldrOpc),scratch)
6778 .addReg(srcOut, RegState::Define).addReg(srcIn)
6779 .addReg(0).addImm(1));
6781 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6782 .addReg(scratch).addReg(destIn)
6783 .addReg(0).addImm(1));
6788 MI->eraseFromParent(); // The instruction is gone now.
6792 // Expand the pseudo op to a loop.
6795 // movw varEnd, # --> with thumb2
6797 // ldrcp varEnd, idx --> without thumb2
6798 // fallthrough --> loopMBB
6800 // PHI varPhi, varEnd, varLoop
6801 // PHI srcPhi, src, srcLoop
6802 // PHI destPhi, dst, destLoop
6803 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
6804 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
6805 // subs varLoop, varPhi, #UnitSize
6807 // fallthrough --> exitMBB
6809 // epilogue to handle left-over bytes
6810 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
6811 // [destOut] = STRB_POST(scratch, destLoop, 1)
6812 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6813 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6814 MF->insert(It, loopMBB);
6815 MF->insert(It, exitMBB);
6817 // Transfer the remainder of BB and its successor edges to exitMBB.
6818 exitMBB->splice(exitMBB->begin(), BB,
6819 llvm::next(MachineBasicBlock::iterator(MI)),
6821 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6823 // Load an immediate to varEnd.
6824 unsigned varEnd = MRI.createVirtualRegister(TRC);
6826 unsigned VReg1 = varEnd;
6827 if ((LoopSize & 0xFFFF0000) != 0)
6828 VReg1 = MRI.createVirtualRegister(TRC);
6829 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), VReg1)
6830 .addImm(LoopSize & 0xFFFF));
6832 if ((LoopSize & 0xFFFF0000) != 0)
6833 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
6835 .addImm(LoopSize >> 16));
6837 MachineConstantPool *ConstantPool = MF->getConstantPool();
6838 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6839 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
6841 // MachineConstantPool wants an explicit alignment.
6842 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6844 Align = getDataLayout()->getTypeAllocSize(C->getType());
6845 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6847 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::LDRcp))
6848 .addReg(varEnd, RegState::Define)
6849 .addConstantPoolIndex(Idx)
6852 BB->addSuccessor(loopMBB);
6854 // Generate the loop body:
6855 // varPhi = PHI(varLoop, varEnd)
6856 // srcPhi = PHI(srcLoop, src)
6857 // destPhi = PHI(destLoop, dst)
6858 MachineBasicBlock *entryBB = BB;
6860 unsigned varLoop = MRI.createVirtualRegister(TRC);
6861 unsigned varPhi = MRI.createVirtualRegister(TRC);
6862 unsigned srcLoop = MRI.createVirtualRegister(TRC);
6863 unsigned srcPhi = MRI.createVirtualRegister(TRC);
6864 unsigned destLoop = MRI.createVirtualRegister(TRC);
6865 unsigned destPhi = MRI.createVirtualRegister(TRC);
6867 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
6868 .addReg(varLoop).addMBB(loopMBB)
6869 .addReg(varEnd).addMBB(entryBB);
6870 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
6871 .addReg(srcLoop).addMBB(loopMBB)
6872 .addReg(src).addMBB(entryBB);
6873 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
6874 .addReg(destLoop).addMBB(loopMBB)
6875 .addReg(dest).addMBB(entryBB);
6877 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
6878 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
6879 unsigned scratch = MRI.createVirtualRegister(UnitSize >= 8 ? TRC_Vec:TRC);
6880 if (UnitSize >= 8) {
6881 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
6882 .addReg(srcLoop, RegState::Define).addReg(srcPhi).addImm(0));
6884 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
6885 .addReg(destPhi).addImm(0).addReg(scratch));
6886 } else if (isThumb2) {
6887 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
6888 .addReg(srcLoop, RegState::Define).addReg(srcPhi).addImm(UnitSize));
6890 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
6891 .addReg(scratch).addReg(destPhi)
6894 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
6895 .addReg(srcLoop, RegState::Define).addReg(srcPhi).addReg(0)
6898 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
6899 .addReg(scratch).addReg(destPhi)
6900 .addReg(0).addImm(UnitSize));
6903 // Decrement loop variable by UnitSize.
6904 MachineInstrBuilder MIB = BuildMI(BB, dl,
6905 TII->get(isThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
6906 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
6907 MIB->getOperand(5).setReg(ARM::CPSR);
6908 MIB->getOperand(5).setIsDef(true);
6910 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6911 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6913 // loopMBB can loop back to loopMBB or fall through to exitMBB.
6914 BB->addSuccessor(loopMBB);
6915 BB->addSuccessor(exitMBB);
6917 // Add epilogue to handle BytesLeft.
6919 MachineInstr *StartOfExit = exitMBB->begin();
6920 ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM;
6921 strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM;
6923 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
6924 // [destOut] = STRB_POST(scratch, destLoop, 1)
6925 unsigned srcIn = srcLoop;
6926 unsigned destIn = destLoop;
6927 for (unsigned i = 0; i < BytesLeft; i++) {
6928 unsigned scratch = MRI.createVirtualRegister(TRC);
6929 unsigned srcOut = MRI.createVirtualRegister(TRC);
6930 unsigned destOut = MRI.createVirtualRegister(TRC);
6932 AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
6933 TII->get(ldrOpc),scratch)
6934 .addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
6936 AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
6937 .addReg(scratch).addReg(destIn)
6940 AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
6941 TII->get(ldrOpc),scratch)
6942 .addReg(srcOut, RegState::Define).addReg(srcIn).addReg(0).addImm(1));
6944 AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
6945 .addReg(scratch).addReg(destIn)
6946 .addReg(0).addImm(1));
6952 MI->eraseFromParent(); // The instruction is gone now.
6957 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6958 MachineBasicBlock *BB) const {
6959 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6960 DebugLoc dl = MI->getDebugLoc();
6961 bool isThumb2 = Subtarget->isThumb2();
6962 switch (MI->getOpcode()) {
6965 llvm_unreachable("Unexpected instr type to insert");
6967 // The Thumb2 pre-indexed stores have the same MI operands, they just
6968 // define them differently in the .td files from the isel patterns, so
6969 // they need pseudos.
6970 case ARM::t2STR_preidx:
6971 MI->setDesc(TII->get(ARM::t2STR_PRE));
6973 case ARM::t2STRB_preidx:
6974 MI->setDesc(TII->get(ARM::t2STRB_PRE));
6976 case ARM::t2STRH_preidx:
6977 MI->setDesc(TII->get(ARM::t2STRH_PRE));
6980 case ARM::STRi_preidx:
6981 case ARM::STRBi_preidx: {
6982 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
6983 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
6984 // Decode the offset.
6985 unsigned Offset = MI->getOperand(4).getImm();
6986 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
6987 Offset = ARM_AM::getAM2Offset(Offset);
6991 MachineMemOperand *MMO = *MI->memoperands_begin();
6992 BuildMI(*BB, MI, dl, TII->get(NewOpc))
6993 .addOperand(MI->getOperand(0)) // Rn_wb
6994 .addOperand(MI->getOperand(1)) // Rt
6995 .addOperand(MI->getOperand(2)) // Rn
6996 .addImm(Offset) // offset (skip GPR==zero_reg)
6997 .addOperand(MI->getOperand(5)) // pred
6998 .addOperand(MI->getOperand(6))
6999 .addMemOperand(MMO);
7000 MI->eraseFromParent();
7003 case ARM::STRr_preidx:
7004 case ARM::STRBr_preidx:
7005 case ARM::STRH_preidx: {
7007 switch (MI->getOpcode()) {
7008 default: llvm_unreachable("unexpected opcode!");
7009 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7010 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7011 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7013 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7014 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7015 MIB.addOperand(MI->getOperand(i));
7016 MI->eraseFromParent();
7019 case ARM::ATOMIC_LOAD_ADD_I8:
7020 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
7021 case ARM::ATOMIC_LOAD_ADD_I16:
7022 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
7023 case ARM::ATOMIC_LOAD_ADD_I32:
7024 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
7026 case ARM::ATOMIC_LOAD_AND_I8:
7027 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
7028 case ARM::ATOMIC_LOAD_AND_I16:
7029 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
7030 case ARM::ATOMIC_LOAD_AND_I32:
7031 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
7033 case ARM::ATOMIC_LOAD_OR_I8:
7034 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
7035 case ARM::ATOMIC_LOAD_OR_I16:
7036 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
7037 case ARM::ATOMIC_LOAD_OR_I32:
7038 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
7040 case ARM::ATOMIC_LOAD_XOR_I8:
7041 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
7042 case ARM::ATOMIC_LOAD_XOR_I16:
7043 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
7044 case ARM::ATOMIC_LOAD_XOR_I32:
7045 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
7047 case ARM::ATOMIC_LOAD_NAND_I8:
7048 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
7049 case ARM::ATOMIC_LOAD_NAND_I16:
7050 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
7051 case ARM::ATOMIC_LOAD_NAND_I32:
7052 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
7054 case ARM::ATOMIC_LOAD_SUB_I8:
7055 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
7056 case ARM::ATOMIC_LOAD_SUB_I16:
7057 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
7058 case ARM::ATOMIC_LOAD_SUB_I32:
7059 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
7061 case ARM::ATOMIC_LOAD_MIN_I8:
7062 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
7063 case ARM::ATOMIC_LOAD_MIN_I16:
7064 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
7065 case ARM::ATOMIC_LOAD_MIN_I32:
7066 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
7068 case ARM::ATOMIC_LOAD_MAX_I8:
7069 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
7070 case ARM::ATOMIC_LOAD_MAX_I16:
7071 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
7072 case ARM::ATOMIC_LOAD_MAX_I32:
7073 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
7075 case ARM::ATOMIC_LOAD_UMIN_I8:
7076 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
7077 case ARM::ATOMIC_LOAD_UMIN_I16:
7078 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
7079 case ARM::ATOMIC_LOAD_UMIN_I32:
7080 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
7082 case ARM::ATOMIC_LOAD_UMAX_I8:
7083 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
7084 case ARM::ATOMIC_LOAD_UMAX_I16:
7085 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
7086 case ARM::ATOMIC_LOAD_UMAX_I32:
7087 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
7089 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
7090 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
7091 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
7093 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
7094 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
7095 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
7098 case ARM::ATOMADD6432:
7099 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr,
7100 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr,
7101 /*NeedsCarry*/ true);
7102 case ARM::ATOMSUB6432:
7103 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7104 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7105 /*NeedsCarry*/ true);
7106 case ARM::ATOMOR6432:
7107 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr,
7108 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
7109 case ARM::ATOMXOR6432:
7110 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr,
7111 isThumb2 ? ARM::t2EORrr : ARM::EORrr);
7112 case ARM::ATOMAND6432:
7113 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr,
7114 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
7115 case ARM::ATOMSWAP6432:
7116 return EmitAtomicBinary64(MI, BB, 0, 0, false);
7117 case ARM::ATOMCMPXCHG6432:
7118 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7119 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7120 /*NeedsCarry*/ false, /*IsCmpxchg*/true);
7121 case ARM::ATOMMIN6432:
7122 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7123 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7124 /*NeedsCarry*/ true, /*IsCmpxchg*/false,
7125 /*IsMinMax*/ true, ARMCC::LE);
7126 case ARM::ATOMMAX6432:
7127 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7128 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7129 /*NeedsCarry*/ true, /*IsCmpxchg*/false,
7130 /*IsMinMax*/ true, ARMCC::GE);
7131 case ARM::ATOMUMIN6432:
7132 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7133 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7134 /*NeedsCarry*/ true, /*IsCmpxchg*/false,
7135 /*IsMinMax*/ true, ARMCC::LS);
7136 case ARM::ATOMUMAX6432:
7137 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7138 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7139 /*NeedsCarry*/ true, /*IsCmpxchg*/false,
7140 /*IsMinMax*/ true, ARMCC::HS);
7142 case ARM::tMOVCCr_pseudo: {
7143 // To "insert" a SELECT_CC instruction, we actually have to insert the
7144 // diamond control-flow pattern. The incoming instruction knows the
7145 // destination vreg to set, the condition code register to branch on, the
7146 // true/false values to select between, and a branch opcode to use.
7147 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7148 MachineFunction::iterator It = BB;
7154 // cmpTY ccX, r1, r2
7156 // fallthrough --> copy0MBB
7157 MachineBasicBlock *thisMBB = BB;
7158 MachineFunction *F = BB->getParent();
7159 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7160 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7161 F->insert(It, copy0MBB);
7162 F->insert(It, sinkMBB);
7164 // Transfer the remainder of BB and its successor edges to sinkMBB.
7165 sinkMBB->splice(sinkMBB->begin(), BB,
7166 llvm::next(MachineBasicBlock::iterator(MI)),
7168 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7170 BB->addSuccessor(copy0MBB);
7171 BB->addSuccessor(sinkMBB);
7173 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7174 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7177 // %FalseValue = ...
7178 // # fallthrough to sinkMBB
7181 // Update machine-CFG edges
7182 BB->addSuccessor(sinkMBB);
7185 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7188 BuildMI(*BB, BB->begin(), dl,
7189 TII->get(ARM::PHI), MI->getOperand(0).getReg())
7190 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7191 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7193 MI->eraseFromParent(); // The pseudo instruction is gone now.
7198 case ARM::BCCZi64: {
7199 // If there is an unconditional branch to the other successor, remove it.
7200 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
7202 // Compare both parts that make up the double comparison separately for
7204 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7206 unsigned LHS1 = MI->getOperand(1).getReg();
7207 unsigned LHS2 = MI->getOperand(2).getReg();
7209 AddDefaultPred(BuildMI(BB, dl,
7210 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7211 .addReg(LHS1).addImm(0));
7212 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7213 .addReg(LHS2).addImm(0)
7214 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7216 unsigned RHS1 = MI->getOperand(3).getReg();
7217 unsigned RHS2 = MI->getOperand(4).getReg();
7218 AddDefaultPred(BuildMI(BB, dl,
7219 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7220 .addReg(LHS1).addReg(RHS1));
7221 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7222 .addReg(LHS2).addReg(RHS2)
7223 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7226 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7227 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7228 if (MI->getOperand(0).getImm() == ARMCC::NE)
7229 std::swap(destMBB, exitMBB);
7231 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7232 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
7234 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7236 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
7238 MI->eraseFromParent(); // The pseudo instruction is gone now.
7242 case ARM::Int_eh_sjlj_setjmp:
7243 case ARM::Int_eh_sjlj_setjmp_nofp:
7244 case ARM::tInt_eh_sjlj_setjmp:
7245 case ARM::t2Int_eh_sjlj_setjmp:
7246 case ARM::t2Int_eh_sjlj_setjmp_nofp:
7247 EmitSjLjDispatchBlock(MI, BB);
7252 // To insert an ABS instruction, we have to insert the
7253 // diamond control-flow pattern. The incoming instruction knows the
7254 // source vreg to test against 0, the destination vreg to set,
7255 // the condition code register to branch on, the
7256 // true/false values to select between, and a branch opcode to use.
7261 // BCC (branch to SinkBB if V0 >= 0)
7262 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
7263 // SinkBB: V1 = PHI(V2, V3)
7264 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7265 MachineFunction::iterator BBI = BB;
7267 MachineFunction *Fn = BB->getParent();
7268 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7269 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7270 Fn->insert(BBI, RSBBB);
7271 Fn->insert(BBI, SinkBB);
7273 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7274 unsigned int ABSDstReg = MI->getOperand(0).getReg();
7275 bool isThumb2 = Subtarget->isThumb2();
7276 MachineRegisterInfo &MRI = Fn->getRegInfo();
7277 // In Thumb mode S must not be specified if source register is the SP or
7278 // PC and if destination register is the SP, so restrict register class
7279 unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ?
7280 (const TargetRegisterClass*)&ARM::rGPRRegClass :
7281 (const TargetRegisterClass*)&ARM::GPRRegClass);
7283 // Transfer the remainder of BB and its successor edges to sinkMBB.
7284 SinkBB->splice(SinkBB->begin(), BB,
7285 llvm::next(MachineBasicBlock::iterator(MI)),
7287 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7289 BB->addSuccessor(RSBBB);
7290 BB->addSuccessor(SinkBB);
7292 // fall through to SinkMBB
7293 RSBBB->addSuccessor(SinkBB);
7295 // insert a cmp at the end of BB
7296 AddDefaultPred(BuildMI(BB, dl,
7297 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7298 .addReg(ABSSrcReg).addImm(0));
7300 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7302 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7303 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
7305 // insert rsbri in RSBBB
7306 // Note: BCC and rsbri will be converted into predicated rsbmi
7307 // by if-conversion pass
7308 BuildMI(*RSBBB, RSBBB->begin(), dl,
7309 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
7310 .addReg(ABSSrcReg, RegState::Kill)
7311 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7313 // insert PHI in SinkBB,
7314 // reuse ABSDstReg to not change uses of ABS instruction
7315 BuildMI(*SinkBB, SinkBB->begin(), dl,
7316 TII->get(ARM::PHI), ABSDstReg)
7317 .addReg(NewRsbDstReg).addMBB(RSBBB)
7318 .addReg(ABSSrcReg).addMBB(BB);
7320 // remove ABS instruction
7321 MI->eraseFromParent();
7323 // return last added BB
7326 case ARM::COPY_STRUCT_BYVAL_I32:
7328 return EmitStructByval(MI, BB);
7332 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
7333 SDNode *Node) const {
7334 if (!MI->hasPostISelHook()) {
7335 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
7336 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
7340 const MCInstrDesc *MCID = &MI->getDesc();
7341 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7342 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7343 // operand is still set to noreg. If needed, set the optional operand's
7344 // register to CPSR, and remove the redundant implicit def.
7346 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7348 // Rename pseudo opcodes.
7349 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7351 const ARMBaseInstrInfo *TII =
7352 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
7353 MCID = &TII->get(NewOpc);
7355 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7356 "converted opcode should be the same except for cc_out");
7360 // Add the optional cc_out operand
7361 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7363 unsigned ccOutIdx = MCID->getNumOperands() - 1;
7365 // Any ARM instruction that sets the 's' bit should specify an optional
7366 // "cc_out" operand in the last operand position.
7367 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7368 assert(!NewOpc && "Optional cc_out operand required");
7371 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7372 // since we already have an optional CPSR def.
7373 bool definesCPSR = false;
7374 bool deadCPSR = false;
7375 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
7377 const MachineOperand &MO = MI->getOperand(i);
7378 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7382 MI->RemoveOperand(i);
7387 assert(!NewOpc && "Optional cc_out operand required");
7390 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
7392 assert(!MI->getOperand(ccOutIdx).getReg() &&
7393 "expect uninitialized optional cc_out operand");
7397 // If this instruction was defined with an optional CPSR def and its dag node
7398 // had a live implicit CPSR def, then activate the optional CPSR def.
7399 MachineOperand &MO = MI->getOperand(ccOutIdx);
7400 MO.setReg(ARM::CPSR);
7404 //===----------------------------------------------------------------------===//
7405 // ARM Optimization Hooks
7406 //===----------------------------------------------------------------------===//
7408 // Helper function that checks if N is a null or all ones constant.
7409 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
7410 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
7413 return AllOnes ? C->isAllOnesValue() : C->isNullValue();
7416 // Return true if N is conditionally 0 or all ones.
7417 // Detects these expressions where cc is an i1 value:
7419 // (select cc 0, y) [AllOnes=0]
7420 // (select cc y, 0) [AllOnes=0]
7421 // (zext cc) [AllOnes=0]
7422 // (sext cc) [AllOnes=0/1]
7423 // (select cc -1, y) [AllOnes=1]
7424 // (select cc y, -1) [AllOnes=1]
7426 // Invert is set when N is the null/all ones constant when CC is false.
7427 // OtherOp is set to the alternative value of N.
7428 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
7429 SDValue &CC, bool &Invert,
7431 SelectionDAG &DAG) {
7432 switch (N->getOpcode()) {
7433 default: return false;
7435 CC = N->getOperand(0);
7436 SDValue N1 = N->getOperand(1);
7437 SDValue N2 = N->getOperand(2);
7438 if (isZeroOrAllOnes(N1, AllOnes)) {
7443 if (isZeroOrAllOnes(N2, AllOnes)) {
7450 case ISD::ZERO_EXTEND:
7451 // (zext cc) can never be the all ones value.
7455 case ISD::SIGN_EXTEND: {
7456 EVT VT = N->getValueType(0);
7457 CC = N->getOperand(0);
7458 if (CC.getValueType() != MVT::i1)
7462 // When looking for an AllOnes constant, N is an sext, and the 'other'
7464 OtherOp = DAG.getConstant(0, VT);
7465 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7466 // When looking for a 0 constant, N can be zext or sext.
7467 OtherOp = DAG.getConstant(1, VT);
7469 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
7475 // Combine a constant select operand into its use:
7477 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
7478 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
7479 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
7480 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
7481 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
7483 // The transform is rejected if the select doesn't have a constant operand that
7484 // is null, or all ones when AllOnes is set.
7486 // Also recognize sext/zext from i1:
7488 // (add (zext cc), x) -> (select cc (add x, 1), x)
7489 // (add (sext cc), x) -> (select cc (add x, -1), x)
7491 // These transformations eventually create predicated instructions.
7493 // @param N The node to transform.
7494 // @param Slct The N operand that is a select.
7495 // @param OtherOp The other N operand (x above).
7496 // @param DCI Context.
7497 // @param AllOnes Require the select constant to be all ones instead of null.
7498 // @returns The new node, or SDValue() on failure.
7500 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
7501 TargetLowering::DAGCombinerInfo &DCI,
7502 bool AllOnes = false) {
7503 SelectionDAG &DAG = DCI.DAG;
7504 EVT VT = N->getValueType(0);
7505 SDValue NonConstantVal;
7508 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
7509 NonConstantVal, DAG))
7512 // Slct is now know to be the desired identity constant when CC is true.
7513 SDValue TrueVal = OtherOp;
7514 SDValue FalseVal = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
7515 OtherOp, NonConstantVal);
7516 // Unless SwapSelectOps says CC should be false.
7518 std::swap(TrueVal, FalseVal);
7520 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
7521 CCOp, TrueVal, FalseVal);
7524 // Attempt combineSelectAndUse on each operand of a commutative operator N.
7526 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
7527 TargetLowering::DAGCombinerInfo &DCI) {
7528 SDValue N0 = N->getOperand(0);
7529 SDValue N1 = N->getOperand(1);
7530 if (N0.getNode()->hasOneUse()) {
7531 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
7532 if (Result.getNode())
7535 if (N1.getNode()->hasOneUse()) {
7536 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
7537 if (Result.getNode())
7543 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
7544 // (only after legalization).
7545 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
7546 TargetLowering::DAGCombinerInfo &DCI,
7547 const ARMSubtarget *Subtarget) {
7549 // Only perform optimization if after legalize, and if NEON is available. We
7550 // also expected both operands to be BUILD_VECTORs.
7551 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
7552 || N0.getOpcode() != ISD::BUILD_VECTOR
7553 || N1.getOpcode() != ISD::BUILD_VECTOR)
7556 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
7557 EVT VT = N->getValueType(0);
7558 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
7561 // Check that the vector operands are of the right form.
7562 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7563 // operands, where N is the size of the formed vector.
7564 // Each EXTRACT_VECTOR should have the same input vector and odd or even
7565 // index such that we have a pair wise add pattern.
7567 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
7568 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7570 SDValue Vec = N0->getOperand(0)->getOperand(0);
7571 SDNode *V = Vec.getNode();
7572 unsigned nextIndex = 0;
7574 // For each operands to the ADD which are BUILD_VECTORs,
7575 // check to see if each of their operands are an EXTRACT_VECTOR with
7576 // the same vector and appropriate index.
7577 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
7578 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7579 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7581 SDValue ExtVec0 = N0->getOperand(i);
7582 SDValue ExtVec1 = N1->getOperand(i);
7584 // First operand is the vector, verify its the same.
7585 if (V != ExtVec0->getOperand(0).getNode() ||
7586 V != ExtVec1->getOperand(0).getNode())
7589 // Second is the constant, verify its correct.
7590 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
7591 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
7593 // For the constant, we want to see all the even or all the odd.
7594 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
7595 || C1->getZExtValue() != nextIndex+1)
7604 // Create VPADDL node.
7605 SelectionDAG &DAG = DCI.DAG;
7606 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7608 // Build operand list.
7609 SmallVector<SDValue, 8> Ops;
7610 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
7611 TLI.getPointerTy()));
7613 // Input is the vector.
7616 // Get widened type and narrowed type.
7618 unsigned numElem = VT.getVectorNumElements();
7619 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
7620 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
7621 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
7622 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
7624 llvm_unreachable("Invalid vector element type for padd optimization.");
7627 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
7628 widenType, &Ops[0], Ops.size());
7629 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp);
7632 static SDValue findMUL_LOHI(SDValue V) {
7633 if (V->getOpcode() == ISD::UMUL_LOHI ||
7634 V->getOpcode() == ISD::SMUL_LOHI)
7639 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
7640 TargetLowering::DAGCombinerInfo &DCI,
7641 const ARMSubtarget *Subtarget) {
7643 if (Subtarget->isThumb1Only()) return SDValue();
7645 // Only perform the checks after legalize when the pattern is available.
7646 if (DCI.isBeforeLegalize()) return SDValue();
7648 // Look for multiply add opportunities.
7649 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
7650 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
7651 // a glue link from the first add to the second add.
7652 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
7653 // a S/UMLAL instruction.
7656 // \ / \ [no multiline comment]
7662 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
7663 SDValue AddcOp0 = AddcNode->getOperand(0);
7664 SDValue AddcOp1 = AddcNode->getOperand(1);
7666 // Check if the two operands are from the same mul_lohi node.
7667 if (AddcOp0.getNode() == AddcOp1.getNode())
7670 assert(AddcNode->getNumValues() == 2 &&
7671 AddcNode->getValueType(0) == MVT::i32 &&
7672 AddcNode->getValueType(1) == MVT::Glue &&
7673 "Expect ADDC with two result values: i32, glue");
7675 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
7676 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
7677 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
7678 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
7679 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
7682 // Look for the glued ADDE.
7683 SDNode* AddeNode = AddcNode->getGluedUser();
7684 if (AddeNode == NULL)
7687 // Make sure it is really an ADDE.
7688 if (AddeNode->getOpcode() != ISD::ADDE)
7691 assert(AddeNode->getNumOperands() == 3 &&
7692 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
7693 "ADDE node has the wrong inputs");
7695 // Check for the triangle shape.
7696 SDValue AddeOp0 = AddeNode->getOperand(0);
7697 SDValue AddeOp1 = AddeNode->getOperand(1);
7699 // Make sure that the ADDE operands are not coming from the same node.
7700 if (AddeOp0.getNode() == AddeOp1.getNode())
7703 // Find the MUL_LOHI node walking up ADDE's operands.
7704 bool IsLeftOperandMUL = false;
7705 SDValue MULOp = findMUL_LOHI(AddeOp0);
7706 if (MULOp == SDValue())
7707 MULOp = findMUL_LOHI(AddeOp1);
7709 IsLeftOperandMUL = true;
7710 if (MULOp == SDValue())
7713 // Figure out the right opcode.
7714 unsigned Opc = MULOp->getOpcode();
7715 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
7717 // Figure out the high and low input values to the MLAL node.
7718 SDValue* HiMul = &MULOp;
7719 SDValue* HiAdd = NULL;
7720 SDValue* LoMul = NULL;
7721 SDValue* LowAdd = NULL;
7723 if (IsLeftOperandMUL)
7729 if (AddcOp0->getOpcode() == Opc) {
7733 if (AddcOp1->getOpcode() == Opc) {
7741 if (LoMul->getNode() != HiMul->getNode())
7744 // Create the merged node.
7745 SelectionDAG &DAG = DCI.DAG;
7747 // Build operand list.
7748 SmallVector<SDValue, 8> Ops;
7749 Ops.push_back(LoMul->getOperand(0));
7750 Ops.push_back(LoMul->getOperand(1));
7751 Ops.push_back(*LowAdd);
7752 Ops.push_back(*HiAdd);
7754 SDValue MLALNode = DAG.getNode(FinalOpc, AddcNode->getDebugLoc(),
7755 DAG.getVTList(MVT::i32, MVT::i32),
7756 &Ops[0], Ops.size());
7758 // Replace the ADDs' nodes uses by the MLA node's values.
7759 SDValue HiMLALResult(MLALNode.getNode(), 1);
7760 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
7762 SDValue LoMLALResult(MLALNode.getNode(), 0);
7763 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
7765 // Return original node to notify the driver to stop replacing.
7766 SDValue resNode(AddcNode, 0);
7770 /// PerformADDCCombine - Target-specific dag combine transform from
7771 /// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
7772 static SDValue PerformADDCCombine(SDNode *N,
7773 TargetLowering::DAGCombinerInfo &DCI,
7774 const ARMSubtarget *Subtarget) {
7776 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
7780 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
7781 /// operands N0 and N1. This is a helper for PerformADDCombine that is
7782 /// called with the default operands, and if that fails, with commuted
7784 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
7785 TargetLowering::DAGCombinerInfo &DCI,
7786 const ARMSubtarget *Subtarget){
7788 // Attempt to create vpaddl for this add.
7789 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
7790 if (Result.getNode())
7793 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
7794 if (N0.getNode()->hasOneUse()) {
7795 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
7796 if (Result.getNode()) return Result;
7801 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
7803 static SDValue PerformADDCombine(SDNode *N,
7804 TargetLowering::DAGCombinerInfo &DCI,
7805 const ARMSubtarget *Subtarget) {
7806 SDValue N0 = N->getOperand(0);
7807 SDValue N1 = N->getOperand(1);
7809 // First try with the default operand order.
7810 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
7811 if (Result.getNode())
7814 // If that didn't work, try again with the operands commuted.
7815 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
7818 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
7820 static SDValue PerformSUBCombine(SDNode *N,
7821 TargetLowering::DAGCombinerInfo &DCI) {
7822 SDValue N0 = N->getOperand(0);
7823 SDValue N1 = N->getOperand(1);
7825 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
7826 if (N1.getNode()->hasOneUse()) {
7827 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
7828 if (Result.getNode()) return Result;
7834 /// PerformVMULCombine
7835 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
7836 /// special multiplier accumulator forwarding.
7842 static SDValue PerformVMULCombine(SDNode *N,
7843 TargetLowering::DAGCombinerInfo &DCI,
7844 const ARMSubtarget *Subtarget) {
7845 if (!Subtarget->hasVMLxForwarding())
7848 SelectionDAG &DAG = DCI.DAG;
7849 SDValue N0 = N->getOperand(0);
7850 SDValue N1 = N->getOperand(1);
7851 unsigned Opcode = N0.getOpcode();
7852 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
7853 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
7854 Opcode = N1.getOpcode();
7855 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
7856 Opcode != ISD::FADD && Opcode != ISD::FSUB)
7861 EVT VT = N->getValueType(0);
7862 DebugLoc DL = N->getDebugLoc();
7863 SDValue N00 = N0->getOperand(0);
7864 SDValue N01 = N0->getOperand(1);
7865 return DAG.getNode(Opcode, DL, VT,
7866 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
7867 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
7870 static SDValue PerformMULCombine(SDNode *N,
7871 TargetLowering::DAGCombinerInfo &DCI,
7872 const ARMSubtarget *Subtarget) {
7873 SelectionDAG &DAG = DCI.DAG;
7875 if (Subtarget->isThumb1Only())
7878 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7881 EVT VT = N->getValueType(0);
7882 if (VT.is64BitVector() || VT.is128BitVector())
7883 return PerformVMULCombine(N, DCI, Subtarget);
7887 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
7891 int64_t MulAmt = C->getSExtValue();
7892 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
7894 ShiftAmt = ShiftAmt & (32 - 1);
7895 SDValue V = N->getOperand(0);
7896 DebugLoc DL = N->getDebugLoc();
7899 MulAmt >>= ShiftAmt;
7902 if (isPowerOf2_32(MulAmt - 1)) {
7903 // (mul x, 2^N + 1) => (add (shl x, N), x)
7904 Res = DAG.getNode(ISD::ADD, DL, VT,
7906 DAG.getNode(ISD::SHL, DL, VT,
7908 DAG.getConstant(Log2_32(MulAmt - 1),
7910 } else if (isPowerOf2_32(MulAmt + 1)) {
7911 // (mul x, 2^N - 1) => (sub (shl x, N), x)
7912 Res = DAG.getNode(ISD::SUB, DL, VT,
7913 DAG.getNode(ISD::SHL, DL, VT,
7915 DAG.getConstant(Log2_32(MulAmt + 1),
7921 uint64_t MulAmtAbs = -MulAmt;
7922 if (isPowerOf2_32(MulAmtAbs + 1)) {
7923 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
7924 Res = DAG.getNode(ISD::SUB, DL, VT,
7926 DAG.getNode(ISD::SHL, DL, VT,
7928 DAG.getConstant(Log2_32(MulAmtAbs + 1),
7930 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
7931 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7932 Res = DAG.getNode(ISD::ADD, DL, VT,
7934 DAG.getNode(ISD::SHL, DL, VT,
7936 DAG.getConstant(Log2_32(MulAmtAbs-1),
7938 Res = DAG.getNode(ISD::SUB, DL, VT,
7939 DAG.getConstant(0, MVT::i32),Res);
7946 Res = DAG.getNode(ISD::SHL, DL, VT,
7947 Res, DAG.getConstant(ShiftAmt, MVT::i32));
7949 // Do not add new nodes to DAG combiner worklist.
7950 DCI.CombineTo(N, Res, false);
7954 static SDValue PerformANDCombine(SDNode *N,
7955 TargetLowering::DAGCombinerInfo &DCI,
7956 const ARMSubtarget *Subtarget) {
7958 // Attempt to use immediate-form VBIC
7959 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
7960 DebugLoc dl = N->getDebugLoc();
7961 EVT VT = N->getValueType(0);
7962 SelectionDAG &DAG = DCI.DAG;
7964 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7967 APInt SplatBits, SplatUndef;
7968 unsigned SplatBitSize;
7971 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
7972 if (SplatBitSize <= 64) {
7974 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
7975 SplatUndef.getZExtValue(), SplatBitSize,
7976 DAG, VbicVT, VT.is128BitVector(),
7978 if (Val.getNode()) {
7980 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
7981 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
7982 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
7987 if (!Subtarget->isThumb1Only()) {
7988 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
7989 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
7990 if (Result.getNode())
7997 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
7998 static SDValue PerformORCombine(SDNode *N,
7999 TargetLowering::DAGCombinerInfo &DCI,
8000 const ARMSubtarget *Subtarget) {
8001 // Attempt to use immediate-form VORR
8002 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8003 DebugLoc dl = N->getDebugLoc();
8004 EVT VT = N->getValueType(0);
8005 SelectionDAG &DAG = DCI.DAG;
8007 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8010 APInt SplatBits, SplatUndef;
8011 unsigned SplatBitSize;
8013 if (BVN && Subtarget->hasNEON() &&
8014 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8015 if (SplatBitSize <= 64) {
8017 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
8018 SplatUndef.getZExtValue(), SplatBitSize,
8019 DAG, VorrVT, VT.is128BitVector(),
8021 if (Val.getNode()) {
8023 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
8024 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
8025 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
8030 if (!Subtarget->isThumb1Only()) {
8031 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8032 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8033 if (Result.getNode())
8037 // The code below optimizes (or (and X, Y), Z).
8038 // The AND operand needs to have a single user to make these optimizations
8040 SDValue N0 = N->getOperand(0);
8041 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8043 SDValue N1 = N->getOperand(1);
8045 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
8046 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8047 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
8049 unsigned SplatBitSize;
8052 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8054 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
8055 HasAnyUndefs) && !HasAnyUndefs) {
8056 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8058 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
8059 HasAnyUndefs) && !HasAnyUndefs &&
8060 SplatBits0 == ~SplatBits1) {
8061 // Canonicalize the vector type to make instruction selection simpler.
8062 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8063 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
8064 N0->getOperand(1), N0->getOperand(0),
8066 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
8071 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
8074 // BFI is only available on V6T2+
8075 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
8078 DebugLoc DL = N->getDebugLoc();
8079 // 1) or (and A, mask), val => ARMbfi A, val, mask
8080 // iff (val & mask) == val
8082 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8083 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
8084 // && mask == ~mask2
8085 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
8086 // && ~mask == mask2
8087 // (i.e., copy a bitfield value into another bitfield of the same width)
8092 SDValue N00 = N0.getOperand(0);
8094 // The value and the mask need to be constants so we can verify this is
8095 // actually a bitfield set. If the mask is 0xffff, we can do better
8096 // via a movt instruction, so don't use BFI in that case.
8097 SDValue MaskOp = N0.getOperand(1);
8098 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
8101 unsigned Mask = MaskC->getZExtValue();
8105 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
8106 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8108 unsigned Val = N1C->getZExtValue();
8109 if ((Val & ~Mask) != Val)
8112 if (ARM::isBitFieldInvertedMask(Mask)) {
8113 Val >>= CountTrailingZeros_32(~Mask);
8115 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
8116 DAG.getConstant(Val, MVT::i32),
8117 DAG.getConstant(Mask, MVT::i32));
8119 // Do not add new nodes to DAG combiner worklist.
8120 DCI.CombineTo(N, Res, false);
8123 } else if (N1.getOpcode() == ISD::AND) {
8124 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8125 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8128 unsigned Mask2 = N11C->getZExtValue();
8130 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8132 if (ARM::isBitFieldInvertedMask(Mask) &&
8134 // The pack halfword instruction works better for masks that fit it,
8135 // so use that when it's available.
8136 if (Subtarget->hasT2ExtractPack() &&
8137 (Mask == 0xffff || Mask == 0xffff0000))
8140 unsigned amt = CountTrailingZeros_32(Mask2);
8141 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
8142 DAG.getConstant(amt, MVT::i32));
8143 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
8144 DAG.getConstant(Mask, MVT::i32));
8145 // Do not add new nodes to DAG combiner worklist.
8146 DCI.CombineTo(N, Res, false);
8148 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
8150 // The pack halfword instruction works better for masks that fit it,
8151 // so use that when it's available.
8152 if (Subtarget->hasT2ExtractPack() &&
8153 (Mask2 == 0xffff || Mask2 == 0xffff0000))
8156 unsigned lsb = CountTrailingZeros_32(Mask);
8157 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
8158 DAG.getConstant(lsb, MVT::i32));
8159 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
8160 DAG.getConstant(Mask2, MVT::i32));
8161 // Do not add new nodes to DAG combiner worklist.
8162 DCI.CombineTo(N, Res, false);
8167 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8168 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8169 ARM::isBitFieldInvertedMask(~Mask)) {
8170 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
8171 // where lsb(mask) == #shamt and masked bits of B are known zero.
8172 SDValue ShAmt = N00.getOperand(1);
8173 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
8174 unsigned LSB = CountTrailingZeros_32(Mask);
8178 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8179 DAG.getConstant(~Mask, MVT::i32));
8181 // Do not add new nodes to DAG combiner worklist.
8182 DCI.CombineTo(N, Res, false);
8188 static SDValue PerformXORCombine(SDNode *N,
8189 TargetLowering::DAGCombinerInfo &DCI,
8190 const ARMSubtarget *Subtarget) {
8191 EVT VT = N->getValueType(0);
8192 SelectionDAG &DAG = DCI.DAG;
8194 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8197 if (!Subtarget->isThumb1Only()) {
8198 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8199 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8200 if (Result.getNode())
8207 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
8208 /// the bits being cleared by the AND are not demanded by the BFI.
8209 static SDValue PerformBFICombine(SDNode *N,
8210 TargetLowering::DAGCombinerInfo &DCI) {
8211 SDValue N1 = N->getOperand(1);
8212 if (N1.getOpcode() == ISD::AND) {
8213 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8216 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
8217 unsigned LSB = CountTrailingZeros_32(~InvMask);
8218 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB;
8219 unsigned Mask = (1 << Width)-1;
8220 unsigned Mask2 = N11C->getZExtValue();
8221 if ((Mask & (~Mask2)) == 0)
8222 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
8223 N->getOperand(0), N1.getOperand(0),
8229 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
8230 /// ARMISD::VMOVRRD.
8231 static SDValue PerformVMOVRRDCombine(SDNode *N,
8232 TargetLowering::DAGCombinerInfo &DCI) {
8233 // vmovrrd(vmovdrr x, y) -> x,y
8234 SDValue InDouble = N->getOperand(0);
8235 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
8236 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
8238 // vmovrrd(load f64) -> (load i32), (load i32)
8239 SDNode *InNode = InDouble.getNode();
8240 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
8241 InNode->getValueType(0) == MVT::f64 &&
8242 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8243 !cast<LoadSDNode>(InNode)->isVolatile()) {
8244 // TODO: Should this be done for non-FrameIndex operands?
8245 LoadSDNode *LD = cast<LoadSDNode>(InNode);
8247 SelectionDAG &DAG = DCI.DAG;
8248 DebugLoc DL = LD->getDebugLoc();
8249 SDValue BasePtr = LD->getBasePtr();
8250 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8251 LD->getPointerInfo(), LD->isVolatile(),
8252 LD->isNonTemporal(), LD->isInvariant(),
8253 LD->getAlignment());
8255 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8256 DAG.getConstant(4, MVT::i32));
8257 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8258 LD->getPointerInfo(), LD->isVolatile(),
8259 LD->isNonTemporal(), LD->isInvariant(),
8260 std::min(4U, LD->getAlignment() / 2));
8262 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
8263 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
8264 DCI.RemoveFromWorklist(LD);
8272 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
8273 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
8274 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
8275 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
8276 SDValue Op0 = N->getOperand(0);
8277 SDValue Op1 = N->getOperand(1);
8278 if (Op0.getOpcode() == ISD::BITCAST)
8279 Op0 = Op0.getOperand(0);
8280 if (Op1.getOpcode() == ISD::BITCAST)
8281 Op1 = Op1.getOperand(0);
8282 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8283 Op0.getNode() == Op1.getNode() &&
8284 Op0.getResNo() == 0 && Op1.getResNo() == 1)
8285 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
8286 N->getValueType(0), Op0.getOperand(0));
8290 /// PerformSTORECombine - Target-specific dag combine xforms for
8292 static SDValue PerformSTORECombine(SDNode *N,
8293 TargetLowering::DAGCombinerInfo &DCI) {
8294 StoreSDNode *St = cast<StoreSDNode>(N);
8295 if (St->isVolatile())
8298 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
8299 // pack all of the elements in one place. Next, store to memory in fewer
8301 SDValue StVal = St->getValue();
8302 EVT VT = StVal.getValueType();
8303 if (St->isTruncatingStore() && VT.isVector()) {
8304 SelectionDAG &DAG = DCI.DAG;
8305 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8306 EVT StVT = St->getMemoryVT();
8307 unsigned NumElems = VT.getVectorNumElements();
8308 assert(StVT != VT && "Cannot truncate to the same type");
8309 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
8310 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
8312 // From, To sizes and ElemCount must be pow of two
8313 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
8315 // We are going to use the original vector elt for storing.
8316 // Accumulated smaller vector elements must be a multiple of the store size.
8317 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
8319 unsigned SizeRatio = FromEltSz / ToEltSz;
8320 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
8322 // Create a type on which we perform the shuffle.
8323 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
8324 NumElems*SizeRatio);
8325 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
8327 DebugLoc DL = St->getDebugLoc();
8328 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
8329 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
8330 for (unsigned i = 0; i < NumElems; ++i) ShuffleVec[i] = i * SizeRatio;
8332 // Can't shuffle using an illegal type.
8333 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
8335 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
8336 DAG.getUNDEF(WideVec.getValueType()),
8338 // At this point all of the data is stored at the bottom of the
8339 // register. We now need to save it to mem.
8341 // Find the largest store unit
8342 MVT StoreType = MVT::i8;
8343 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
8344 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
8345 MVT Tp = (MVT::SimpleValueType)tp;
8346 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
8349 // Didn't find a legal store type.
8350 if (!TLI.isTypeLegal(StoreType))
8353 // Bitcast the original vector into a vector of store-size units
8354 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
8355 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
8356 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
8357 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
8358 SmallVector<SDValue, 8> Chains;
8359 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
8360 TLI.getPointerTy());
8361 SDValue BasePtr = St->getBasePtr();
8363 // Perform one or more big stores into memory.
8364 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
8365 for (unsigned I = 0; I < E; I++) {
8366 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
8367 StoreType, ShuffWide,
8368 DAG.getIntPtrConstant(I));
8369 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
8370 St->getPointerInfo(), St->isVolatile(),
8371 St->isNonTemporal(), St->getAlignment());
8372 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
8374 Chains.push_back(Ch);
8376 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &Chains[0],
8380 if (!ISD::isNormalStore(St))
8383 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
8384 // ARM stores of arguments in the same cache line.
8385 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
8386 StVal.getNode()->hasOneUse()) {
8387 SelectionDAG &DAG = DCI.DAG;
8388 DebugLoc DL = St->getDebugLoc();
8389 SDValue BasePtr = St->getBasePtr();
8390 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
8391 StVal.getNode()->getOperand(0), BasePtr,
8392 St->getPointerInfo(), St->isVolatile(),
8393 St->isNonTemporal(), St->getAlignment());
8395 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8396 DAG.getConstant(4, MVT::i32));
8397 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
8398 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
8399 St->isNonTemporal(),
8400 std::min(4U, St->getAlignment() / 2));
8403 if (StVal.getValueType() != MVT::i64 ||
8404 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8407 // Bitcast an i64 store extracted from a vector to f64.
8408 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8409 SelectionDAG &DAG = DCI.DAG;
8410 DebugLoc dl = StVal.getDebugLoc();
8411 SDValue IntVec = StVal.getOperand(0);
8412 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8413 IntVec.getValueType().getVectorNumElements());
8414 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
8415 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8416 Vec, StVal.getOperand(1));
8417 dl = N->getDebugLoc();
8418 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
8419 // Make the DAGCombiner fold the bitcasts.
8420 DCI.AddToWorklist(Vec.getNode());
8421 DCI.AddToWorklist(ExtElt.getNode());
8422 DCI.AddToWorklist(V.getNode());
8423 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
8424 St->getPointerInfo(), St->isVolatile(),
8425 St->isNonTemporal(), St->getAlignment(),
8429 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
8430 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
8431 /// i64 vector to have f64 elements, since the value can then be loaded
8432 /// directly into a VFP register.
8433 static bool hasNormalLoadOperand(SDNode *N) {
8434 unsigned NumElts = N->getValueType(0).getVectorNumElements();
8435 for (unsigned i = 0; i < NumElts; ++i) {
8436 SDNode *Elt = N->getOperand(i).getNode();
8437 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
8443 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
8444 /// ISD::BUILD_VECTOR.
8445 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
8446 TargetLowering::DAGCombinerInfo &DCI){
8447 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
8448 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
8449 // into a pair of GPRs, which is fine when the value is used as a scalar,
8450 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
8451 SelectionDAG &DAG = DCI.DAG;
8452 if (N->getNumOperands() == 2) {
8453 SDValue RV = PerformVMOVDRRCombine(N, DAG);
8458 // Load i64 elements as f64 values so that type legalization does not split
8459 // them up into i32 values.
8460 EVT VT = N->getValueType(0);
8461 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8463 DebugLoc dl = N->getDebugLoc();
8464 SmallVector<SDValue, 8> Ops;
8465 unsigned NumElts = VT.getVectorNumElements();
8466 for (unsigned i = 0; i < NumElts; ++i) {
8467 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
8469 // Make the DAGCombiner fold the bitcast.
8470 DCI.AddToWorklist(V.getNode());
8472 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
8473 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
8474 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8477 /// PerformInsertEltCombine - Target-specific dag combine xforms for
8478 /// ISD::INSERT_VECTOR_ELT.
8479 static SDValue PerformInsertEltCombine(SDNode *N,
8480 TargetLowering::DAGCombinerInfo &DCI) {
8481 // Bitcast an i64 load inserted into a vector to f64.
8482 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8483 EVT VT = N->getValueType(0);
8484 SDNode *Elt = N->getOperand(1).getNode();
8485 if (VT.getVectorElementType() != MVT::i64 ||
8486 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
8489 SelectionDAG &DAG = DCI.DAG;
8490 DebugLoc dl = N->getDebugLoc();
8491 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8492 VT.getVectorNumElements());
8493 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
8494 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
8495 // Make the DAGCombiner fold the bitcasts.
8496 DCI.AddToWorklist(Vec.getNode());
8497 DCI.AddToWorklist(V.getNode());
8498 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
8499 Vec, V, N->getOperand(2));
8500 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
8503 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
8504 /// ISD::VECTOR_SHUFFLE.
8505 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
8506 // The LLVM shufflevector instruction does not require the shuffle mask
8507 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
8508 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
8509 // operands do not match the mask length, they are extended by concatenating
8510 // them with undef vectors. That is probably the right thing for other
8511 // targets, but for NEON it is better to concatenate two double-register
8512 // size vector operands into a single quad-register size vector. Do that
8513 // transformation here:
8514 // shuffle(concat(v1, undef), concat(v2, undef)) ->
8515 // shuffle(concat(v1, v2), undef)
8516 SDValue Op0 = N->getOperand(0);
8517 SDValue Op1 = N->getOperand(1);
8518 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
8519 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
8520 Op0.getNumOperands() != 2 ||
8521 Op1.getNumOperands() != 2)
8523 SDValue Concat0Op1 = Op0.getOperand(1);
8524 SDValue Concat1Op1 = Op1.getOperand(1);
8525 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
8526 Concat1Op1.getOpcode() != ISD::UNDEF)
8528 // Skip the transformation if any of the types are illegal.
8529 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8530 EVT VT = N->getValueType(0);
8531 if (!TLI.isTypeLegal(VT) ||
8532 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
8533 !TLI.isTypeLegal(Concat1Op1.getValueType()))
8536 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
8537 Op0.getOperand(0), Op1.getOperand(0));
8538 // Translate the shuffle mask.
8539 SmallVector<int, 16> NewMask;
8540 unsigned NumElts = VT.getVectorNumElements();
8541 unsigned HalfElts = NumElts/2;
8542 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8543 for (unsigned n = 0; n < NumElts; ++n) {
8544 int MaskElt = SVN->getMaskElt(n);
8546 if (MaskElt < (int)HalfElts)
8548 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
8549 NewElt = HalfElts + MaskElt - NumElts;
8550 NewMask.push_back(NewElt);
8552 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
8553 DAG.getUNDEF(VT), NewMask.data());
8556 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
8557 /// NEON load/store intrinsics to merge base address updates.
8558 static SDValue CombineBaseUpdate(SDNode *N,
8559 TargetLowering::DAGCombinerInfo &DCI) {
8560 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8563 SelectionDAG &DAG = DCI.DAG;
8564 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
8565 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
8566 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
8567 SDValue Addr = N->getOperand(AddrOpIdx);
8569 // Search for a use of the address operand that is an increment.
8570 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8571 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8573 if (User->getOpcode() != ISD::ADD ||
8574 UI.getUse().getResNo() != Addr.getResNo())
8577 // Check that the add is independent of the load/store. Otherwise, folding
8578 // it would create a cycle.
8579 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8582 // Find the new opcode for the updating load/store.
8584 bool isLaneOp = false;
8585 unsigned NewOpc = 0;
8586 unsigned NumVecs = 0;
8588 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8590 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8591 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
8593 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
8595 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
8597 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
8599 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
8600 NumVecs = 2; isLaneOp = true; break;
8601 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
8602 NumVecs = 3; isLaneOp = true; break;
8603 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
8604 NumVecs = 4; isLaneOp = true; break;
8605 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
8606 NumVecs = 1; isLoad = false; break;
8607 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
8608 NumVecs = 2; isLoad = false; break;
8609 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
8610 NumVecs = 3; isLoad = false; break;
8611 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
8612 NumVecs = 4; isLoad = false; break;
8613 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
8614 NumVecs = 2; isLoad = false; isLaneOp = true; break;
8615 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
8616 NumVecs = 3; isLoad = false; isLaneOp = true; break;
8617 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
8618 NumVecs = 4; isLoad = false; isLaneOp = true; break;
8622 switch (N->getOpcode()) {
8623 default: llvm_unreachable("unexpected opcode for Neon base update");
8624 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
8625 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
8626 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
8630 // Find the size of memory referenced by the load/store.
8633 VecTy = N->getValueType(0);
8635 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
8636 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8638 NumBytes /= VecTy.getVectorNumElements();
8640 // If the increment is a constant, it must match the memory ref size.
8641 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8642 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8643 uint64_t IncVal = CInc->getZExtValue();
8644 if (IncVal != NumBytes)
8646 } else if (NumBytes >= 3 * 16) {
8647 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
8648 // separate instructions that make it harder to use a non-constant update.
8652 // Create the new updating load/store node.
8654 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
8656 for (n = 0; n < NumResultVecs; ++n)
8658 Tys[n++] = MVT::i32;
8659 Tys[n] = MVT::Other;
8660 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
8661 SmallVector<SDValue, 8> Ops;
8662 Ops.push_back(N->getOperand(0)); // incoming chain
8663 Ops.push_back(N->getOperand(AddrOpIdx));
8665 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
8666 Ops.push_back(N->getOperand(i));
8668 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8669 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
8670 Ops.data(), Ops.size(),
8671 MemInt->getMemoryVT(),
8672 MemInt->getMemOperand());
8675 std::vector<SDValue> NewResults;
8676 for (unsigned i = 0; i < NumResultVecs; ++i) {
8677 NewResults.push_back(SDValue(UpdN.getNode(), i));
8679 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
8680 DCI.CombineTo(N, NewResults);
8681 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8688 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
8689 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
8690 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
8692 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8693 SelectionDAG &DAG = DCI.DAG;
8694 EVT VT = N->getValueType(0);
8695 // vldN-dup instructions only support 64-bit vectors for N > 1.
8696 if (!VT.is64BitVector())
8699 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
8700 SDNode *VLD = N->getOperand(0).getNode();
8701 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
8703 unsigned NumVecs = 0;
8704 unsigned NewOpc = 0;
8705 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
8706 if (IntNo == Intrinsic::arm_neon_vld2lane) {
8708 NewOpc = ARMISD::VLD2DUP;
8709 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
8711 NewOpc = ARMISD::VLD3DUP;
8712 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
8714 NewOpc = ARMISD::VLD4DUP;
8719 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
8720 // numbers match the load.
8721 unsigned VLDLaneNo =
8722 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
8723 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
8725 // Ignore uses of the chain result.
8726 if (UI.getUse().getResNo() == NumVecs)
8729 if (User->getOpcode() != ARMISD::VDUPLANE ||
8730 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
8734 // Create the vldN-dup node.
8737 for (n = 0; n < NumVecs; ++n)
8739 Tys[n] = MVT::Other;
8740 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
8741 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
8742 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
8743 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
8744 Ops, 2, VLDMemInt->getMemoryVT(),
8745 VLDMemInt->getMemOperand());
8748 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
8750 unsigned ResNo = UI.getUse().getResNo();
8751 // Ignore uses of the chain result.
8752 if (ResNo == NumVecs)
8755 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
8758 // Now the vldN-lane intrinsic is dead except for its chain result.
8759 // Update uses of the chain.
8760 std::vector<SDValue> VLDDupResults;
8761 for (unsigned n = 0; n < NumVecs; ++n)
8762 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
8763 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
8764 DCI.CombineTo(VLD, VLDDupResults);
8769 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
8770 /// ARMISD::VDUPLANE.
8771 static SDValue PerformVDUPLANECombine(SDNode *N,
8772 TargetLowering::DAGCombinerInfo &DCI) {
8773 SDValue Op = N->getOperand(0);
8775 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
8776 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
8777 if (CombineVLDDUP(N, DCI))
8778 return SDValue(N, 0);
8780 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
8781 // redundant. Ignore bit_converts for now; element sizes are checked below.
8782 while (Op.getOpcode() == ISD::BITCAST)
8783 Op = Op.getOperand(0);
8784 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
8787 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
8788 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
8789 // The canonical VMOV for a zero vector uses a 32-bit element size.
8790 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8792 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
8794 EVT VT = N->getValueType(0);
8795 if (EltSize > VT.getVectorElementType().getSizeInBits())
8798 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
8801 // isConstVecPow2 - Return true if each vector element is a power of 2, all
8802 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
8803 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
8807 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
8809 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
8814 APFloat APF = C->getValueAPF();
8815 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
8816 != APFloat::opOK || !isExact)
8819 c0 = (I == 0) ? cN : c0;
8820 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
8827 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
8828 /// can replace combinations of VMUL and VCVT (floating-point to integer)
8829 /// when the VMUL has a constant operand that is a power of 2.
8831 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
8832 /// vmul.f32 d16, d17, d16
8833 /// vcvt.s32.f32 d16, d16
8835 /// vcvt.s32.f32 d16, d16, #3
8836 static SDValue PerformVCVTCombine(SDNode *N,
8837 TargetLowering::DAGCombinerInfo &DCI,
8838 const ARMSubtarget *Subtarget) {
8839 SelectionDAG &DAG = DCI.DAG;
8840 SDValue Op = N->getOperand(0);
8842 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
8843 Op.getOpcode() != ISD::FMUL)
8847 SDValue N0 = Op->getOperand(0);
8848 SDValue ConstVec = Op->getOperand(1);
8849 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
8851 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
8852 !isConstVecPow2(ConstVec, isSigned, C))
8855 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
8856 Intrinsic::arm_neon_vcvtfp2fxu;
8857 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
8859 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
8860 DAG.getConstant(Log2_64(C), MVT::i32));
8863 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
8864 /// can replace combinations of VCVT (integer to floating-point) and VDIV
8865 /// when the VDIV has a constant operand that is a power of 2.
8867 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
8868 /// vcvt.f32.s32 d16, d16
8869 /// vdiv.f32 d16, d17, d16
8871 /// vcvt.f32.s32 d16, d16, #3
8872 static SDValue PerformVDIVCombine(SDNode *N,
8873 TargetLowering::DAGCombinerInfo &DCI,
8874 const ARMSubtarget *Subtarget) {
8875 SelectionDAG &DAG = DCI.DAG;
8876 SDValue Op = N->getOperand(0);
8877 unsigned OpOpcode = Op.getNode()->getOpcode();
8879 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
8880 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
8884 SDValue ConstVec = N->getOperand(1);
8885 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
8887 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
8888 !isConstVecPow2(ConstVec, isSigned, C))
8891 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
8892 Intrinsic::arm_neon_vcvtfxu2fp;
8893 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
8895 DAG.getConstant(IntrinsicOpcode, MVT::i32),
8896 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32));
8899 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
8900 /// operand of a vector shift operation, where all the elements of the
8901 /// build_vector must have the same constant integer value.
8902 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
8903 // Ignore bit_converts.
8904 while (Op.getOpcode() == ISD::BITCAST)
8905 Op = Op.getOperand(0);
8906 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
8907 APInt SplatBits, SplatUndef;
8908 unsigned SplatBitSize;
8910 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
8911 HasAnyUndefs, ElementBits) ||
8912 SplatBitSize > ElementBits)
8914 Cnt = SplatBits.getSExtValue();
8918 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
8919 /// operand of a vector shift left operation. That value must be in the range:
8920 /// 0 <= Value < ElementBits for a left shift; or
8921 /// 0 <= Value <= ElementBits for a long left shift.
8922 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
8923 assert(VT.isVector() && "vector shift count is not a vector type");
8924 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
8925 if (! getVShiftImm(Op, ElementBits, Cnt))
8927 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
8930 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
8931 /// operand of a vector shift right operation. For a shift opcode, the value
8932 /// is positive, but for an intrinsic the value count must be negative. The
8933 /// absolute value must be in the range:
8934 /// 1 <= |Value| <= ElementBits for a right shift; or
8935 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
8936 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
8938 assert(VT.isVector() && "vector shift count is not a vector type");
8939 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
8940 if (! getVShiftImm(Op, ElementBits, Cnt))
8944 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
8947 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
8948 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
8949 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
8952 // Don't do anything for most intrinsics.
8955 // Vector shifts: check for immediate versions and lower them.
8956 // Note: This is done during DAG combining instead of DAG legalizing because
8957 // the build_vectors for 64-bit vector element shift counts are generally
8958 // not legal, and it is hard to see their values after they get legalized to
8959 // loads from a constant pool.
8960 case Intrinsic::arm_neon_vshifts:
8961 case Intrinsic::arm_neon_vshiftu:
8962 case Intrinsic::arm_neon_vshiftls:
8963 case Intrinsic::arm_neon_vshiftlu:
8964 case Intrinsic::arm_neon_vshiftn:
8965 case Intrinsic::arm_neon_vrshifts:
8966 case Intrinsic::arm_neon_vrshiftu:
8967 case Intrinsic::arm_neon_vrshiftn:
8968 case Intrinsic::arm_neon_vqshifts:
8969 case Intrinsic::arm_neon_vqshiftu:
8970 case Intrinsic::arm_neon_vqshiftsu:
8971 case Intrinsic::arm_neon_vqshiftns:
8972 case Intrinsic::arm_neon_vqshiftnu:
8973 case Intrinsic::arm_neon_vqshiftnsu:
8974 case Intrinsic::arm_neon_vqrshiftns:
8975 case Intrinsic::arm_neon_vqrshiftnu:
8976 case Intrinsic::arm_neon_vqrshiftnsu: {
8977 EVT VT = N->getOperand(1).getValueType();
8979 unsigned VShiftOpc = 0;
8982 case Intrinsic::arm_neon_vshifts:
8983 case Intrinsic::arm_neon_vshiftu:
8984 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
8985 VShiftOpc = ARMISD::VSHL;
8988 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
8989 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
8990 ARMISD::VSHRs : ARMISD::VSHRu);
8995 case Intrinsic::arm_neon_vshiftls:
8996 case Intrinsic::arm_neon_vshiftlu:
8997 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
8999 llvm_unreachable("invalid shift count for vshll intrinsic");
9001 case Intrinsic::arm_neon_vrshifts:
9002 case Intrinsic::arm_neon_vrshiftu:
9003 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
9007 case Intrinsic::arm_neon_vqshifts:
9008 case Intrinsic::arm_neon_vqshiftu:
9009 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9013 case Intrinsic::arm_neon_vqshiftsu:
9014 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9016 llvm_unreachable("invalid shift count for vqshlu intrinsic");
9018 case Intrinsic::arm_neon_vshiftn:
9019 case Intrinsic::arm_neon_vrshiftn:
9020 case Intrinsic::arm_neon_vqshiftns:
9021 case Intrinsic::arm_neon_vqshiftnu:
9022 case Intrinsic::arm_neon_vqshiftnsu:
9023 case Intrinsic::arm_neon_vqrshiftns:
9024 case Intrinsic::arm_neon_vqrshiftnu:
9025 case Intrinsic::arm_neon_vqrshiftnsu:
9026 // Narrowing shifts require an immediate right shift.
9027 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
9029 llvm_unreachable("invalid shift count for narrowing vector shift "
9033 llvm_unreachable("unhandled vector shift");
9037 case Intrinsic::arm_neon_vshifts:
9038 case Intrinsic::arm_neon_vshiftu:
9039 // Opcode already set above.
9041 case Intrinsic::arm_neon_vshiftls:
9042 case Intrinsic::arm_neon_vshiftlu:
9043 if (Cnt == VT.getVectorElementType().getSizeInBits())
9044 VShiftOpc = ARMISD::VSHLLi;
9046 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
9047 ARMISD::VSHLLs : ARMISD::VSHLLu);
9049 case Intrinsic::arm_neon_vshiftn:
9050 VShiftOpc = ARMISD::VSHRN; break;
9051 case Intrinsic::arm_neon_vrshifts:
9052 VShiftOpc = ARMISD::VRSHRs; break;
9053 case Intrinsic::arm_neon_vrshiftu:
9054 VShiftOpc = ARMISD::VRSHRu; break;
9055 case Intrinsic::arm_neon_vrshiftn:
9056 VShiftOpc = ARMISD::VRSHRN; break;
9057 case Intrinsic::arm_neon_vqshifts:
9058 VShiftOpc = ARMISD::VQSHLs; break;
9059 case Intrinsic::arm_neon_vqshiftu:
9060 VShiftOpc = ARMISD::VQSHLu; break;
9061 case Intrinsic::arm_neon_vqshiftsu:
9062 VShiftOpc = ARMISD::VQSHLsu; break;
9063 case Intrinsic::arm_neon_vqshiftns:
9064 VShiftOpc = ARMISD::VQSHRNs; break;
9065 case Intrinsic::arm_neon_vqshiftnu:
9066 VShiftOpc = ARMISD::VQSHRNu; break;
9067 case Intrinsic::arm_neon_vqshiftnsu:
9068 VShiftOpc = ARMISD::VQSHRNsu; break;
9069 case Intrinsic::arm_neon_vqrshiftns:
9070 VShiftOpc = ARMISD::VQRSHRNs; break;
9071 case Intrinsic::arm_neon_vqrshiftnu:
9072 VShiftOpc = ARMISD::VQRSHRNu; break;
9073 case Intrinsic::arm_neon_vqrshiftnsu:
9074 VShiftOpc = ARMISD::VQRSHRNsu; break;
9077 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
9078 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
9081 case Intrinsic::arm_neon_vshiftins: {
9082 EVT VT = N->getOperand(1).getValueType();
9084 unsigned VShiftOpc = 0;
9086 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
9087 VShiftOpc = ARMISD::VSLI;
9088 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
9089 VShiftOpc = ARMISD::VSRI;
9091 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
9094 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
9095 N->getOperand(1), N->getOperand(2),
9096 DAG.getConstant(Cnt, MVT::i32));
9099 case Intrinsic::arm_neon_vqrshifts:
9100 case Intrinsic::arm_neon_vqrshiftu:
9101 // No immediate versions of these to check for.
9108 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
9109 /// lowers them. As with the vector shift intrinsics, this is done during DAG
9110 /// combining instead of DAG legalizing because the build_vectors for 64-bit
9111 /// vector element shift counts are generally not legal, and it is hard to see
9112 /// their values after they get legalized to loads from a constant pool.
9113 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
9114 const ARMSubtarget *ST) {
9115 EVT VT = N->getValueType(0);
9116 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9117 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
9118 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
9119 SDValue N1 = N->getOperand(1);
9120 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
9121 SDValue N0 = N->getOperand(0);
9122 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9123 DAG.MaskedValueIsZero(N0.getOperand(0),
9124 APInt::getHighBitsSet(32, 16)))
9125 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, N0, N1);
9129 // Nothing to be done for scalar shifts.
9130 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9131 if (!VT.isVector() || !TLI.isTypeLegal(VT))
9134 assert(ST->hasNEON() && "unexpected vector shift");
9137 switch (N->getOpcode()) {
9138 default: llvm_unreachable("unexpected shift opcode");
9141 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
9142 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
9143 DAG.getConstant(Cnt, MVT::i32));
9148 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
9149 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
9150 ARMISD::VSHRs : ARMISD::VSHRu);
9151 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
9152 DAG.getConstant(Cnt, MVT::i32));
9158 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
9159 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
9160 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
9161 const ARMSubtarget *ST) {
9162 SDValue N0 = N->getOperand(0);
9164 // Check for sign- and zero-extensions of vector extract operations of 8-
9165 // and 16-bit vector elements. NEON supports these directly. They are
9166 // handled during DAG combining because type legalization will promote them
9167 // to 32-bit types and it is messy to recognize the operations after that.
9168 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9169 SDValue Vec = N0.getOperand(0);
9170 SDValue Lane = N0.getOperand(1);
9171 EVT VT = N->getValueType(0);
9172 EVT EltVT = N0.getValueType();
9173 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9175 if (VT == MVT::i32 &&
9176 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
9177 TLI.isTypeLegal(Vec.getValueType()) &&
9178 isa<ConstantSDNode>(Lane)) {
9181 switch (N->getOpcode()) {
9182 default: llvm_unreachable("unexpected opcode");
9183 case ISD::SIGN_EXTEND:
9184 Opc = ARMISD::VGETLANEs;
9186 case ISD::ZERO_EXTEND:
9187 case ISD::ANY_EXTEND:
9188 Opc = ARMISD::VGETLANEu;
9191 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
9198 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
9199 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
9200 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
9201 const ARMSubtarget *ST) {
9202 // If the target supports NEON, try to use vmax/vmin instructions for f32
9203 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
9204 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
9205 // a NaN; only do the transformation when it matches that behavior.
9207 // For now only do this when using NEON for FP operations; if using VFP, it
9208 // is not obvious that the benefit outweighs the cost of switching to the
9210 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
9211 N->getValueType(0) != MVT::f32)
9214 SDValue CondLHS = N->getOperand(0);
9215 SDValue CondRHS = N->getOperand(1);
9216 SDValue LHS = N->getOperand(2);
9217 SDValue RHS = N->getOperand(3);
9218 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9220 unsigned Opcode = 0;
9222 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
9223 IsReversed = false; // x CC y ? x : y
9224 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
9225 IsReversed = true ; // x CC y ? y : x
9239 // If LHS is NaN, an ordered comparison will be false and the result will
9240 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
9241 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9242 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
9243 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9245 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
9246 // will return -0, so vmin can only be used for unsafe math or if one of
9247 // the operands is known to be nonzero.
9248 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
9249 !DAG.getTarget().Options.UnsafeFPMath &&
9250 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9252 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
9261 // If LHS is NaN, an ordered comparison will be false and the result will
9262 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
9263 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9264 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
9265 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9267 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
9268 // will return +0, so vmax can only be used for unsafe math or if one of
9269 // the operands is known to be nonzero.
9270 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
9271 !DAG.getTarget().Options.UnsafeFPMath &&
9272 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9274 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
9280 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
9283 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
9285 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
9286 SDValue Cmp = N->getOperand(4);
9287 if (Cmp.getOpcode() != ARMISD::CMPZ)
9288 // Only looking at EQ and NE cases.
9291 EVT VT = N->getValueType(0);
9292 DebugLoc dl = N->getDebugLoc();
9293 SDValue LHS = Cmp.getOperand(0);
9294 SDValue RHS = Cmp.getOperand(1);
9295 SDValue FalseVal = N->getOperand(0);
9296 SDValue TrueVal = N->getOperand(1);
9297 SDValue ARMcc = N->getOperand(2);
9298 ARMCC::CondCodes CC =
9299 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
9317 /// FIXME: Turn this into a target neutral optimization?
9319 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
9320 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
9321 N->getOperand(3), Cmp);
9322 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
9324 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
9325 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
9326 N->getOperand(3), NewCmp);
9329 if (Res.getNode()) {
9330 APInt KnownZero, KnownOne;
9331 DAG.ComputeMaskedBits(SDValue(N,0), KnownZero, KnownOne);
9332 // Capture demanded bits information that would be otherwise lost.
9333 if (KnownZero == 0xfffffffe)
9334 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9335 DAG.getValueType(MVT::i1));
9336 else if (KnownZero == 0xffffff00)
9337 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9338 DAG.getValueType(MVT::i8));
9339 else if (KnownZero == 0xffff0000)
9340 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9341 DAG.getValueType(MVT::i16));
9347 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
9348 DAGCombinerInfo &DCI) const {
9349 switch (N->getOpcode()) {
9351 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
9352 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
9353 case ISD::SUB: return PerformSUBCombine(N, DCI);
9354 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
9355 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
9356 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
9357 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
9358 case ARMISD::BFI: return PerformBFICombine(N, DCI);
9359 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
9360 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
9361 case ISD::STORE: return PerformSTORECombine(N, DCI);
9362 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
9363 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
9364 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
9365 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
9366 case ISD::FP_TO_SINT:
9367 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
9368 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
9369 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
9372 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
9373 case ISD::SIGN_EXTEND:
9374 case ISD::ZERO_EXTEND:
9375 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
9376 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
9377 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
9378 case ARMISD::VLD2DUP:
9379 case ARMISD::VLD3DUP:
9380 case ARMISD::VLD4DUP:
9381 return CombineBaseUpdate(N, DCI);
9382 case ISD::INTRINSIC_VOID:
9383 case ISD::INTRINSIC_W_CHAIN:
9384 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9385 case Intrinsic::arm_neon_vld1:
9386 case Intrinsic::arm_neon_vld2:
9387 case Intrinsic::arm_neon_vld3:
9388 case Intrinsic::arm_neon_vld4:
9389 case Intrinsic::arm_neon_vld2lane:
9390 case Intrinsic::arm_neon_vld3lane:
9391 case Intrinsic::arm_neon_vld4lane:
9392 case Intrinsic::arm_neon_vst1:
9393 case Intrinsic::arm_neon_vst2:
9394 case Intrinsic::arm_neon_vst3:
9395 case Intrinsic::arm_neon_vst4:
9396 case Intrinsic::arm_neon_vst2lane:
9397 case Intrinsic::arm_neon_vst3lane:
9398 case Intrinsic::arm_neon_vst4lane:
9399 return CombineBaseUpdate(N, DCI);
9407 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
9409 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
9412 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
9413 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
9414 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
9416 switch (VT.getSimpleVT().SimpleTy) {
9422 // Unaligned access can use (for example) LRDB, LRDH, LDR
9423 if (AllowsUnaligned) {
9425 *Fast = Subtarget->hasV7Ops();
9432 // For any little-endian targets with neon, we can support unaligned ld/st
9433 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
9434 // A big-endian target may also explictly support unaligned accesses
9435 if (Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian())) {
9445 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
9446 unsigned AlignCheck) {
9447 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
9448 (DstAlign == 0 || DstAlign % AlignCheck == 0));
9451 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
9452 unsigned DstAlign, unsigned SrcAlign,
9455 MachineFunction &MF) const {
9456 const Function *F = MF.getFunction();
9458 // See if we can use NEON instructions for this...
9460 Subtarget->hasNEON() &&
9461 !F->getFnAttributes().hasAttribute(Attributes::NoImplicitFloat)) {
9464 (memOpAlign(SrcAlign, DstAlign, 16) ||
9465 (allowsUnalignedMemoryAccesses(MVT::v2f64, &Fast) && Fast))) {
9467 } else if (Size >= 8 &&
9468 (memOpAlign(SrcAlign, DstAlign, 8) ||
9469 (allowsUnalignedMemoryAccesses(MVT::f64, &Fast) && Fast))) {
9474 // Lowering to i32/i16 if the size permits.
9480 // Let the target-independent logic figure it out.
9484 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9485 if (Val.getOpcode() != ISD::LOAD)
9488 EVT VT1 = Val.getValueType();
9489 if (!VT1.isSimple() || !VT1.isInteger() ||
9490 !VT2.isSimple() || !VT2.isInteger())
9493 switch (VT1.getSimpleVT().SimpleTy) {
9498 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
9505 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
9510 switch (VT.getSimpleVT().SimpleTy) {
9511 default: return false;
9526 if ((V & (Scale - 1)) != 0)
9529 return V == (V & ((1LL << 5) - 1));
9532 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
9533 const ARMSubtarget *Subtarget) {
9540 switch (VT.getSimpleVT().SimpleTy) {
9541 default: return false;
9546 // + imm12 or - imm8
9548 return V == (V & ((1LL << 8) - 1));
9549 return V == (V & ((1LL << 12) - 1));
9552 // Same as ARM mode. FIXME: NEON?
9553 if (!Subtarget->hasVFP2())
9558 return V == (V & ((1LL << 8) - 1));
9562 /// isLegalAddressImmediate - Return true if the integer value can be used
9563 /// as the offset of the target addressing mode for load / store of the
9565 static bool isLegalAddressImmediate(int64_t V, EVT VT,
9566 const ARMSubtarget *Subtarget) {
9573 if (Subtarget->isThumb1Only())
9574 return isLegalT1AddressImmediate(V, VT);
9575 else if (Subtarget->isThumb2())
9576 return isLegalT2AddressImmediate(V, VT, Subtarget);
9581 switch (VT.getSimpleVT().SimpleTy) {
9582 default: return false;
9587 return V == (V & ((1LL << 12) - 1));
9590 return V == (V & ((1LL << 8) - 1));
9593 if (!Subtarget->hasVFP2()) // FIXME: NEON?
9598 return V == (V & ((1LL << 8) - 1));
9602 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
9604 int Scale = AM.Scale;
9608 switch (VT.getSimpleVT().SimpleTy) {
9609 default: return false;
9618 return Scale == 2 || Scale == 4 || Scale == 8;
9621 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
9625 // Note, we allow "void" uses (basically, uses that aren't loads or
9626 // stores), because arm allows folding a scale into many arithmetic
9627 // operations. This should be made more precise and revisited later.
9629 // Allow r << imm, but the imm has to be a multiple of two.
9630 if (Scale & 1) return false;
9631 return isPowerOf2_32(Scale);
9635 /// isLegalAddressingMode - Return true if the addressing mode represented
9636 /// by AM is legal for this target, for a load/store of the specified type.
9637 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9639 EVT VT = getValueType(Ty, true);
9640 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
9643 // Can never fold addr of global into load/store.
9648 case 0: // no scale reg, must be "r+i" or "r", or "i".
9651 if (Subtarget->isThumb1Only())
9655 // ARM doesn't support any R+R*scale+imm addr modes.
9662 if (Subtarget->isThumb2())
9663 return isLegalT2ScaledAddressingMode(AM, VT);
9665 int Scale = AM.Scale;
9666 switch (VT.getSimpleVT().SimpleTy) {
9667 default: return false;
9671 if (Scale < 0) Scale = -Scale;
9675 return isPowerOf2_32(Scale & ~1);
9679 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
9684 // Note, we allow "void" uses (basically, uses that aren't loads or
9685 // stores), because arm allows folding a scale into many arithmetic
9686 // operations. This should be made more precise and revisited later.
9688 // Allow r << imm, but the imm has to be a multiple of two.
9689 if (Scale & 1) return false;
9690 return isPowerOf2_32(Scale);
9696 /// isLegalICmpImmediate - Return true if the specified immediate is legal
9697 /// icmp immediate, that is the target has icmp instructions which can compare
9698 /// a register against the immediate without having to materialize the
9699 /// immediate into a register.
9700 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9701 // Thumb2 and ARM modes can use cmn for negative immediates.
9702 if (!Subtarget->isThumb())
9703 return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1;
9704 if (Subtarget->isThumb2())
9705 return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1;
9706 // Thumb1 doesn't have cmn, and only 8-bit immediates.
9707 return Imm >= 0 && Imm <= 255;
9710 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
9711 /// *or sub* immediate, that is the target has add or sub instructions which can
9712 /// add a register with the immediate without having to materialize the
9713 /// immediate into a register.
9714 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9715 // Same encoding for add/sub, just flip the sign.
9716 int64_t AbsImm = llvm::abs64(Imm);
9717 if (!Subtarget->isThumb())
9718 return ARM_AM::getSOImmVal(AbsImm) != -1;
9719 if (Subtarget->isThumb2())
9720 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
9721 // Thumb1 only has 8-bit unsigned immediate.
9722 return AbsImm >= 0 && AbsImm <= 255;
9725 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
9726 bool isSEXTLoad, SDValue &Base,
9727 SDValue &Offset, bool &isInc,
9728 SelectionDAG &DAG) {
9729 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
9732 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
9734 Base = Ptr->getOperand(0);
9735 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
9736 int RHSC = (int)RHS->getZExtValue();
9737 if (RHSC < 0 && RHSC > -256) {
9738 assert(Ptr->getOpcode() == ISD::ADD);
9740 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
9744 isInc = (Ptr->getOpcode() == ISD::ADD);
9745 Offset = Ptr->getOperand(1);
9747 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
9749 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
9750 int RHSC = (int)RHS->getZExtValue();
9751 if (RHSC < 0 && RHSC > -0x1000) {
9752 assert(Ptr->getOpcode() == ISD::ADD);
9754 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
9755 Base = Ptr->getOperand(0);
9760 if (Ptr->getOpcode() == ISD::ADD) {
9762 ARM_AM::ShiftOpc ShOpcVal=
9763 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
9764 if (ShOpcVal != ARM_AM::no_shift) {
9765 Base = Ptr->getOperand(1);
9766 Offset = Ptr->getOperand(0);
9768 Base = Ptr->getOperand(0);
9769 Offset = Ptr->getOperand(1);
9774 isInc = (Ptr->getOpcode() == ISD::ADD);
9775 Base = Ptr->getOperand(0);
9776 Offset = Ptr->getOperand(1);
9780 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
9784 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
9785 bool isSEXTLoad, SDValue &Base,
9786 SDValue &Offset, bool &isInc,
9787 SelectionDAG &DAG) {
9788 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
9791 Base = Ptr->getOperand(0);
9792 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
9793 int RHSC = (int)RHS->getZExtValue();
9794 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
9795 assert(Ptr->getOpcode() == ISD::ADD);
9797 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
9799 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
9800 isInc = Ptr->getOpcode() == ISD::ADD;
9801 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
9809 /// getPreIndexedAddressParts - returns true by value, base pointer and
9810 /// offset pointer and addressing mode by reference if the node's address
9811 /// can be legally represented as pre-indexed load / store address.
9813 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
9815 ISD::MemIndexedMode &AM,
9816 SelectionDAG &DAG) const {
9817 if (Subtarget->isThumb1Only())
9822 bool isSEXTLoad = false;
9823 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9824 Ptr = LD->getBasePtr();
9825 VT = LD->getMemoryVT();
9826 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
9827 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9828 Ptr = ST->getBasePtr();
9829 VT = ST->getMemoryVT();
9834 bool isLegal = false;
9835 if (Subtarget->isThumb2())
9836 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
9837 Offset, isInc, DAG);
9839 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
9840 Offset, isInc, DAG);
9844 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
9848 /// getPostIndexedAddressParts - returns true by value, base pointer and
9849 /// offset pointer and addressing mode by reference if this node can be
9850 /// combined with a load / store to form a post-indexed load / store.
9851 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
9854 ISD::MemIndexedMode &AM,
9855 SelectionDAG &DAG) const {
9856 if (Subtarget->isThumb1Only())
9861 bool isSEXTLoad = false;
9862 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9863 VT = LD->getMemoryVT();
9864 Ptr = LD->getBasePtr();
9865 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
9866 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9867 VT = ST->getMemoryVT();
9868 Ptr = ST->getBasePtr();
9873 bool isLegal = false;
9874 if (Subtarget->isThumb2())
9875 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
9878 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
9884 // Swap base ptr and offset to catch more post-index load / store when
9885 // it's legal. In Thumb2 mode, offset must be an immediate.
9886 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
9887 !Subtarget->isThumb2())
9888 std::swap(Base, Offset);
9890 // Post-indexed load / store update the base pointer.
9895 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
9899 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
9902 const SelectionDAG &DAG,
9903 unsigned Depth) const {
9904 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
9905 switch (Op.getOpcode()) {
9907 case ARMISD::CMOV: {
9908 // Bits are known zero/one if known on the LHS and RHS.
9909 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
9910 if (KnownZero == 0 && KnownOne == 0) return;
9912 APInt KnownZeroRHS, KnownOneRHS;
9913 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
9914 KnownZero &= KnownZeroRHS;
9915 KnownOne &= KnownOneRHS;
9921 //===----------------------------------------------------------------------===//
9922 // ARM Inline Assembly Support
9923 //===----------------------------------------------------------------------===//
9925 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
9926 // Looking for "rev" which is V6+.
9927 if (!Subtarget->hasV6Ops())
9930 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9931 std::string AsmStr = IA->getAsmString();
9932 SmallVector<StringRef, 4> AsmPieces;
9933 SplitString(AsmStr, AsmPieces, ";\n");
9935 switch (AsmPieces.size()) {
9936 default: return false;
9938 AsmStr = AsmPieces[0];
9940 SplitString(AsmStr, AsmPieces, " \t,");
9943 if (AsmPieces.size() == 3 &&
9944 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
9945 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
9946 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9947 if (Ty && Ty->getBitWidth() == 32)
9948 return IntrinsicLowering::LowerToByteSwap(CI);
9956 /// getConstraintType - Given a constraint letter, return the type of
9957 /// constraint it is for this target.
9958 ARMTargetLowering::ConstraintType
9959 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
9960 if (Constraint.size() == 1) {
9961 switch (Constraint[0]) {
9963 case 'l': return C_RegisterClass;
9964 case 'w': return C_RegisterClass;
9965 case 'h': return C_RegisterClass;
9966 case 'x': return C_RegisterClass;
9967 case 't': return C_RegisterClass;
9968 case 'j': return C_Other; // Constant for movw.
9969 // An address with a single base register. Due to the way we
9970 // currently handle addresses it is the same as an 'r' memory constraint.
9971 case 'Q': return C_Memory;
9973 } else if (Constraint.size() == 2) {
9974 switch (Constraint[0]) {
9976 // All 'U+' constraints are addresses.
9977 case 'U': return C_Memory;
9980 return TargetLowering::getConstraintType(Constraint);
9983 /// Examine constraint type and operand type and determine a weight value.
9984 /// This object must already have been set up with the operand type
9985 /// and the current alternative constraint selected.
9986 TargetLowering::ConstraintWeight
9987 ARMTargetLowering::getSingleConstraintMatchWeight(
9988 AsmOperandInfo &info, const char *constraint) const {
9989 ConstraintWeight weight = CW_Invalid;
9990 Value *CallOperandVal = info.CallOperandVal;
9991 // If we don't have a value, we can't do a match,
9992 // but allow it at the lowest weight.
9993 if (CallOperandVal == NULL)
9995 Type *type = CallOperandVal->getType();
9996 // Look at the constraint type.
9997 switch (*constraint) {
9999 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10002 if (type->isIntegerTy()) {
10003 if (Subtarget->isThumb())
10004 weight = CW_SpecificReg;
10006 weight = CW_Register;
10010 if (type->isFloatingPointTy())
10011 weight = CW_Register;
10017 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10019 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10021 if (Constraint.size() == 1) {
10022 // GCC ARM Constraint Letters
10023 switch (Constraint[0]) {
10024 case 'l': // Low regs or general regs.
10025 if (Subtarget->isThumb())
10026 return RCPair(0U, &ARM::tGPRRegClass);
10027 return RCPair(0U, &ARM::GPRRegClass);
10028 case 'h': // High regs or no regs.
10029 if (Subtarget->isThumb())
10030 return RCPair(0U, &ARM::hGPRRegClass);
10033 return RCPair(0U, &ARM::GPRRegClass);
10035 if (VT == MVT::f32)
10036 return RCPair(0U, &ARM::SPRRegClass);
10037 if (VT.getSizeInBits() == 64)
10038 return RCPair(0U, &ARM::DPRRegClass);
10039 if (VT.getSizeInBits() == 128)
10040 return RCPair(0U, &ARM::QPRRegClass);
10043 if (VT == MVT::f32)
10044 return RCPair(0U, &ARM::SPR_8RegClass);
10045 if (VT.getSizeInBits() == 64)
10046 return RCPair(0U, &ARM::DPR_8RegClass);
10047 if (VT.getSizeInBits() == 128)
10048 return RCPair(0U, &ARM::QPR_8RegClass);
10051 if (VT == MVT::f32)
10052 return RCPair(0U, &ARM::SPRRegClass);
10056 if (StringRef("{cc}").equals_lower(Constraint))
10057 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
10059 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10062 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10063 /// vector. If it is invalid, don't add anything to Ops.
10064 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10065 std::string &Constraint,
10066 std::vector<SDValue>&Ops,
10067 SelectionDAG &DAG) const {
10068 SDValue Result(0, 0);
10070 // Currently only support length 1 constraints.
10071 if (Constraint.length() != 1) return;
10073 char ConstraintLetter = Constraint[0];
10074 switch (ConstraintLetter) {
10077 case 'I': case 'J': case 'K': case 'L':
10078 case 'M': case 'N': case 'O':
10079 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
10083 int64_t CVal64 = C->getSExtValue();
10084 int CVal = (int) CVal64;
10085 // None of these constraints allow values larger than 32 bits. Check
10086 // that the value fits in an int.
10087 if (CVal != CVal64)
10090 switch (ConstraintLetter) {
10092 // Constant suitable for movw, must be between 0 and
10094 if (Subtarget->hasV6T2Ops())
10095 if (CVal >= 0 && CVal <= 65535)
10099 if (Subtarget->isThumb1Only()) {
10100 // This must be a constant between 0 and 255, for ADD
10102 if (CVal >= 0 && CVal <= 255)
10104 } else if (Subtarget->isThumb2()) {
10105 // A constant that can be used as an immediate value in a
10106 // data-processing instruction.
10107 if (ARM_AM::getT2SOImmVal(CVal) != -1)
10110 // A constant that can be used as an immediate value in a
10111 // data-processing instruction.
10112 if (ARM_AM::getSOImmVal(CVal) != -1)
10118 if (Subtarget->isThumb()) { // FIXME thumb2
10119 // This must be a constant between -255 and -1, for negated ADD
10120 // immediates. This can be used in GCC with an "n" modifier that
10121 // prints the negated value, for use with SUB instructions. It is
10122 // not useful otherwise but is implemented for compatibility.
10123 if (CVal >= -255 && CVal <= -1)
10126 // This must be a constant between -4095 and 4095. It is not clear
10127 // what this constraint is intended for. Implemented for
10128 // compatibility with GCC.
10129 if (CVal >= -4095 && CVal <= 4095)
10135 if (Subtarget->isThumb1Only()) {
10136 // A 32-bit value where only one byte has a nonzero value. Exclude
10137 // zero to match GCC. This constraint is used by GCC internally for
10138 // constants that can be loaded with a move/shift combination.
10139 // It is not useful otherwise but is implemented for compatibility.
10140 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
10142 } else if (Subtarget->isThumb2()) {
10143 // A constant whose bitwise inverse can be used as an immediate
10144 // value in a data-processing instruction. This can be used in GCC
10145 // with a "B" modifier that prints the inverted value, for use with
10146 // BIC and MVN instructions. It is not useful otherwise but is
10147 // implemented for compatibility.
10148 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
10151 // A constant whose bitwise inverse can be used as an immediate
10152 // value in a data-processing instruction. This can be used in GCC
10153 // with a "B" modifier that prints the inverted value, for use with
10154 // BIC and MVN instructions. It is not useful otherwise but is
10155 // implemented for compatibility.
10156 if (ARM_AM::getSOImmVal(~CVal) != -1)
10162 if (Subtarget->isThumb1Only()) {
10163 // This must be a constant between -7 and 7,
10164 // for 3-operand ADD/SUB immediate instructions.
10165 if (CVal >= -7 && CVal < 7)
10167 } else if (Subtarget->isThumb2()) {
10168 // A constant whose negation can be used as an immediate value in a
10169 // data-processing instruction. This can be used in GCC with an "n"
10170 // modifier that prints the negated value, for use with SUB
10171 // instructions. It is not useful otherwise but is implemented for
10173 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
10176 // A constant whose negation can be used as an immediate value in a
10177 // data-processing instruction. This can be used in GCC with an "n"
10178 // modifier that prints the negated value, for use with SUB
10179 // instructions. It is not useful otherwise but is implemented for
10181 if (ARM_AM::getSOImmVal(-CVal) != -1)
10187 if (Subtarget->isThumb()) { // FIXME thumb2
10188 // This must be a multiple of 4 between 0 and 1020, for
10189 // ADD sp + immediate.
10190 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
10193 // A power of two or a constant between 0 and 32. This is used in
10194 // GCC for the shift amount on shifted register operands, but it is
10195 // useful in general for any shift amounts.
10196 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
10202 if (Subtarget->isThumb()) { // FIXME thumb2
10203 // This must be a constant between 0 and 31, for shift amounts.
10204 if (CVal >= 0 && CVal <= 31)
10210 if (Subtarget->isThumb()) { // FIXME thumb2
10211 // This must be a multiple of 4 between -508 and 508, for
10212 // ADD/SUB sp = sp + immediate.
10213 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
10218 Result = DAG.getTargetConstant(CVal, Op.getValueType());
10222 if (Result.getNode()) {
10223 Ops.push_back(Result);
10226 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10230 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
10231 // The ARM target isn't yet aware of offsets.
10235 bool ARM::isBitFieldInvertedMask(unsigned v) {
10236 if (v == 0xffffffff)
10238 // there can be 1's on either or both "outsides", all the "inside"
10239 // bits must be 0's
10240 unsigned int lsb = 0, msb = 31;
10241 while (v & (1 << msb)) --msb;
10242 while (v & (1 << lsb)) ++lsb;
10243 for (unsigned int i = lsb; i <= msb; ++i) {
10250 /// isFPImmLegal - Returns true if the target can instruction select the
10251 /// specified FP immediate natively. If false, the legalizer will
10252 /// materialize the FP immediate as a load from a constant pool.
10253 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
10254 if (!Subtarget->hasVFP3())
10256 if (VT == MVT::f32)
10257 return ARM_AM::getFP32Imm(Imm) != -1;
10258 if (VT == MVT::f64)
10259 return ARM_AM::getFP64Imm(Imm) != -1;
10263 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
10264 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
10265 /// specified in the intrinsic calls.
10266 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
10268 unsigned Intrinsic) const {
10269 switch (Intrinsic) {
10270 case Intrinsic::arm_neon_vld1:
10271 case Intrinsic::arm_neon_vld2:
10272 case Intrinsic::arm_neon_vld3:
10273 case Intrinsic::arm_neon_vld4:
10274 case Intrinsic::arm_neon_vld2lane:
10275 case Intrinsic::arm_neon_vld3lane:
10276 case Intrinsic::arm_neon_vld4lane: {
10277 Info.opc = ISD::INTRINSIC_W_CHAIN;
10278 // Conservatively set memVT to the entire set of vectors loaded.
10279 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
10280 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10281 Info.ptrVal = I.getArgOperand(0);
10283 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10284 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10285 Info.vol = false; // volatile loads with NEON intrinsics not supported
10286 Info.readMem = true;
10287 Info.writeMem = false;
10290 case Intrinsic::arm_neon_vst1:
10291 case Intrinsic::arm_neon_vst2:
10292 case Intrinsic::arm_neon_vst3:
10293 case Intrinsic::arm_neon_vst4:
10294 case Intrinsic::arm_neon_vst2lane:
10295 case Intrinsic::arm_neon_vst3lane:
10296 case Intrinsic::arm_neon_vst4lane: {
10297 Info.opc = ISD::INTRINSIC_VOID;
10298 // Conservatively set memVT to the entire set of vectors stored.
10299 unsigned NumElts = 0;
10300 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
10301 Type *ArgTy = I.getArgOperand(ArgI)->getType();
10302 if (!ArgTy->isVectorTy())
10304 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
10306 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10307 Info.ptrVal = I.getArgOperand(0);
10309 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10310 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10311 Info.vol = false; // volatile stores with NEON intrinsics not supported
10312 Info.readMem = false;
10313 Info.writeMem = true;
10316 case Intrinsic::arm_strexd: {
10317 Info.opc = ISD::INTRINSIC_W_CHAIN;
10318 Info.memVT = MVT::i64;
10319 Info.ptrVal = I.getArgOperand(2);
10323 Info.readMem = false;
10324 Info.writeMem = true;
10327 case Intrinsic::arm_ldrexd: {
10328 Info.opc = ISD::INTRINSIC_W_CHAIN;
10329 Info.memVT = MVT::i64;
10330 Info.ptrVal = I.getArgOperand(0);
10334 Info.readMem = true;
10335 Info.writeMem = false;
10346 ARMScalarTargetTransformImpl::getIntImmCost(const APInt &Imm, Type *Ty) const {
10347 assert(Ty->isIntegerTy());
10349 unsigned Bits = Ty->getPrimitiveSizeInBits();
10350 if (Bits == 0 || Bits > 32)
10353 int32_t SImmVal = Imm.getSExtValue();
10354 uint32_t ZImmVal = Imm.getZExtValue();
10355 if (!Subtarget->isThumb()) {
10356 if ((SImmVal >= 0 && SImmVal < 65536) ||
10357 (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
10358 (ARM_AM::getSOImmVal(~ZImmVal) != -1))
10360 return Subtarget->hasV6T2Ops() ? 2 : 3;
10361 } else if (Subtarget->isThumb2()) {
10362 if ((SImmVal >= 0 && SImmVal < 65536) ||
10363 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
10364 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
10366 return Subtarget->hasV6T2Ops() ? 2 : 3;
10367 } else /*Thumb1*/ {
10368 if (SImmVal >= 0 && SImmVal < 256)
10370 if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
10372 // Load from constantpool.