1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Instruction.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Type.h"
33 #include "llvm/CodeGen/CallingConvLower.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/MC/MCSectionMachO.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/ADT/VectorExtras.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
52 STATISTIC(NumTailCalls, "Number of tail calls");
54 // This option should go away when tail calls fully work.
56 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
57 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
61 EnableARMLongCalls("arm-long-calls", cl::Hidden,
62 cl::desc("Generate calls via indirect call instructions."),
66 ARMInterworking("arm-interworking", cl::Hidden,
67 cl::desc("Enable / disable ARM interworking (for debugging only)"),
71 EnableARMCodePlacement("arm-code-placement", cl::Hidden,
72 cl::desc("Enable code placement pass for ARM."),
75 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
76 CCValAssign::LocInfo &LocInfo,
77 ISD::ArgFlagsTy &ArgFlags,
79 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
80 CCValAssign::LocInfo &LocInfo,
81 ISD::ArgFlagsTy &ArgFlags,
83 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
84 CCValAssign::LocInfo &LocInfo,
85 ISD::ArgFlagsTy &ArgFlags,
87 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
88 CCValAssign::LocInfo &LocInfo,
89 ISD::ArgFlagsTy &ArgFlags,
92 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
93 EVT PromotedBitwiseVT) {
94 if (VT != PromotedLdStVT) {
95 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
96 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
97 PromotedLdStVT.getSimpleVT());
99 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
100 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
101 PromotedLdStVT.getSimpleVT());
104 EVT ElemTy = VT.getVectorElementType();
105 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
106 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
107 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
108 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
109 if (ElemTy != MVT::i32) {
110 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
111 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
112 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
113 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
116 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
117 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
118 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
119 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
120 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
121 if (VT.isInteger()) {
122 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
123 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
124 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
127 // Promote all bit-wise operations.
128 if (VT.isInteger() && VT != PromotedBitwiseVT) {
129 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
130 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
131 PromotedBitwiseVT.getSimpleVT());
132 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
133 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
134 PromotedBitwiseVT.getSimpleVT());
135 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
136 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
137 PromotedBitwiseVT.getSimpleVT());
140 // Neon does not support vector divide/remainder operations.
141 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
142 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
143 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
144 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
145 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
146 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
149 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
150 addRegisterClass(VT, ARM::DPRRegisterClass);
151 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
154 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
155 addRegisterClass(VT, ARM::QPRRegisterClass);
156 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
159 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
160 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
161 return new TargetLoweringObjectFileMachO();
163 return new ARMElfTargetObjectFile();
166 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
167 : TargetLowering(TM, createTLOF(TM)) {
168 Subtarget = &TM.getSubtarget<ARMSubtarget>();
170 if (Subtarget->isTargetDarwin()) {
171 // Uses VFP for Thumb libfuncs if available.
172 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
173 // Single-precision floating-point arithmetic.
174 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
175 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
176 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
177 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
179 // Double-precision floating-point arithmetic.
180 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
181 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
182 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
183 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
185 // Single-precision comparisons.
186 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
187 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
188 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
189 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
190 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
191 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
192 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
193 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
195 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
196 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
201 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
202 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
204 // Double-precision comparisons.
205 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
206 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
207 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
208 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
209 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
210 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
211 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
212 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
214 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
218 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
219 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
220 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
221 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
223 // Floating-point to integer conversions.
224 // i64 conversions are done via library routines even when generating VFP
225 // instructions, so use the same ones.
226 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
227 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
228 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
229 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
231 // Conversions between floating types.
232 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
233 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
235 // Integer to floating-point conversions.
236 // i64 conversions are done via library routines even when generating VFP
237 // instructions, so use the same ones.
238 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
239 // e.g., __floatunsidf vs. __floatunssidfvfp.
240 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
241 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
242 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
243 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
247 // These libcalls are not available in 32-bit.
248 setLibcallName(RTLIB::SHL_I128, 0);
249 setLibcallName(RTLIB::SRL_I128, 0);
250 setLibcallName(RTLIB::SRA_I128, 0);
252 // Libcalls should use the AAPCS base standard ABI, even if hard float
253 // is in effect, as per the ARM RTABI specification, section 4.1.2.
254 if (Subtarget->isAAPCS_ABI()) {
255 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
256 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
257 CallingConv::ARM_AAPCS);
261 if (Subtarget->isThumb1Only())
262 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
264 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
265 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
266 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
267 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
269 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
272 if (Subtarget->hasNEON()) {
273 addDRTypeForNEON(MVT::v2f32);
274 addDRTypeForNEON(MVT::v8i8);
275 addDRTypeForNEON(MVT::v4i16);
276 addDRTypeForNEON(MVT::v2i32);
277 addDRTypeForNEON(MVT::v1i64);
279 addQRTypeForNEON(MVT::v4f32);
280 addQRTypeForNEON(MVT::v2f64);
281 addQRTypeForNEON(MVT::v16i8);
282 addQRTypeForNEON(MVT::v8i16);
283 addQRTypeForNEON(MVT::v4i32);
284 addQRTypeForNEON(MVT::v2i64);
286 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
287 // neither Neon nor VFP support any arithmetic operations on it.
288 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
289 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
290 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
291 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
292 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
293 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
294 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
295 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
296 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
297 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
298 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
299 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
300 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
301 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
302 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
303 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
304 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
305 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
306 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
307 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
308 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
309 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
310 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
311 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
313 // Neon does not support some operations on v1i64 and v2i64 types.
314 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
315 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
316 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
317 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
319 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
320 setTargetDAGCombine(ISD::SHL);
321 setTargetDAGCombine(ISD::SRL);
322 setTargetDAGCombine(ISD::SRA);
323 setTargetDAGCombine(ISD::SIGN_EXTEND);
324 setTargetDAGCombine(ISD::ZERO_EXTEND);
325 setTargetDAGCombine(ISD::ANY_EXTEND);
326 setTargetDAGCombine(ISD::SELECT_CC);
329 computeRegisterProperties();
331 // ARM does not have f32 extending load.
332 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
334 // ARM does not have i1 sign extending load.
335 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
337 // ARM supports all 4 flavors of integer indexed load / store.
338 if (!Subtarget->isThumb1Only()) {
339 for (unsigned im = (unsigned)ISD::PRE_INC;
340 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
341 setIndexedLoadAction(im, MVT::i1, Legal);
342 setIndexedLoadAction(im, MVT::i8, Legal);
343 setIndexedLoadAction(im, MVT::i16, Legal);
344 setIndexedLoadAction(im, MVT::i32, Legal);
345 setIndexedStoreAction(im, MVT::i1, Legal);
346 setIndexedStoreAction(im, MVT::i8, Legal);
347 setIndexedStoreAction(im, MVT::i16, Legal);
348 setIndexedStoreAction(im, MVT::i32, Legal);
352 // i64 operation support.
353 if (Subtarget->isThumb1Only()) {
354 setOperationAction(ISD::MUL, MVT::i64, Expand);
355 setOperationAction(ISD::MULHU, MVT::i32, Expand);
356 setOperationAction(ISD::MULHS, MVT::i32, Expand);
357 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
358 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
360 setOperationAction(ISD::MUL, MVT::i64, Expand);
361 setOperationAction(ISD::MULHU, MVT::i32, Expand);
362 if (!Subtarget->hasV6Ops())
363 setOperationAction(ISD::MULHS, MVT::i32, Expand);
365 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
366 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
367 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
368 setOperationAction(ISD::SRL, MVT::i64, Custom);
369 setOperationAction(ISD::SRA, MVT::i64, Custom);
371 // ARM does not have ROTL.
372 setOperationAction(ISD::ROTL, MVT::i32, Expand);
373 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
374 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
375 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
376 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
378 // Only ARMv6 has BSWAP.
379 if (!Subtarget->hasV6Ops())
380 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
382 // These are expanded into libcalls.
383 if (!Subtarget->hasDivide()) {
384 // v7M has a hardware divider
385 setOperationAction(ISD::SDIV, MVT::i32, Expand);
386 setOperationAction(ISD::UDIV, MVT::i32, Expand);
388 setOperationAction(ISD::SREM, MVT::i32, Expand);
389 setOperationAction(ISD::UREM, MVT::i32, Expand);
390 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
391 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
393 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
394 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
395 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
396 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
397 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
399 setOperationAction(ISD::TRAP, MVT::Other, Legal);
401 // Use the default implementation.
402 setOperationAction(ISD::VASTART, MVT::Other, Custom);
403 setOperationAction(ISD::VAARG, MVT::Other, Expand);
404 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
405 setOperationAction(ISD::VAEND, MVT::Other, Expand);
406 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
407 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
408 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
409 // FIXME: Shouldn't need this, since no register is used, but the legalizer
410 // doesn't yet know how to not do that for SjLj.
411 setExceptionSelectorRegister(ARM::R0);
412 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
413 // Handle atomics directly for ARMv[67] (except for Thumb1), otherwise
414 // use the default expansion.
415 bool canHandleAtomics =
416 (Subtarget->hasV7Ops() ||
417 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only()));
418 if (canHandleAtomics) {
419 // membarrier needs custom lowering; the rest are legal and handled
421 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
423 // Set them all for expansion, which will force libcalls.
424 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
425 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
426 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
427 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
428 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
429 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
430 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
431 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
432 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
433 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
434 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
435 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
436 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
437 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
438 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
439 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
440 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
441 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
442 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
443 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
444 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
445 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
446 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
447 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
448 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
449 // Since the libcalls include locking, fold in the fences
450 setShouldFoldAtomicFences(true);
452 // 64-bit versions are always libcalls (for now)
453 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
454 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
455 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
456 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
457 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
458 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
459 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
460 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
462 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
463 if (!Subtarget->hasV6Ops()) {
464 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
465 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
469 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
470 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
471 // iff target supports vfp2.
472 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
474 // We want to custom lower some of our intrinsics.
475 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
477 setOperationAction(ISD::SETCC, MVT::i32, Expand);
478 setOperationAction(ISD::SETCC, MVT::f32, Expand);
479 setOperationAction(ISD::SETCC, MVT::f64, Expand);
480 setOperationAction(ISD::SELECT, MVT::i32, Expand);
481 setOperationAction(ISD::SELECT, MVT::f32, Expand);
482 setOperationAction(ISD::SELECT, MVT::f64, Expand);
483 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
484 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
485 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
487 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
488 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
489 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
490 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
491 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
493 // We don't support sin/cos/fmod/copysign/pow
494 setOperationAction(ISD::FSIN, MVT::f64, Expand);
495 setOperationAction(ISD::FSIN, MVT::f32, Expand);
496 setOperationAction(ISD::FCOS, MVT::f32, Expand);
497 setOperationAction(ISD::FCOS, MVT::f64, Expand);
498 setOperationAction(ISD::FREM, MVT::f64, Expand);
499 setOperationAction(ISD::FREM, MVT::f32, Expand);
500 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
501 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
502 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
504 setOperationAction(ISD::FPOW, MVT::f64, Expand);
505 setOperationAction(ISD::FPOW, MVT::f32, Expand);
507 // Various VFP goodness
508 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
509 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
510 if (Subtarget->hasVFP2()) {
511 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
512 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
513 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
514 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
516 // Special handling for half-precision FP.
517 if (!Subtarget->hasFP16()) {
518 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
519 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
523 // We have target-specific dag combine patterns for the following nodes:
524 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
525 setTargetDAGCombine(ISD::ADD);
526 setTargetDAGCombine(ISD::SUB);
527 setTargetDAGCombine(ISD::MUL);
529 setStackPointerRegisterToSaveRestore(ARM::SP);
531 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
532 setSchedulingPreference(Sched::RegPressure);
534 setSchedulingPreference(Sched::Hybrid);
536 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
538 if (EnableARMCodePlacement)
539 benefitFromCodePlacementOpt = true;
542 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
545 case ARMISD::Wrapper: return "ARMISD::Wrapper";
546 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
547 case ARMISD::CALL: return "ARMISD::CALL";
548 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
549 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
550 case ARMISD::tCALL: return "ARMISD::tCALL";
551 case ARMISD::BRCOND: return "ARMISD::BRCOND";
552 case ARMISD::BR_JT: return "ARMISD::BR_JT";
553 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
554 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
555 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
556 case ARMISD::CMP: return "ARMISD::CMP";
557 case ARMISD::CMPZ: return "ARMISD::CMPZ";
558 case ARMISD::CMPFP: return "ARMISD::CMPFP";
559 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
560 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
561 case ARMISD::CMOV: return "ARMISD::CMOV";
562 case ARMISD::CNEG: return "ARMISD::CNEG";
564 case ARMISD::RBIT: return "ARMISD::RBIT";
566 case ARMISD::FTOSI: return "ARMISD::FTOSI";
567 case ARMISD::FTOUI: return "ARMISD::FTOUI";
568 case ARMISD::SITOF: return "ARMISD::SITOF";
569 case ARMISD::UITOF: return "ARMISD::UITOF";
571 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
572 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
573 case ARMISD::RRX: return "ARMISD::RRX";
575 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
576 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
578 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
579 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
581 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
583 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
585 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
587 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
588 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
590 case ARMISD::VCEQ: return "ARMISD::VCEQ";
591 case ARMISD::VCGE: return "ARMISD::VCGE";
592 case ARMISD::VCGEU: return "ARMISD::VCGEU";
593 case ARMISD::VCGT: return "ARMISD::VCGT";
594 case ARMISD::VCGTU: return "ARMISD::VCGTU";
595 case ARMISD::VTST: return "ARMISD::VTST";
597 case ARMISD::VSHL: return "ARMISD::VSHL";
598 case ARMISD::VSHRs: return "ARMISD::VSHRs";
599 case ARMISD::VSHRu: return "ARMISD::VSHRu";
600 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
601 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
602 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
603 case ARMISD::VSHRN: return "ARMISD::VSHRN";
604 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
605 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
606 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
607 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
608 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
609 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
610 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
611 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
612 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
613 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
614 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
615 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
616 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
617 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
618 case ARMISD::VDUP: return "ARMISD::VDUP";
619 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
620 case ARMISD::VEXT: return "ARMISD::VEXT";
621 case ARMISD::VREV64: return "ARMISD::VREV64";
622 case ARMISD::VREV32: return "ARMISD::VREV32";
623 case ARMISD::VREV16: return "ARMISD::VREV16";
624 case ARMISD::VZIP: return "ARMISD::VZIP";
625 case ARMISD::VUZP: return "ARMISD::VUZP";
626 case ARMISD::VTRN: return "ARMISD::VTRN";
627 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
628 case ARMISD::FMAX: return "ARMISD::FMAX";
629 case ARMISD::FMIN: return "ARMISD::FMIN";
633 /// getRegClassFor - Return the register class that should be used for the
634 /// specified value type.
635 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
636 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
637 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
638 // load / store 4 to 8 consecutive D registers.
639 if (Subtarget->hasNEON()) {
640 if (VT == MVT::v4i64)
641 return ARM::QQPRRegisterClass;
642 else if (VT == MVT::v8i64)
643 return ARM::QQQQPRRegisterClass;
645 return TargetLowering::getRegClassFor(VT);
648 /// getFunctionAlignment - Return the Log2 alignment of this function.
649 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
650 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1;
653 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
654 unsigned NumVals = N->getNumValues();
656 return Sched::RegPressure;
658 for (unsigned i = 0; i != NumVals; ++i) {
659 EVT VT = N->getValueType(i);
660 if (VT.isFloatingPoint() || VT.isVector())
661 return Sched::Latency;
664 if (!N->isMachineOpcode())
665 return Sched::RegPressure;
667 // Load are scheduled for latency even if there instruction itinerary
669 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
670 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
672 return Sched::Latency;
674 const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData();
675 if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2)
676 return Sched::Latency;
677 return Sched::RegPressure;
680 //===----------------------------------------------------------------------===//
682 //===----------------------------------------------------------------------===//
684 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
685 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
687 default: llvm_unreachable("Unknown condition code!");
688 case ISD::SETNE: return ARMCC::NE;
689 case ISD::SETEQ: return ARMCC::EQ;
690 case ISD::SETGT: return ARMCC::GT;
691 case ISD::SETGE: return ARMCC::GE;
692 case ISD::SETLT: return ARMCC::LT;
693 case ISD::SETLE: return ARMCC::LE;
694 case ISD::SETUGT: return ARMCC::HI;
695 case ISD::SETUGE: return ARMCC::HS;
696 case ISD::SETULT: return ARMCC::LO;
697 case ISD::SETULE: return ARMCC::LS;
701 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
702 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
703 ARMCC::CondCodes &CondCode2) {
704 CondCode2 = ARMCC::AL;
706 default: llvm_unreachable("Unknown FP condition!");
708 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
710 case ISD::SETOGT: CondCode = ARMCC::GT; break;
712 case ISD::SETOGE: CondCode = ARMCC::GE; break;
713 case ISD::SETOLT: CondCode = ARMCC::MI; break;
714 case ISD::SETOLE: CondCode = ARMCC::LS; break;
715 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
716 case ISD::SETO: CondCode = ARMCC::VC; break;
717 case ISD::SETUO: CondCode = ARMCC::VS; break;
718 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
719 case ISD::SETUGT: CondCode = ARMCC::HI; break;
720 case ISD::SETUGE: CondCode = ARMCC::PL; break;
722 case ISD::SETULT: CondCode = ARMCC::LT; break;
724 case ISD::SETULE: CondCode = ARMCC::LE; break;
726 case ISD::SETUNE: CondCode = ARMCC::NE; break;
730 //===----------------------------------------------------------------------===//
731 // Calling Convention Implementation
732 //===----------------------------------------------------------------------===//
734 #include "ARMGenCallingConv.inc"
736 // APCS f64 is in register pairs, possibly split to stack
737 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
738 CCValAssign::LocInfo &LocInfo,
739 CCState &State, bool CanFail) {
740 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
742 // Try to get the first register.
743 if (unsigned Reg = State.AllocateReg(RegList, 4))
744 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
746 // For the 2nd half of a v2f64, do not fail.
750 // Put the whole thing on the stack.
751 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
752 State.AllocateStack(8, 4),
757 // Try to get the second register.
758 if (unsigned Reg = State.AllocateReg(RegList, 4))
759 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
761 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
762 State.AllocateStack(4, 4),
767 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
768 CCValAssign::LocInfo &LocInfo,
769 ISD::ArgFlagsTy &ArgFlags,
771 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
773 if (LocVT == MVT::v2f64 &&
774 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
776 return true; // we handled it
779 // AAPCS f64 is in aligned register pairs
780 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
781 CCValAssign::LocInfo &LocInfo,
782 CCState &State, bool CanFail) {
783 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
784 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
786 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
788 // For the 2nd half of a v2f64, do not just fail.
792 // Put the whole thing on the stack.
793 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
794 State.AllocateStack(8, 8),
800 for (i = 0; i < 2; ++i)
801 if (HiRegList[i] == Reg)
804 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
805 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
810 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
811 CCValAssign::LocInfo &LocInfo,
812 ISD::ArgFlagsTy &ArgFlags,
814 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
816 if (LocVT == MVT::v2f64 &&
817 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
819 return true; // we handled it
822 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
823 CCValAssign::LocInfo &LocInfo, CCState &State) {
824 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
825 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
827 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
829 return false; // we didn't handle it
832 for (i = 0; i < 2; ++i)
833 if (HiRegList[i] == Reg)
836 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
837 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
842 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
843 CCValAssign::LocInfo &LocInfo,
844 ISD::ArgFlagsTy &ArgFlags,
846 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
848 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
850 return true; // we handled it
853 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
854 CCValAssign::LocInfo &LocInfo,
855 ISD::ArgFlagsTy &ArgFlags,
857 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
861 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
862 /// given CallingConvention value.
863 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
865 bool isVarArg) const {
868 llvm_unreachable("Unsupported calling convention");
870 case CallingConv::Fast:
871 // Use target triple & subtarget features to do actual dispatch.
872 if (Subtarget->isAAPCS_ABI()) {
873 if (Subtarget->hasVFP2() &&
874 FloatABIType == FloatABI::Hard && !isVarArg)
875 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
877 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
879 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
880 case CallingConv::ARM_AAPCS_VFP:
881 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
882 case CallingConv::ARM_AAPCS:
883 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
884 case CallingConv::ARM_APCS:
885 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
889 /// LowerCallResult - Lower the result values of a call into the
890 /// appropriate copies out of appropriate physical registers.
892 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
893 CallingConv::ID CallConv, bool isVarArg,
894 const SmallVectorImpl<ISD::InputArg> &Ins,
895 DebugLoc dl, SelectionDAG &DAG,
896 SmallVectorImpl<SDValue> &InVals) const {
898 // Assign locations to each value returned by this call.
899 SmallVector<CCValAssign, 16> RVLocs;
900 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
901 RVLocs, *DAG.getContext());
902 CCInfo.AnalyzeCallResult(Ins,
903 CCAssignFnForNode(CallConv, /* Return*/ true,
906 // Copy all of the result registers out of their specified physreg.
907 for (unsigned i = 0; i != RVLocs.size(); ++i) {
908 CCValAssign VA = RVLocs[i];
911 if (VA.needsCustom()) {
912 // Handle f64 or half of a v2f64.
913 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
915 Chain = Lo.getValue(1);
916 InFlag = Lo.getValue(2);
917 VA = RVLocs[++i]; // skip ahead to next loc
918 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
920 Chain = Hi.getValue(1);
921 InFlag = Hi.getValue(2);
922 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
924 if (VA.getLocVT() == MVT::v2f64) {
925 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
926 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
927 DAG.getConstant(0, MVT::i32));
929 VA = RVLocs[++i]; // skip ahead to next loc
930 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
931 Chain = Lo.getValue(1);
932 InFlag = Lo.getValue(2);
933 VA = RVLocs[++i]; // skip ahead to next loc
934 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
935 Chain = Hi.getValue(1);
936 InFlag = Hi.getValue(2);
937 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
938 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
939 DAG.getConstant(1, MVT::i32));
942 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
944 Chain = Val.getValue(1);
945 InFlag = Val.getValue(2);
948 switch (VA.getLocInfo()) {
949 default: llvm_unreachable("Unknown loc info!");
950 case CCValAssign::Full: break;
951 case CCValAssign::BCvt:
952 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
956 InVals.push_back(Val);
962 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
963 /// by "Src" to address "Dst" of size "Size". Alignment information is
964 /// specified by the specific parameter attribute. The copy will be passed as
965 /// a byval function parameter.
966 /// Sometimes what we are copying is the end of a larger object, the part that
967 /// does not fit in registers.
969 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
970 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
972 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
973 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
974 /*isVolatile=*/false, /*AlwaysInline=*/false,
978 /// LowerMemOpCallTo - Store the argument to the stack.
980 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
981 SDValue StackPtr, SDValue Arg,
982 DebugLoc dl, SelectionDAG &DAG,
983 const CCValAssign &VA,
984 ISD::ArgFlagsTy Flags) const {
985 unsigned LocMemOffset = VA.getLocMemOffset();
986 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
987 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
988 if (Flags.isByVal()) {
989 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
991 return DAG.getStore(Chain, dl, Arg, PtrOff,
992 PseudoSourceValue::getStack(), LocMemOffset,
996 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
997 SDValue Chain, SDValue &Arg,
998 RegsToPassVector &RegsToPass,
999 CCValAssign &VA, CCValAssign &NextVA,
1001 SmallVector<SDValue, 8> &MemOpChains,
1002 ISD::ArgFlagsTy Flags) const {
1004 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1005 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1006 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1008 if (NextVA.isRegLoc())
1009 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1011 assert(NextVA.isMemLoc());
1012 if (StackPtr.getNode() == 0)
1013 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1015 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1021 /// LowerCall - Lowering a call into a callseq_start <-
1022 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1025 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1026 CallingConv::ID CallConv, bool isVarArg,
1028 const SmallVectorImpl<ISD::OutputArg> &Outs,
1029 const SmallVectorImpl<ISD::InputArg> &Ins,
1030 DebugLoc dl, SelectionDAG &DAG,
1031 SmallVectorImpl<SDValue> &InVals) const {
1032 MachineFunction &MF = DAG.getMachineFunction();
1033 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1034 bool IsSibCall = false;
1035 // Temporarily disable tail calls so things don't break.
1036 if (!EnableARMTailCalls)
1039 // Check if it's really possible to do a tail call.
1040 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1041 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1043 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1044 // detected sibcalls.
1051 // Analyze operands of the call, assigning locations to each operand.
1052 SmallVector<CCValAssign, 16> ArgLocs;
1053 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1055 CCInfo.AnalyzeCallOperands(Outs,
1056 CCAssignFnForNode(CallConv, /* Return*/ false,
1059 // Get a count of how many bytes are to be pushed on the stack.
1060 unsigned NumBytes = CCInfo.getNextStackOffset();
1062 // For tail calls, memory operands are available in our caller's stack.
1066 // Adjust the stack pointer for the new arguments...
1067 // These operations are automatically eliminated by the prolog/epilog pass
1069 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1071 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1073 RegsToPassVector RegsToPass;
1074 SmallVector<SDValue, 8> MemOpChains;
1076 // Walk the register/memloc assignments, inserting copies/loads. In the case
1077 // of tail call optimization, arguments are handled later.
1078 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1080 ++i, ++realArgIdx) {
1081 CCValAssign &VA = ArgLocs[i];
1082 SDValue Arg = Outs[realArgIdx].Val;
1083 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1085 // Promote the value if needed.
1086 switch (VA.getLocInfo()) {
1087 default: llvm_unreachable("Unknown loc info!");
1088 case CCValAssign::Full: break;
1089 case CCValAssign::SExt:
1090 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1092 case CCValAssign::ZExt:
1093 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1095 case CCValAssign::AExt:
1096 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1098 case CCValAssign::BCvt:
1099 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1103 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1104 if (VA.needsCustom()) {
1105 if (VA.getLocVT() == MVT::v2f64) {
1106 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1107 DAG.getConstant(0, MVT::i32));
1108 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1109 DAG.getConstant(1, MVT::i32));
1111 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1112 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1114 VA = ArgLocs[++i]; // skip ahead to next loc
1115 if (VA.isRegLoc()) {
1116 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1117 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1119 assert(VA.isMemLoc());
1121 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1122 dl, DAG, VA, Flags));
1125 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1126 StackPtr, MemOpChains, Flags);
1128 } else if (VA.isRegLoc()) {
1129 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1130 } else if (!IsSibCall) {
1131 assert(VA.isMemLoc());
1133 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1134 dl, DAG, VA, Flags));
1138 if (!MemOpChains.empty())
1139 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1140 &MemOpChains[0], MemOpChains.size());
1142 // Build a sequence of copy-to-reg nodes chained together with token chain
1143 // and flag operands which copy the outgoing args into the appropriate regs.
1145 // Tail call byval lowering might overwrite argument registers so in case of
1146 // tail call optimization the copies to registers are lowered later.
1148 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1149 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1150 RegsToPass[i].second, InFlag);
1151 InFlag = Chain.getValue(1);
1154 // For tail calls lower the arguments to the 'real' stack slot.
1156 // Force all the incoming stack arguments to be loaded from the stack
1157 // before any new outgoing arguments are stored to the stack, because the
1158 // outgoing stack slots may alias the incoming argument stack slots, and
1159 // the alias isn't otherwise explicit. This is slightly more conservative
1160 // than necessary, because it means that each store effectively depends
1161 // on every argument instead of just those arguments it would clobber.
1163 // Do not flag preceeding copytoreg stuff together with the following stuff.
1165 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1166 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1167 RegsToPass[i].second, InFlag);
1168 InFlag = Chain.getValue(1);
1173 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1174 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1175 // node so that legalize doesn't hack it.
1176 bool isDirect = false;
1177 bool isARMFunc = false;
1178 bool isLocalARMFunc = false;
1179 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1181 if (EnableARMLongCalls) {
1182 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1183 && "long-calls with non-static relocation model!");
1184 // Handle a global address or an external symbol. If it's not one of
1185 // those, the target's already in a register, so we don't need to do
1187 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1188 const GlobalValue *GV = G->getGlobal();
1189 // Create a constant pool entry for the callee address
1190 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1191 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1194 // Get the address of the callee into a register
1195 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1196 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1197 Callee = DAG.getLoad(getPointerTy(), dl,
1198 DAG.getEntryNode(), CPAddr,
1199 PseudoSourceValue::getConstantPool(), 0,
1201 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1202 const char *Sym = S->getSymbol();
1204 // Create a constant pool entry for the callee address
1205 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1206 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1207 Sym, ARMPCLabelIndex, 0);
1208 // Get the address of the callee into a register
1209 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1210 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1211 Callee = DAG.getLoad(getPointerTy(), dl,
1212 DAG.getEntryNode(), CPAddr,
1213 PseudoSourceValue::getConstantPool(), 0,
1216 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1217 const GlobalValue *GV = G->getGlobal();
1219 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1220 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1221 getTargetMachine().getRelocationModel() != Reloc::Static;
1222 isARMFunc = !Subtarget->isThumb() || isStub;
1223 // ARM call to a local ARM function is predicable.
1224 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1225 // tBX takes a register source operand.
1226 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1227 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1228 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1231 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1232 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1233 Callee = DAG.getLoad(getPointerTy(), dl,
1234 DAG.getEntryNode(), CPAddr,
1235 PseudoSourceValue::getConstantPool(), 0,
1237 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1238 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1239 getPointerTy(), Callee, PICLabel);
1241 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
1242 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1244 bool isStub = Subtarget->isTargetDarwin() &&
1245 getTargetMachine().getRelocationModel() != Reloc::Static;
1246 isARMFunc = !Subtarget->isThumb() || isStub;
1247 // tBX takes a register source operand.
1248 const char *Sym = S->getSymbol();
1249 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1250 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1251 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1252 Sym, ARMPCLabelIndex, 4);
1253 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1254 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1255 Callee = DAG.getLoad(getPointerTy(), dl,
1256 DAG.getEntryNode(), CPAddr,
1257 PseudoSourceValue::getConstantPool(), 0,
1259 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1260 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1261 getPointerTy(), Callee, PICLabel);
1263 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1266 // FIXME: handle tail calls differently.
1268 if (Subtarget->isThumb()) {
1269 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1270 CallOpc = ARMISD::CALL_NOLINK;
1272 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1274 CallOpc = (isDirect || Subtarget->hasV5TOps())
1275 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1276 : ARMISD::CALL_NOLINK;
1278 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1279 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1280 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1281 InFlag = Chain.getValue(1);
1284 std::vector<SDValue> Ops;
1285 Ops.push_back(Chain);
1286 Ops.push_back(Callee);
1288 // Add argument registers to the end of the list so that they are known live
1290 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1291 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1292 RegsToPass[i].second.getValueType()));
1294 if (InFlag.getNode())
1295 Ops.push_back(InFlag);
1297 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1299 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1301 // Returns a chain and a flag for retval copy to use.
1302 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1303 InFlag = Chain.getValue(1);
1305 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1306 DAG.getIntPtrConstant(0, true), InFlag);
1308 InFlag = Chain.getValue(1);
1310 // Handle result values, copying them out of physregs into vregs that we
1312 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1316 /// MatchingStackOffset - Return true if the given stack call argument is
1317 /// already available in the same position (relatively) of the caller's
1318 /// incoming argument stack.
1320 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1321 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1322 const ARMInstrInfo *TII) {
1323 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1325 if (Arg.getOpcode() == ISD::CopyFromReg) {
1326 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1327 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1329 MachineInstr *Def = MRI->getVRegDef(VR);
1332 if (!Flags.isByVal()) {
1333 if (!TII->isLoadFromStackSlot(Def, FI))
1336 // unsigned Opcode = Def->getOpcode();
1337 // if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
1338 // Def->getOperand(1).isFI()) {
1339 // FI = Def->getOperand(1).getIndex();
1340 // Bytes = Flags.getByValSize();
1344 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1345 if (Flags.isByVal())
1346 // ByVal argument is passed in as a pointer but it's now being
1347 // dereferenced. e.g.
1348 // define @foo(%struct.X* %A) {
1349 // tail call @bar(%struct.X* byval %A)
1352 SDValue Ptr = Ld->getBasePtr();
1353 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1356 FI = FINode->getIndex();
1360 assert(FI != INT_MAX);
1361 if (!MFI->isFixedObjectIndex(FI))
1363 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1366 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1367 /// for tail call optimization. Targets which want to do tail call
1368 /// optimization should implement this function.
1370 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1371 CallingConv::ID CalleeCC,
1373 bool isCalleeStructRet,
1374 bool isCallerStructRet,
1375 const SmallVectorImpl<ISD::OutputArg> &Outs,
1376 const SmallVectorImpl<ISD::InputArg> &Ins,
1377 SelectionDAG& DAG) const {
1378 const Function *CallerF = DAG.getMachineFunction().getFunction();
1379 CallingConv::ID CallerCC = CallerF->getCallingConv();
1380 bool CCMatch = CallerCC == CalleeCC;
1382 // Look for obvious safe cases to perform tail call optimization that do not
1383 // require ABI changes. This is what gcc calls sibcall.
1385 // Do not sibcall optimize vararg calls unless the call site is not passing
1387 if (isVarArg && !Outs.empty())
1390 // Also avoid sibcall optimization if either caller or callee uses struct
1391 // return semantics.
1392 if (isCalleeStructRet || isCallerStructRet)
1395 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1396 // emitEpilogue is not ready for them.
1397 if (Subtarget->isThumb1Only())
1400 // For the moment, we can only do this to functions defined in this
1401 // compilation, or to indirect calls. A Thumb B to an ARM function,
1402 // or vice versa, is not easily fixed up in the linker unlike BL.
1403 // (We could do this by loading the address of the callee into a register;
1404 // that is an extra instruction over the direct call and burns a register
1405 // as well, so is not likely to be a win.)
1406 if (isa<ExternalSymbolSDNode>(Callee))
1409 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1410 const GlobalValue *GV = G->getGlobal();
1411 if (GV->isDeclaration() || GV->isWeakForLinker())
1415 // If the calling conventions do not match, then we'd better make sure the
1416 // results are returned in the same way as what the caller expects.
1418 SmallVector<CCValAssign, 16> RVLocs1;
1419 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1420 RVLocs1, *DAG.getContext());
1421 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1423 SmallVector<CCValAssign, 16> RVLocs2;
1424 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1425 RVLocs2, *DAG.getContext());
1426 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1428 if (RVLocs1.size() != RVLocs2.size())
1430 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1431 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1433 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1435 if (RVLocs1[i].isRegLoc()) {
1436 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1439 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1445 // If the callee takes no arguments then go on to check the results of the
1447 if (!Outs.empty()) {
1448 // Check if stack adjustment is needed. For now, do not do this if any
1449 // argument is passed on the stack.
1450 SmallVector<CCValAssign, 16> ArgLocs;
1451 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1452 ArgLocs, *DAG.getContext());
1453 CCInfo.AnalyzeCallOperands(Outs,
1454 CCAssignFnForNode(CalleeCC, false, isVarArg));
1455 if (CCInfo.getNextStackOffset()) {
1456 MachineFunction &MF = DAG.getMachineFunction();
1458 // Check if the arguments are already laid out in the right way as
1459 // the caller's fixed stack objects.
1460 MachineFrameInfo *MFI = MF.getFrameInfo();
1461 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1462 const ARMInstrInfo *TII =
1463 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1464 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1466 ++i, ++realArgIdx) {
1467 CCValAssign &VA = ArgLocs[i];
1468 EVT RegVT = VA.getLocVT();
1469 SDValue Arg = Outs[realArgIdx].Val;
1470 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1471 if (VA.getLocInfo() == CCValAssign::Indirect)
1473 if (VA.needsCustom()) {
1474 // f64 and vector types are split into multiple registers or
1475 // register/stack-slot combinations. The types will not match
1476 // the registers; give up on memory f64 refs until we figure
1477 // out what to do about this.
1480 if (!ArgLocs[++i].isRegLoc())
1482 if (RegVT == MVT::v2f64) {
1483 if (!ArgLocs[++i].isRegLoc())
1485 if (!ArgLocs[++i].isRegLoc())
1488 } else if (!VA.isRegLoc()) {
1489 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1501 ARMTargetLowering::LowerReturn(SDValue Chain,
1502 CallingConv::ID CallConv, bool isVarArg,
1503 const SmallVectorImpl<ISD::OutputArg> &Outs,
1504 DebugLoc dl, SelectionDAG &DAG) const {
1506 // CCValAssign - represent the assignment of the return value to a location.
1507 SmallVector<CCValAssign, 16> RVLocs;
1509 // CCState - Info about the registers and stack slots.
1510 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1513 // Analyze outgoing return values.
1514 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1517 // If this is the first return lowered for this function, add
1518 // the regs to the liveout set for the function.
1519 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1520 for (unsigned i = 0; i != RVLocs.size(); ++i)
1521 if (RVLocs[i].isRegLoc())
1522 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1527 // Copy the result values into the output registers.
1528 for (unsigned i = 0, realRVLocIdx = 0;
1530 ++i, ++realRVLocIdx) {
1531 CCValAssign &VA = RVLocs[i];
1532 assert(VA.isRegLoc() && "Can only return in registers!");
1534 SDValue Arg = Outs[realRVLocIdx].Val;
1536 switch (VA.getLocInfo()) {
1537 default: llvm_unreachable("Unknown loc info!");
1538 case CCValAssign::Full: break;
1539 case CCValAssign::BCvt:
1540 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1544 if (VA.needsCustom()) {
1545 if (VA.getLocVT() == MVT::v2f64) {
1546 // Extract the first half and return it in two registers.
1547 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1548 DAG.getConstant(0, MVT::i32));
1549 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1550 DAG.getVTList(MVT::i32, MVT::i32), Half);
1552 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1553 Flag = Chain.getValue(1);
1554 VA = RVLocs[++i]; // skip ahead to next loc
1555 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1556 HalfGPRs.getValue(1), Flag);
1557 Flag = Chain.getValue(1);
1558 VA = RVLocs[++i]; // skip ahead to next loc
1560 // Extract the 2nd half and fall through to handle it as an f64 value.
1561 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1562 DAG.getConstant(1, MVT::i32));
1564 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1566 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1567 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1568 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1569 Flag = Chain.getValue(1);
1570 VA = RVLocs[++i]; // skip ahead to next loc
1571 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1574 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1576 // Guarantee that all emitted copies are
1577 // stuck together, avoiding something bad.
1578 Flag = Chain.getValue(1);
1583 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1585 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1590 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1591 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1592 // one of the above mentioned nodes. It has to be wrapped because otherwise
1593 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1594 // be used to form addressing mode. These wrapped nodes will be selected
1596 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1597 EVT PtrVT = Op.getValueType();
1598 // FIXME there is no actual debug info here
1599 DebugLoc dl = Op.getDebugLoc();
1600 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1602 if (CP->isMachineConstantPoolEntry())
1603 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1604 CP->getAlignment());
1606 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1607 CP->getAlignment());
1608 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1611 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1612 SelectionDAG &DAG) const {
1613 MachineFunction &MF = DAG.getMachineFunction();
1614 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1615 unsigned ARMPCLabelIndex = 0;
1616 DebugLoc DL = Op.getDebugLoc();
1617 EVT PtrVT = getPointerTy();
1618 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1619 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1621 if (RelocM == Reloc::Static) {
1622 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1624 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1625 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1626 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1627 ARMCP::CPBlockAddress,
1629 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1631 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1632 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1633 PseudoSourceValue::getConstantPool(), 0,
1635 if (RelocM == Reloc::Static)
1637 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1638 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1641 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1643 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1644 SelectionDAG &DAG) const {
1645 DebugLoc dl = GA->getDebugLoc();
1646 EVT PtrVT = getPointerTy();
1647 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1648 MachineFunction &MF = DAG.getMachineFunction();
1649 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1650 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1651 ARMConstantPoolValue *CPV =
1652 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1653 ARMCP::CPValue, PCAdj, "tlsgd", true);
1654 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1655 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1656 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1657 PseudoSourceValue::getConstantPool(), 0,
1659 SDValue Chain = Argument.getValue(1);
1661 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1662 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1664 // call __tls_get_addr.
1667 Entry.Node = Argument;
1668 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1669 Args.push_back(Entry);
1670 // FIXME: is there useful debug info available here?
1671 std::pair<SDValue, SDValue> CallResult =
1672 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1673 false, false, false, false,
1674 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1675 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1676 return CallResult.first;
1679 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1680 // "local exec" model.
1682 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1683 SelectionDAG &DAG) const {
1684 const GlobalValue *GV = GA->getGlobal();
1685 DebugLoc dl = GA->getDebugLoc();
1687 SDValue Chain = DAG.getEntryNode();
1688 EVT PtrVT = getPointerTy();
1689 // Get the Thread Pointer
1690 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1692 if (GV->isDeclaration()) {
1693 MachineFunction &MF = DAG.getMachineFunction();
1694 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1695 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1696 // Initial exec model.
1697 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1698 ARMConstantPoolValue *CPV =
1699 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1700 ARMCP::CPValue, PCAdj, "gottpoff", true);
1701 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1702 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1703 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1704 PseudoSourceValue::getConstantPool(), 0,
1706 Chain = Offset.getValue(1);
1708 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1709 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1711 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1712 PseudoSourceValue::getConstantPool(), 0,
1716 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1717 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1718 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1719 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1720 PseudoSourceValue::getConstantPool(), 0,
1724 // The address of the thread local variable is the add of the thread
1725 // pointer with the offset of the variable.
1726 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1730 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1731 // TODO: implement the "local dynamic" model
1732 assert(Subtarget->isTargetELF() &&
1733 "TLS not implemented for non-ELF targets");
1734 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1735 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1736 // otherwise use the "Local Exec" TLS Model
1737 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1738 return LowerToTLSGeneralDynamicModel(GA, DAG);
1740 return LowerToTLSExecModels(GA, DAG);
1743 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1744 SelectionDAG &DAG) const {
1745 EVT PtrVT = getPointerTy();
1746 DebugLoc dl = Op.getDebugLoc();
1747 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1748 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1749 if (RelocM == Reloc::PIC_) {
1750 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1751 ARMConstantPoolValue *CPV =
1752 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1753 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1754 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1755 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1757 PseudoSourceValue::getConstantPool(), 0,
1759 SDValue Chain = Result.getValue(1);
1760 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1761 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1763 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1764 PseudoSourceValue::getGOT(), 0,
1768 // If we have T2 ops, we can materialize the address directly via movt/movw
1769 // pair. This is always cheaper.
1770 if (Subtarget->useMovt()) {
1771 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1772 DAG.getTargetGlobalAddress(GV, PtrVT));
1774 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1775 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1776 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1777 PseudoSourceValue::getConstantPool(), 0,
1783 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1784 SelectionDAG &DAG) const {
1785 MachineFunction &MF = DAG.getMachineFunction();
1786 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1787 unsigned ARMPCLabelIndex = 0;
1788 EVT PtrVT = getPointerTy();
1789 DebugLoc dl = Op.getDebugLoc();
1790 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1791 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1793 if (RelocM == Reloc::Static)
1794 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1796 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1797 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1798 ARMConstantPoolValue *CPV =
1799 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1800 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1802 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1804 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1805 PseudoSourceValue::getConstantPool(), 0,
1807 SDValue Chain = Result.getValue(1);
1809 if (RelocM == Reloc::PIC_) {
1810 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1811 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1814 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1815 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1816 PseudoSourceValue::getGOT(), 0,
1822 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1823 SelectionDAG &DAG) const {
1824 assert(Subtarget->isTargetELF() &&
1825 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1826 MachineFunction &MF = DAG.getMachineFunction();
1827 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1828 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1829 EVT PtrVT = getPointerTy();
1830 DebugLoc dl = Op.getDebugLoc();
1831 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1832 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1833 "_GLOBAL_OFFSET_TABLE_",
1834 ARMPCLabelIndex, PCAdj);
1835 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1836 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1837 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1838 PseudoSourceValue::getConstantPool(), 0,
1840 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1841 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1845 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1846 DebugLoc dl = Op.getDebugLoc();
1847 SDValue Val = DAG.getConstant(0, MVT::i32);
1848 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1849 Op.getOperand(1), Val);
1853 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1854 DebugLoc dl = Op.getDebugLoc();
1855 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1856 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1860 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1861 const ARMSubtarget *Subtarget) const {
1862 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1863 DebugLoc dl = Op.getDebugLoc();
1865 default: return SDValue(); // Don't custom lower most intrinsics.
1866 case Intrinsic::arm_thread_pointer: {
1867 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1868 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1870 case Intrinsic::eh_sjlj_lsda: {
1871 MachineFunction &MF = DAG.getMachineFunction();
1872 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1873 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1874 EVT PtrVT = getPointerTy();
1875 DebugLoc dl = Op.getDebugLoc();
1876 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1878 unsigned PCAdj = (RelocM != Reloc::PIC_)
1879 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1880 ARMConstantPoolValue *CPV =
1881 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1882 ARMCP::CPLSDA, PCAdj);
1883 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1884 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1886 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1887 PseudoSourceValue::getConstantPool(), 0,
1889 SDValue Chain = Result.getValue(1);
1891 if (RelocM == Reloc::PIC_) {
1892 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1893 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1900 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1901 const ARMSubtarget *Subtarget) {
1902 DebugLoc dl = Op.getDebugLoc();
1903 SDValue Op5 = Op.getOperand(5);
1904 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1905 // v6 and v7 can both handle barriers directly, but need handled a bit
1906 // differently. Thumb1 and pre-v6 ARM mode use a libcall instead and should
1908 unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER;
1909 if (Subtarget->hasV7Ops())
1910 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0));
1911 else if (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())
1912 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0),
1913 DAG.getConstant(0, MVT::i32));
1914 assert(0 && "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
1918 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
1919 MachineFunction &MF = DAG.getMachineFunction();
1920 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
1922 // vastart just stores the address of the VarArgsFrameIndex slot into the
1923 // memory location argument.
1924 DebugLoc dl = Op.getDebugLoc();
1925 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1926 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1927 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1928 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
1933 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1934 SelectionDAG &DAG) const {
1935 SDNode *Node = Op.getNode();
1936 DebugLoc dl = Node->getDebugLoc();
1937 EVT VT = Node->getValueType(0);
1938 SDValue Chain = Op.getOperand(0);
1939 SDValue Size = Op.getOperand(1);
1940 SDValue Align = Op.getOperand(2);
1942 // Chain the dynamic stack allocation so that it doesn't modify the stack
1943 // pointer when other instructions are using the stack.
1944 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1946 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1947 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1948 if (AlignVal > StackAlign)
1949 // Do this now since selection pass cannot introduce new target
1950 // independent node.
1951 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1953 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1954 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1955 // do even more horrible hack later.
1956 MachineFunction &MF = DAG.getMachineFunction();
1957 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1958 if (AFI->isThumb1OnlyFunction()) {
1960 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1962 uint32_t Val = C->getZExtValue();
1963 if (Val <= 508 && ((Val & 3) == 0))
1967 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1970 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1971 SDValue Ops1[] = { Chain, Size, Align };
1972 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1973 Chain = Res.getValue(1);
1974 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1975 DAG.getIntPtrConstant(0, true), SDValue());
1976 SDValue Ops2[] = { Res, Chain };
1977 return DAG.getMergeValues(Ops2, 2, dl);
1981 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1982 SDValue &Root, SelectionDAG &DAG,
1983 DebugLoc dl) const {
1984 MachineFunction &MF = DAG.getMachineFunction();
1985 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1987 TargetRegisterClass *RC;
1988 if (AFI->isThumb1OnlyFunction())
1989 RC = ARM::tGPRRegisterClass;
1991 RC = ARM::GPRRegisterClass;
1993 // Transform the arguments stored in physical registers into virtual ones.
1994 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1995 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1998 if (NextVA.isMemLoc()) {
1999 MachineFrameInfo *MFI = MF.getFrameInfo();
2000 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true, false);
2002 // Create load node to retrieve arguments from the stack.
2003 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2004 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2005 PseudoSourceValue::getFixedStack(FI), 0,
2008 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2009 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2012 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2016 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2017 CallingConv::ID CallConv, bool isVarArg,
2018 const SmallVectorImpl<ISD::InputArg>
2020 DebugLoc dl, SelectionDAG &DAG,
2021 SmallVectorImpl<SDValue> &InVals)
2024 MachineFunction &MF = DAG.getMachineFunction();
2025 MachineFrameInfo *MFI = MF.getFrameInfo();
2027 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2029 // Assign locations to all of the incoming arguments.
2030 SmallVector<CCValAssign, 16> ArgLocs;
2031 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2033 CCInfo.AnalyzeFormalArguments(Ins,
2034 CCAssignFnForNode(CallConv, /* Return*/ false,
2037 SmallVector<SDValue, 16> ArgValues;
2039 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2040 CCValAssign &VA = ArgLocs[i];
2042 // Arguments stored in registers.
2043 if (VA.isRegLoc()) {
2044 EVT RegVT = VA.getLocVT();
2047 if (VA.needsCustom()) {
2048 // f64 and vector types are split up into multiple registers or
2049 // combinations of registers and stack slots.
2050 if (VA.getLocVT() == MVT::v2f64) {
2051 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2053 VA = ArgLocs[++i]; // skip ahead to next loc
2055 if (VA.isMemLoc()) {
2056 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(),
2058 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2059 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2060 PseudoSourceValue::getFixedStack(FI), 0,
2063 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2066 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2067 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2068 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2069 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2070 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2072 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2075 TargetRegisterClass *RC;
2077 if (RegVT == MVT::f32)
2078 RC = ARM::SPRRegisterClass;
2079 else if (RegVT == MVT::f64)
2080 RC = ARM::DPRRegisterClass;
2081 else if (RegVT == MVT::v2f64)
2082 RC = ARM::QPRRegisterClass;
2083 else if (RegVT == MVT::i32)
2084 RC = (AFI->isThumb1OnlyFunction() ?
2085 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2087 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2089 // Transform the arguments in physical registers into virtual ones.
2090 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2091 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2094 // If this is an 8 or 16-bit value, it is really passed promoted
2095 // to 32 bits. Insert an assert[sz]ext to capture this, then
2096 // truncate to the right size.
2097 switch (VA.getLocInfo()) {
2098 default: llvm_unreachable("Unknown loc info!");
2099 case CCValAssign::Full: break;
2100 case CCValAssign::BCvt:
2101 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2103 case CCValAssign::SExt:
2104 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2105 DAG.getValueType(VA.getValVT()));
2106 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2108 case CCValAssign::ZExt:
2109 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2110 DAG.getValueType(VA.getValVT()));
2111 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2115 InVals.push_back(ArgValue);
2117 } else { // VA.isRegLoc()
2120 assert(VA.isMemLoc());
2121 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2123 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2124 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2127 // Create load nodes to retrieve arguments from the stack.
2128 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2129 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2130 PseudoSourceValue::getFixedStack(FI), 0,
2137 static const unsigned GPRArgRegs[] = {
2138 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2141 unsigned NumGPRs = CCInfo.getFirstUnallocated
2142 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2144 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2145 unsigned VARegSize = (4 - NumGPRs) * 4;
2146 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2147 unsigned ArgOffset = CCInfo.getNextStackOffset();
2148 if (VARegSaveSize) {
2149 // If this function is vararg, store any remaining integer argument regs
2150 // to their spots on the stack so that they may be loaded by deferencing
2151 // the result of va_next.
2152 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2153 AFI->setVarArgsFrameIndex(
2154 MFI->CreateFixedObject(VARegSaveSize,
2155 ArgOffset + VARegSaveSize - VARegSize,
2157 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2160 SmallVector<SDValue, 4> MemOps;
2161 for (; NumGPRs < 4; ++NumGPRs) {
2162 TargetRegisterClass *RC;
2163 if (AFI->isThumb1OnlyFunction())
2164 RC = ARM::tGPRRegisterClass;
2166 RC = ARM::GPRRegisterClass;
2168 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2169 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2171 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2172 PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()),
2173 0, false, false, 0);
2174 MemOps.push_back(Store);
2175 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2176 DAG.getConstant(4, getPointerTy()));
2178 if (!MemOps.empty())
2179 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2180 &MemOps[0], MemOps.size());
2182 // This will point to the next argument passed via stack.
2183 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset,
2190 /// isFloatingPointZero - Return true if this is +0.0.
2191 static bool isFloatingPointZero(SDValue Op) {
2192 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2193 return CFP->getValueAPF().isPosZero();
2194 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2195 // Maybe this has already been legalized into the constant pool?
2196 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2197 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2198 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2199 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2200 return CFP->getValueAPF().isPosZero();
2206 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2207 /// the given operands.
2209 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2210 SDValue &ARMCC, SelectionDAG &DAG,
2211 DebugLoc dl) const {
2212 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2213 unsigned C = RHSC->getZExtValue();
2214 if (!isLegalICmpImmediate(C)) {
2215 // Constant does not fit, try adjusting it by one?
2220 if (isLegalICmpImmediate(C-1)) {
2221 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2222 RHS = DAG.getConstant(C-1, MVT::i32);
2227 if (C > 0 && isLegalICmpImmediate(C-1)) {
2228 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2229 RHS = DAG.getConstant(C-1, MVT::i32);
2234 if (isLegalICmpImmediate(C+1)) {
2235 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2236 RHS = DAG.getConstant(C+1, MVT::i32);
2241 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
2242 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2243 RHS = DAG.getConstant(C+1, MVT::i32);
2250 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2251 ARMISD::NodeType CompareType;
2254 CompareType = ARMISD::CMP;
2259 CompareType = ARMISD::CMPZ;
2262 ARMCC = DAG.getConstant(CondCode, MVT::i32);
2263 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2266 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2267 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2270 if (!isFloatingPointZero(RHS))
2271 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2273 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2274 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2277 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2278 EVT VT = Op.getValueType();
2279 SDValue LHS = Op.getOperand(0);
2280 SDValue RHS = Op.getOperand(1);
2281 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2282 SDValue TrueVal = Op.getOperand(2);
2283 SDValue FalseVal = Op.getOperand(3);
2284 DebugLoc dl = Op.getDebugLoc();
2286 if (LHS.getValueType() == MVT::i32) {
2288 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2289 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2290 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
2293 ARMCC::CondCodes CondCode, CondCode2;
2294 FPCCToARMCC(CC, CondCode, CondCode2);
2296 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
2297 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2298 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2299 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2301 if (CondCode2 != ARMCC::AL) {
2302 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
2303 // FIXME: Needs another CMP because flag can have but one use.
2304 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2305 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2306 Result, TrueVal, ARMCC2, CCR, Cmp2);
2311 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2312 SDValue Chain = Op.getOperand(0);
2313 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2314 SDValue LHS = Op.getOperand(2);
2315 SDValue RHS = Op.getOperand(3);
2316 SDValue Dest = Op.getOperand(4);
2317 DebugLoc dl = Op.getDebugLoc();
2319 if (LHS.getValueType() == MVT::i32) {
2321 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2322 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2323 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2324 Chain, Dest, ARMCC, CCR,Cmp);
2327 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2328 ARMCC::CondCodes CondCode, CondCode2;
2329 FPCCToARMCC(CC, CondCode, CondCode2);
2331 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2332 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
2333 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2334 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2335 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
2336 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2337 if (CondCode2 != ARMCC::AL) {
2338 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
2339 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
2340 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2345 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2346 SDValue Chain = Op.getOperand(0);
2347 SDValue Table = Op.getOperand(1);
2348 SDValue Index = Op.getOperand(2);
2349 DebugLoc dl = Op.getDebugLoc();
2351 EVT PTy = getPointerTy();
2352 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2353 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2354 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2355 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2356 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2357 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2358 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2359 if (Subtarget->isThumb2()) {
2360 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2361 // which does another jump to the destination. This also makes it easier
2362 // to translate it to TBB / TBH later.
2363 // FIXME: This might not work if the function is extremely large.
2364 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2365 Addr, Op.getOperand(2), JTI, UId);
2367 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2368 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2369 PseudoSourceValue::getJumpTable(), 0,
2371 Chain = Addr.getValue(1);
2372 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2373 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2375 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2376 PseudoSourceValue::getJumpTable(), 0, false, false, 0);
2377 Chain = Addr.getValue(1);
2378 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2382 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2383 DebugLoc dl = Op.getDebugLoc();
2386 switch (Op.getOpcode()) {
2388 assert(0 && "Invalid opcode!");
2389 case ISD::FP_TO_SINT:
2390 Opc = ARMISD::FTOSI;
2392 case ISD::FP_TO_UINT:
2393 Opc = ARMISD::FTOUI;
2396 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2397 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2400 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2401 EVT VT = Op.getValueType();
2402 DebugLoc dl = Op.getDebugLoc();
2405 switch (Op.getOpcode()) {
2407 assert(0 && "Invalid opcode!");
2408 case ISD::SINT_TO_FP:
2409 Opc = ARMISD::SITOF;
2411 case ISD::UINT_TO_FP:
2412 Opc = ARMISD::UITOF;
2416 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2417 return DAG.getNode(Opc, dl, VT, Op);
2420 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
2421 // Implement fcopysign with a fabs and a conditional fneg.
2422 SDValue Tmp0 = Op.getOperand(0);
2423 SDValue Tmp1 = Op.getOperand(1);
2424 DebugLoc dl = Op.getDebugLoc();
2425 EVT VT = Op.getValueType();
2426 EVT SrcVT = Tmp1.getValueType();
2427 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2428 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
2429 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
2430 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2431 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
2434 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2435 MachineFunction &MF = DAG.getMachineFunction();
2436 MachineFrameInfo *MFI = MF.getFrameInfo();
2437 MFI->setReturnAddressIsTaken(true);
2439 EVT VT = Op.getValueType();
2440 DebugLoc dl = Op.getDebugLoc();
2441 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2443 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2444 SDValue Offset = DAG.getConstant(4, MVT::i32);
2445 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2446 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2447 NULL, 0, false, false, 0);
2450 // Return LR, which contains the return address. Mark it an implicit live-in.
2451 unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass);
2452 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2455 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2456 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2457 MFI->setFrameAddressIsTaken(true);
2459 EVT VT = Op.getValueType();
2460 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2461 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2462 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2463 ? ARM::R7 : ARM::R11;
2464 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2466 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
2471 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2472 /// expand a bit convert where either the source or destination type is i64 to
2473 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2474 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2475 /// vectors), since the legalizer won't know what to do with that.
2476 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2477 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2478 DebugLoc dl = N->getDebugLoc();
2479 SDValue Op = N->getOperand(0);
2481 // This function is only supposed to be called for i64 types, either as the
2482 // source or destination of the bit convert.
2483 EVT SrcVT = Op.getValueType();
2484 EVT DstVT = N->getValueType(0);
2485 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2486 "ExpandBIT_CONVERT called for non-i64 type");
2488 // Turn i64->f64 into VMOVDRR.
2489 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2490 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2491 DAG.getConstant(0, MVT::i32));
2492 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2493 DAG.getConstant(1, MVT::i32));
2494 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2495 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2498 // Turn f64->i64 into VMOVRRD.
2499 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2500 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2501 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2502 // Merge the pieces into a single i64 value.
2503 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2509 /// getZeroVector - Returns a vector of specified type with all zero elements.
2511 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2512 assert(VT.isVector() && "Expected a vector type");
2514 // Zero vectors are used to represent vector negation and in those cases
2515 // will be implemented with the NEON VNEG instruction. However, VNEG does
2516 // not support i64 elements, so sometimes the zero vectors will need to be
2517 // explicitly constructed. For those cases, and potentially other uses in
2518 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
2519 // to their dest type. This ensures they get CSE'd.
2521 SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
2522 SmallVector<SDValue, 8> Ops;
2525 if (VT.getSizeInBits() == 64) {
2526 Ops.assign(8, Cst); TVT = MVT::v8i8;
2528 Ops.assign(16, Cst); TVT = MVT::v16i8;
2530 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2532 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2535 /// getOnesVector - Returns a vector of specified type with all bits set.
2537 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2538 assert(VT.isVector() && "Expected a vector type");
2540 // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their
2541 // dest type. This ensures they get CSE'd.
2543 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
2544 SmallVector<SDValue, 8> Ops;
2547 if (VT.getSizeInBits() == 64) {
2548 Ops.assign(8, Cst); TVT = MVT::v8i8;
2550 Ops.assign(16, Cst); TVT = MVT::v16i8;
2552 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2554 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2557 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2558 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2559 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2560 SelectionDAG &DAG) const {
2561 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2562 EVT VT = Op.getValueType();
2563 unsigned VTBits = VT.getSizeInBits();
2564 DebugLoc dl = Op.getDebugLoc();
2565 SDValue ShOpLo = Op.getOperand(0);
2566 SDValue ShOpHi = Op.getOperand(1);
2567 SDValue ShAmt = Op.getOperand(2);
2569 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2571 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2573 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2574 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2575 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2576 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2577 DAG.getConstant(VTBits, MVT::i32));
2578 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2579 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2580 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2582 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2583 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2585 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2586 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC,
2589 SDValue Ops[2] = { Lo, Hi };
2590 return DAG.getMergeValues(Ops, 2, dl);
2593 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2594 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2595 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2596 SelectionDAG &DAG) const {
2597 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2598 EVT VT = Op.getValueType();
2599 unsigned VTBits = VT.getSizeInBits();
2600 DebugLoc dl = Op.getDebugLoc();
2601 SDValue ShOpLo = Op.getOperand(0);
2602 SDValue ShOpHi = Op.getOperand(1);
2603 SDValue ShAmt = Op.getOperand(2);
2606 assert(Op.getOpcode() == ISD::SHL_PARTS);
2607 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2608 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2609 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2610 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2611 DAG.getConstant(VTBits, MVT::i32));
2612 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2613 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2615 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2616 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2617 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2619 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2620 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC,
2623 SDValue Ops[2] = { Lo, Hi };
2624 return DAG.getMergeValues(Ops, 2, dl);
2627 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2628 const ARMSubtarget *ST) {
2629 EVT VT = N->getValueType(0);
2630 DebugLoc dl = N->getDebugLoc();
2632 if (!ST->hasV6T2Ops())
2635 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2636 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2639 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2640 const ARMSubtarget *ST) {
2641 EVT VT = N->getValueType(0);
2642 DebugLoc dl = N->getDebugLoc();
2644 // Lower vector shifts on NEON to use VSHL.
2645 if (VT.isVector()) {
2646 assert(ST->hasNEON() && "unexpected vector shift");
2648 // Left shifts translate directly to the vshiftu intrinsic.
2649 if (N->getOpcode() == ISD::SHL)
2650 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2651 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2652 N->getOperand(0), N->getOperand(1));
2654 assert((N->getOpcode() == ISD::SRA ||
2655 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2657 // NEON uses the same intrinsics for both left and right shifts. For
2658 // right shifts, the shift amounts are negative, so negate the vector of
2660 EVT ShiftVT = N->getOperand(1).getValueType();
2661 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2662 getZeroVector(ShiftVT, DAG, dl),
2664 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2665 Intrinsic::arm_neon_vshifts :
2666 Intrinsic::arm_neon_vshiftu);
2667 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2668 DAG.getConstant(vshiftInt, MVT::i32),
2669 N->getOperand(0), NegatedCount);
2672 // We can get here for a node like i32 = ISD::SHL i32, i64
2676 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2677 "Unknown shift to lower!");
2679 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2680 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2681 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2684 // If we are in thumb mode, we don't have RRX.
2685 if (ST->isThumb1Only()) return SDValue();
2687 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2688 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2689 DAG.getConstant(0, MVT::i32));
2690 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2691 DAG.getConstant(1, MVT::i32));
2693 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2694 // captures the result into a carry flag.
2695 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2696 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2698 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2699 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2701 // Merge the pieces into a single i64 value.
2702 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2705 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2706 SDValue TmpOp0, TmpOp1;
2707 bool Invert = false;
2711 SDValue Op0 = Op.getOperand(0);
2712 SDValue Op1 = Op.getOperand(1);
2713 SDValue CC = Op.getOperand(2);
2714 EVT VT = Op.getValueType();
2715 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2716 DebugLoc dl = Op.getDebugLoc();
2718 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2719 switch (SetCCOpcode) {
2720 default: llvm_unreachable("Illegal FP comparison"); break;
2722 case ISD::SETNE: Invert = true; // Fallthrough
2724 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2726 case ISD::SETLT: Swap = true; // Fallthrough
2728 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2730 case ISD::SETLE: Swap = true; // Fallthrough
2732 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2733 case ISD::SETUGE: Swap = true; // Fallthrough
2734 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2735 case ISD::SETUGT: Swap = true; // Fallthrough
2736 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2737 case ISD::SETUEQ: Invert = true; // Fallthrough
2739 // Expand this to (OLT | OGT).
2743 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2744 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2746 case ISD::SETUO: Invert = true; // Fallthrough
2748 // Expand this to (OLT | OGE).
2752 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2753 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2757 // Integer comparisons.
2758 switch (SetCCOpcode) {
2759 default: llvm_unreachable("Illegal integer comparison"); break;
2760 case ISD::SETNE: Invert = true;
2761 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2762 case ISD::SETLT: Swap = true;
2763 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2764 case ISD::SETLE: Swap = true;
2765 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2766 case ISD::SETULT: Swap = true;
2767 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2768 case ISD::SETULE: Swap = true;
2769 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2772 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2773 if (Opc == ARMISD::VCEQ) {
2776 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2778 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2781 // Ignore bitconvert.
2782 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2783 AndOp = AndOp.getOperand(0);
2785 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2787 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2788 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2795 std::swap(Op0, Op1);
2797 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2800 Result = DAG.getNOT(dl, Result, VT);
2805 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
2806 /// valid vector constant for a NEON instruction with a "modified immediate"
2807 /// operand (e.g., VMOV). If so, return either the constant being
2808 /// splatted or the encoded value, depending on the DoEncode parameter. The
2809 /// format of the encoded value is: bit12=Op, bits11-8=Cmode,
2810 /// bits7-0=Immediate.
2811 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
2812 unsigned SplatBitSize, SelectionDAG &DAG,
2813 bool isVMOV, bool DoEncode) {
2814 unsigned Op, Cmode, Imm;
2817 // SplatBitSize is set to the smallest size that splats the vector, so a
2818 // zero vector will always have SplatBitSize == 8. However, NEON modified
2819 // immediate instructions others than VMOV do not support the 8-bit encoding
2820 // of a zero vector, and the default encoding of zero is supposed to be the
2826 switch (SplatBitSize) {
2828 // Any 1-byte value is OK. Op=0, Cmode=1110.
2829 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2836 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2838 if ((SplatBits & ~0xff) == 0) {
2839 // Value = 0x00nn: Op=x, Cmode=100x.
2844 if ((SplatBits & ~0xff00) == 0) {
2845 // Value = 0xnn00: Op=x, Cmode=101x.
2847 Imm = SplatBits >> 8;
2853 // NEON's 32-bit VMOV supports splat values where:
2854 // * only one byte is nonzero, or
2855 // * the least significant byte is 0xff and the second byte is nonzero, or
2856 // * the least significant 2 bytes are 0xff and the third is nonzero.
2858 if ((SplatBits & ~0xff) == 0) {
2859 // Value = 0x000000nn: Op=x, Cmode=000x.
2864 if ((SplatBits & ~0xff00) == 0) {
2865 // Value = 0x0000nn00: Op=x, Cmode=001x.
2867 Imm = SplatBits >> 8;
2870 if ((SplatBits & ~0xff0000) == 0) {
2871 // Value = 0x00nn0000: Op=x, Cmode=010x.
2873 Imm = SplatBits >> 16;
2876 if ((SplatBits & ~0xff000000) == 0) {
2877 // Value = 0xnn000000: Op=x, Cmode=011x.
2879 Imm = SplatBits >> 24;
2883 if ((SplatBits & ~0xffff) == 0 &&
2884 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
2885 // Value = 0x0000nnff: Op=x, Cmode=1100.
2887 Imm = SplatBits >> 8;
2892 if ((SplatBits & ~0xffffff) == 0 &&
2893 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
2894 // Value = 0x00nnffff: Op=x, Cmode=1101.
2896 Imm = SplatBits >> 16;
2897 SplatBits |= 0xffff;
2901 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2902 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2903 // VMOV.I32. A (very) minor optimization would be to replicate the value
2904 // and fall through here to test for a valid 64-bit splat. But, then the
2905 // caller would also need to check and handle the change in size.
2909 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2912 uint64_t BitMask = 0xff;
2914 unsigned ImmMask = 1;
2916 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2917 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
2920 } else if ((SplatBits & BitMask) != 0) {
2926 // Op=1, Cmode=1110.
2935 llvm_unreachable("unexpected size for isNEONModifiedImm");
2940 return DAG.getTargetConstant((Op << 12) | (Cmode << 8) | Imm, MVT::i32);
2941 return DAG.getTargetConstant(SplatBits, VT);
2945 /// getNEONModImm - If this is a valid vector constant for a NEON instruction
2946 /// with a "modified immediate" operand (e.g., VMOV) of the specified element
2947 /// size, return the encoded value for that immediate. The ByteSize field
2948 /// indicates the number of bytes of each element [1248].
2949 SDValue ARM::getNEONModImm(SDNode *N, unsigned ByteSize, bool isVMOV,
2950 SelectionDAG &DAG) {
2951 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2952 APInt SplatBits, SplatUndef;
2953 unsigned SplatBitSize;
2955 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2956 HasAnyUndefs, ByteSize * 8))
2959 if (SplatBitSize > ByteSize * 8)
2962 return isNEONModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2963 SplatBitSize, DAG, isVMOV, true);
2966 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
2967 bool &ReverseVEXT, unsigned &Imm) {
2968 unsigned NumElts = VT.getVectorNumElements();
2969 ReverseVEXT = false;
2972 // If this is a VEXT shuffle, the immediate value is the index of the first
2973 // element. The other shuffle indices must be the successive elements after
2975 unsigned ExpectedElt = Imm;
2976 for (unsigned i = 1; i < NumElts; ++i) {
2977 // Increment the expected index. If it wraps around, it may still be
2978 // a VEXT but the source vectors must be swapped.
2980 if (ExpectedElt == NumElts * 2) {
2985 if (ExpectedElt != static_cast<unsigned>(M[i]))
2989 // Adjust the index value if the source operands will be swapped.
2996 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2997 /// instruction with the specified blocksize. (The order of the elements
2998 /// within each block of the vector is reversed.)
2999 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3000 unsigned BlockSize) {
3001 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3002 "Only possible block sizes for VREV are: 16, 32, 64");
3004 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3008 unsigned NumElts = VT.getVectorNumElements();
3009 unsigned BlockElts = M[0] + 1;
3011 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3014 for (unsigned i = 0; i < NumElts; ++i) {
3015 if ((unsigned) M[i] !=
3016 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3023 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3024 unsigned &WhichResult) {
3025 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3029 unsigned NumElts = VT.getVectorNumElements();
3030 WhichResult = (M[0] == 0 ? 0 : 1);
3031 for (unsigned i = 0; i < NumElts; i += 2) {
3032 if ((unsigned) M[i] != i + WhichResult ||
3033 (unsigned) M[i+1] != i + NumElts + WhichResult)
3039 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3040 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3041 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3042 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3043 unsigned &WhichResult) {
3044 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3048 unsigned NumElts = VT.getVectorNumElements();
3049 WhichResult = (M[0] == 0 ? 0 : 1);
3050 for (unsigned i = 0; i < NumElts; i += 2) {
3051 if ((unsigned) M[i] != i + WhichResult ||
3052 (unsigned) M[i+1] != i + WhichResult)
3058 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3059 unsigned &WhichResult) {
3060 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3064 unsigned NumElts = VT.getVectorNumElements();
3065 WhichResult = (M[0] == 0 ? 0 : 1);
3066 for (unsigned i = 0; i != NumElts; ++i) {
3067 if ((unsigned) M[i] != 2 * i + WhichResult)
3071 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3072 if (VT.is64BitVector() && EltSz == 32)
3078 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3079 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3080 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3081 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3082 unsigned &WhichResult) {
3083 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3087 unsigned Half = VT.getVectorNumElements() / 2;
3088 WhichResult = (M[0] == 0 ? 0 : 1);
3089 for (unsigned j = 0; j != 2; ++j) {
3090 unsigned Idx = WhichResult;
3091 for (unsigned i = 0; i != Half; ++i) {
3092 if ((unsigned) M[i + j * Half] != Idx)
3098 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3099 if (VT.is64BitVector() && EltSz == 32)
3105 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3106 unsigned &WhichResult) {
3107 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3111 unsigned NumElts = VT.getVectorNumElements();
3112 WhichResult = (M[0] == 0 ? 0 : 1);
3113 unsigned Idx = WhichResult * NumElts / 2;
3114 for (unsigned i = 0; i != NumElts; i += 2) {
3115 if ((unsigned) M[i] != Idx ||
3116 (unsigned) M[i+1] != Idx + NumElts)
3121 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3122 if (VT.is64BitVector() && EltSz == 32)
3128 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3129 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3130 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3131 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3132 unsigned &WhichResult) {
3133 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3137 unsigned NumElts = VT.getVectorNumElements();
3138 WhichResult = (M[0] == 0 ? 0 : 1);
3139 unsigned Idx = WhichResult * NumElts / 2;
3140 for (unsigned i = 0; i != NumElts; i += 2) {
3141 if ((unsigned) M[i] != Idx ||
3142 (unsigned) M[i+1] != Idx)
3147 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3148 if (VT.is64BitVector() && EltSz == 32)
3155 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3156 // Canonicalize all-zeros and all-ones vectors.
3157 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
3158 if (ConstVal->isNullValue())
3159 return getZeroVector(VT, DAG, dl);
3160 if (ConstVal->isAllOnesValue())
3161 return getOnesVector(VT, DAG, dl);
3164 if (VT.is64BitVector()) {
3165 switch (Val.getValueType().getSizeInBits()) {
3166 case 8: CanonicalVT = MVT::v8i8; break;
3167 case 16: CanonicalVT = MVT::v4i16; break;
3168 case 32: CanonicalVT = MVT::v2i32; break;
3169 case 64: CanonicalVT = MVT::v1i64; break;
3170 default: llvm_unreachable("unexpected splat element type"); break;
3173 assert(VT.is128BitVector() && "unknown splat vector size");
3174 switch (Val.getValueType().getSizeInBits()) {
3175 case 8: CanonicalVT = MVT::v16i8; break;
3176 case 16: CanonicalVT = MVT::v8i16; break;
3177 case 32: CanonicalVT = MVT::v4i32; break;
3178 case 64: CanonicalVT = MVT::v2i64; break;
3179 default: llvm_unreachable("unexpected splat element type"); break;
3183 // Build a canonical splat for this value.
3184 SmallVector<SDValue, 8> Ops;
3185 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
3186 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
3188 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
3191 // If this is a case we can't handle, return null and let the default
3192 // expansion code take care of it.
3193 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3194 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3195 DebugLoc dl = Op.getDebugLoc();
3196 EVT VT = Op.getValueType();
3198 APInt SplatBits, SplatUndef;
3199 unsigned SplatBitSize;
3201 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3202 if (SplatBitSize <= 64) {
3203 // Check if an immediate VMOV works.
3204 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3205 SplatUndef.getZExtValue(),
3206 SplatBitSize, DAG, true, false);
3208 return BuildSplat(Val, VT, DAG, dl);
3212 // Scan through the operands to see if only one value is used.
3213 unsigned NumElts = VT.getVectorNumElements();
3214 bool isOnlyLowElement = true;
3215 bool usesOnlyOneValue = true;
3216 bool isConstant = true;
3218 for (unsigned i = 0; i < NumElts; ++i) {
3219 SDValue V = Op.getOperand(i);
3220 if (V.getOpcode() == ISD::UNDEF)
3223 isOnlyLowElement = false;
3224 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3227 if (!Value.getNode())
3229 else if (V != Value)
3230 usesOnlyOneValue = false;
3233 if (!Value.getNode())
3234 return DAG.getUNDEF(VT);
3236 if (isOnlyLowElement)
3237 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3239 // If all elements are constants, fall back to the default expansion, which
3240 // will generate a load from the constant pool.
3244 // Use VDUP for non-constant splats.
3245 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3246 if (usesOnlyOneValue && EltSize <= 32)
3247 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3249 // Vectors with 32- or 64-bit elements can be built by directly assigning
3250 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3251 // will be legalized.
3252 if (EltSize >= 32) {
3253 // Do the expansion with floating-point types, since that is what the VFP
3254 // registers are defined to use, and since i64 is not legal.
3255 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3256 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3257 SmallVector<SDValue, 8> Ops;
3258 for (unsigned i = 0; i < NumElts; ++i)
3259 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3260 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3261 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3267 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3268 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3269 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3270 /// are assumed to be legal.
3272 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3274 if (VT.getVectorNumElements() == 4 &&
3275 (VT.is128BitVector() || VT.is64BitVector())) {
3276 unsigned PFIndexes[4];
3277 for (unsigned i = 0; i != 4; ++i) {
3281 PFIndexes[i] = M[i];
3284 // Compute the index in the perfect shuffle table.
3285 unsigned PFTableIndex =
3286 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3287 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3288 unsigned Cost = (PFEntry >> 30);
3295 unsigned Imm, WhichResult;
3297 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3298 return (EltSize >= 32 ||
3299 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3300 isVREVMask(M, VT, 64) ||
3301 isVREVMask(M, VT, 32) ||
3302 isVREVMask(M, VT, 16) ||
3303 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3304 isVTRNMask(M, VT, WhichResult) ||
3305 isVUZPMask(M, VT, WhichResult) ||
3306 isVZIPMask(M, VT, WhichResult) ||
3307 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3308 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3309 isVZIP_v_undef_Mask(M, VT, WhichResult));
3312 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3313 /// the specified operations to build the shuffle.
3314 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3315 SDValue RHS, SelectionDAG &DAG,
3317 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3318 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3319 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3322 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3331 OP_VUZPL, // VUZP, left result
3332 OP_VUZPR, // VUZP, right result
3333 OP_VZIPL, // VZIP, left result
3334 OP_VZIPR, // VZIP, right result
3335 OP_VTRNL, // VTRN, left result
3336 OP_VTRNR // VTRN, right result
3339 if (OpNum == OP_COPY) {
3340 if (LHSID == (1*9+2)*9+3) return LHS;
3341 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3345 SDValue OpLHS, OpRHS;
3346 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3347 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3348 EVT VT = OpLHS.getValueType();
3351 default: llvm_unreachable("Unknown shuffle opcode!");
3353 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3358 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3359 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3363 return DAG.getNode(ARMISD::VEXT, dl, VT,
3365 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3368 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3369 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3372 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3373 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3376 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3377 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3381 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3382 SDValue V1 = Op.getOperand(0);
3383 SDValue V2 = Op.getOperand(1);
3384 DebugLoc dl = Op.getDebugLoc();
3385 EVT VT = Op.getValueType();
3386 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3387 SmallVector<int, 8> ShuffleMask;
3389 // Convert shuffles that are directly supported on NEON to target-specific
3390 // DAG nodes, instead of keeping them as shuffles and matching them again
3391 // during code selection. This is more efficient and avoids the possibility
3392 // of inconsistencies between legalization and selection.
3393 // FIXME: floating-point vectors should be canonicalized to integer vectors
3394 // of the same time so that they get CSEd properly.
3395 SVN->getMask(ShuffleMask);
3397 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3398 if (EltSize <= 32) {
3399 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3400 int Lane = SVN->getSplatIndex();
3401 // If this is undef splat, generate it via "just" vdup, if possible.
3402 if (Lane == -1) Lane = 0;
3404 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3405 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3407 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3408 DAG.getConstant(Lane, MVT::i32));
3413 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3416 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3417 DAG.getConstant(Imm, MVT::i32));
3420 if (isVREVMask(ShuffleMask, VT, 64))
3421 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3422 if (isVREVMask(ShuffleMask, VT, 32))
3423 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3424 if (isVREVMask(ShuffleMask, VT, 16))
3425 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3427 // Check for Neon shuffles that modify both input vectors in place.
3428 // If both results are used, i.e., if there are two shuffles with the same
3429 // source operands and with masks corresponding to both results of one of
3430 // these operations, DAG memoization will ensure that a single node is
3431 // used for both shuffles.
3432 unsigned WhichResult;
3433 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3434 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3435 V1, V2).getValue(WhichResult);
3436 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3437 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3438 V1, V2).getValue(WhichResult);
3439 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3440 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3441 V1, V2).getValue(WhichResult);
3443 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3444 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3445 V1, V1).getValue(WhichResult);
3446 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3447 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3448 V1, V1).getValue(WhichResult);
3449 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3450 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3451 V1, V1).getValue(WhichResult);
3454 // If the shuffle is not directly supported and it has 4 elements, use
3455 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3456 unsigned NumElts = VT.getVectorNumElements();
3458 unsigned PFIndexes[4];
3459 for (unsigned i = 0; i != 4; ++i) {
3460 if (ShuffleMask[i] < 0)
3463 PFIndexes[i] = ShuffleMask[i];
3466 // Compute the index in the perfect shuffle table.
3467 unsigned PFTableIndex =
3468 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3469 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3470 unsigned Cost = (PFEntry >> 30);
3473 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3476 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3477 if (EltSize >= 32) {
3478 // Do the expansion with floating-point types, since that is what the VFP
3479 // registers are defined to use, and since i64 is not legal.
3480 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3481 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3482 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3483 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3484 SmallVector<SDValue, 8> Ops;
3485 for (unsigned i = 0; i < NumElts; ++i) {
3486 if (ShuffleMask[i] < 0)
3487 Ops.push_back(DAG.getUNDEF(EltVT));
3489 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3490 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3491 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3494 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3495 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3501 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3502 EVT VT = Op.getValueType();
3503 DebugLoc dl = Op.getDebugLoc();
3504 SDValue Vec = Op.getOperand(0);
3505 SDValue Lane = Op.getOperand(1);
3506 assert(VT == MVT::i32 &&
3507 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3508 "unexpected type for custom-lowering vector extract");
3509 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3512 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3513 // The only time a CONCAT_VECTORS operation can have legal types is when
3514 // two 64-bit vectors are concatenated to a 128-bit vector.
3515 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3516 "unexpected CONCAT_VECTORS");
3517 DebugLoc dl = Op.getDebugLoc();
3518 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3519 SDValue Op0 = Op.getOperand(0);
3520 SDValue Op1 = Op.getOperand(1);
3521 if (Op0.getOpcode() != ISD::UNDEF)
3522 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3523 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3524 DAG.getIntPtrConstant(0));
3525 if (Op1.getOpcode() != ISD::UNDEF)
3526 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3527 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3528 DAG.getIntPtrConstant(1));
3529 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3532 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3533 switch (Op.getOpcode()) {
3534 default: llvm_unreachable("Don't know how to custom lower this!");
3535 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3536 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3537 case ISD::GlobalAddress:
3538 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3539 LowerGlobalAddressELF(Op, DAG);
3540 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3541 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3542 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3543 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3544 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3545 case ISD::VASTART: return LowerVASTART(Op, DAG);
3546 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3547 case ISD::SINT_TO_FP:
3548 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3549 case ISD::FP_TO_SINT:
3550 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3551 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3552 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3553 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3554 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3555 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3556 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3557 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3559 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3562 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3563 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3564 case ISD::SRL_PARTS:
3565 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3566 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3567 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3568 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3569 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3570 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3571 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3576 /// ReplaceNodeResults - Replace the results of node with an illegal result
3577 /// type with new values built out of custom code.
3578 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3579 SmallVectorImpl<SDValue>&Results,
3580 SelectionDAG &DAG) const {
3582 switch (N->getOpcode()) {
3584 llvm_unreachable("Don't know how to custom expand this!");
3586 case ISD::BIT_CONVERT:
3587 Res = ExpandBIT_CONVERT(N, DAG);
3591 Res = LowerShift(N, DAG, Subtarget);
3595 Results.push_back(Res);
3598 //===----------------------------------------------------------------------===//
3599 // ARM Scheduler Hooks
3600 //===----------------------------------------------------------------------===//
3603 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3604 MachineBasicBlock *BB,
3605 unsigned Size) const {
3606 unsigned dest = MI->getOperand(0).getReg();
3607 unsigned ptr = MI->getOperand(1).getReg();
3608 unsigned oldval = MI->getOperand(2).getReg();
3609 unsigned newval = MI->getOperand(3).getReg();
3610 unsigned scratch = BB->getParent()->getRegInfo()
3611 .createVirtualRegister(ARM::GPRRegisterClass);
3612 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3613 DebugLoc dl = MI->getDebugLoc();
3614 bool isThumb2 = Subtarget->isThumb2();
3616 unsigned ldrOpc, strOpc;
3618 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3620 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3621 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3624 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3625 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3628 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3629 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3633 MachineFunction *MF = BB->getParent();
3634 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3635 MachineFunction::iterator It = BB;
3636 ++It; // insert the new blocks after the current block
3638 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3639 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3640 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3641 MF->insert(It, loop1MBB);
3642 MF->insert(It, loop2MBB);
3643 MF->insert(It, exitMBB);
3644 exitMBB->transferSuccessors(BB);
3648 // fallthrough --> loop1MBB
3649 BB->addSuccessor(loop1MBB);
3652 // ldrex dest, [ptr]
3656 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3657 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3658 .addReg(dest).addReg(oldval));
3659 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3660 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3661 BB->addSuccessor(loop2MBB);
3662 BB->addSuccessor(exitMBB);
3665 // strex scratch, newval, [ptr]
3669 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3671 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3672 .addReg(scratch).addImm(0));
3673 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3674 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3675 BB->addSuccessor(loop1MBB);
3676 BB->addSuccessor(exitMBB);
3682 MF->DeleteMachineInstr(MI); // The instruction is gone now.
3688 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3689 unsigned Size, unsigned BinOpcode) const {
3690 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3691 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3693 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3694 MachineFunction *MF = BB->getParent();
3695 MachineFunction::iterator It = BB;
3698 unsigned dest = MI->getOperand(0).getReg();
3699 unsigned ptr = MI->getOperand(1).getReg();
3700 unsigned incr = MI->getOperand(2).getReg();
3701 DebugLoc dl = MI->getDebugLoc();
3703 bool isThumb2 = Subtarget->isThumb2();
3704 unsigned ldrOpc, strOpc;
3706 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3708 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3709 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3712 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3713 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3716 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3717 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3721 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3722 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3723 MF->insert(It, loopMBB);
3724 MF->insert(It, exitMBB);
3725 exitMBB->transferSuccessors(BB);
3727 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3728 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3729 unsigned scratch2 = (!BinOpcode) ? incr :
3730 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3734 // fallthrough --> loopMBB
3735 BB->addSuccessor(loopMBB);
3739 // <binop> scratch2, dest, incr
3740 // strex scratch, scratch2, ptr
3743 // fallthrough --> exitMBB
3745 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3747 // operand order needs to go the other way for NAND
3748 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3749 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3750 addReg(incr).addReg(dest)).addReg(0);
3752 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3753 addReg(dest).addReg(incr)).addReg(0);
3756 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3758 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3759 .addReg(scratch).addImm(0));
3760 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3761 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3763 BB->addSuccessor(loopMBB);
3764 BB->addSuccessor(exitMBB);
3770 MF->DeleteMachineInstr(MI); // The instruction is gone now.
3776 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3777 MachineBasicBlock *BB) const {
3778 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3779 DebugLoc dl = MI->getDebugLoc();
3780 bool isThumb2 = Subtarget->isThumb2();
3781 switch (MI->getOpcode()) {
3784 llvm_unreachable("Unexpected instr type to insert");
3786 case ARM::ATOMIC_LOAD_ADD_I8:
3787 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3788 case ARM::ATOMIC_LOAD_ADD_I16:
3789 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3790 case ARM::ATOMIC_LOAD_ADD_I32:
3791 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3793 case ARM::ATOMIC_LOAD_AND_I8:
3794 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3795 case ARM::ATOMIC_LOAD_AND_I16:
3796 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3797 case ARM::ATOMIC_LOAD_AND_I32:
3798 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3800 case ARM::ATOMIC_LOAD_OR_I8:
3801 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3802 case ARM::ATOMIC_LOAD_OR_I16:
3803 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3804 case ARM::ATOMIC_LOAD_OR_I32:
3805 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3807 case ARM::ATOMIC_LOAD_XOR_I8:
3808 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3809 case ARM::ATOMIC_LOAD_XOR_I16:
3810 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3811 case ARM::ATOMIC_LOAD_XOR_I32:
3812 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3814 case ARM::ATOMIC_LOAD_NAND_I8:
3815 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3816 case ARM::ATOMIC_LOAD_NAND_I16:
3817 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3818 case ARM::ATOMIC_LOAD_NAND_I32:
3819 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3821 case ARM::ATOMIC_LOAD_SUB_I8:
3822 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3823 case ARM::ATOMIC_LOAD_SUB_I16:
3824 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3825 case ARM::ATOMIC_LOAD_SUB_I32:
3826 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3828 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3829 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3830 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
3832 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3833 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3834 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
3836 case ARM::tMOVCCr_pseudo: {
3837 // To "insert" a SELECT_CC instruction, we actually have to insert the
3838 // diamond control-flow pattern. The incoming instruction knows the
3839 // destination vreg to set, the condition code register to branch on, the
3840 // true/false values to select between, and a branch opcode to use.
3841 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3842 MachineFunction::iterator It = BB;
3848 // cmpTY ccX, r1, r2
3850 // fallthrough --> copy0MBB
3851 MachineBasicBlock *thisMBB = BB;
3852 MachineFunction *F = BB->getParent();
3853 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3854 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3855 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
3856 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
3857 F->insert(It, copy0MBB);
3858 F->insert(It, sinkMBB);
3859 // Update machine-CFG edges by first adding all successors of the current
3860 // block to the new block which will contain the Phi node for the select.
3861 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
3862 E = BB->succ_end(); I != E; ++I)
3863 sinkMBB->addSuccessor(*I);
3864 // Next, remove all successors of the current block, and add the true
3865 // and fallthrough blocks as its successors.
3866 while (!BB->succ_empty())
3867 BB->removeSuccessor(BB->succ_begin());
3868 BB->addSuccessor(copy0MBB);
3869 BB->addSuccessor(sinkMBB);
3872 // %FalseValue = ...
3873 // # fallthrough to sinkMBB
3876 // Update machine-CFG edges
3877 BB->addSuccessor(sinkMBB);
3880 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3883 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
3884 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
3885 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3887 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3894 case ARM::t2SUBrSPi_:
3895 case ARM::t2SUBrSPi12_:
3896 case ARM::t2SUBrSPs_: {
3897 MachineFunction *MF = BB->getParent();
3898 unsigned DstReg = MI->getOperand(0).getReg();
3899 unsigned SrcReg = MI->getOperand(1).getReg();
3900 bool DstIsDead = MI->getOperand(0).isDead();
3901 bool SrcIsKill = MI->getOperand(1).isKill();
3903 if (SrcReg != ARM::SP) {
3904 // Copy the source to SP from virtual register.
3905 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
3906 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3907 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
3908 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
3909 .addReg(SrcReg, getKillRegState(SrcIsKill));
3913 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
3914 switch (MI->getOpcode()) {
3916 llvm_unreachable("Unexpected pseudo instruction!");
3922 OpOpc = ARM::tADDspr;
3925 OpOpc = ARM::tSUBspi;
3927 case ARM::t2SUBrSPi_:
3928 OpOpc = ARM::t2SUBrSPi;
3929 NeedPred = true; NeedCC = true;
3931 case ARM::t2SUBrSPi12_:
3932 OpOpc = ARM::t2SUBrSPi12;
3935 case ARM::t2SUBrSPs_:
3936 OpOpc = ARM::t2SUBrSPs;
3937 NeedPred = true; NeedCC = true; NeedOp3 = true;
3940 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
3941 if (OpOpc == ARM::tAND)
3942 AddDefaultT1CC(MIB);
3943 MIB.addReg(ARM::SP);
3944 MIB.addOperand(MI->getOperand(2));
3946 MIB.addOperand(MI->getOperand(3));
3948 AddDefaultPred(MIB);
3952 // Copy the result from SP to virtual register.
3953 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
3954 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3955 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
3956 BuildMI(BB, dl, TII->get(CopyOpc))
3957 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
3959 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3965 //===----------------------------------------------------------------------===//
3966 // ARM Optimization Hooks
3967 //===----------------------------------------------------------------------===//
3970 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
3971 TargetLowering::DAGCombinerInfo &DCI) {
3972 SelectionDAG &DAG = DCI.DAG;
3973 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3974 EVT VT = N->getValueType(0);
3975 unsigned Opc = N->getOpcode();
3976 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
3977 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
3978 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
3979 ISD::CondCode CC = ISD::SETCC_INVALID;
3982 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
3984 SDValue CCOp = Slct.getOperand(0);
3985 if (CCOp.getOpcode() == ISD::SETCC)
3986 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
3989 bool DoXform = false;
3991 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
3994 if (LHS.getOpcode() == ISD::Constant &&
3995 cast<ConstantSDNode>(LHS)->isNullValue()) {
3997 } else if (CC != ISD::SETCC_INVALID &&
3998 RHS.getOpcode() == ISD::Constant &&
3999 cast<ConstantSDNode>(RHS)->isNullValue()) {
4000 std::swap(LHS, RHS);
4001 SDValue Op0 = Slct.getOperand(0);
4002 EVT OpVT = isSlctCC ? Op0.getValueType() :
4003 Op0.getOperand(0).getValueType();
4004 bool isInt = OpVT.isInteger();
4005 CC = ISD::getSetCCInverse(CC, isInt);
4007 if (!TLI.isCondCodeLegal(CC, OpVT))
4008 return SDValue(); // Inverse operator isn't legal.
4015 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4017 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4018 Slct.getOperand(0), Slct.getOperand(1), CC);
4019 SDValue CCOp = Slct.getOperand(0);
4021 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4022 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4023 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4024 CCOp, OtherOp, Result);
4029 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4030 static SDValue PerformADDCombine(SDNode *N,
4031 TargetLowering::DAGCombinerInfo &DCI) {
4032 // added by evan in r37685 with no testcase.
4033 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4035 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4036 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4037 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4038 if (Result.getNode()) return Result;
4040 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4041 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4042 if (Result.getNode()) return Result;
4048 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4049 static SDValue PerformSUBCombine(SDNode *N,
4050 TargetLowering::DAGCombinerInfo &DCI) {
4051 // added by evan in r37685 with no testcase.
4052 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4054 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4055 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4056 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4057 if (Result.getNode()) return Result;
4063 static SDValue PerformMULCombine(SDNode *N,
4064 TargetLowering::DAGCombinerInfo &DCI,
4065 const ARMSubtarget *Subtarget) {
4066 SelectionDAG &DAG = DCI.DAG;
4068 if (Subtarget->isThumb1Only())
4071 if (DAG.getMachineFunction().
4072 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
4075 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4078 EVT VT = N->getValueType(0);
4082 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4086 uint64_t MulAmt = C->getZExtValue();
4087 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4088 ShiftAmt = ShiftAmt & (32 - 1);
4089 SDValue V = N->getOperand(0);
4090 DebugLoc DL = N->getDebugLoc();
4093 MulAmt >>= ShiftAmt;
4094 if (isPowerOf2_32(MulAmt - 1)) {
4095 // (mul x, 2^N + 1) => (add (shl x, N), x)
4096 Res = DAG.getNode(ISD::ADD, DL, VT,
4097 V, DAG.getNode(ISD::SHL, DL, VT,
4098 V, DAG.getConstant(Log2_32(MulAmt-1),
4100 } else if (isPowerOf2_32(MulAmt + 1)) {
4101 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4102 Res = DAG.getNode(ISD::SUB, DL, VT,
4103 DAG.getNode(ISD::SHL, DL, VT,
4104 V, DAG.getConstant(Log2_32(MulAmt+1),
4111 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4112 DAG.getConstant(ShiftAmt, MVT::i32));
4114 // Do not add new nodes to DAG combiner worklist.
4115 DCI.CombineTo(N, Res, false);
4119 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4120 /// ARMISD::VMOVRRD.
4121 static SDValue PerformVMOVRRDCombine(SDNode *N,
4122 TargetLowering::DAGCombinerInfo &DCI) {
4123 // fmrrd(fmdrr x, y) -> x,y
4124 SDValue InDouble = N->getOperand(0);
4125 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4126 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4130 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4131 /// operand of a vector shift operation, where all the elements of the
4132 /// build_vector must have the same constant integer value.
4133 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4134 // Ignore bit_converts.
4135 while (Op.getOpcode() == ISD::BIT_CONVERT)
4136 Op = Op.getOperand(0);
4137 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4138 APInt SplatBits, SplatUndef;
4139 unsigned SplatBitSize;
4141 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4142 HasAnyUndefs, ElementBits) ||
4143 SplatBitSize > ElementBits)
4145 Cnt = SplatBits.getSExtValue();
4149 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4150 /// operand of a vector shift left operation. That value must be in the range:
4151 /// 0 <= Value < ElementBits for a left shift; or
4152 /// 0 <= Value <= ElementBits for a long left shift.
4153 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4154 assert(VT.isVector() && "vector shift count is not a vector type");
4155 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4156 if (! getVShiftImm(Op, ElementBits, Cnt))
4158 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4161 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4162 /// operand of a vector shift right operation. For a shift opcode, the value
4163 /// is positive, but for an intrinsic the value count must be negative. The
4164 /// absolute value must be in the range:
4165 /// 1 <= |Value| <= ElementBits for a right shift; or
4166 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4167 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4169 assert(VT.isVector() && "vector shift count is not a vector type");
4170 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4171 if (! getVShiftImm(Op, ElementBits, Cnt))
4175 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4178 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4179 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4180 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4183 // Don't do anything for most intrinsics.
4186 // Vector shifts: check for immediate versions and lower them.
4187 // Note: This is done during DAG combining instead of DAG legalizing because
4188 // the build_vectors for 64-bit vector element shift counts are generally
4189 // not legal, and it is hard to see their values after they get legalized to
4190 // loads from a constant pool.
4191 case Intrinsic::arm_neon_vshifts:
4192 case Intrinsic::arm_neon_vshiftu:
4193 case Intrinsic::arm_neon_vshiftls:
4194 case Intrinsic::arm_neon_vshiftlu:
4195 case Intrinsic::arm_neon_vshiftn:
4196 case Intrinsic::arm_neon_vrshifts:
4197 case Intrinsic::arm_neon_vrshiftu:
4198 case Intrinsic::arm_neon_vrshiftn:
4199 case Intrinsic::arm_neon_vqshifts:
4200 case Intrinsic::arm_neon_vqshiftu:
4201 case Intrinsic::arm_neon_vqshiftsu:
4202 case Intrinsic::arm_neon_vqshiftns:
4203 case Intrinsic::arm_neon_vqshiftnu:
4204 case Intrinsic::arm_neon_vqshiftnsu:
4205 case Intrinsic::arm_neon_vqrshiftns:
4206 case Intrinsic::arm_neon_vqrshiftnu:
4207 case Intrinsic::arm_neon_vqrshiftnsu: {
4208 EVT VT = N->getOperand(1).getValueType();
4210 unsigned VShiftOpc = 0;
4213 case Intrinsic::arm_neon_vshifts:
4214 case Intrinsic::arm_neon_vshiftu:
4215 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4216 VShiftOpc = ARMISD::VSHL;
4219 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4220 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4221 ARMISD::VSHRs : ARMISD::VSHRu);
4226 case Intrinsic::arm_neon_vshiftls:
4227 case Intrinsic::arm_neon_vshiftlu:
4228 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4230 llvm_unreachable("invalid shift count for vshll intrinsic");
4232 case Intrinsic::arm_neon_vrshifts:
4233 case Intrinsic::arm_neon_vrshiftu:
4234 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4238 case Intrinsic::arm_neon_vqshifts:
4239 case Intrinsic::arm_neon_vqshiftu:
4240 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4244 case Intrinsic::arm_neon_vqshiftsu:
4245 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4247 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4249 case Intrinsic::arm_neon_vshiftn:
4250 case Intrinsic::arm_neon_vrshiftn:
4251 case Intrinsic::arm_neon_vqshiftns:
4252 case Intrinsic::arm_neon_vqshiftnu:
4253 case Intrinsic::arm_neon_vqshiftnsu:
4254 case Intrinsic::arm_neon_vqrshiftns:
4255 case Intrinsic::arm_neon_vqrshiftnu:
4256 case Intrinsic::arm_neon_vqrshiftnsu:
4257 // Narrowing shifts require an immediate right shift.
4258 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4260 llvm_unreachable("invalid shift count for narrowing vector shift "
4264 llvm_unreachable("unhandled vector shift");
4268 case Intrinsic::arm_neon_vshifts:
4269 case Intrinsic::arm_neon_vshiftu:
4270 // Opcode already set above.
4272 case Intrinsic::arm_neon_vshiftls:
4273 case Intrinsic::arm_neon_vshiftlu:
4274 if (Cnt == VT.getVectorElementType().getSizeInBits())
4275 VShiftOpc = ARMISD::VSHLLi;
4277 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4278 ARMISD::VSHLLs : ARMISD::VSHLLu);
4280 case Intrinsic::arm_neon_vshiftn:
4281 VShiftOpc = ARMISD::VSHRN; break;
4282 case Intrinsic::arm_neon_vrshifts:
4283 VShiftOpc = ARMISD::VRSHRs; break;
4284 case Intrinsic::arm_neon_vrshiftu:
4285 VShiftOpc = ARMISD::VRSHRu; break;
4286 case Intrinsic::arm_neon_vrshiftn:
4287 VShiftOpc = ARMISD::VRSHRN; break;
4288 case Intrinsic::arm_neon_vqshifts:
4289 VShiftOpc = ARMISD::VQSHLs; break;
4290 case Intrinsic::arm_neon_vqshiftu:
4291 VShiftOpc = ARMISD::VQSHLu; break;
4292 case Intrinsic::arm_neon_vqshiftsu:
4293 VShiftOpc = ARMISD::VQSHLsu; break;
4294 case Intrinsic::arm_neon_vqshiftns:
4295 VShiftOpc = ARMISD::VQSHRNs; break;
4296 case Intrinsic::arm_neon_vqshiftnu:
4297 VShiftOpc = ARMISD::VQSHRNu; break;
4298 case Intrinsic::arm_neon_vqshiftnsu:
4299 VShiftOpc = ARMISD::VQSHRNsu; break;
4300 case Intrinsic::arm_neon_vqrshiftns:
4301 VShiftOpc = ARMISD::VQRSHRNs; break;
4302 case Intrinsic::arm_neon_vqrshiftnu:
4303 VShiftOpc = ARMISD::VQRSHRNu; break;
4304 case Intrinsic::arm_neon_vqrshiftnsu:
4305 VShiftOpc = ARMISD::VQRSHRNsu; break;
4308 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4309 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4312 case Intrinsic::arm_neon_vshiftins: {
4313 EVT VT = N->getOperand(1).getValueType();
4315 unsigned VShiftOpc = 0;
4317 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4318 VShiftOpc = ARMISD::VSLI;
4319 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4320 VShiftOpc = ARMISD::VSRI;
4322 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4325 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4326 N->getOperand(1), N->getOperand(2),
4327 DAG.getConstant(Cnt, MVT::i32));
4330 case Intrinsic::arm_neon_vqrshifts:
4331 case Intrinsic::arm_neon_vqrshiftu:
4332 // No immediate versions of these to check for.
4339 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4340 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4341 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4342 /// vector element shift counts are generally not legal, and it is hard to see
4343 /// their values after they get legalized to loads from a constant pool.
4344 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4345 const ARMSubtarget *ST) {
4346 EVT VT = N->getValueType(0);
4348 // Nothing to be done for scalar shifts.
4349 if (! VT.isVector())
4352 assert(ST->hasNEON() && "unexpected vector shift");
4355 switch (N->getOpcode()) {
4356 default: llvm_unreachable("unexpected shift opcode");
4359 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4360 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4361 DAG.getConstant(Cnt, MVT::i32));
4366 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4367 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4368 ARMISD::VSHRs : ARMISD::VSHRu);
4369 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4370 DAG.getConstant(Cnt, MVT::i32));
4376 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4377 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4378 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4379 const ARMSubtarget *ST) {
4380 SDValue N0 = N->getOperand(0);
4382 // Check for sign- and zero-extensions of vector extract operations of 8-
4383 // and 16-bit vector elements. NEON supports these directly. They are
4384 // handled during DAG combining because type legalization will promote them
4385 // to 32-bit types and it is messy to recognize the operations after that.
4386 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4387 SDValue Vec = N0.getOperand(0);
4388 SDValue Lane = N0.getOperand(1);
4389 EVT VT = N->getValueType(0);
4390 EVT EltVT = N0.getValueType();
4391 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4393 if (VT == MVT::i32 &&
4394 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4395 TLI.isTypeLegal(Vec.getValueType())) {
4398 switch (N->getOpcode()) {
4399 default: llvm_unreachable("unexpected opcode");
4400 case ISD::SIGN_EXTEND:
4401 Opc = ARMISD::VGETLANEs;
4403 case ISD::ZERO_EXTEND:
4404 case ISD::ANY_EXTEND:
4405 Opc = ARMISD::VGETLANEu;
4408 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4415 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4416 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4417 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4418 const ARMSubtarget *ST) {
4419 // If the target supports NEON, try to use vmax/vmin instructions for f32
4420 // selects like "x < y ? x : y". Unless the FiniteOnlyFPMath option is set,
4421 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4422 // a NaN; only do the transformation when it matches that behavior.
4424 // For now only do this when using NEON for FP operations; if using VFP, it
4425 // is not obvious that the benefit outweighs the cost of switching to the
4427 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4428 N->getValueType(0) != MVT::f32)
4431 SDValue CondLHS = N->getOperand(0);
4432 SDValue CondRHS = N->getOperand(1);
4433 SDValue LHS = N->getOperand(2);
4434 SDValue RHS = N->getOperand(3);
4435 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4437 unsigned Opcode = 0;
4439 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4440 IsReversed = false; // x CC y ? x : y
4441 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4442 IsReversed = true ; // x CC y ? y : x
4456 // If LHS is NaN, an ordered comparison will be false and the result will
4457 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4458 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4459 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4460 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4462 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4463 // will return -0, so vmin can only be used for unsafe math or if one of
4464 // the operands is known to be nonzero.
4465 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4467 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4469 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4478 // If LHS is NaN, an ordered comparison will be false and the result will
4479 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4480 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4481 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4482 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4484 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4485 // will return +0, so vmax can only be used for unsafe math or if one of
4486 // the operands is known to be nonzero.
4487 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4489 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4491 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4497 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
4500 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
4501 DAGCombinerInfo &DCI) const {
4502 switch (N->getOpcode()) {
4504 case ISD::ADD: return PerformADDCombine(N, DCI);
4505 case ISD::SUB: return PerformSUBCombine(N, DCI);
4506 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
4507 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
4508 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
4511 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
4512 case ISD::SIGN_EXTEND:
4513 case ISD::ZERO_EXTEND:
4514 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
4515 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
4520 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
4521 if (!Subtarget->hasV6Ops())
4522 // Pre-v6 does not support unaligned mem access.
4525 // v6+ may or may not support unaligned mem access depending on the system
4527 // FIXME: This is pretty conservative. Should we provide cmdline option to
4528 // control the behaviour?
4529 if (!Subtarget->isTargetDarwin())
4532 switch (VT.getSimpleVT().SimpleTy) {
4539 // FIXME: VLD1 etc with standard alignment is legal.
4543 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
4548 switch (VT.getSimpleVT().SimpleTy) {
4549 default: return false;
4564 if ((V & (Scale - 1)) != 0)
4567 return V == (V & ((1LL << 5) - 1));
4570 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
4571 const ARMSubtarget *Subtarget) {
4578 switch (VT.getSimpleVT().SimpleTy) {
4579 default: return false;
4584 // + imm12 or - imm8
4586 return V == (V & ((1LL << 8) - 1));
4587 return V == (V & ((1LL << 12) - 1));
4590 // Same as ARM mode. FIXME: NEON?
4591 if (!Subtarget->hasVFP2())
4596 return V == (V & ((1LL << 8) - 1));
4600 /// isLegalAddressImmediate - Return true if the integer value can be used
4601 /// as the offset of the target addressing mode for load / store of the
4603 static bool isLegalAddressImmediate(int64_t V, EVT VT,
4604 const ARMSubtarget *Subtarget) {
4611 if (Subtarget->isThumb1Only())
4612 return isLegalT1AddressImmediate(V, VT);
4613 else if (Subtarget->isThumb2())
4614 return isLegalT2AddressImmediate(V, VT, Subtarget);
4619 switch (VT.getSimpleVT().SimpleTy) {
4620 default: return false;
4625 return V == (V & ((1LL << 12) - 1));
4628 return V == (V & ((1LL << 8) - 1));
4631 if (!Subtarget->hasVFP2()) // FIXME: NEON?
4636 return V == (V & ((1LL << 8) - 1));
4640 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
4642 int Scale = AM.Scale;
4646 switch (VT.getSimpleVT().SimpleTy) {
4647 default: return false;
4656 return Scale == 2 || Scale == 4 || Scale == 8;
4659 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4663 // Note, we allow "void" uses (basically, uses that aren't loads or
4664 // stores), because arm allows folding a scale into many arithmetic
4665 // operations. This should be made more precise and revisited later.
4667 // Allow r << imm, but the imm has to be a multiple of two.
4668 if (Scale & 1) return false;
4669 return isPowerOf2_32(Scale);
4673 /// isLegalAddressingMode - Return true if the addressing mode represented
4674 /// by AM is legal for this target, for a load/store of the specified type.
4675 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4676 const Type *Ty) const {
4677 EVT VT = getValueType(Ty, true);
4678 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
4681 // Can never fold addr of global into load/store.
4686 case 0: // no scale reg, must be "r+i" or "r", or "i".
4689 if (Subtarget->isThumb1Only())
4693 // ARM doesn't support any R+R*scale+imm addr modes.
4700 if (Subtarget->isThumb2())
4701 return isLegalT2ScaledAddressingMode(AM, VT);
4703 int Scale = AM.Scale;
4704 switch (VT.getSimpleVT().SimpleTy) {
4705 default: return false;
4709 if (Scale < 0) Scale = -Scale;
4713 return isPowerOf2_32(Scale & ~1);
4717 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4722 // Note, we allow "void" uses (basically, uses that aren't loads or
4723 // stores), because arm allows folding a scale into many arithmetic
4724 // operations. This should be made more precise and revisited later.
4726 // Allow r << imm, but the imm has to be a multiple of two.
4727 if (Scale & 1) return false;
4728 return isPowerOf2_32(Scale);
4735 /// isLegalICmpImmediate - Return true if the specified immediate is legal
4736 /// icmp immediate, that is the target has icmp instructions which can compare
4737 /// a register against the immediate without having to materialize the
4738 /// immediate into a register.
4739 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
4740 if (!Subtarget->isThumb())
4741 return ARM_AM::getSOImmVal(Imm) != -1;
4742 if (Subtarget->isThumb2())
4743 return ARM_AM::getT2SOImmVal(Imm) != -1;
4744 return Imm >= 0 && Imm <= 255;
4747 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
4748 bool isSEXTLoad, SDValue &Base,
4749 SDValue &Offset, bool &isInc,
4750 SelectionDAG &DAG) {
4751 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4754 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
4756 Base = Ptr->getOperand(0);
4757 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4758 int RHSC = (int)RHS->getZExtValue();
4759 if (RHSC < 0 && RHSC > -256) {
4760 assert(Ptr->getOpcode() == ISD::ADD);
4762 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4766 isInc = (Ptr->getOpcode() == ISD::ADD);
4767 Offset = Ptr->getOperand(1);
4769 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
4771 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4772 int RHSC = (int)RHS->getZExtValue();
4773 if (RHSC < 0 && RHSC > -0x1000) {
4774 assert(Ptr->getOpcode() == ISD::ADD);
4776 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4777 Base = Ptr->getOperand(0);
4782 if (Ptr->getOpcode() == ISD::ADD) {
4784 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
4785 if (ShOpcVal != ARM_AM::no_shift) {
4786 Base = Ptr->getOperand(1);
4787 Offset = Ptr->getOperand(0);
4789 Base = Ptr->getOperand(0);
4790 Offset = Ptr->getOperand(1);
4795 isInc = (Ptr->getOpcode() == ISD::ADD);
4796 Base = Ptr->getOperand(0);
4797 Offset = Ptr->getOperand(1);
4801 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
4805 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
4806 bool isSEXTLoad, SDValue &Base,
4807 SDValue &Offset, bool &isInc,
4808 SelectionDAG &DAG) {
4809 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4812 Base = Ptr->getOperand(0);
4813 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4814 int RHSC = (int)RHS->getZExtValue();
4815 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
4816 assert(Ptr->getOpcode() == ISD::ADD);
4818 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4820 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
4821 isInc = Ptr->getOpcode() == ISD::ADD;
4822 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
4830 /// getPreIndexedAddressParts - returns true by value, base pointer and
4831 /// offset pointer and addressing mode by reference if the node's address
4832 /// can be legally represented as pre-indexed load / store address.
4834 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
4836 ISD::MemIndexedMode &AM,
4837 SelectionDAG &DAG) const {
4838 if (Subtarget->isThumb1Only())
4843 bool isSEXTLoad = false;
4844 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4845 Ptr = LD->getBasePtr();
4846 VT = LD->getMemoryVT();
4847 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4848 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4849 Ptr = ST->getBasePtr();
4850 VT = ST->getMemoryVT();
4855 bool isLegal = false;
4856 if (Subtarget->isThumb2())
4857 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4858 Offset, isInc, DAG);
4860 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4861 Offset, isInc, DAG);
4865 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
4869 /// getPostIndexedAddressParts - returns true by value, base pointer and
4870 /// offset pointer and addressing mode by reference if this node can be
4871 /// combined with a load / store to form a post-indexed load / store.
4872 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
4875 ISD::MemIndexedMode &AM,
4876 SelectionDAG &DAG) const {
4877 if (Subtarget->isThumb1Only())
4882 bool isSEXTLoad = false;
4883 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4884 VT = LD->getMemoryVT();
4885 Ptr = LD->getBasePtr();
4886 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4887 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4888 VT = ST->getMemoryVT();
4889 Ptr = ST->getBasePtr();
4894 bool isLegal = false;
4895 if (Subtarget->isThumb2())
4896 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4899 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4905 // Swap base ptr and offset to catch more post-index load / store when
4906 // it's legal. In Thumb2 mode, offset must be an immediate.
4907 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
4908 !Subtarget->isThumb2())
4909 std::swap(Base, Offset);
4911 // Post-indexed load / store update the base pointer.
4916 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
4920 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
4924 const SelectionDAG &DAG,
4925 unsigned Depth) const {
4926 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4927 switch (Op.getOpcode()) {
4929 case ARMISD::CMOV: {
4930 // Bits are known zero/one if known on the LHS and RHS.
4931 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
4932 if (KnownZero == 0 && KnownOne == 0) return;
4934 APInt KnownZeroRHS, KnownOneRHS;
4935 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
4936 KnownZeroRHS, KnownOneRHS, Depth+1);
4937 KnownZero &= KnownZeroRHS;
4938 KnownOne &= KnownOneRHS;
4944 //===----------------------------------------------------------------------===//
4945 // ARM Inline Assembly Support
4946 //===----------------------------------------------------------------------===//
4948 /// getConstraintType - Given a constraint letter, return the type of
4949 /// constraint it is for this target.
4950 ARMTargetLowering::ConstraintType
4951 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
4952 if (Constraint.size() == 1) {
4953 switch (Constraint[0]) {
4955 case 'l': return C_RegisterClass;
4956 case 'w': return C_RegisterClass;
4959 return TargetLowering::getConstraintType(Constraint);
4962 std::pair<unsigned, const TargetRegisterClass*>
4963 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4965 if (Constraint.size() == 1) {
4966 // GCC ARM Constraint Letters
4967 switch (Constraint[0]) {
4969 if (Subtarget->isThumb())
4970 return std::make_pair(0U, ARM::tGPRRegisterClass);
4972 return std::make_pair(0U, ARM::GPRRegisterClass);
4974 return std::make_pair(0U, ARM::GPRRegisterClass);
4977 return std::make_pair(0U, ARM::SPRRegisterClass);
4978 if (VT.getSizeInBits() == 64)
4979 return std::make_pair(0U, ARM::DPRRegisterClass);
4980 if (VT.getSizeInBits() == 128)
4981 return std::make_pair(0U, ARM::QPRRegisterClass);
4985 if (StringRef("{cc}").equals_lower(Constraint))
4986 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
4988 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4991 std::vector<unsigned> ARMTargetLowering::
4992 getRegClassForInlineAsmConstraint(const std::string &Constraint,
4994 if (Constraint.size() != 1)
4995 return std::vector<unsigned>();
4997 switch (Constraint[0]) { // GCC ARM Constraint Letters
5000 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5001 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5004 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5005 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5006 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5007 ARM::R12, ARM::LR, 0);
5010 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5011 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5012 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5013 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5014 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5015 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5016 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5017 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5018 if (VT.getSizeInBits() == 64)
5019 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5020 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5021 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5022 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5023 if (VT.getSizeInBits() == 128)
5024 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5025 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5029 return std::vector<unsigned>();
5032 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5033 /// vector. If it is invalid, don't add anything to Ops.
5034 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5036 std::vector<SDValue>&Ops,
5037 SelectionDAG &DAG) const {
5038 SDValue Result(0, 0);
5040 switch (Constraint) {
5042 case 'I': case 'J': case 'K': case 'L':
5043 case 'M': case 'N': case 'O':
5044 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5048 int64_t CVal64 = C->getSExtValue();
5049 int CVal = (int) CVal64;
5050 // None of these constraints allow values larger than 32 bits. Check
5051 // that the value fits in an int.
5055 switch (Constraint) {
5057 if (Subtarget->isThumb1Only()) {
5058 // This must be a constant between 0 and 255, for ADD
5060 if (CVal >= 0 && CVal <= 255)
5062 } else if (Subtarget->isThumb2()) {
5063 // A constant that can be used as an immediate value in a
5064 // data-processing instruction.
5065 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5068 // A constant that can be used as an immediate value in a
5069 // data-processing instruction.
5070 if (ARM_AM::getSOImmVal(CVal) != -1)
5076 if (Subtarget->isThumb()) { // FIXME thumb2
5077 // This must be a constant between -255 and -1, for negated ADD
5078 // immediates. This can be used in GCC with an "n" modifier that
5079 // prints the negated value, for use with SUB instructions. It is
5080 // not useful otherwise but is implemented for compatibility.
5081 if (CVal >= -255 && CVal <= -1)
5084 // This must be a constant between -4095 and 4095. It is not clear
5085 // what this constraint is intended for. Implemented for
5086 // compatibility with GCC.
5087 if (CVal >= -4095 && CVal <= 4095)
5093 if (Subtarget->isThumb1Only()) {
5094 // A 32-bit value where only one byte has a nonzero value. Exclude
5095 // zero to match GCC. This constraint is used by GCC internally for
5096 // constants that can be loaded with a move/shift combination.
5097 // It is not useful otherwise but is implemented for compatibility.
5098 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5100 } else if (Subtarget->isThumb2()) {
5101 // A constant whose bitwise inverse can be used as an immediate
5102 // value in a data-processing instruction. This can be used in GCC
5103 // with a "B" modifier that prints the inverted value, for use with
5104 // BIC and MVN instructions. It is not useful otherwise but is
5105 // implemented for compatibility.
5106 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5109 // A constant whose bitwise inverse can be used as an immediate
5110 // value in a data-processing instruction. This can be used in GCC
5111 // with a "B" modifier that prints the inverted value, for use with
5112 // BIC and MVN instructions. It is not useful otherwise but is
5113 // implemented for compatibility.
5114 if (ARM_AM::getSOImmVal(~CVal) != -1)
5120 if (Subtarget->isThumb1Only()) {
5121 // This must be a constant between -7 and 7,
5122 // for 3-operand ADD/SUB immediate instructions.
5123 if (CVal >= -7 && CVal < 7)
5125 } else if (Subtarget->isThumb2()) {
5126 // A constant whose negation can be used as an immediate value in a
5127 // data-processing instruction. This can be used in GCC with an "n"
5128 // modifier that prints the negated value, for use with SUB
5129 // instructions. It is not useful otherwise but is implemented for
5131 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5134 // A constant whose negation can be used as an immediate value in a
5135 // data-processing instruction. This can be used in GCC with an "n"
5136 // modifier that prints the negated value, for use with SUB
5137 // instructions. It is not useful otherwise but is implemented for
5139 if (ARM_AM::getSOImmVal(-CVal) != -1)
5145 if (Subtarget->isThumb()) { // FIXME thumb2
5146 // This must be a multiple of 4 between 0 and 1020, for
5147 // ADD sp + immediate.
5148 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5151 // A power of two or a constant between 0 and 32. This is used in
5152 // GCC for the shift amount on shifted register operands, but it is
5153 // useful in general for any shift amounts.
5154 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5160 if (Subtarget->isThumb()) { // FIXME thumb2
5161 // This must be a constant between 0 and 31, for shift amounts.
5162 if (CVal >= 0 && CVal <= 31)
5168 if (Subtarget->isThumb()) { // FIXME thumb2
5169 // This must be a multiple of 4 between -508 and 508, for
5170 // ADD/SUB sp = sp + immediate.
5171 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5176 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5180 if (Result.getNode()) {
5181 Ops.push_back(Result);
5184 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5188 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5189 // The ARM target isn't yet aware of offsets.
5193 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5194 APInt Imm = FPImm.bitcastToAPInt();
5195 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5196 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5197 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5199 // We can handle 4 bits of mantissa.
5200 // mantissa = (16+UInt(e:f:g:h))/16.
5201 if (Mantissa & 0x7ffff)
5204 if ((Mantissa & 0xf) != Mantissa)
5207 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5208 if (Exp < -3 || Exp > 4)
5210 Exp = ((Exp+3) & 0x7) ^ 4;
5212 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5215 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5216 APInt Imm = FPImm.bitcastToAPInt();
5217 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5218 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5219 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5221 // We can handle 4 bits of mantissa.
5222 // mantissa = (16+UInt(e:f:g:h))/16.
5223 if (Mantissa & 0xffffffffffffLL)
5226 if ((Mantissa & 0xf) != Mantissa)
5229 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5230 if (Exp < -3 || Exp > 4)
5232 Exp = ((Exp+3) & 0x7) ^ 4;
5234 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5237 /// isFPImmLegal - Returns true if the target can instruction select the
5238 /// specified FP immediate natively. If false, the legalizer will
5239 /// materialize the FP immediate as a load from a constant pool.
5240 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5241 if (!Subtarget->hasVFP3())
5244 return ARM::getVFPf32Imm(Imm) != -1;
5246 return ARM::getVFPf64Imm(Imm) != -1;