1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Instruction.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Type.h"
33 #include "llvm/CodeGen/CallingConvLower.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/MC/MCSectionMachO.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/ADT/VectorExtras.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
52 STATISTIC(NumTailCalls, "Number of tail calls");
54 // This option should go away when tail calls fully work.
56 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
57 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
61 EnableARMLongCalls("arm-long-calls", cl::Hidden,
62 cl::desc("Generate calls via indirect call instructions"),
66 ARMInterworking("arm-interworking", cl::Hidden,
67 cl::desc("Enable / disable ARM interworking (for debugging only)"),
71 EnableARMCodePlacement("arm-code-placement", cl::Hidden,
72 cl::desc("Enable code placement pass for ARM"),
75 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
76 CCValAssign::LocInfo &LocInfo,
77 ISD::ArgFlagsTy &ArgFlags,
79 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
80 CCValAssign::LocInfo &LocInfo,
81 ISD::ArgFlagsTy &ArgFlags,
83 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
84 CCValAssign::LocInfo &LocInfo,
85 ISD::ArgFlagsTy &ArgFlags,
87 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
88 CCValAssign::LocInfo &LocInfo,
89 ISD::ArgFlagsTy &ArgFlags,
92 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
93 EVT PromotedBitwiseVT) {
94 if (VT != PromotedLdStVT) {
95 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
96 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
97 PromotedLdStVT.getSimpleVT());
99 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
100 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
101 PromotedLdStVT.getSimpleVT());
104 EVT ElemTy = VT.getVectorElementType();
105 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
106 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
107 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
108 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
109 if (ElemTy != MVT::i32) {
110 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
111 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
112 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
113 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
116 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
117 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
118 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
119 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
120 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
121 if (VT.isInteger()) {
122 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
123 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
124 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
127 // Promote all bit-wise operations.
128 if (VT.isInteger() && VT != PromotedBitwiseVT) {
129 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
130 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
131 PromotedBitwiseVT.getSimpleVT());
132 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
133 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
134 PromotedBitwiseVT.getSimpleVT());
135 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
136 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
137 PromotedBitwiseVT.getSimpleVT());
140 // Neon does not support vector divide/remainder operations.
141 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
142 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
143 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
144 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
145 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
146 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
149 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
150 addRegisterClass(VT, ARM::DPRRegisterClass);
151 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
154 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
155 addRegisterClass(VT, ARM::QPRRegisterClass);
156 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
159 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
160 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
161 return new TargetLoweringObjectFileMachO();
163 return new ARMElfTargetObjectFile();
166 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
167 : TargetLowering(TM, createTLOF(TM)) {
168 Subtarget = &TM.getSubtarget<ARMSubtarget>();
170 if (Subtarget->isTargetDarwin()) {
171 // Uses VFP for Thumb libfuncs if available.
172 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
173 // Single-precision floating-point arithmetic.
174 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
175 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
176 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
177 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
179 // Double-precision floating-point arithmetic.
180 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
181 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
182 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
183 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
185 // Single-precision comparisons.
186 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
187 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
188 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
189 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
190 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
191 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
192 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
193 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
195 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
196 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
201 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
202 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
204 // Double-precision comparisons.
205 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
206 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
207 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
208 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
209 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
210 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
211 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
212 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
214 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
218 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
219 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
220 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
221 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
223 // Floating-point to integer conversions.
224 // i64 conversions are done via library routines even when generating VFP
225 // instructions, so use the same ones.
226 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
227 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
228 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
229 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
231 // Conversions between floating types.
232 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
233 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
235 // Integer to floating-point conversions.
236 // i64 conversions are done via library routines even when generating VFP
237 // instructions, so use the same ones.
238 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
239 // e.g., __floatunsidf vs. __floatunssidfvfp.
240 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
241 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
242 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
243 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
247 // These libcalls are not available in 32-bit.
248 setLibcallName(RTLIB::SHL_I128, 0);
249 setLibcallName(RTLIB::SRL_I128, 0);
250 setLibcallName(RTLIB::SRA_I128, 0);
252 // Libcalls should use the AAPCS base standard ABI, even if hard float
253 // is in effect, as per the ARM RTABI specification, section 4.1.2.
254 if (Subtarget->isAAPCS_ABI()) {
255 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
256 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
257 CallingConv::ARM_AAPCS);
261 if (Subtarget->isThumb1Only())
262 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
264 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
265 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
266 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
267 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
269 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
272 if (Subtarget->hasNEON()) {
273 addDRTypeForNEON(MVT::v2f32);
274 addDRTypeForNEON(MVT::v8i8);
275 addDRTypeForNEON(MVT::v4i16);
276 addDRTypeForNEON(MVT::v2i32);
277 addDRTypeForNEON(MVT::v1i64);
279 addQRTypeForNEON(MVT::v4f32);
280 addQRTypeForNEON(MVT::v2f64);
281 addQRTypeForNEON(MVT::v16i8);
282 addQRTypeForNEON(MVT::v8i16);
283 addQRTypeForNEON(MVT::v4i32);
284 addQRTypeForNEON(MVT::v2i64);
286 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
287 // neither Neon nor VFP support any arithmetic operations on it.
288 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
289 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
290 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
291 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
292 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
293 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
294 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
295 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
296 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
297 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
298 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
299 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
300 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
301 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
302 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
303 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
304 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
305 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
306 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
307 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
308 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
309 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
310 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
311 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
313 // Neon does not support some operations on v1i64 and v2i64 types.
314 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
315 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
316 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
317 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
319 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
320 setTargetDAGCombine(ISD::SHL);
321 setTargetDAGCombine(ISD::SRL);
322 setTargetDAGCombine(ISD::SRA);
323 setTargetDAGCombine(ISD::SIGN_EXTEND);
324 setTargetDAGCombine(ISD::ZERO_EXTEND);
325 setTargetDAGCombine(ISD::ANY_EXTEND);
326 setTargetDAGCombine(ISD::SELECT_CC);
329 computeRegisterProperties();
331 // ARM does not have f32 extending load.
332 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
334 // ARM does not have i1 sign extending load.
335 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
337 // ARM supports all 4 flavors of integer indexed load / store.
338 if (!Subtarget->isThumb1Only()) {
339 for (unsigned im = (unsigned)ISD::PRE_INC;
340 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
341 setIndexedLoadAction(im, MVT::i1, Legal);
342 setIndexedLoadAction(im, MVT::i8, Legal);
343 setIndexedLoadAction(im, MVT::i16, Legal);
344 setIndexedLoadAction(im, MVT::i32, Legal);
345 setIndexedStoreAction(im, MVT::i1, Legal);
346 setIndexedStoreAction(im, MVT::i8, Legal);
347 setIndexedStoreAction(im, MVT::i16, Legal);
348 setIndexedStoreAction(im, MVT::i32, Legal);
352 // i64 operation support.
353 if (Subtarget->isThumb1Only()) {
354 setOperationAction(ISD::MUL, MVT::i64, Expand);
355 setOperationAction(ISD::MULHU, MVT::i32, Expand);
356 setOperationAction(ISD::MULHS, MVT::i32, Expand);
357 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
358 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
360 setOperationAction(ISD::MUL, MVT::i64, Expand);
361 setOperationAction(ISD::MULHU, MVT::i32, Expand);
362 if (!Subtarget->hasV6Ops())
363 setOperationAction(ISD::MULHS, MVT::i32, Expand);
365 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
366 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
367 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
368 setOperationAction(ISD::SRL, MVT::i64, Custom);
369 setOperationAction(ISD::SRA, MVT::i64, Custom);
371 // ARM does not have ROTL.
372 setOperationAction(ISD::ROTL, MVT::i32, Expand);
373 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
374 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
375 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
376 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
378 // Only ARMv6 has BSWAP.
379 if (!Subtarget->hasV6Ops())
380 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
382 // These are expanded into libcalls.
383 if (!Subtarget->hasDivide()) {
384 // v7M has a hardware divider
385 setOperationAction(ISD::SDIV, MVT::i32, Expand);
386 setOperationAction(ISD::UDIV, MVT::i32, Expand);
388 setOperationAction(ISD::SREM, MVT::i32, Expand);
389 setOperationAction(ISD::UREM, MVT::i32, Expand);
390 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
391 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
393 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
394 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
395 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
396 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
397 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
399 setOperationAction(ISD::TRAP, MVT::Other, Legal);
401 // Use the default implementation.
402 setOperationAction(ISD::VASTART, MVT::Other, Custom);
403 setOperationAction(ISD::VAARG, MVT::Other, Expand);
404 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
405 setOperationAction(ISD::VAEND, MVT::Other, Expand);
406 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
407 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
408 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
409 // FIXME: Shouldn't need this, since no register is used, but the legalizer
410 // doesn't yet know how to not do that for SjLj.
411 setExceptionSelectorRegister(ARM::R0);
412 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
413 // Handle atomics directly for ARMv[67] (except for Thumb1), otherwise
414 // use the default expansion.
415 bool canHandleAtomics =
416 (Subtarget->hasV7Ops() ||
417 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only()));
418 if (canHandleAtomics) {
419 // membarrier needs custom lowering; the rest are legal and handled
421 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
423 // Set them all for expansion, which will force libcalls.
424 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
425 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
426 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
427 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
428 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
429 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
430 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
431 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
432 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
433 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
434 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
435 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
436 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
437 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
438 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
439 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
440 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
441 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
442 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
443 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
444 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
445 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
446 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
447 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
448 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
449 // Since the libcalls include locking, fold in the fences
450 setShouldFoldAtomicFences(true);
452 // 64-bit versions are always libcalls (for now)
453 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
454 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
455 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
456 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
457 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
458 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
459 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
460 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
462 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
463 if (!Subtarget->hasV6Ops()) {
464 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
465 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
469 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
470 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
471 // iff target supports vfp2.
472 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
474 // We want to custom lower some of our intrinsics.
475 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
476 if (Subtarget->isTargetDarwin()) {
477 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
478 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
481 setOperationAction(ISD::SETCC, MVT::i32, Expand);
482 setOperationAction(ISD::SETCC, MVT::f32, Expand);
483 setOperationAction(ISD::SETCC, MVT::f64, Expand);
484 setOperationAction(ISD::SELECT, MVT::i32, Expand);
485 setOperationAction(ISD::SELECT, MVT::f32, Expand);
486 setOperationAction(ISD::SELECT, MVT::f64, Expand);
487 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
488 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
489 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
491 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
492 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
493 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
494 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
495 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
497 // We don't support sin/cos/fmod/copysign/pow
498 setOperationAction(ISD::FSIN, MVT::f64, Expand);
499 setOperationAction(ISD::FSIN, MVT::f32, Expand);
500 setOperationAction(ISD::FCOS, MVT::f32, Expand);
501 setOperationAction(ISD::FCOS, MVT::f64, Expand);
502 setOperationAction(ISD::FREM, MVT::f64, Expand);
503 setOperationAction(ISD::FREM, MVT::f32, Expand);
504 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
505 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
506 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
508 setOperationAction(ISD::FPOW, MVT::f64, Expand);
509 setOperationAction(ISD::FPOW, MVT::f32, Expand);
511 // Various VFP goodness
512 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
513 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
514 if (Subtarget->hasVFP2()) {
515 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
516 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
517 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
518 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
520 // Special handling for half-precision FP.
521 if (!Subtarget->hasFP16()) {
522 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
523 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
527 // We have target-specific dag combine patterns for the following nodes:
528 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
529 setTargetDAGCombine(ISD::ADD);
530 setTargetDAGCombine(ISD::SUB);
531 setTargetDAGCombine(ISD::MUL);
533 setStackPointerRegisterToSaveRestore(ARM::SP);
535 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
536 setSchedulingPreference(Sched::RegPressure);
538 setSchedulingPreference(Sched::Hybrid);
540 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
542 // On ARM arguments smaller than 4 bytes are extended, so all arguments
543 // are at least 4 bytes aligned.
544 setMinStackArgumentAlignment(4);
546 if (EnableARMCodePlacement)
547 benefitFromCodePlacementOpt = true;
550 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
553 case ARMISD::Wrapper: return "ARMISD::Wrapper";
554 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
555 case ARMISD::CALL: return "ARMISD::CALL";
556 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
557 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
558 case ARMISD::tCALL: return "ARMISD::tCALL";
559 case ARMISD::BRCOND: return "ARMISD::BRCOND";
560 case ARMISD::BR_JT: return "ARMISD::BR_JT";
561 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
562 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
563 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
564 case ARMISD::CMP: return "ARMISD::CMP";
565 case ARMISD::CMPZ: return "ARMISD::CMPZ";
566 case ARMISD::CMPFP: return "ARMISD::CMPFP";
567 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
568 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
569 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
570 case ARMISD::CMOV: return "ARMISD::CMOV";
571 case ARMISD::CNEG: return "ARMISD::CNEG";
573 case ARMISD::RBIT: return "ARMISD::RBIT";
575 case ARMISD::FTOSI: return "ARMISD::FTOSI";
576 case ARMISD::FTOUI: return "ARMISD::FTOUI";
577 case ARMISD::SITOF: return "ARMISD::SITOF";
578 case ARMISD::UITOF: return "ARMISD::UITOF";
580 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
581 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
582 case ARMISD::RRX: return "ARMISD::RRX";
584 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
585 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
587 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
588 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
590 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
592 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
594 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
596 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
597 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
599 case ARMISD::VCEQ: return "ARMISD::VCEQ";
600 case ARMISD::VCGE: return "ARMISD::VCGE";
601 case ARMISD::VCGEU: return "ARMISD::VCGEU";
602 case ARMISD::VCGT: return "ARMISD::VCGT";
603 case ARMISD::VCGTU: return "ARMISD::VCGTU";
604 case ARMISD::VTST: return "ARMISD::VTST";
606 case ARMISD::VSHL: return "ARMISD::VSHL";
607 case ARMISD::VSHRs: return "ARMISD::VSHRs";
608 case ARMISD::VSHRu: return "ARMISD::VSHRu";
609 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
610 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
611 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
612 case ARMISD::VSHRN: return "ARMISD::VSHRN";
613 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
614 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
615 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
616 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
617 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
618 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
619 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
620 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
621 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
622 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
623 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
624 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
625 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
626 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
627 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
628 case ARMISD::VDUP: return "ARMISD::VDUP";
629 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
630 case ARMISD::VEXT: return "ARMISD::VEXT";
631 case ARMISD::VREV64: return "ARMISD::VREV64";
632 case ARMISD::VREV32: return "ARMISD::VREV32";
633 case ARMISD::VREV16: return "ARMISD::VREV16";
634 case ARMISD::VZIP: return "ARMISD::VZIP";
635 case ARMISD::VUZP: return "ARMISD::VUZP";
636 case ARMISD::VTRN: return "ARMISD::VTRN";
637 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
638 case ARMISD::FMAX: return "ARMISD::FMAX";
639 case ARMISD::FMIN: return "ARMISD::FMIN";
643 /// getRegClassFor - Return the register class that should be used for the
644 /// specified value type.
645 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
646 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
647 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
648 // load / store 4 to 8 consecutive D registers.
649 if (Subtarget->hasNEON()) {
650 if (VT == MVT::v4i64)
651 return ARM::QQPRRegisterClass;
652 else if (VT == MVT::v8i64)
653 return ARM::QQQQPRRegisterClass;
655 return TargetLowering::getRegClassFor(VT);
658 /// getFunctionAlignment - Return the Log2 alignment of this function.
659 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
660 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
663 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
664 unsigned NumVals = N->getNumValues();
666 return Sched::RegPressure;
668 for (unsigned i = 0; i != NumVals; ++i) {
669 EVT VT = N->getValueType(i);
670 if (VT.isFloatingPoint() || VT.isVector())
671 return Sched::Latency;
674 if (!N->isMachineOpcode())
675 return Sched::RegPressure;
677 // Load are scheduled for latency even if there instruction itinerary
679 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
680 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
682 return Sched::Latency;
684 const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData();
685 if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2)
686 return Sched::Latency;
687 return Sched::RegPressure;
690 //===----------------------------------------------------------------------===//
692 //===----------------------------------------------------------------------===//
694 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
695 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
697 default: llvm_unreachable("Unknown condition code!");
698 case ISD::SETNE: return ARMCC::NE;
699 case ISD::SETEQ: return ARMCC::EQ;
700 case ISD::SETGT: return ARMCC::GT;
701 case ISD::SETGE: return ARMCC::GE;
702 case ISD::SETLT: return ARMCC::LT;
703 case ISD::SETLE: return ARMCC::LE;
704 case ISD::SETUGT: return ARMCC::HI;
705 case ISD::SETUGE: return ARMCC::HS;
706 case ISD::SETULT: return ARMCC::LO;
707 case ISD::SETULE: return ARMCC::LS;
711 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
712 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
713 ARMCC::CondCodes &CondCode2) {
714 CondCode2 = ARMCC::AL;
716 default: llvm_unreachable("Unknown FP condition!");
718 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
720 case ISD::SETOGT: CondCode = ARMCC::GT; break;
722 case ISD::SETOGE: CondCode = ARMCC::GE; break;
723 case ISD::SETOLT: CondCode = ARMCC::MI; break;
724 case ISD::SETOLE: CondCode = ARMCC::LS; break;
725 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
726 case ISD::SETO: CondCode = ARMCC::VC; break;
727 case ISD::SETUO: CondCode = ARMCC::VS; break;
728 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
729 case ISD::SETUGT: CondCode = ARMCC::HI; break;
730 case ISD::SETUGE: CondCode = ARMCC::PL; break;
732 case ISD::SETULT: CondCode = ARMCC::LT; break;
734 case ISD::SETULE: CondCode = ARMCC::LE; break;
736 case ISD::SETUNE: CondCode = ARMCC::NE; break;
740 //===----------------------------------------------------------------------===//
741 // Calling Convention Implementation
742 //===----------------------------------------------------------------------===//
744 #include "ARMGenCallingConv.inc"
746 // APCS f64 is in register pairs, possibly split to stack
747 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
748 CCValAssign::LocInfo &LocInfo,
749 CCState &State, bool CanFail) {
750 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
752 // Try to get the first register.
753 if (unsigned Reg = State.AllocateReg(RegList, 4))
754 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
756 // For the 2nd half of a v2f64, do not fail.
760 // Put the whole thing on the stack.
761 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
762 State.AllocateStack(8, 4),
767 // Try to get the second register.
768 if (unsigned Reg = State.AllocateReg(RegList, 4))
769 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
771 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
772 State.AllocateStack(4, 4),
777 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
778 CCValAssign::LocInfo &LocInfo,
779 ISD::ArgFlagsTy &ArgFlags,
781 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
783 if (LocVT == MVT::v2f64 &&
784 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
786 return true; // we handled it
789 // AAPCS f64 is in aligned register pairs
790 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
791 CCValAssign::LocInfo &LocInfo,
792 CCState &State, bool CanFail) {
793 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
794 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
796 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
798 // For the 2nd half of a v2f64, do not just fail.
802 // Put the whole thing on the stack.
803 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
804 State.AllocateStack(8, 8),
810 for (i = 0; i < 2; ++i)
811 if (HiRegList[i] == Reg)
814 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
815 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
820 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
821 CCValAssign::LocInfo &LocInfo,
822 ISD::ArgFlagsTy &ArgFlags,
824 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
826 if (LocVT == MVT::v2f64 &&
827 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
829 return true; // we handled it
832 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
833 CCValAssign::LocInfo &LocInfo, CCState &State) {
834 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
835 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
837 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
839 return false; // we didn't handle it
842 for (i = 0; i < 2; ++i)
843 if (HiRegList[i] == Reg)
846 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
847 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
852 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
853 CCValAssign::LocInfo &LocInfo,
854 ISD::ArgFlagsTy &ArgFlags,
856 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
858 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
860 return true; // we handled it
863 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
864 CCValAssign::LocInfo &LocInfo,
865 ISD::ArgFlagsTy &ArgFlags,
867 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
871 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
872 /// given CallingConvention value.
873 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
875 bool isVarArg) const {
878 llvm_unreachable("Unsupported calling convention");
880 case CallingConv::Fast:
881 // Use target triple & subtarget features to do actual dispatch.
882 if (Subtarget->isAAPCS_ABI()) {
883 if (Subtarget->hasVFP2() &&
884 FloatABIType == FloatABI::Hard && !isVarArg)
885 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
887 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
889 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
890 case CallingConv::ARM_AAPCS_VFP:
891 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
892 case CallingConv::ARM_AAPCS:
893 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
894 case CallingConv::ARM_APCS:
895 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
899 /// LowerCallResult - Lower the result values of a call into the
900 /// appropriate copies out of appropriate physical registers.
902 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
903 CallingConv::ID CallConv, bool isVarArg,
904 const SmallVectorImpl<ISD::InputArg> &Ins,
905 DebugLoc dl, SelectionDAG &DAG,
906 SmallVectorImpl<SDValue> &InVals) const {
908 // Assign locations to each value returned by this call.
909 SmallVector<CCValAssign, 16> RVLocs;
910 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
911 RVLocs, *DAG.getContext());
912 CCInfo.AnalyzeCallResult(Ins,
913 CCAssignFnForNode(CallConv, /* Return*/ true,
916 // Copy all of the result registers out of their specified physreg.
917 for (unsigned i = 0; i != RVLocs.size(); ++i) {
918 CCValAssign VA = RVLocs[i];
921 if (VA.needsCustom()) {
922 // Handle f64 or half of a v2f64.
923 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
925 Chain = Lo.getValue(1);
926 InFlag = Lo.getValue(2);
927 VA = RVLocs[++i]; // skip ahead to next loc
928 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
930 Chain = Hi.getValue(1);
931 InFlag = Hi.getValue(2);
932 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
934 if (VA.getLocVT() == MVT::v2f64) {
935 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
936 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
937 DAG.getConstant(0, MVT::i32));
939 VA = RVLocs[++i]; // skip ahead to next loc
940 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
941 Chain = Lo.getValue(1);
942 InFlag = Lo.getValue(2);
943 VA = RVLocs[++i]; // skip ahead to next loc
944 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
945 Chain = Hi.getValue(1);
946 InFlag = Hi.getValue(2);
947 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
948 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
949 DAG.getConstant(1, MVT::i32));
952 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
954 Chain = Val.getValue(1);
955 InFlag = Val.getValue(2);
958 switch (VA.getLocInfo()) {
959 default: llvm_unreachable("Unknown loc info!");
960 case CCValAssign::Full: break;
961 case CCValAssign::BCvt:
962 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
966 InVals.push_back(Val);
972 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
973 /// by "Src" to address "Dst" of size "Size". Alignment information is
974 /// specified by the specific parameter attribute. The copy will be passed as
975 /// a byval function parameter.
976 /// Sometimes what we are copying is the end of a larger object, the part that
977 /// does not fit in registers.
979 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
980 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
982 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
983 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
984 /*isVolatile=*/false, /*AlwaysInline=*/false,
988 /// LowerMemOpCallTo - Store the argument to the stack.
990 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
991 SDValue StackPtr, SDValue Arg,
992 DebugLoc dl, SelectionDAG &DAG,
993 const CCValAssign &VA,
994 ISD::ArgFlagsTy Flags) const {
995 unsigned LocMemOffset = VA.getLocMemOffset();
996 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
997 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
998 if (Flags.isByVal()) {
999 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1001 return DAG.getStore(Chain, dl, Arg, PtrOff,
1002 PseudoSourceValue::getStack(), LocMemOffset,
1006 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1007 SDValue Chain, SDValue &Arg,
1008 RegsToPassVector &RegsToPass,
1009 CCValAssign &VA, CCValAssign &NextVA,
1011 SmallVector<SDValue, 8> &MemOpChains,
1012 ISD::ArgFlagsTy Flags) const {
1014 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1015 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1016 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1018 if (NextVA.isRegLoc())
1019 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1021 assert(NextVA.isMemLoc());
1022 if (StackPtr.getNode() == 0)
1023 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1025 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1031 /// LowerCall - Lowering a call into a callseq_start <-
1032 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1035 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1036 CallingConv::ID CallConv, bool isVarArg,
1038 const SmallVectorImpl<ISD::OutputArg> &Outs,
1039 const SmallVectorImpl<SDValue> &OutVals,
1040 const SmallVectorImpl<ISD::InputArg> &Ins,
1041 DebugLoc dl, SelectionDAG &DAG,
1042 SmallVectorImpl<SDValue> &InVals) const {
1043 MachineFunction &MF = DAG.getMachineFunction();
1044 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1045 bool IsSibCall = false;
1046 // Temporarily disable tail calls so things don't break.
1047 if (!EnableARMTailCalls)
1050 // Check if it's really possible to do a tail call.
1051 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1052 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1053 Outs, OutVals, Ins, DAG);
1054 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1055 // detected sibcalls.
1062 // Analyze operands of the call, assigning locations to each operand.
1063 SmallVector<CCValAssign, 16> ArgLocs;
1064 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1066 CCInfo.AnalyzeCallOperands(Outs,
1067 CCAssignFnForNode(CallConv, /* Return*/ false,
1070 // Get a count of how many bytes are to be pushed on the stack.
1071 unsigned NumBytes = CCInfo.getNextStackOffset();
1073 // For tail calls, memory operands are available in our caller's stack.
1077 // Adjust the stack pointer for the new arguments...
1078 // These operations are automatically eliminated by the prolog/epilog pass
1080 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1082 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1084 RegsToPassVector RegsToPass;
1085 SmallVector<SDValue, 8> MemOpChains;
1087 // Walk the register/memloc assignments, inserting copies/loads. In the case
1088 // of tail call optimization, arguments are handled later.
1089 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1091 ++i, ++realArgIdx) {
1092 CCValAssign &VA = ArgLocs[i];
1093 SDValue Arg = OutVals[realArgIdx];
1094 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1096 // Promote the value if needed.
1097 switch (VA.getLocInfo()) {
1098 default: llvm_unreachable("Unknown loc info!");
1099 case CCValAssign::Full: break;
1100 case CCValAssign::SExt:
1101 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1103 case CCValAssign::ZExt:
1104 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1106 case CCValAssign::AExt:
1107 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1109 case CCValAssign::BCvt:
1110 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1114 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1115 if (VA.needsCustom()) {
1116 if (VA.getLocVT() == MVT::v2f64) {
1117 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1118 DAG.getConstant(0, MVT::i32));
1119 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1120 DAG.getConstant(1, MVT::i32));
1122 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1123 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1125 VA = ArgLocs[++i]; // skip ahead to next loc
1126 if (VA.isRegLoc()) {
1127 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1128 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1130 assert(VA.isMemLoc());
1132 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1133 dl, DAG, VA, Flags));
1136 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1137 StackPtr, MemOpChains, Flags);
1139 } else if (VA.isRegLoc()) {
1140 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1141 } else if (!IsSibCall) {
1142 assert(VA.isMemLoc());
1144 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1145 dl, DAG, VA, Flags));
1149 if (!MemOpChains.empty())
1150 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1151 &MemOpChains[0], MemOpChains.size());
1153 // Build a sequence of copy-to-reg nodes chained together with token chain
1154 // and flag operands which copy the outgoing args into the appropriate regs.
1156 // Tail call byval lowering might overwrite argument registers so in case of
1157 // tail call optimization the copies to registers are lowered later.
1159 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1160 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1161 RegsToPass[i].second, InFlag);
1162 InFlag = Chain.getValue(1);
1165 // For tail calls lower the arguments to the 'real' stack slot.
1167 // Force all the incoming stack arguments to be loaded from the stack
1168 // before any new outgoing arguments are stored to the stack, because the
1169 // outgoing stack slots may alias the incoming argument stack slots, and
1170 // the alias isn't otherwise explicit. This is slightly more conservative
1171 // than necessary, because it means that each store effectively depends
1172 // on every argument instead of just those arguments it would clobber.
1174 // Do not flag preceeding copytoreg stuff together with the following stuff.
1176 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1177 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1178 RegsToPass[i].second, InFlag);
1179 InFlag = Chain.getValue(1);
1184 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1185 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1186 // node so that legalize doesn't hack it.
1187 bool isDirect = false;
1188 bool isARMFunc = false;
1189 bool isLocalARMFunc = false;
1190 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1192 if (EnableARMLongCalls) {
1193 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1194 && "long-calls with non-static relocation model!");
1195 // Handle a global address or an external symbol. If it's not one of
1196 // those, the target's already in a register, so we don't need to do
1198 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1199 const GlobalValue *GV = G->getGlobal();
1200 // Create a constant pool entry for the callee address
1201 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1202 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1205 // Get the address of the callee into a register
1206 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1207 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1208 Callee = DAG.getLoad(getPointerTy(), dl,
1209 DAG.getEntryNode(), CPAddr,
1210 PseudoSourceValue::getConstantPool(), 0,
1212 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1213 const char *Sym = S->getSymbol();
1215 // Create a constant pool entry for the callee address
1216 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1217 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1218 Sym, ARMPCLabelIndex, 0);
1219 // Get the address of the callee into a register
1220 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1221 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1222 Callee = DAG.getLoad(getPointerTy(), dl,
1223 DAG.getEntryNode(), CPAddr,
1224 PseudoSourceValue::getConstantPool(), 0,
1227 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1228 const GlobalValue *GV = G->getGlobal();
1230 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1231 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1232 getTargetMachine().getRelocationModel() != Reloc::Static;
1233 isARMFunc = !Subtarget->isThumb() || isStub;
1234 // ARM call to a local ARM function is predicable.
1235 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1236 // tBX takes a register source operand.
1237 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1238 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1239 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1242 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1243 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1244 Callee = DAG.getLoad(getPointerTy(), dl,
1245 DAG.getEntryNode(), CPAddr,
1246 PseudoSourceValue::getConstantPool(), 0,
1248 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1249 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1250 getPointerTy(), Callee, PICLabel);
1252 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
1253 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1255 bool isStub = Subtarget->isTargetDarwin() &&
1256 getTargetMachine().getRelocationModel() != Reloc::Static;
1257 isARMFunc = !Subtarget->isThumb() || isStub;
1258 // tBX takes a register source operand.
1259 const char *Sym = S->getSymbol();
1260 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1261 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1262 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1263 Sym, ARMPCLabelIndex, 4);
1264 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1265 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1266 Callee = DAG.getLoad(getPointerTy(), dl,
1267 DAG.getEntryNode(), CPAddr,
1268 PseudoSourceValue::getConstantPool(), 0,
1270 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1271 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1272 getPointerTy(), Callee, PICLabel);
1274 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1277 // FIXME: handle tail calls differently.
1279 if (Subtarget->isThumb()) {
1280 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1281 CallOpc = ARMISD::CALL_NOLINK;
1283 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1285 CallOpc = (isDirect || Subtarget->hasV5TOps())
1286 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1287 : ARMISD::CALL_NOLINK;
1290 std::vector<SDValue> Ops;
1291 Ops.push_back(Chain);
1292 Ops.push_back(Callee);
1294 // Add argument registers to the end of the list so that they are known live
1296 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1297 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1298 RegsToPass[i].second.getValueType()));
1300 if (InFlag.getNode())
1301 Ops.push_back(InFlag);
1303 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1305 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1307 // Returns a chain and a flag for retval copy to use.
1308 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1309 InFlag = Chain.getValue(1);
1311 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1312 DAG.getIntPtrConstant(0, true), InFlag);
1314 InFlag = Chain.getValue(1);
1316 // Handle result values, copying them out of physregs into vregs that we
1318 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1322 /// MatchingStackOffset - Return true if the given stack call argument is
1323 /// already available in the same position (relatively) of the caller's
1324 /// incoming argument stack.
1326 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1327 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1328 const ARMInstrInfo *TII) {
1329 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1331 if (Arg.getOpcode() == ISD::CopyFromReg) {
1332 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1333 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1335 MachineInstr *Def = MRI->getVRegDef(VR);
1338 if (!Flags.isByVal()) {
1339 if (!TII->isLoadFromStackSlot(Def, FI))
1344 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1345 if (Flags.isByVal())
1346 // ByVal argument is passed in as a pointer but it's now being
1347 // dereferenced. e.g.
1348 // define @foo(%struct.X* %A) {
1349 // tail call @bar(%struct.X* byval %A)
1352 SDValue Ptr = Ld->getBasePtr();
1353 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1356 FI = FINode->getIndex();
1360 assert(FI != INT_MAX);
1361 if (!MFI->isFixedObjectIndex(FI))
1363 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1366 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1367 /// for tail call optimization. Targets which want to do tail call
1368 /// optimization should implement this function.
1370 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1371 CallingConv::ID CalleeCC,
1373 bool isCalleeStructRet,
1374 bool isCallerStructRet,
1375 const SmallVectorImpl<ISD::OutputArg> &Outs,
1376 const SmallVectorImpl<SDValue> &OutVals,
1377 const SmallVectorImpl<ISD::InputArg> &Ins,
1378 SelectionDAG& DAG) const {
1379 const Function *CallerF = DAG.getMachineFunction().getFunction();
1380 CallingConv::ID CallerCC = CallerF->getCallingConv();
1381 bool CCMatch = CallerCC == CalleeCC;
1383 // Look for obvious safe cases to perform tail call optimization that do not
1384 // require ABI changes. This is what gcc calls sibcall.
1386 // Do not sibcall optimize vararg calls unless the call site is not passing
1388 if (isVarArg && !Outs.empty())
1391 // Also avoid sibcall optimization if either caller or callee uses struct
1392 // return semantics.
1393 if (isCalleeStructRet || isCallerStructRet)
1396 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1397 // emitEpilogue is not ready for them.
1398 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1399 // LR. This means if we need to reload LR, it takes an extra instructions,
1400 // which outweighs the value of the tail call; but here we don't know yet
1401 // whether LR is going to be used. Probably the right approach is to
1402 // generate the tail call here and turn it back into CALL/RET in
1403 // emitEpilogue if LR is used.
1404 if (Subtarget->isThumb1Only())
1407 // For the moment, we can only do this to functions defined in this
1408 // compilation, or to indirect calls. A Thumb B to an ARM function,
1409 // or vice versa, is not easily fixed up in the linker unlike BL.
1410 // (We could do this by loading the address of the callee into a register;
1411 // that is an extra instruction over the direct call and burns a register
1412 // as well, so is not likely to be a win.)
1414 // It might be safe to remove this restriction on non-Darwin.
1416 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1417 // but we need to make sure there are enough registers; the only valid
1418 // registers are the 4 used for parameters. We don't currently do this
1420 if (isa<ExternalSymbolSDNode>(Callee))
1423 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1424 const GlobalValue *GV = G->getGlobal();
1425 if (GV->isDeclaration() || GV->isWeakForLinker())
1429 // If the calling conventions do not match, then we'd better make sure the
1430 // results are returned in the same way as what the caller expects.
1432 SmallVector<CCValAssign, 16> RVLocs1;
1433 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1434 RVLocs1, *DAG.getContext());
1435 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1437 SmallVector<CCValAssign, 16> RVLocs2;
1438 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1439 RVLocs2, *DAG.getContext());
1440 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1442 if (RVLocs1.size() != RVLocs2.size())
1444 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1445 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1447 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1449 if (RVLocs1[i].isRegLoc()) {
1450 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1453 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1459 // If the callee takes no arguments then go on to check the results of the
1461 if (!Outs.empty()) {
1462 // Check if stack adjustment is needed. For now, do not do this if any
1463 // argument is passed on the stack.
1464 SmallVector<CCValAssign, 16> ArgLocs;
1465 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1466 ArgLocs, *DAG.getContext());
1467 CCInfo.AnalyzeCallOperands(Outs,
1468 CCAssignFnForNode(CalleeCC, false, isVarArg));
1469 if (CCInfo.getNextStackOffset()) {
1470 MachineFunction &MF = DAG.getMachineFunction();
1472 // Check if the arguments are already laid out in the right way as
1473 // the caller's fixed stack objects.
1474 MachineFrameInfo *MFI = MF.getFrameInfo();
1475 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1476 const ARMInstrInfo *TII =
1477 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1478 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1480 ++i, ++realArgIdx) {
1481 CCValAssign &VA = ArgLocs[i];
1482 EVT RegVT = VA.getLocVT();
1483 SDValue Arg = OutVals[realArgIdx];
1484 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1485 if (VA.getLocInfo() == CCValAssign::Indirect)
1487 if (VA.needsCustom()) {
1488 // f64 and vector types are split into multiple registers or
1489 // register/stack-slot combinations. The types will not match
1490 // the registers; give up on memory f64 refs until we figure
1491 // out what to do about this.
1494 if (!ArgLocs[++i].isRegLoc())
1496 if (RegVT == MVT::v2f64) {
1497 if (!ArgLocs[++i].isRegLoc())
1499 if (!ArgLocs[++i].isRegLoc())
1502 } else if (!VA.isRegLoc()) {
1503 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1515 ARMTargetLowering::LowerReturn(SDValue Chain,
1516 CallingConv::ID CallConv, bool isVarArg,
1517 const SmallVectorImpl<ISD::OutputArg> &Outs,
1518 const SmallVectorImpl<SDValue> &OutVals,
1519 DebugLoc dl, SelectionDAG &DAG) const {
1521 // CCValAssign - represent the assignment of the return value to a location.
1522 SmallVector<CCValAssign, 16> RVLocs;
1524 // CCState - Info about the registers and stack slots.
1525 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1528 // Analyze outgoing return values.
1529 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1532 // If this is the first return lowered for this function, add
1533 // the regs to the liveout set for the function.
1534 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1535 for (unsigned i = 0; i != RVLocs.size(); ++i)
1536 if (RVLocs[i].isRegLoc())
1537 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1542 // Copy the result values into the output registers.
1543 for (unsigned i = 0, realRVLocIdx = 0;
1545 ++i, ++realRVLocIdx) {
1546 CCValAssign &VA = RVLocs[i];
1547 assert(VA.isRegLoc() && "Can only return in registers!");
1549 SDValue Arg = OutVals[realRVLocIdx];
1551 switch (VA.getLocInfo()) {
1552 default: llvm_unreachable("Unknown loc info!");
1553 case CCValAssign::Full: break;
1554 case CCValAssign::BCvt:
1555 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1559 if (VA.needsCustom()) {
1560 if (VA.getLocVT() == MVT::v2f64) {
1561 // Extract the first half and return it in two registers.
1562 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1563 DAG.getConstant(0, MVT::i32));
1564 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1565 DAG.getVTList(MVT::i32, MVT::i32), Half);
1567 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1568 Flag = Chain.getValue(1);
1569 VA = RVLocs[++i]; // skip ahead to next loc
1570 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1571 HalfGPRs.getValue(1), Flag);
1572 Flag = Chain.getValue(1);
1573 VA = RVLocs[++i]; // skip ahead to next loc
1575 // Extract the 2nd half and fall through to handle it as an f64 value.
1576 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1577 DAG.getConstant(1, MVT::i32));
1579 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1581 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1582 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1583 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1584 Flag = Chain.getValue(1);
1585 VA = RVLocs[++i]; // skip ahead to next loc
1586 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1589 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1591 // Guarantee that all emitted copies are
1592 // stuck together, avoiding something bad.
1593 Flag = Chain.getValue(1);
1598 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1600 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1605 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1606 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1607 // one of the above mentioned nodes. It has to be wrapped because otherwise
1608 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1609 // be used to form addressing mode. These wrapped nodes will be selected
1611 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1612 EVT PtrVT = Op.getValueType();
1613 // FIXME there is no actual debug info here
1614 DebugLoc dl = Op.getDebugLoc();
1615 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1617 if (CP->isMachineConstantPoolEntry())
1618 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1619 CP->getAlignment());
1621 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1622 CP->getAlignment());
1623 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1626 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1627 SelectionDAG &DAG) const {
1628 MachineFunction &MF = DAG.getMachineFunction();
1629 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1630 unsigned ARMPCLabelIndex = 0;
1631 DebugLoc DL = Op.getDebugLoc();
1632 EVT PtrVT = getPointerTy();
1633 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1634 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1636 if (RelocM == Reloc::Static) {
1637 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1639 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1640 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1641 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1642 ARMCP::CPBlockAddress,
1644 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1646 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1647 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1648 PseudoSourceValue::getConstantPool(), 0,
1650 if (RelocM == Reloc::Static)
1652 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1653 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1656 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1658 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1659 SelectionDAG &DAG) const {
1660 DebugLoc dl = GA->getDebugLoc();
1661 EVT PtrVT = getPointerTy();
1662 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1663 MachineFunction &MF = DAG.getMachineFunction();
1664 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1665 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1666 ARMConstantPoolValue *CPV =
1667 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1668 ARMCP::CPValue, PCAdj, "tlsgd", true);
1669 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1670 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1671 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1672 PseudoSourceValue::getConstantPool(), 0,
1674 SDValue Chain = Argument.getValue(1);
1676 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1677 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1679 // call __tls_get_addr.
1682 Entry.Node = Argument;
1683 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1684 Args.push_back(Entry);
1685 // FIXME: is there useful debug info available here?
1686 std::pair<SDValue, SDValue> CallResult =
1687 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1688 false, false, false, false,
1689 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1690 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1691 return CallResult.first;
1694 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1695 // "local exec" model.
1697 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1698 SelectionDAG &DAG) const {
1699 const GlobalValue *GV = GA->getGlobal();
1700 DebugLoc dl = GA->getDebugLoc();
1702 SDValue Chain = DAG.getEntryNode();
1703 EVT PtrVT = getPointerTy();
1704 // Get the Thread Pointer
1705 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1707 if (GV->isDeclaration()) {
1708 MachineFunction &MF = DAG.getMachineFunction();
1709 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1710 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1711 // Initial exec model.
1712 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1713 ARMConstantPoolValue *CPV =
1714 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1715 ARMCP::CPValue, PCAdj, "gottpoff", true);
1716 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1717 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1718 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1719 PseudoSourceValue::getConstantPool(), 0,
1721 Chain = Offset.getValue(1);
1723 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1724 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1726 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1727 PseudoSourceValue::getConstantPool(), 0,
1731 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1732 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1733 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1734 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1735 PseudoSourceValue::getConstantPool(), 0,
1739 // The address of the thread local variable is the add of the thread
1740 // pointer with the offset of the variable.
1741 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1745 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1746 // TODO: implement the "local dynamic" model
1747 assert(Subtarget->isTargetELF() &&
1748 "TLS not implemented for non-ELF targets");
1749 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1750 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1751 // otherwise use the "Local Exec" TLS Model
1752 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1753 return LowerToTLSGeneralDynamicModel(GA, DAG);
1755 return LowerToTLSExecModels(GA, DAG);
1758 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1759 SelectionDAG &DAG) const {
1760 EVT PtrVT = getPointerTy();
1761 DebugLoc dl = Op.getDebugLoc();
1762 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1763 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1764 if (RelocM == Reloc::PIC_) {
1765 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1766 ARMConstantPoolValue *CPV =
1767 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1768 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1769 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1770 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1772 PseudoSourceValue::getConstantPool(), 0,
1774 SDValue Chain = Result.getValue(1);
1775 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1776 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1778 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1779 PseudoSourceValue::getGOT(), 0,
1783 // If we have T2 ops, we can materialize the address directly via movt/movw
1784 // pair. This is always cheaper.
1785 if (Subtarget->useMovt()) {
1786 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1787 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1789 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1790 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1791 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1792 PseudoSourceValue::getConstantPool(), 0,
1798 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1799 SelectionDAG &DAG) const {
1800 MachineFunction &MF = DAG.getMachineFunction();
1801 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1802 unsigned ARMPCLabelIndex = 0;
1803 EVT PtrVT = getPointerTy();
1804 DebugLoc dl = Op.getDebugLoc();
1805 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1806 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1808 if (RelocM == Reloc::Static)
1809 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1811 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1812 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1813 ARMConstantPoolValue *CPV =
1814 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1815 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1817 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1819 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1820 PseudoSourceValue::getConstantPool(), 0,
1822 SDValue Chain = Result.getValue(1);
1824 if (RelocM == Reloc::PIC_) {
1825 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1826 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1829 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1830 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1831 PseudoSourceValue::getGOT(), 0,
1837 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1838 SelectionDAG &DAG) const {
1839 assert(Subtarget->isTargetELF() &&
1840 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1841 MachineFunction &MF = DAG.getMachineFunction();
1842 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1843 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1844 EVT PtrVT = getPointerTy();
1845 DebugLoc dl = Op.getDebugLoc();
1846 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1847 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1848 "_GLOBAL_OFFSET_TABLE_",
1849 ARMPCLabelIndex, PCAdj);
1850 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1851 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1852 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1853 PseudoSourceValue::getConstantPool(), 0,
1855 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1856 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1860 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1861 DebugLoc dl = Op.getDebugLoc();
1862 SDValue Val = DAG.getConstant(0, MVT::i32);
1863 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1864 Op.getOperand(1), Val);
1868 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1869 DebugLoc dl = Op.getDebugLoc();
1870 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1871 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1875 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1876 const ARMSubtarget *Subtarget) const {
1877 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1878 DebugLoc dl = Op.getDebugLoc();
1880 default: return SDValue(); // Don't custom lower most intrinsics.
1881 case Intrinsic::arm_thread_pointer: {
1882 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1883 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1885 case Intrinsic::eh_sjlj_lsda: {
1886 MachineFunction &MF = DAG.getMachineFunction();
1887 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1888 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1889 EVT PtrVT = getPointerTy();
1890 DebugLoc dl = Op.getDebugLoc();
1891 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1893 unsigned PCAdj = (RelocM != Reloc::PIC_)
1894 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1895 ARMConstantPoolValue *CPV =
1896 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1897 ARMCP::CPLSDA, PCAdj);
1898 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1899 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1901 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1902 PseudoSourceValue::getConstantPool(), 0,
1905 if (RelocM == Reloc::PIC_) {
1906 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1907 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1914 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1915 const ARMSubtarget *Subtarget) {
1916 DebugLoc dl = Op.getDebugLoc();
1917 SDValue Op5 = Op.getOperand(5);
1918 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1919 // v6 and v7 can both handle barriers directly, but need handled a bit
1920 // differently. Thumb1 and pre-v6 ARM mode use a libcall instead and should
1922 unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER;
1923 if (Subtarget->hasV7Ops())
1924 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0));
1925 else if (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())
1926 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0),
1927 DAG.getConstant(0, MVT::i32));
1928 assert(0 && "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
1932 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
1933 MachineFunction &MF = DAG.getMachineFunction();
1934 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
1936 // vastart just stores the address of the VarArgsFrameIndex slot into the
1937 // memory location argument.
1938 DebugLoc dl = Op.getDebugLoc();
1939 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1940 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1941 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1942 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
1947 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1948 SelectionDAG &DAG) const {
1949 SDNode *Node = Op.getNode();
1950 DebugLoc dl = Node->getDebugLoc();
1951 EVT VT = Node->getValueType(0);
1952 SDValue Chain = Op.getOperand(0);
1953 SDValue Size = Op.getOperand(1);
1954 SDValue Align = Op.getOperand(2);
1956 // Chain the dynamic stack allocation so that it doesn't modify the stack
1957 // pointer when other instructions are using the stack.
1958 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1960 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1961 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1962 if (AlignVal > StackAlign)
1963 // Do this now since selection pass cannot introduce new target
1964 // independent node.
1965 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1967 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1968 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1969 // do even more horrible hack later.
1970 MachineFunction &MF = DAG.getMachineFunction();
1971 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1972 if (AFI->isThumb1OnlyFunction()) {
1974 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1976 uint32_t Val = C->getZExtValue();
1977 if (Val <= 508 && ((Val & 3) == 0))
1981 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1984 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1985 SDValue Ops1[] = { Chain, Size, Align };
1986 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1987 Chain = Res.getValue(1);
1988 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1989 DAG.getIntPtrConstant(0, true), SDValue());
1990 SDValue Ops2[] = { Res, Chain };
1991 return DAG.getMergeValues(Ops2, 2, dl);
1995 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1996 SDValue &Root, SelectionDAG &DAG,
1997 DebugLoc dl) const {
1998 MachineFunction &MF = DAG.getMachineFunction();
1999 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2001 TargetRegisterClass *RC;
2002 if (AFI->isThumb1OnlyFunction())
2003 RC = ARM::tGPRRegisterClass;
2005 RC = ARM::GPRRegisterClass;
2007 // Transform the arguments stored in physical registers into virtual ones.
2008 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2009 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2012 if (NextVA.isMemLoc()) {
2013 MachineFrameInfo *MFI = MF.getFrameInfo();
2014 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2016 // Create load node to retrieve arguments from the stack.
2017 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2018 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2019 PseudoSourceValue::getFixedStack(FI), 0,
2022 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2023 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2026 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2030 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2031 CallingConv::ID CallConv, bool isVarArg,
2032 const SmallVectorImpl<ISD::InputArg>
2034 DebugLoc dl, SelectionDAG &DAG,
2035 SmallVectorImpl<SDValue> &InVals)
2038 MachineFunction &MF = DAG.getMachineFunction();
2039 MachineFrameInfo *MFI = MF.getFrameInfo();
2041 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2043 // Assign locations to all of the incoming arguments.
2044 SmallVector<CCValAssign, 16> ArgLocs;
2045 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2047 CCInfo.AnalyzeFormalArguments(Ins,
2048 CCAssignFnForNode(CallConv, /* Return*/ false,
2051 SmallVector<SDValue, 16> ArgValues;
2053 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2054 CCValAssign &VA = ArgLocs[i];
2056 // Arguments stored in registers.
2057 if (VA.isRegLoc()) {
2058 EVT RegVT = VA.getLocVT();
2061 if (VA.needsCustom()) {
2062 // f64 and vector types are split up into multiple registers or
2063 // combinations of registers and stack slots.
2064 if (VA.getLocVT() == MVT::v2f64) {
2065 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2067 VA = ArgLocs[++i]; // skip ahead to next loc
2069 if (VA.isMemLoc()) {
2070 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2071 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2072 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2073 PseudoSourceValue::getFixedStack(FI), 0,
2076 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2079 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2080 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2081 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2082 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2083 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2085 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2088 TargetRegisterClass *RC;
2090 if (RegVT == MVT::f32)
2091 RC = ARM::SPRRegisterClass;
2092 else if (RegVT == MVT::f64)
2093 RC = ARM::DPRRegisterClass;
2094 else if (RegVT == MVT::v2f64)
2095 RC = ARM::QPRRegisterClass;
2096 else if (RegVT == MVT::i32)
2097 RC = (AFI->isThumb1OnlyFunction() ?
2098 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2100 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2102 // Transform the arguments in physical registers into virtual ones.
2103 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2104 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2107 // If this is an 8 or 16-bit value, it is really passed promoted
2108 // to 32 bits. Insert an assert[sz]ext to capture this, then
2109 // truncate to the right size.
2110 switch (VA.getLocInfo()) {
2111 default: llvm_unreachable("Unknown loc info!");
2112 case CCValAssign::Full: break;
2113 case CCValAssign::BCvt:
2114 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2116 case CCValAssign::SExt:
2117 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2118 DAG.getValueType(VA.getValVT()));
2119 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2121 case CCValAssign::ZExt:
2122 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2123 DAG.getValueType(VA.getValVT()));
2124 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2128 InVals.push_back(ArgValue);
2130 } else { // VA.isRegLoc()
2133 assert(VA.isMemLoc());
2134 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2136 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2137 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2139 // Create load nodes to retrieve arguments from the stack.
2140 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2141 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2142 PseudoSourceValue::getFixedStack(FI), 0,
2149 static const unsigned GPRArgRegs[] = {
2150 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2153 unsigned NumGPRs = CCInfo.getFirstUnallocated
2154 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2156 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2157 unsigned VARegSize = (4 - NumGPRs) * 4;
2158 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2159 unsigned ArgOffset = CCInfo.getNextStackOffset();
2160 if (VARegSaveSize) {
2161 // If this function is vararg, store any remaining integer argument regs
2162 // to their spots on the stack so that they may be loaded by deferencing
2163 // the result of va_next.
2164 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2165 AFI->setVarArgsFrameIndex(
2166 MFI->CreateFixedObject(VARegSaveSize,
2167 ArgOffset + VARegSaveSize - VARegSize,
2169 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2172 SmallVector<SDValue, 4> MemOps;
2173 for (; NumGPRs < 4; ++NumGPRs) {
2174 TargetRegisterClass *RC;
2175 if (AFI->isThumb1OnlyFunction())
2176 RC = ARM::tGPRRegisterClass;
2178 RC = ARM::GPRRegisterClass;
2180 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2181 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2183 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2184 PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()),
2185 0, false, false, 0);
2186 MemOps.push_back(Store);
2187 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2188 DAG.getConstant(4, getPointerTy()));
2190 if (!MemOps.empty())
2191 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2192 &MemOps[0], MemOps.size());
2194 // This will point to the next argument passed via stack.
2195 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2201 /// isFloatingPointZero - Return true if this is +0.0.
2202 static bool isFloatingPointZero(SDValue Op) {
2203 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2204 return CFP->getValueAPF().isPosZero();
2205 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2206 // Maybe this has already been legalized into the constant pool?
2207 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2208 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2209 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2210 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2211 return CFP->getValueAPF().isPosZero();
2217 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2218 /// the given operands.
2220 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2221 SDValue &ARMcc, SelectionDAG &DAG,
2222 DebugLoc dl) const {
2223 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2224 unsigned C = RHSC->getZExtValue();
2225 if (!isLegalICmpImmediate(C)) {
2226 // Constant does not fit, try adjusting it by one?
2231 if (isLegalICmpImmediate(C-1)) {
2232 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2233 RHS = DAG.getConstant(C-1, MVT::i32);
2238 if (C > 0 && isLegalICmpImmediate(C-1)) {
2239 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2240 RHS = DAG.getConstant(C-1, MVT::i32);
2245 if (isLegalICmpImmediate(C+1)) {
2246 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2247 RHS = DAG.getConstant(C+1, MVT::i32);
2252 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
2253 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2254 RHS = DAG.getConstant(C+1, MVT::i32);
2261 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2262 ARMISD::NodeType CompareType;
2265 CompareType = ARMISD::CMP;
2270 CompareType = ARMISD::CMPZ;
2273 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2274 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2277 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2279 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2280 DebugLoc dl) const {
2282 if (!isFloatingPointZero(RHS))
2283 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2285 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2286 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2289 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2290 EVT VT = Op.getValueType();
2291 SDValue LHS = Op.getOperand(0);
2292 SDValue RHS = Op.getOperand(1);
2293 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2294 SDValue TrueVal = Op.getOperand(2);
2295 SDValue FalseVal = Op.getOperand(3);
2296 DebugLoc dl = Op.getDebugLoc();
2298 if (LHS.getValueType() == MVT::i32) {
2300 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2301 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2302 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2305 ARMCC::CondCodes CondCode, CondCode2;
2306 FPCCToARMCC(CC, CondCode, CondCode2);
2308 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2309 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2310 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2311 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2313 if (CondCode2 != ARMCC::AL) {
2314 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2315 // FIXME: Needs another CMP because flag can have but one use.
2316 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2317 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2318 Result, TrueVal, ARMcc2, CCR, Cmp2);
2323 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2324 /// to morph to an integer compare sequence.
2325 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2326 const ARMSubtarget *Subtarget) {
2327 SDNode *N = Op.getNode();
2328 if (!N->hasOneUse())
2329 // Otherwise it requires moving the value from fp to integer registers.
2331 if (!N->getNumValues())
2333 EVT VT = Op.getValueType();
2334 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2335 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2336 // vmrs are very slow, e.g. cortex-a8.
2339 if (isFloatingPointZero(Op)) {
2343 return ISD::isNormalLoad(N);
2346 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2347 if (isFloatingPointZero(Op))
2348 return DAG.getConstant(0, MVT::i32);
2350 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2351 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2352 Ld->getChain(), Ld->getBasePtr(),
2353 Ld->getSrcValue(), Ld->getSrcValueOffset(),
2354 Ld->isVolatile(), Ld->isNonTemporal(),
2355 Ld->getAlignment());
2357 llvm_unreachable("Unknown VFP cmp argument!");
2360 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2361 SDValue &RetVal1, SDValue &RetVal2) {
2362 if (isFloatingPointZero(Op)) {
2363 RetVal1 = DAG.getConstant(0, MVT::i32);
2364 RetVal2 = DAG.getConstant(0, MVT::i32);
2368 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2369 SDValue Ptr = Ld->getBasePtr();
2370 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2371 Ld->getChain(), Ptr,
2372 Ld->getSrcValue(), Ld->getSrcValueOffset(),
2373 Ld->isVolatile(), Ld->isNonTemporal(),
2374 Ld->getAlignment());
2376 EVT PtrType = Ptr.getValueType();
2377 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2378 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2379 PtrType, Ptr, DAG.getConstant(4, PtrType));
2380 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2381 Ld->getChain(), NewPtr,
2382 Ld->getSrcValue(), Ld->getSrcValueOffset() + 4,
2383 Ld->isVolatile(), Ld->isNonTemporal(),
2388 llvm_unreachable("Unknown VFP cmp argument!");
2391 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2392 /// f32 and even f64 comparisons to integer ones.
2394 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2395 SDValue Chain = Op.getOperand(0);
2396 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2397 SDValue LHS = Op.getOperand(2);
2398 SDValue RHS = Op.getOperand(3);
2399 SDValue Dest = Op.getOperand(4);
2400 DebugLoc dl = Op.getDebugLoc();
2402 bool SeenZero = false;
2403 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2404 canChangeToInt(RHS, SeenZero, Subtarget) &&
2405 // If one of the operand is zero, it's safe to ignore the NaN case.
2406 (FiniteOnlyFPMath() || SeenZero)) {
2407 // If unsafe fp math optimization is enabled and there are no othter uses of
2408 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2409 // to an integer comparison.
2410 if (CC == ISD::SETOEQ)
2412 else if (CC == ISD::SETUNE)
2416 if (LHS.getValueType() == MVT::f32) {
2417 LHS = bitcastf32Toi32(LHS, DAG);
2418 RHS = bitcastf32Toi32(RHS, DAG);
2419 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2420 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2421 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2422 Chain, Dest, ARMcc, CCR, Cmp);
2427 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2428 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2429 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2430 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2431 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2432 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2433 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2439 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2440 SDValue Chain = Op.getOperand(0);
2441 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2442 SDValue LHS = Op.getOperand(2);
2443 SDValue RHS = Op.getOperand(3);
2444 SDValue Dest = Op.getOperand(4);
2445 DebugLoc dl = Op.getDebugLoc();
2447 if (LHS.getValueType() == MVT::i32) {
2449 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2450 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2451 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2452 Chain, Dest, ARMcc, CCR, Cmp);
2455 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2458 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2459 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2460 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2461 if (Result.getNode())
2465 ARMCC::CondCodes CondCode, CondCode2;
2466 FPCCToARMCC(CC, CondCode, CondCode2);
2468 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2469 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2470 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2471 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2472 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2473 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2474 if (CondCode2 != ARMCC::AL) {
2475 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2476 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2477 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2482 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2483 SDValue Chain = Op.getOperand(0);
2484 SDValue Table = Op.getOperand(1);
2485 SDValue Index = Op.getOperand(2);
2486 DebugLoc dl = Op.getDebugLoc();
2488 EVT PTy = getPointerTy();
2489 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2490 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2491 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2492 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2493 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2494 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2495 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2496 if (Subtarget->isThumb2()) {
2497 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2498 // which does another jump to the destination. This also makes it easier
2499 // to translate it to TBB / TBH later.
2500 // FIXME: This might not work if the function is extremely large.
2501 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2502 Addr, Op.getOperand(2), JTI, UId);
2504 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2505 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2506 PseudoSourceValue::getJumpTable(), 0,
2508 Chain = Addr.getValue(1);
2509 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2510 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2512 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2513 PseudoSourceValue::getJumpTable(), 0, false, false, 0);
2514 Chain = Addr.getValue(1);
2515 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2519 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2520 DebugLoc dl = Op.getDebugLoc();
2523 switch (Op.getOpcode()) {
2525 assert(0 && "Invalid opcode!");
2526 case ISD::FP_TO_SINT:
2527 Opc = ARMISD::FTOSI;
2529 case ISD::FP_TO_UINT:
2530 Opc = ARMISD::FTOUI;
2533 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2534 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2537 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2538 EVT VT = Op.getValueType();
2539 DebugLoc dl = Op.getDebugLoc();
2542 switch (Op.getOpcode()) {
2544 assert(0 && "Invalid opcode!");
2545 case ISD::SINT_TO_FP:
2546 Opc = ARMISD::SITOF;
2548 case ISD::UINT_TO_FP:
2549 Opc = ARMISD::UITOF;
2553 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2554 return DAG.getNode(Opc, dl, VT, Op);
2557 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2558 // Implement fcopysign with a fabs and a conditional fneg.
2559 SDValue Tmp0 = Op.getOperand(0);
2560 SDValue Tmp1 = Op.getOperand(1);
2561 DebugLoc dl = Op.getDebugLoc();
2562 EVT VT = Op.getValueType();
2563 EVT SrcVT = Tmp1.getValueType();
2564 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2565 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2566 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2567 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2568 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2569 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2572 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2573 MachineFunction &MF = DAG.getMachineFunction();
2574 MachineFrameInfo *MFI = MF.getFrameInfo();
2575 MFI->setReturnAddressIsTaken(true);
2577 EVT VT = Op.getValueType();
2578 DebugLoc dl = Op.getDebugLoc();
2579 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2581 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2582 SDValue Offset = DAG.getConstant(4, MVT::i32);
2583 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2584 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2585 NULL, 0, false, false, 0);
2588 // Return LR, which contains the return address. Mark it an implicit live-in.
2589 unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass);
2590 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2593 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2594 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2595 MFI->setFrameAddressIsTaken(true);
2597 EVT VT = Op.getValueType();
2598 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2599 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2600 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2601 ? ARM::R7 : ARM::R11;
2602 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2604 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
2609 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2610 /// expand a bit convert where either the source or destination type is i64 to
2611 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2612 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2613 /// vectors), since the legalizer won't know what to do with that.
2614 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2615 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2616 DebugLoc dl = N->getDebugLoc();
2617 SDValue Op = N->getOperand(0);
2619 // This function is only supposed to be called for i64 types, either as the
2620 // source or destination of the bit convert.
2621 EVT SrcVT = Op.getValueType();
2622 EVT DstVT = N->getValueType(0);
2623 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2624 "ExpandBIT_CONVERT called for non-i64 type");
2626 // Turn i64->f64 into VMOVDRR.
2627 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2628 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2629 DAG.getConstant(0, MVT::i32));
2630 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2631 DAG.getConstant(1, MVT::i32));
2632 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2633 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2636 // Turn f64->i64 into VMOVRRD.
2637 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2638 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2639 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2640 // Merge the pieces into a single i64 value.
2641 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2647 /// getZeroVector - Returns a vector of specified type with all zero elements.
2648 /// Zero vectors are used to represent vector negation and in those cases
2649 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2650 /// not support i64 elements, so sometimes the zero vectors will need to be
2651 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2653 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2654 assert(VT.isVector() && "Expected a vector type");
2655 // The canonical modified immediate encoding of a zero vector is....0!
2656 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2657 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2658 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2659 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
2662 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2663 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2664 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2665 SelectionDAG &DAG) const {
2666 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2667 EVT VT = Op.getValueType();
2668 unsigned VTBits = VT.getSizeInBits();
2669 DebugLoc dl = Op.getDebugLoc();
2670 SDValue ShOpLo = Op.getOperand(0);
2671 SDValue ShOpHi = Op.getOperand(1);
2672 SDValue ShAmt = Op.getOperand(2);
2674 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2676 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2678 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2679 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2680 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2681 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2682 DAG.getConstant(VTBits, MVT::i32));
2683 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2684 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2685 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2687 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2688 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2690 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2691 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2694 SDValue Ops[2] = { Lo, Hi };
2695 return DAG.getMergeValues(Ops, 2, dl);
2698 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2699 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2700 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2701 SelectionDAG &DAG) const {
2702 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2703 EVT VT = Op.getValueType();
2704 unsigned VTBits = VT.getSizeInBits();
2705 DebugLoc dl = Op.getDebugLoc();
2706 SDValue ShOpLo = Op.getOperand(0);
2707 SDValue ShOpHi = Op.getOperand(1);
2708 SDValue ShAmt = Op.getOperand(2);
2711 assert(Op.getOpcode() == ISD::SHL_PARTS);
2712 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2713 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2714 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2715 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2716 DAG.getConstant(VTBits, MVT::i32));
2717 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2718 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2720 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2721 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2722 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2724 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2725 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2728 SDValue Ops[2] = { Lo, Hi };
2729 return DAG.getMergeValues(Ops, 2, dl);
2732 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2733 const ARMSubtarget *ST) {
2734 EVT VT = N->getValueType(0);
2735 DebugLoc dl = N->getDebugLoc();
2737 if (!ST->hasV6T2Ops())
2740 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2741 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2744 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2745 const ARMSubtarget *ST) {
2746 EVT VT = N->getValueType(0);
2747 DebugLoc dl = N->getDebugLoc();
2749 // Lower vector shifts on NEON to use VSHL.
2750 if (VT.isVector()) {
2751 assert(ST->hasNEON() && "unexpected vector shift");
2753 // Left shifts translate directly to the vshiftu intrinsic.
2754 if (N->getOpcode() == ISD::SHL)
2755 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2756 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2757 N->getOperand(0), N->getOperand(1));
2759 assert((N->getOpcode() == ISD::SRA ||
2760 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2762 // NEON uses the same intrinsics for both left and right shifts. For
2763 // right shifts, the shift amounts are negative, so negate the vector of
2765 EVT ShiftVT = N->getOperand(1).getValueType();
2766 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2767 getZeroVector(ShiftVT, DAG, dl),
2769 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2770 Intrinsic::arm_neon_vshifts :
2771 Intrinsic::arm_neon_vshiftu);
2772 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2773 DAG.getConstant(vshiftInt, MVT::i32),
2774 N->getOperand(0), NegatedCount);
2777 // We can get here for a node like i32 = ISD::SHL i32, i64
2781 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2782 "Unknown shift to lower!");
2784 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2785 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2786 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2789 // If we are in thumb mode, we don't have RRX.
2790 if (ST->isThumb1Only()) return SDValue();
2792 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2793 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2794 DAG.getConstant(0, MVT::i32));
2795 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2796 DAG.getConstant(1, MVT::i32));
2798 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2799 // captures the result into a carry flag.
2800 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2801 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2803 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2804 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2806 // Merge the pieces into a single i64 value.
2807 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2810 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2811 SDValue TmpOp0, TmpOp1;
2812 bool Invert = false;
2816 SDValue Op0 = Op.getOperand(0);
2817 SDValue Op1 = Op.getOperand(1);
2818 SDValue CC = Op.getOperand(2);
2819 EVT VT = Op.getValueType();
2820 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2821 DebugLoc dl = Op.getDebugLoc();
2823 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2824 switch (SetCCOpcode) {
2825 default: llvm_unreachable("Illegal FP comparison"); break;
2827 case ISD::SETNE: Invert = true; // Fallthrough
2829 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2831 case ISD::SETLT: Swap = true; // Fallthrough
2833 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2835 case ISD::SETLE: Swap = true; // Fallthrough
2837 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2838 case ISD::SETUGE: Swap = true; // Fallthrough
2839 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2840 case ISD::SETUGT: Swap = true; // Fallthrough
2841 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2842 case ISD::SETUEQ: Invert = true; // Fallthrough
2844 // Expand this to (OLT | OGT).
2848 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2849 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2851 case ISD::SETUO: Invert = true; // Fallthrough
2853 // Expand this to (OLT | OGE).
2857 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2858 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2862 // Integer comparisons.
2863 switch (SetCCOpcode) {
2864 default: llvm_unreachable("Illegal integer comparison"); break;
2865 case ISD::SETNE: Invert = true;
2866 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2867 case ISD::SETLT: Swap = true;
2868 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2869 case ISD::SETLE: Swap = true;
2870 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2871 case ISD::SETULT: Swap = true;
2872 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2873 case ISD::SETULE: Swap = true;
2874 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2877 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2878 if (Opc == ARMISD::VCEQ) {
2881 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2883 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2886 // Ignore bitconvert.
2887 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2888 AndOp = AndOp.getOperand(0);
2890 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2892 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2893 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2900 std::swap(Op0, Op1);
2902 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2905 Result = DAG.getNOT(dl, Result, VT);
2910 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
2911 /// valid vector constant for a NEON instruction with a "modified immediate"
2912 /// operand (e.g., VMOV). If so, return the encoded value.
2913 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
2914 unsigned SplatBitSize, SelectionDAG &DAG,
2915 EVT &VT, bool is128Bits, bool isVMOV) {
2916 unsigned OpCmode, Imm;
2918 // SplatBitSize is set to the smallest size that splats the vector, so a
2919 // zero vector will always have SplatBitSize == 8. However, NEON modified
2920 // immediate instructions others than VMOV do not support the 8-bit encoding
2921 // of a zero vector, and the default encoding of zero is supposed to be the
2926 switch (SplatBitSize) {
2928 // Any 1-byte value is OK. Op=0, Cmode=1110.
2929 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2932 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
2936 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2937 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
2938 if ((SplatBits & ~0xff) == 0) {
2939 // Value = 0x00nn: Op=x, Cmode=100x.
2944 if ((SplatBits & ~0xff00) == 0) {
2945 // Value = 0xnn00: Op=x, Cmode=101x.
2947 Imm = SplatBits >> 8;
2953 // NEON's 32-bit VMOV supports splat values where:
2954 // * only one byte is nonzero, or
2955 // * the least significant byte is 0xff and the second byte is nonzero, or
2956 // * the least significant 2 bytes are 0xff and the third is nonzero.
2957 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
2958 if ((SplatBits & ~0xff) == 0) {
2959 // Value = 0x000000nn: Op=x, Cmode=000x.
2964 if ((SplatBits & ~0xff00) == 0) {
2965 // Value = 0x0000nn00: Op=x, Cmode=001x.
2967 Imm = SplatBits >> 8;
2970 if ((SplatBits & ~0xff0000) == 0) {
2971 // Value = 0x00nn0000: Op=x, Cmode=010x.
2973 Imm = SplatBits >> 16;
2976 if ((SplatBits & ~0xff000000) == 0) {
2977 // Value = 0xnn000000: Op=x, Cmode=011x.
2979 Imm = SplatBits >> 24;
2983 if ((SplatBits & ~0xffff) == 0 &&
2984 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
2985 // Value = 0x0000nnff: Op=x, Cmode=1100.
2987 Imm = SplatBits >> 8;
2992 if ((SplatBits & ~0xffffff) == 0 &&
2993 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
2994 // Value = 0x00nnffff: Op=x, Cmode=1101.
2996 Imm = SplatBits >> 16;
2997 SplatBits |= 0xffff;
3001 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3002 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3003 // VMOV.I32. A (very) minor optimization would be to replicate the value
3004 // and fall through here to test for a valid 64-bit splat. But, then the
3005 // caller would also need to check and handle the change in size.
3009 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3012 uint64_t BitMask = 0xff;
3014 unsigned ImmMask = 1;
3016 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3017 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3020 } else if ((SplatBits & BitMask) != 0) {
3026 // Op=1, Cmode=1110.
3029 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3034 llvm_unreachable("unexpected size for isNEONModifiedImm");
3038 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3039 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3042 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3043 bool &ReverseVEXT, unsigned &Imm) {
3044 unsigned NumElts = VT.getVectorNumElements();
3045 ReverseVEXT = false;
3048 // If this is a VEXT shuffle, the immediate value is the index of the first
3049 // element. The other shuffle indices must be the successive elements after
3051 unsigned ExpectedElt = Imm;
3052 for (unsigned i = 1; i < NumElts; ++i) {
3053 // Increment the expected index. If it wraps around, it may still be
3054 // a VEXT but the source vectors must be swapped.
3056 if (ExpectedElt == NumElts * 2) {
3061 if (ExpectedElt != static_cast<unsigned>(M[i]))
3065 // Adjust the index value if the source operands will be swapped.
3072 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3073 /// instruction with the specified blocksize. (The order of the elements
3074 /// within each block of the vector is reversed.)
3075 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3076 unsigned BlockSize) {
3077 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3078 "Only possible block sizes for VREV are: 16, 32, 64");
3080 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3084 unsigned NumElts = VT.getVectorNumElements();
3085 unsigned BlockElts = M[0] + 1;
3087 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3090 for (unsigned i = 0; i < NumElts; ++i) {
3091 if ((unsigned) M[i] !=
3092 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3099 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3100 unsigned &WhichResult) {
3101 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3105 unsigned NumElts = VT.getVectorNumElements();
3106 WhichResult = (M[0] == 0 ? 0 : 1);
3107 for (unsigned i = 0; i < NumElts; i += 2) {
3108 if ((unsigned) M[i] != i + WhichResult ||
3109 (unsigned) M[i+1] != i + NumElts + WhichResult)
3115 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3116 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3117 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3118 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3119 unsigned &WhichResult) {
3120 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3124 unsigned NumElts = VT.getVectorNumElements();
3125 WhichResult = (M[0] == 0 ? 0 : 1);
3126 for (unsigned i = 0; i < NumElts; i += 2) {
3127 if ((unsigned) M[i] != i + WhichResult ||
3128 (unsigned) M[i+1] != i + WhichResult)
3134 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3135 unsigned &WhichResult) {
3136 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3140 unsigned NumElts = VT.getVectorNumElements();
3141 WhichResult = (M[0] == 0 ? 0 : 1);
3142 for (unsigned i = 0; i != NumElts; ++i) {
3143 if ((unsigned) M[i] != 2 * i + WhichResult)
3147 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3148 if (VT.is64BitVector() && EltSz == 32)
3154 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3155 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3156 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3157 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3158 unsigned &WhichResult) {
3159 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3163 unsigned Half = VT.getVectorNumElements() / 2;
3164 WhichResult = (M[0] == 0 ? 0 : 1);
3165 for (unsigned j = 0; j != 2; ++j) {
3166 unsigned Idx = WhichResult;
3167 for (unsigned i = 0; i != Half; ++i) {
3168 if ((unsigned) M[i + j * Half] != Idx)
3174 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3175 if (VT.is64BitVector() && EltSz == 32)
3181 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3182 unsigned &WhichResult) {
3183 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3187 unsigned NumElts = VT.getVectorNumElements();
3188 WhichResult = (M[0] == 0 ? 0 : 1);
3189 unsigned Idx = WhichResult * NumElts / 2;
3190 for (unsigned i = 0; i != NumElts; i += 2) {
3191 if ((unsigned) M[i] != Idx ||
3192 (unsigned) M[i+1] != Idx + NumElts)
3197 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3198 if (VT.is64BitVector() && EltSz == 32)
3204 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3205 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3206 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3207 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3208 unsigned &WhichResult) {
3209 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3213 unsigned NumElts = VT.getVectorNumElements();
3214 WhichResult = (M[0] == 0 ? 0 : 1);
3215 unsigned Idx = WhichResult * NumElts / 2;
3216 for (unsigned i = 0; i != NumElts; i += 2) {
3217 if ((unsigned) M[i] != Idx ||
3218 (unsigned) M[i+1] != Idx)
3223 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3224 if (VT.is64BitVector() && EltSz == 32)
3230 // If this is a case we can't handle, return null and let the default
3231 // expansion code take care of it.
3232 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3233 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3234 DebugLoc dl = Op.getDebugLoc();
3235 EVT VT = Op.getValueType();
3237 APInt SplatBits, SplatUndef;
3238 unsigned SplatBitSize;
3240 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3241 if (SplatBitSize <= 64) {
3242 // Check if an immediate VMOV works.
3244 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3245 SplatUndef.getZExtValue(), SplatBitSize,
3246 DAG, VmovVT, VT.is128BitVector(), true);
3247 if (Val.getNode()) {
3248 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3249 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3254 // Scan through the operands to see if only one value is used.
3255 unsigned NumElts = VT.getVectorNumElements();
3256 bool isOnlyLowElement = true;
3257 bool usesOnlyOneValue = true;
3258 bool isConstant = true;
3260 for (unsigned i = 0; i < NumElts; ++i) {
3261 SDValue V = Op.getOperand(i);
3262 if (V.getOpcode() == ISD::UNDEF)
3265 isOnlyLowElement = false;
3266 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3269 if (!Value.getNode())
3271 else if (V != Value)
3272 usesOnlyOneValue = false;
3275 if (!Value.getNode())
3276 return DAG.getUNDEF(VT);
3278 if (isOnlyLowElement)
3279 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3281 // If all elements are constants, fall back to the default expansion, which
3282 // will generate a load from the constant pool.
3286 // Use VDUP for non-constant splats.
3287 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3288 if (usesOnlyOneValue && EltSize <= 32)
3289 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3291 // Vectors with 32- or 64-bit elements can be built by directly assigning
3292 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3293 // will be legalized.
3294 if (EltSize >= 32) {
3295 // Do the expansion with floating-point types, since that is what the VFP
3296 // registers are defined to use, and since i64 is not legal.
3297 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3298 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3299 SmallVector<SDValue, 8> Ops;
3300 for (unsigned i = 0; i < NumElts; ++i)
3301 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3302 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3303 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3309 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3310 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3311 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3312 /// are assumed to be legal.
3314 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3316 if (VT.getVectorNumElements() == 4 &&
3317 (VT.is128BitVector() || VT.is64BitVector())) {
3318 unsigned PFIndexes[4];
3319 for (unsigned i = 0; i != 4; ++i) {
3323 PFIndexes[i] = M[i];
3326 // Compute the index in the perfect shuffle table.
3327 unsigned PFTableIndex =
3328 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3329 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3330 unsigned Cost = (PFEntry >> 30);
3337 unsigned Imm, WhichResult;
3339 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3340 return (EltSize >= 32 ||
3341 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3342 isVREVMask(M, VT, 64) ||
3343 isVREVMask(M, VT, 32) ||
3344 isVREVMask(M, VT, 16) ||
3345 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3346 isVTRNMask(M, VT, WhichResult) ||
3347 isVUZPMask(M, VT, WhichResult) ||
3348 isVZIPMask(M, VT, WhichResult) ||
3349 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3350 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3351 isVZIP_v_undef_Mask(M, VT, WhichResult));
3354 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3355 /// the specified operations to build the shuffle.
3356 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3357 SDValue RHS, SelectionDAG &DAG,
3359 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3360 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3361 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3364 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3373 OP_VUZPL, // VUZP, left result
3374 OP_VUZPR, // VUZP, right result
3375 OP_VZIPL, // VZIP, left result
3376 OP_VZIPR, // VZIP, right result
3377 OP_VTRNL, // VTRN, left result
3378 OP_VTRNR // VTRN, right result
3381 if (OpNum == OP_COPY) {
3382 if (LHSID == (1*9+2)*9+3) return LHS;
3383 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3387 SDValue OpLHS, OpRHS;
3388 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3389 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3390 EVT VT = OpLHS.getValueType();
3393 default: llvm_unreachable("Unknown shuffle opcode!");
3395 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3400 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3401 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3405 return DAG.getNode(ARMISD::VEXT, dl, VT,
3407 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3410 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3411 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3414 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3415 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3418 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3419 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3423 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3424 SDValue V1 = Op.getOperand(0);
3425 SDValue V2 = Op.getOperand(1);
3426 DebugLoc dl = Op.getDebugLoc();
3427 EVT VT = Op.getValueType();
3428 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3429 SmallVector<int, 8> ShuffleMask;
3431 // Convert shuffles that are directly supported on NEON to target-specific
3432 // DAG nodes, instead of keeping them as shuffles and matching them again
3433 // during code selection. This is more efficient and avoids the possibility
3434 // of inconsistencies between legalization and selection.
3435 // FIXME: floating-point vectors should be canonicalized to integer vectors
3436 // of the same time so that they get CSEd properly.
3437 SVN->getMask(ShuffleMask);
3439 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3440 if (EltSize <= 32) {
3441 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3442 int Lane = SVN->getSplatIndex();
3443 // If this is undef splat, generate it via "just" vdup, if possible.
3444 if (Lane == -1) Lane = 0;
3446 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3447 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3449 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3450 DAG.getConstant(Lane, MVT::i32));
3455 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3458 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3459 DAG.getConstant(Imm, MVT::i32));
3462 if (isVREVMask(ShuffleMask, VT, 64))
3463 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3464 if (isVREVMask(ShuffleMask, VT, 32))
3465 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3466 if (isVREVMask(ShuffleMask, VT, 16))
3467 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3469 // Check for Neon shuffles that modify both input vectors in place.
3470 // If both results are used, i.e., if there are two shuffles with the same
3471 // source operands and with masks corresponding to both results of one of
3472 // these operations, DAG memoization will ensure that a single node is
3473 // used for both shuffles.
3474 unsigned WhichResult;
3475 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3476 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3477 V1, V2).getValue(WhichResult);
3478 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3479 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3480 V1, V2).getValue(WhichResult);
3481 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3482 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3483 V1, V2).getValue(WhichResult);
3485 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3486 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3487 V1, V1).getValue(WhichResult);
3488 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3489 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3490 V1, V1).getValue(WhichResult);
3491 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3492 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3493 V1, V1).getValue(WhichResult);
3496 // If the shuffle is not directly supported and it has 4 elements, use
3497 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3498 unsigned NumElts = VT.getVectorNumElements();
3500 unsigned PFIndexes[4];
3501 for (unsigned i = 0; i != 4; ++i) {
3502 if (ShuffleMask[i] < 0)
3505 PFIndexes[i] = ShuffleMask[i];
3508 // Compute the index in the perfect shuffle table.
3509 unsigned PFTableIndex =
3510 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3511 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3512 unsigned Cost = (PFEntry >> 30);
3515 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3518 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3519 if (EltSize >= 32) {
3520 // Do the expansion with floating-point types, since that is what the VFP
3521 // registers are defined to use, and since i64 is not legal.
3522 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3523 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3524 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3525 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3526 SmallVector<SDValue, 8> Ops;
3527 for (unsigned i = 0; i < NumElts; ++i) {
3528 if (ShuffleMask[i] < 0)
3529 Ops.push_back(DAG.getUNDEF(EltVT));
3531 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3532 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3533 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3536 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3537 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3543 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3544 EVT VT = Op.getValueType();
3545 DebugLoc dl = Op.getDebugLoc();
3546 SDValue Vec = Op.getOperand(0);
3547 SDValue Lane = Op.getOperand(1);
3548 assert(VT == MVT::i32 &&
3549 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3550 "unexpected type for custom-lowering vector extract");
3551 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3554 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3555 // The only time a CONCAT_VECTORS operation can have legal types is when
3556 // two 64-bit vectors are concatenated to a 128-bit vector.
3557 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3558 "unexpected CONCAT_VECTORS");
3559 DebugLoc dl = Op.getDebugLoc();
3560 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3561 SDValue Op0 = Op.getOperand(0);
3562 SDValue Op1 = Op.getOperand(1);
3563 if (Op0.getOpcode() != ISD::UNDEF)
3564 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3565 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3566 DAG.getIntPtrConstant(0));
3567 if (Op1.getOpcode() != ISD::UNDEF)
3568 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3569 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3570 DAG.getIntPtrConstant(1));
3571 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3574 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3575 switch (Op.getOpcode()) {
3576 default: llvm_unreachable("Don't know how to custom lower this!");
3577 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3578 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3579 case ISD::GlobalAddress:
3580 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3581 LowerGlobalAddressELF(Op, DAG);
3582 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3583 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3584 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3585 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3586 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3587 case ISD::VASTART: return LowerVASTART(Op, DAG);
3588 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3589 case ISD::SINT_TO_FP:
3590 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3591 case ISD::FP_TO_SINT:
3592 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3593 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3594 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3595 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3596 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3597 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3598 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3599 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3601 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3604 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3605 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3606 case ISD::SRL_PARTS:
3607 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3608 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3609 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3610 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3611 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3612 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3613 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3618 /// ReplaceNodeResults - Replace the results of node with an illegal result
3619 /// type with new values built out of custom code.
3620 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3621 SmallVectorImpl<SDValue>&Results,
3622 SelectionDAG &DAG) const {
3624 switch (N->getOpcode()) {
3626 llvm_unreachable("Don't know how to custom expand this!");
3628 case ISD::BIT_CONVERT:
3629 Res = ExpandBIT_CONVERT(N, DAG);
3633 Res = LowerShift(N, DAG, Subtarget);
3637 Results.push_back(Res);
3640 //===----------------------------------------------------------------------===//
3641 // ARM Scheduler Hooks
3642 //===----------------------------------------------------------------------===//
3645 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3646 MachineBasicBlock *BB,
3647 unsigned Size) const {
3648 unsigned dest = MI->getOperand(0).getReg();
3649 unsigned ptr = MI->getOperand(1).getReg();
3650 unsigned oldval = MI->getOperand(2).getReg();
3651 unsigned newval = MI->getOperand(3).getReg();
3652 unsigned scratch = BB->getParent()->getRegInfo()
3653 .createVirtualRegister(ARM::GPRRegisterClass);
3654 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3655 DebugLoc dl = MI->getDebugLoc();
3656 bool isThumb2 = Subtarget->isThumb2();
3658 unsigned ldrOpc, strOpc;
3660 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3662 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3663 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3666 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3667 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3670 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3671 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3675 MachineFunction *MF = BB->getParent();
3676 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3677 MachineFunction::iterator It = BB;
3678 ++It; // insert the new blocks after the current block
3680 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3681 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3682 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3683 MF->insert(It, loop1MBB);
3684 MF->insert(It, loop2MBB);
3685 MF->insert(It, exitMBB);
3687 // Transfer the remainder of BB and its successor edges to exitMBB.
3688 exitMBB->splice(exitMBB->begin(), BB,
3689 llvm::next(MachineBasicBlock::iterator(MI)),
3691 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3695 // fallthrough --> loop1MBB
3696 BB->addSuccessor(loop1MBB);
3699 // ldrex dest, [ptr]
3703 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3704 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3705 .addReg(dest).addReg(oldval));
3706 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3707 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3708 BB->addSuccessor(loop2MBB);
3709 BB->addSuccessor(exitMBB);
3712 // strex scratch, newval, [ptr]
3716 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3718 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3719 .addReg(scratch).addImm(0));
3720 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3721 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3722 BB->addSuccessor(loop1MBB);
3723 BB->addSuccessor(exitMBB);
3729 MI->eraseFromParent(); // The instruction is gone now.
3735 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3736 unsigned Size, unsigned BinOpcode) const {
3737 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3738 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3740 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3741 MachineFunction *MF = BB->getParent();
3742 MachineFunction::iterator It = BB;
3745 unsigned dest = MI->getOperand(0).getReg();
3746 unsigned ptr = MI->getOperand(1).getReg();
3747 unsigned incr = MI->getOperand(2).getReg();
3748 DebugLoc dl = MI->getDebugLoc();
3750 bool isThumb2 = Subtarget->isThumb2();
3751 unsigned ldrOpc, strOpc;
3753 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3755 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3756 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3759 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3760 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3763 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3764 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3768 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3769 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3770 MF->insert(It, loopMBB);
3771 MF->insert(It, exitMBB);
3773 // Transfer the remainder of BB and its successor edges to exitMBB.
3774 exitMBB->splice(exitMBB->begin(), BB,
3775 llvm::next(MachineBasicBlock::iterator(MI)),
3777 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3779 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3780 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3781 unsigned scratch2 = (!BinOpcode) ? incr :
3782 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3786 // fallthrough --> loopMBB
3787 BB->addSuccessor(loopMBB);
3791 // <binop> scratch2, dest, incr
3792 // strex scratch, scratch2, ptr
3795 // fallthrough --> exitMBB
3797 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3799 // operand order needs to go the other way for NAND
3800 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3801 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3802 addReg(incr).addReg(dest)).addReg(0);
3804 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3805 addReg(dest).addReg(incr)).addReg(0);
3808 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3810 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3811 .addReg(scratch).addImm(0));
3812 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3813 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3815 BB->addSuccessor(loopMBB);
3816 BB->addSuccessor(exitMBB);
3822 MI->eraseFromParent(); // The instruction is gone now.
3828 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
3829 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
3830 E = MBB->succ_end(); I != E; ++I)
3833 llvm_unreachable("Expecting a BB with two successors!");
3837 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3838 MachineBasicBlock *BB) const {
3839 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3840 DebugLoc dl = MI->getDebugLoc();
3841 bool isThumb2 = Subtarget->isThumb2();
3842 switch (MI->getOpcode()) {
3845 llvm_unreachable("Unexpected instr type to insert");
3847 case ARM::ATOMIC_LOAD_ADD_I8:
3848 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3849 case ARM::ATOMIC_LOAD_ADD_I16:
3850 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3851 case ARM::ATOMIC_LOAD_ADD_I32:
3852 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3854 case ARM::ATOMIC_LOAD_AND_I8:
3855 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3856 case ARM::ATOMIC_LOAD_AND_I16:
3857 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3858 case ARM::ATOMIC_LOAD_AND_I32:
3859 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3861 case ARM::ATOMIC_LOAD_OR_I8:
3862 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3863 case ARM::ATOMIC_LOAD_OR_I16:
3864 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3865 case ARM::ATOMIC_LOAD_OR_I32:
3866 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3868 case ARM::ATOMIC_LOAD_XOR_I8:
3869 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3870 case ARM::ATOMIC_LOAD_XOR_I16:
3871 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3872 case ARM::ATOMIC_LOAD_XOR_I32:
3873 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3875 case ARM::ATOMIC_LOAD_NAND_I8:
3876 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3877 case ARM::ATOMIC_LOAD_NAND_I16:
3878 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3879 case ARM::ATOMIC_LOAD_NAND_I32:
3880 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3882 case ARM::ATOMIC_LOAD_SUB_I8:
3883 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3884 case ARM::ATOMIC_LOAD_SUB_I16:
3885 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3886 case ARM::ATOMIC_LOAD_SUB_I32:
3887 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3889 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3890 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3891 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
3893 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3894 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3895 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
3897 case ARM::tMOVCCr_pseudo: {
3898 // To "insert" a SELECT_CC instruction, we actually have to insert the
3899 // diamond control-flow pattern. The incoming instruction knows the
3900 // destination vreg to set, the condition code register to branch on, the
3901 // true/false values to select between, and a branch opcode to use.
3902 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3903 MachineFunction::iterator It = BB;
3909 // cmpTY ccX, r1, r2
3911 // fallthrough --> copy0MBB
3912 MachineBasicBlock *thisMBB = BB;
3913 MachineFunction *F = BB->getParent();
3914 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3915 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3916 F->insert(It, copy0MBB);
3917 F->insert(It, sinkMBB);
3919 // Transfer the remainder of BB and its successor edges to sinkMBB.
3920 sinkMBB->splice(sinkMBB->begin(), BB,
3921 llvm::next(MachineBasicBlock::iterator(MI)),
3923 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3925 BB->addSuccessor(copy0MBB);
3926 BB->addSuccessor(sinkMBB);
3928 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
3929 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
3932 // %FalseValue = ...
3933 // # fallthrough to sinkMBB
3936 // Update machine-CFG edges
3937 BB->addSuccessor(sinkMBB);
3940 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3943 BuildMI(*BB, BB->begin(), dl,
3944 TII->get(ARM::PHI), MI->getOperand(0).getReg())
3945 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
3946 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3948 MI->eraseFromParent(); // The pseudo instruction is gone now.
3953 case ARM::BCCZi64: {
3954 // Compare both parts that make up the double comparison separately for
3956 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
3958 unsigned LHS1 = MI->getOperand(1).getReg();
3959 unsigned LHS2 = MI->getOperand(2).getReg();
3961 AddDefaultPred(BuildMI(BB, dl,
3962 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3963 .addReg(LHS1).addImm(0));
3964 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3965 .addReg(LHS2).addImm(0)
3966 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
3968 unsigned RHS1 = MI->getOperand(3).getReg();
3969 unsigned RHS2 = MI->getOperand(4).getReg();
3970 AddDefaultPred(BuildMI(BB, dl,
3971 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3972 .addReg(LHS1).addReg(RHS1));
3973 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3974 .addReg(LHS2).addReg(RHS2)
3975 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
3978 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
3979 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
3980 if (MI->getOperand(0).getImm() == ARMCC::NE)
3981 std::swap(destMBB, exitMBB);
3983 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3984 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
3985 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
3988 MI->eraseFromParent(); // The pseudo instruction is gone now.
3995 case ARM::t2SUBrSPi_:
3996 case ARM::t2SUBrSPi12_:
3997 case ARM::t2SUBrSPs_: {
3998 MachineFunction *MF = BB->getParent();
3999 unsigned DstReg = MI->getOperand(0).getReg();
4000 unsigned SrcReg = MI->getOperand(1).getReg();
4001 bool DstIsDead = MI->getOperand(0).isDead();
4002 bool SrcIsKill = MI->getOperand(1).isKill();
4004 if (SrcReg != ARM::SP) {
4005 // Copy the source to SP from virtual register.
4006 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
4007 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
4008 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
4009 BuildMI(*BB, MI, dl, TII->get(CopyOpc), ARM::SP)
4010 .addReg(SrcReg, getKillRegState(SrcIsKill));
4014 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
4015 switch (MI->getOpcode()) {
4017 llvm_unreachable("Unexpected pseudo instruction!");
4023 OpOpc = ARM::tADDspr;
4026 OpOpc = ARM::tSUBspi;
4028 case ARM::t2SUBrSPi_:
4029 OpOpc = ARM::t2SUBrSPi;
4030 NeedPred = true; NeedCC = true;
4032 case ARM::t2SUBrSPi12_:
4033 OpOpc = ARM::t2SUBrSPi12;
4036 case ARM::t2SUBrSPs_:
4037 OpOpc = ARM::t2SUBrSPs;
4038 NeedPred = true; NeedCC = true; NeedOp3 = true;
4041 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(OpOpc), ARM::SP);
4042 if (OpOpc == ARM::tAND)
4043 AddDefaultT1CC(MIB);
4044 MIB.addReg(ARM::SP);
4045 MIB.addOperand(MI->getOperand(2));
4047 MIB.addOperand(MI->getOperand(3));
4049 AddDefaultPred(MIB);
4053 // Copy the result from SP to virtual register.
4054 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
4055 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
4056 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
4057 BuildMI(*BB, MI, dl, TII->get(CopyOpc))
4058 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
4060 MI->eraseFromParent(); // The pseudo instruction is gone now.
4066 //===----------------------------------------------------------------------===//
4067 // ARM Optimization Hooks
4068 //===----------------------------------------------------------------------===//
4071 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4072 TargetLowering::DAGCombinerInfo &DCI) {
4073 SelectionDAG &DAG = DCI.DAG;
4074 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4075 EVT VT = N->getValueType(0);
4076 unsigned Opc = N->getOpcode();
4077 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4078 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4079 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4080 ISD::CondCode CC = ISD::SETCC_INVALID;
4083 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4085 SDValue CCOp = Slct.getOperand(0);
4086 if (CCOp.getOpcode() == ISD::SETCC)
4087 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4090 bool DoXform = false;
4092 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4095 if (LHS.getOpcode() == ISD::Constant &&
4096 cast<ConstantSDNode>(LHS)->isNullValue()) {
4098 } else if (CC != ISD::SETCC_INVALID &&
4099 RHS.getOpcode() == ISD::Constant &&
4100 cast<ConstantSDNode>(RHS)->isNullValue()) {
4101 std::swap(LHS, RHS);
4102 SDValue Op0 = Slct.getOperand(0);
4103 EVT OpVT = isSlctCC ? Op0.getValueType() :
4104 Op0.getOperand(0).getValueType();
4105 bool isInt = OpVT.isInteger();
4106 CC = ISD::getSetCCInverse(CC, isInt);
4108 if (!TLI.isCondCodeLegal(CC, OpVT))
4109 return SDValue(); // Inverse operator isn't legal.
4116 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4118 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4119 Slct.getOperand(0), Slct.getOperand(1), CC);
4120 SDValue CCOp = Slct.getOperand(0);
4122 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4123 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4124 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4125 CCOp, OtherOp, Result);
4130 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4131 static SDValue PerformADDCombine(SDNode *N,
4132 TargetLowering::DAGCombinerInfo &DCI) {
4133 // added by evan in r37685 with no testcase.
4134 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4136 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4137 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4138 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4139 if (Result.getNode()) return Result;
4141 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4142 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4143 if (Result.getNode()) return Result;
4149 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4150 static SDValue PerformSUBCombine(SDNode *N,
4151 TargetLowering::DAGCombinerInfo &DCI) {
4152 // added by evan in r37685 with no testcase.
4153 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4155 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4156 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4157 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4158 if (Result.getNode()) return Result;
4164 static SDValue PerformMULCombine(SDNode *N,
4165 TargetLowering::DAGCombinerInfo &DCI,
4166 const ARMSubtarget *Subtarget) {
4167 SelectionDAG &DAG = DCI.DAG;
4169 if (Subtarget->isThumb1Only())
4172 if (DAG.getMachineFunction().
4173 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
4176 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4179 EVT VT = N->getValueType(0);
4183 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4187 uint64_t MulAmt = C->getZExtValue();
4188 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4189 ShiftAmt = ShiftAmt & (32 - 1);
4190 SDValue V = N->getOperand(0);
4191 DebugLoc DL = N->getDebugLoc();
4194 MulAmt >>= ShiftAmt;
4195 if (isPowerOf2_32(MulAmt - 1)) {
4196 // (mul x, 2^N + 1) => (add (shl x, N), x)
4197 Res = DAG.getNode(ISD::ADD, DL, VT,
4198 V, DAG.getNode(ISD::SHL, DL, VT,
4199 V, DAG.getConstant(Log2_32(MulAmt-1),
4201 } else if (isPowerOf2_32(MulAmt + 1)) {
4202 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4203 Res = DAG.getNode(ISD::SUB, DL, VT,
4204 DAG.getNode(ISD::SHL, DL, VT,
4205 V, DAG.getConstant(Log2_32(MulAmt+1),
4212 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4213 DAG.getConstant(ShiftAmt, MVT::i32));
4215 // Do not add new nodes to DAG combiner worklist.
4216 DCI.CombineTo(N, Res, false);
4220 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4221 /// ARMISD::VMOVRRD.
4222 static SDValue PerformVMOVRRDCombine(SDNode *N,
4223 TargetLowering::DAGCombinerInfo &DCI) {
4224 // fmrrd(fmdrr x, y) -> x,y
4225 SDValue InDouble = N->getOperand(0);
4226 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4227 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4231 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4232 /// operand of a vector shift operation, where all the elements of the
4233 /// build_vector must have the same constant integer value.
4234 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4235 // Ignore bit_converts.
4236 while (Op.getOpcode() == ISD::BIT_CONVERT)
4237 Op = Op.getOperand(0);
4238 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4239 APInt SplatBits, SplatUndef;
4240 unsigned SplatBitSize;
4242 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4243 HasAnyUndefs, ElementBits) ||
4244 SplatBitSize > ElementBits)
4246 Cnt = SplatBits.getSExtValue();
4250 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4251 /// operand of a vector shift left operation. That value must be in the range:
4252 /// 0 <= Value < ElementBits for a left shift; or
4253 /// 0 <= Value <= ElementBits for a long left shift.
4254 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4255 assert(VT.isVector() && "vector shift count is not a vector type");
4256 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4257 if (! getVShiftImm(Op, ElementBits, Cnt))
4259 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4262 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4263 /// operand of a vector shift right operation. For a shift opcode, the value
4264 /// is positive, but for an intrinsic the value count must be negative. The
4265 /// absolute value must be in the range:
4266 /// 1 <= |Value| <= ElementBits for a right shift; or
4267 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4268 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4270 assert(VT.isVector() && "vector shift count is not a vector type");
4271 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4272 if (! getVShiftImm(Op, ElementBits, Cnt))
4276 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4279 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4280 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4281 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4284 // Don't do anything for most intrinsics.
4287 // Vector shifts: check for immediate versions and lower them.
4288 // Note: This is done during DAG combining instead of DAG legalizing because
4289 // the build_vectors for 64-bit vector element shift counts are generally
4290 // not legal, and it is hard to see their values after they get legalized to
4291 // loads from a constant pool.
4292 case Intrinsic::arm_neon_vshifts:
4293 case Intrinsic::arm_neon_vshiftu:
4294 case Intrinsic::arm_neon_vshiftls:
4295 case Intrinsic::arm_neon_vshiftlu:
4296 case Intrinsic::arm_neon_vshiftn:
4297 case Intrinsic::arm_neon_vrshifts:
4298 case Intrinsic::arm_neon_vrshiftu:
4299 case Intrinsic::arm_neon_vrshiftn:
4300 case Intrinsic::arm_neon_vqshifts:
4301 case Intrinsic::arm_neon_vqshiftu:
4302 case Intrinsic::arm_neon_vqshiftsu:
4303 case Intrinsic::arm_neon_vqshiftns:
4304 case Intrinsic::arm_neon_vqshiftnu:
4305 case Intrinsic::arm_neon_vqshiftnsu:
4306 case Intrinsic::arm_neon_vqrshiftns:
4307 case Intrinsic::arm_neon_vqrshiftnu:
4308 case Intrinsic::arm_neon_vqrshiftnsu: {
4309 EVT VT = N->getOperand(1).getValueType();
4311 unsigned VShiftOpc = 0;
4314 case Intrinsic::arm_neon_vshifts:
4315 case Intrinsic::arm_neon_vshiftu:
4316 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4317 VShiftOpc = ARMISD::VSHL;
4320 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4321 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4322 ARMISD::VSHRs : ARMISD::VSHRu);
4327 case Intrinsic::arm_neon_vshiftls:
4328 case Intrinsic::arm_neon_vshiftlu:
4329 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4331 llvm_unreachable("invalid shift count for vshll intrinsic");
4333 case Intrinsic::arm_neon_vrshifts:
4334 case Intrinsic::arm_neon_vrshiftu:
4335 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4339 case Intrinsic::arm_neon_vqshifts:
4340 case Intrinsic::arm_neon_vqshiftu:
4341 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4345 case Intrinsic::arm_neon_vqshiftsu:
4346 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4348 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4350 case Intrinsic::arm_neon_vshiftn:
4351 case Intrinsic::arm_neon_vrshiftn:
4352 case Intrinsic::arm_neon_vqshiftns:
4353 case Intrinsic::arm_neon_vqshiftnu:
4354 case Intrinsic::arm_neon_vqshiftnsu:
4355 case Intrinsic::arm_neon_vqrshiftns:
4356 case Intrinsic::arm_neon_vqrshiftnu:
4357 case Intrinsic::arm_neon_vqrshiftnsu:
4358 // Narrowing shifts require an immediate right shift.
4359 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4361 llvm_unreachable("invalid shift count for narrowing vector shift "
4365 llvm_unreachable("unhandled vector shift");
4369 case Intrinsic::arm_neon_vshifts:
4370 case Intrinsic::arm_neon_vshiftu:
4371 // Opcode already set above.
4373 case Intrinsic::arm_neon_vshiftls:
4374 case Intrinsic::arm_neon_vshiftlu:
4375 if (Cnt == VT.getVectorElementType().getSizeInBits())
4376 VShiftOpc = ARMISD::VSHLLi;
4378 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4379 ARMISD::VSHLLs : ARMISD::VSHLLu);
4381 case Intrinsic::arm_neon_vshiftn:
4382 VShiftOpc = ARMISD::VSHRN; break;
4383 case Intrinsic::arm_neon_vrshifts:
4384 VShiftOpc = ARMISD::VRSHRs; break;
4385 case Intrinsic::arm_neon_vrshiftu:
4386 VShiftOpc = ARMISD::VRSHRu; break;
4387 case Intrinsic::arm_neon_vrshiftn:
4388 VShiftOpc = ARMISD::VRSHRN; break;
4389 case Intrinsic::arm_neon_vqshifts:
4390 VShiftOpc = ARMISD::VQSHLs; break;
4391 case Intrinsic::arm_neon_vqshiftu:
4392 VShiftOpc = ARMISD::VQSHLu; break;
4393 case Intrinsic::arm_neon_vqshiftsu:
4394 VShiftOpc = ARMISD::VQSHLsu; break;
4395 case Intrinsic::arm_neon_vqshiftns:
4396 VShiftOpc = ARMISD::VQSHRNs; break;
4397 case Intrinsic::arm_neon_vqshiftnu:
4398 VShiftOpc = ARMISD::VQSHRNu; break;
4399 case Intrinsic::arm_neon_vqshiftnsu:
4400 VShiftOpc = ARMISD::VQSHRNsu; break;
4401 case Intrinsic::arm_neon_vqrshiftns:
4402 VShiftOpc = ARMISD::VQRSHRNs; break;
4403 case Intrinsic::arm_neon_vqrshiftnu:
4404 VShiftOpc = ARMISD::VQRSHRNu; break;
4405 case Intrinsic::arm_neon_vqrshiftnsu:
4406 VShiftOpc = ARMISD::VQRSHRNsu; break;
4409 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4410 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4413 case Intrinsic::arm_neon_vshiftins: {
4414 EVT VT = N->getOperand(1).getValueType();
4416 unsigned VShiftOpc = 0;
4418 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4419 VShiftOpc = ARMISD::VSLI;
4420 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4421 VShiftOpc = ARMISD::VSRI;
4423 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4426 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4427 N->getOperand(1), N->getOperand(2),
4428 DAG.getConstant(Cnt, MVT::i32));
4431 case Intrinsic::arm_neon_vqrshifts:
4432 case Intrinsic::arm_neon_vqrshiftu:
4433 // No immediate versions of these to check for.
4440 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4441 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4442 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4443 /// vector element shift counts are generally not legal, and it is hard to see
4444 /// their values after they get legalized to loads from a constant pool.
4445 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4446 const ARMSubtarget *ST) {
4447 EVT VT = N->getValueType(0);
4449 // Nothing to be done for scalar shifts.
4450 if (! VT.isVector())
4453 assert(ST->hasNEON() && "unexpected vector shift");
4456 switch (N->getOpcode()) {
4457 default: llvm_unreachable("unexpected shift opcode");
4460 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4461 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4462 DAG.getConstant(Cnt, MVT::i32));
4467 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4468 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4469 ARMISD::VSHRs : ARMISD::VSHRu);
4470 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4471 DAG.getConstant(Cnt, MVT::i32));
4477 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4478 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4479 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4480 const ARMSubtarget *ST) {
4481 SDValue N0 = N->getOperand(0);
4483 // Check for sign- and zero-extensions of vector extract operations of 8-
4484 // and 16-bit vector elements. NEON supports these directly. They are
4485 // handled during DAG combining because type legalization will promote them
4486 // to 32-bit types and it is messy to recognize the operations after that.
4487 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4488 SDValue Vec = N0.getOperand(0);
4489 SDValue Lane = N0.getOperand(1);
4490 EVT VT = N->getValueType(0);
4491 EVT EltVT = N0.getValueType();
4492 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4494 if (VT == MVT::i32 &&
4495 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4496 TLI.isTypeLegal(Vec.getValueType())) {
4499 switch (N->getOpcode()) {
4500 default: llvm_unreachable("unexpected opcode");
4501 case ISD::SIGN_EXTEND:
4502 Opc = ARMISD::VGETLANEs;
4504 case ISD::ZERO_EXTEND:
4505 case ISD::ANY_EXTEND:
4506 Opc = ARMISD::VGETLANEu;
4509 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4516 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4517 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4518 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4519 const ARMSubtarget *ST) {
4520 // If the target supports NEON, try to use vmax/vmin instructions for f32
4521 // selects like "x < y ? x : y". Unless the FiniteOnlyFPMath option is set,
4522 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4523 // a NaN; only do the transformation when it matches that behavior.
4525 // For now only do this when using NEON for FP operations; if using VFP, it
4526 // is not obvious that the benefit outweighs the cost of switching to the
4528 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4529 N->getValueType(0) != MVT::f32)
4532 SDValue CondLHS = N->getOperand(0);
4533 SDValue CondRHS = N->getOperand(1);
4534 SDValue LHS = N->getOperand(2);
4535 SDValue RHS = N->getOperand(3);
4536 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4538 unsigned Opcode = 0;
4540 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4541 IsReversed = false; // x CC y ? x : y
4542 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4543 IsReversed = true ; // x CC y ? y : x
4557 // If LHS is NaN, an ordered comparison will be false and the result will
4558 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4559 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4560 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4561 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4563 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4564 // will return -0, so vmin can only be used for unsafe math or if one of
4565 // the operands is known to be nonzero.
4566 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4568 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4570 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4579 // If LHS is NaN, an ordered comparison will be false and the result will
4580 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4581 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4582 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4583 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4585 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4586 // will return +0, so vmax can only be used for unsafe math or if one of
4587 // the operands is known to be nonzero.
4588 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4590 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4592 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4598 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
4601 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
4602 DAGCombinerInfo &DCI) const {
4603 switch (N->getOpcode()) {
4605 case ISD::ADD: return PerformADDCombine(N, DCI);
4606 case ISD::SUB: return PerformSUBCombine(N, DCI);
4607 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
4608 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
4609 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
4612 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
4613 case ISD::SIGN_EXTEND:
4614 case ISD::ZERO_EXTEND:
4615 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
4616 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
4621 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
4622 if (!Subtarget->hasV6Ops())
4623 // Pre-v6 does not support unaligned mem access.
4626 // v6+ may or may not support unaligned mem access depending on the system
4628 // FIXME: This is pretty conservative. Should we provide cmdline option to
4629 // control the behaviour?
4630 if (!Subtarget->isTargetDarwin())
4633 switch (VT.getSimpleVT().SimpleTy) {
4640 // FIXME: VLD1 etc with standard alignment is legal.
4644 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
4649 switch (VT.getSimpleVT().SimpleTy) {
4650 default: return false;
4665 if ((V & (Scale - 1)) != 0)
4668 return V == (V & ((1LL << 5) - 1));
4671 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
4672 const ARMSubtarget *Subtarget) {
4679 switch (VT.getSimpleVT().SimpleTy) {
4680 default: return false;
4685 // + imm12 or - imm8
4687 return V == (V & ((1LL << 8) - 1));
4688 return V == (V & ((1LL << 12) - 1));
4691 // Same as ARM mode. FIXME: NEON?
4692 if (!Subtarget->hasVFP2())
4697 return V == (V & ((1LL << 8) - 1));
4701 /// isLegalAddressImmediate - Return true if the integer value can be used
4702 /// as the offset of the target addressing mode for load / store of the
4704 static bool isLegalAddressImmediate(int64_t V, EVT VT,
4705 const ARMSubtarget *Subtarget) {
4712 if (Subtarget->isThumb1Only())
4713 return isLegalT1AddressImmediate(V, VT);
4714 else if (Subtarget->isThumb2())
4715 return isLegalT2AddressImmediate(V, VT, Subtarget);
4720 switch (VT.getSimpleVT().SimpleTy) {
4721 default: return false;
4726 return V == (V & ((1LL << 12) - 1));
4729 return V == (V & ((1LL << 8) - 1));
4732 if (!Subtarget->hasVFP2()) // FIXME: NEON?
4737 return V == (V & ((1LL << 8) - 1));
4741 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
4743 int Scale = AM.Scale;
4747 switch (VT.getSimpleVT().SimpleTy) {
4748 default: return false;
4757 return Scale == 2 || Scale == 4 || Scale == 8;
4760 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4764 // Note, we allow "void" uses (basically, uses that aren't loads or
4765 // stores), because arm allows folding a scale into many arithmetic
4766 // operations. This should be made more precise and revisited later.
4768 // Allow r << imm, but the imm has to be a multiple of two.
4769 if (Scale & 1) return false;
4770 return isPowerOf2_32(Scale);
4774 /// isLegalAddressingMode - Return true if the addressing mode represented
4775 /// by AM is legal for this target, for a load/store of the specified type.
4776 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4777 const Type *Ty) const {
4778 EVT VT = getValueType(Ty, true);
4779 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
4782 // Can never fold addr of global into load/store.
4787 case 0: // no scale reg, must be "r+i" or "r", or "i".
4790 if (Subtarget->isThumb1Only())
4794 // ARM doesn't support any R+R*scale+imm addr modes.
4801 if (Subtarget->isThumb2())
4802 return isLegalT2ScaledAddressingMode(AM, VT);
4804 int Scale = AM.Scale;
4805 switch (VT.getSimpleVT().SimpleTy) {
4806 default: return false;
4810 if (Scale < 0) Scale = -Scale;
4814 return isPowerOf2_32(Scale & ~1);
4818 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4823 // Note, we allow "void" uses (basically, uses that aren't loads or
4824 // stores), because arm allows folding a scale into many arithmetic
4825 // operations. This should be made more precise and revisited later.
4827 // Allow r << imm, but the imm has to be a multiple of two.
4828 if (Scale & 1) return false;
4829 return isPowerOf2_32(Scale);
4836 /// isLegalICmpImmediate - Return true if the specified immediate is legal
4837 /// icmp immediate, that is the target has icmp instructions which can compare
4838 /// a register against the immediate without having to materialize the
4839 /// immediate into a register.
4840 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
4841 if (!Subtarget->isThumb())
4842 return ARM_AM::getSOImmVal(Imm) != -1;
4843 if (Subtarget->isThumb2())
4844 return ARM_AM::getT2SOImmVal(Imm) != -1;
4845 return Imm >= 0 && Imm <= 255;
4848 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
4849 bool isSEXTLoad, SDValue &Base,
4850 SDValue &Offset, bool &isInc,
4851 SelectionDAG &DAG) {
4852 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4855 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
4857 Base = Ptr->getOperand(0);
4858 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4859 int RHSC = (int)RHS->getZExtValue();
4860 if (RHSC < 0 && RHSC > -256) {
4861 assert(Ptr->getOpcode() == ISD::ADD);
4863 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4867 isInc = (Ptr->getOpcode() == ISD::ADD);
4868 Offset = Ptr->getOperand(1);
4870 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
4872 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4873 int RHSC = (int)RHS->getZExtValue();
4874 if (RHSC < 0 && RHSC > -0x1000) {
4875 assert(Ptr->getOpcode() == ISD::ADD);
4877 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4878 Base = Ptr->getOperand(0);
4883 if (Ptr->getOpcode() == ISD::ADD) {
4885 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
4886 if (ShOpcVal != ARM_AM::no_shift) {
4887 Base = Ptr->getOperand(1);
4888 Offset = Ptr->getOperand(0);
4890 Base = Ptr->getOperand(0);
4891 Offset = Ptr->getOperand(1);
4896 isInc = (Ptr->getOpcode() == ISD::ADD);
4897 Base = Ptr->getOperand(0);
4898 Offset = Ptr->getOperand(1);
4902 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
4906 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
4907 bool isSEXTLoad, SDValue &Base,
4908 SDValue &Offset, bool &isInc,
4909 SelectionDAG &DAG) {
4910 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4913 Base = Ptr->getOperand(0);
4914 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4915 int RHSC = (int)RHS->getZExtValue();
4916 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
4917 assert(Ptr->getOpcode() == ISD::ADD);
4919 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4921 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
4922 isInc = Ptr->getOpcode() == ISD::ADD;
4923 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
4931 /// getPreIndexedAddressParts - returns true by value, base pointer and
4932 /// offset pointer and addressing mode by reference if the node's address
4933 /// can be legally represented as pre-indexed load / store address.
4935 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
4937 ISD::MemIndexedMode &AM,
4938 SelectionDAG &DAG) const {
4939 if (Subtarget->isThumb1Only())
4944 bool isSEXTLoad = false;
4945 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4946 Ptr = LD->getBasePtr();
4947 VT = LD->getMemoryVT();
4948 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4949 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4950 Ptr = ST->getBasePtr();
4951 VT = ST->getMemoryVT();
4956 bool isLegal = false;
4957 if (Subtarget->isThumb2())
4958 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4959 Offset, isInc, DAG);
4961 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4962 Offset, isInc, DAG);
4966 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
4970 /// getPostIndexedAddressParts - returns true by value, base pointer and
4971 /// offset pointer and addressing mode by reference if this node can be
4972 /// combined with a load / store to form a post-indexed load / store.
4973 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
4976 ISD::MemIndexedMode &AM,
4977 SelectionDAG &DAG) const {
4978 if (Subtarget->isThumb1Only())
4983 bool isSEXTLoad = false;
4984 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4985 VT = LD->getMemoryVT();
4986 Ptr = LD->getBasePtr();
4987 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4988 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4989 VT = ST->getMemoryVT();
4990 Ptr = ST->getBasePtr();
4995 bool isLegal = false;
4996 if (Subtarget->isThumb2())
4997 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5000 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5006 // Swap base ptr and offset to catch more post-index load / store when
5007 // it's legal. In Thumb2 mode, offset must be an immediate.
5008 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5009 !Subtarget->isThumb2())
5010 std::swap(Base, Offset);
5012 // Post-indexed load / store update the base pointer.
5017 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5021 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5025 const SelectionDAG &DAG,
5026 unsigned Depth) const {
5027 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5028 switch (Op.getOpcode()) {
5030 case ARMISD::CMOV: {
5031 // Bits are known zero/one if known on the LHS and RHS.
5032 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5033 if (KnownZero == 0 && KnownOne == 0) return;
5035 APInt KnownZeroRHS, KnownOneRHS;
5036 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5037 KnownZeroRHS, KnownOneRHS, Depth+1);
5038 KnownZero &= KnownZeroRHS;
5039 KnownOne &= KnownOneRHS;
5045 //===----------------------------------------------------------------------===//
5046 // ARM Inline Assembly Support
5047 //===----------------------------------------------------------------------===//
5049 /// getConstraintType - Given a constraint letter, return the type of
5050 /// constraint it is for this target.
5051 ARMTargetLowering::ConstraintType
5052 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5053 if (Constraint.size() == 1) {
5054 switch (Constraint[0]) {
5056 case 'l': return C_RegisterClass;
5057 case 'w': return C_RegisterClass;
5060 return TargetLowering::getConstraintType(Constraint);
5063 std::pair<unsigned, const TargetRegisterClass*>
5064 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5066 if (Constraint.size() == 1) {
5067 // GCC ARM Constraint Letters
5068 switch (Constraint[0]) {
5070 if (Subtarget->isThumb())
5071 return std::make_pair(0U, ARM::tGPRRegisterClass);
5073 return std::make_pair(0U, ARM::GPRRegisterClass);
5075 return std::make_pair(0U, ARM::GPRRegisterClass);
5078 return std::make_pair(0U, ARM::SPRRegisterClass);
5079 if (VT.getSizeInBits() == 64)
5080 return std::make_pair(0U, ARM::DPRRegisterClass);
5081 if (VT.getSizeInBits() == 128)
5082 return std::make_pair(0U, ARM::QPRRegisterClass);
5086 if (StringRef("{cc}").equals_lower(Constraint))
5087 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5089 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5092 std::vector<unsigned> ARMTargetLowering::
5093 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5095 if (Constraint.size() != 1)
5096 return std::vector<unsigned>();
5098 switch (Constraint[0]) { // GCC ARM Constraint Letters
5101 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5102 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5105 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5106 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5107 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5108 ARM::R12, ARM::LR, 0);
5111 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5112 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5113 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5114 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5115 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5116 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5117 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5118 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5119 if (VT.getSizeInBits() == 64)
5120 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5121 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5122 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5123 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5124 if (VT.getSizeInBits() == 128)
5125 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5126 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5130 return std::vector<unsigned>();
5133 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5134 /// vector. If it is invalid, don't add anything to Ops.
5135 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5137 std::vector<SDValue>&Ops,
5138 SelectionDAG &DAG) const {
5139 SDValue Result(0, 0);
5141 switch (Constraint) {
5143 case 'I': case 'J': case 'K': case 'L':
5144 case 'M': case 'N': case 'O':
5145 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5149 int64_t CVal64 = C->getSExtValue();
5150 int CVal = (int) CVal64;
5151 // None of these constraints allow values larger than 32 bits. Check
5152 // that the value fits in an int.
5156 switch (Constraint) {
5158 if (Subtarget->isThumb1Only()) {
5159 // This must be a constant between 0 and 255, for ADD
5161 if (CVal >= 0 && CVal <= 255)
5163 } else if (Subtarget->isThumb2()) {
5164 // A constant that can be used as an immediate value in a
5165 // data-processing instruction.
5166 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5169 // A constant that can be used as an immediate value in a
5170 // data-processing instruction.
5171 if (ARM_AM::getSOImmVal(CVal) != -1)
5177 if (Subtarget->isThumb()) { // FIXME thumb2
5178 // This must be a constant between -255 and -1, for negated ADD
5179 // immediates. This can be used in GCC with an "n" modifier that
5180 // prints the negated value, for use with SUB instructions. It is
5181 // not useful otherwise but is implemented for compatibility.
5182 if (CVal >= -255 && CVal <= -1)
5185 // This must be a constant between -4095 and 4095. It is not clear
5186 // what this constraint is intended for. Implemented for
5187 // compatibility with GCC.
5188 if (CVal >= -4095 && CVal <= 4095)
5194 if (Subtarget->isThumb1Only()) {
5195 // A 32-bit value where only one byte has a nonzero value. Exclude
5196 // zero to match GCC. This constraint is used by GCC internally for
5197 // constants that can be loaded with a move/shift combination.
5198 // It is not useful otherwise but is implemented for compatibility.
5199 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5201 } else if (Subtarget->isThumb2()) {
5202 // A constant whose bitwise inverse can be used as an immediate
5203 // value in a data-processing instruction. This can be used in GCC
5204 // with a "B" modifier that prints the inverted value, for use with
5205 // BIC and MVN instructions. It is not useful otherwise but is
5206 // implemented for compatibility.
5207 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5210 // A constant whose bitwise inverse can be used as an immediate
5211 // value in a data-processing instruction. This can be used in GCC
5212 // with a "B" modifier that prints the inverted value, for use with
5213 // BIC and MVN instructions. It is not useful otherwise but is
5214 // implemented for compatibility.
5215 if (ARM_AM::getSOImmVal(~CVal) != -1)
5221 if (Subtarget->isThumb1Only()) {
5222 // This must be a constant between -7 and 7,
5223 // for 3-operand ADD/SUB immediate instructions.
5224 if (CVal >= -7 && CVal < 7)
5226 } else if (Subtarget->isThumb2()) {
5227 // A constant whose negation can be used as an immediate value in a
5228 // data-processing instruction. This can be used in GCC with an "n"
5229 // modifier that prints the negated value, for use with SUB
5230 // instructions. It is not useful otherwise but is implemented for
5232 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5235 // A constant whose negation can be used as an immediate value in a
5236 // data-processing instruction. This can be used in GCC with an "n"
5237 // modifier that prints the negated value, for use with SUB
5238 // instructions. It is not useful otherwise but is implemented for
5240 if (ARM_AM::getSOImmVal(-CVal) != -1)
5246 if (Subtarget->isThumb()) { // FIXME thumb2
5247 // This must be a multiple of 4 between 0 and 1020, for
5248 // ADD sp + immediate.
5249 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5252 // A power of two or a constant between 0 and 32. This is used in
5253 // GCC for the shift amount on shifted register operands, but it is
5254 // useful in general for any shift amounts.
5255 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5261 if (Subtarget->isThumb()) { // FIXME thumb2
5262 // This must be a constant between 0 and 31, for shift amounts.
5263 if (CVal >= 0 && CVal <= 31)
5269 if (Subtarget->isThumb()) { // FIXME thumb2
5270 // This must be a multiple of 4 between -508 and 508, for
5271 // ADD/SUB sp = sp + immediate.
5272 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5277 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5281 if (Result.getNode()) {
5282 Ops.push_back(Result);
5285 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5289 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5290 // The ARM target isn't yet aware of offsets.
5294 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5295 APInt Imm = FPImm.bitcastToAPInt();
5296 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5297 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5298 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5300 // We can handle 4 bits of mantissa.
5301 // mantissa = (16+UInt(e:f:g:h))/16.
5302 if (Mantissa & 0x7ffff)
5305 if ((Mantissa & 0xf) != Mantissa)
5308 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5309 if (Exp < -3 || Exp > 4)
5311 Exp = ((Exp+3) & 0x7) ^ 4;
5313 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5316 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5317 APInt Imm = FPImm.bitcastToAPInt();
5318 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5319 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5320 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5322 // We can handle 4 bits of mantissa.
5323 // mantissa = (16+UInt(e:f:g:h))/16.
5324 if (Mantissa & 0xffffffffffffLL)
5327 if ((Mantissa & 0xf) != Mantissa)
5330 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5331 if (Exp < -3 || Exp > 4)
5333 Exp = ((Exp+3) & 0x7) ^ 4;
5335 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5338 /// isFPImmLegal - Returns true if the target can instruction select the
5339 /// specified FP immediate natively. If false, the legalizer will
5340 /// materialize the FP immediate as a load from a constant pool.
5341 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5342 if (!Subtarget->hasVFP3())
5345 return ARM::getVFPf32Imm(Imm) != -1;
5347 return ARM::getVFPf64Imm(Imm) != -1;