1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Function.h"
27 #include "llvm/Instruction.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/MachineBasicBlock.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/VectorExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/MathExtras.h"
44 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
48 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
49 CCValAssign::LocInfo &LocInfo,
50 ISD::ArgFlagsTy &ArgFlags,
52 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
53 CCValAssign::LocInfo &LocInfo,
54 ISD::ArgFlagsTy &ArgFlags,
56 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
57 CCValAssign::LocInfo &LocInfo,
58 ISD::ArgFlagsTy &ArgFlags,
61 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
62 EVT PromotedBitwiseVT) {
63 if (VT != PromotedLdStVT) {
64 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
65 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
66 PromotedLdStVT.getSimpleVT());
68 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
69 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
70 PromotedLdStVT.getSimpleVT());
73 EVT ElemTy = VT.getVectorElementType();
74 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
75 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
76 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
77 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
78 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
79 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
80 setOperationAction(ISD::SCALAR_TO_VECTOR, VT.getSimpleVT(), Custom);
81 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
83 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
84 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
85 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
88 // Promote all bit-wise operations.
89 if (VT.isInteger() && VT != PromotedBitwiseVT) {
90 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
91 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
92 PromotedBitwiseVT.getSimpleVT());
93 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
94 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
95 PromotedBitwiseVT.getSimpleVT());
96 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
97 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
98 PromotedBitwiseVT.getSimpleVT());
102 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
103 addRegisterClass(VT, ARM::DPRRegisterClass);
104 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
107 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
108 addRegisterClass(VT, ARM::QPRRegisterClass);
109 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
112 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
113 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
114 return new TargetLoweringObjectFileMachO();
115 return new ARMElfTargetObjectFile();
118 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
119 : TargetLowering(TM, createTLOF(TM)), ARMPCLabelIndex(0) {
120 Subtarget = &TM.getSubtarget<ARMSubtarget>();
122 if (Subtarget->isTargetDarwin()) {
123 // Uses VFP for Thumb libfuncs if available.
124 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
125 // Single-precision floating-point arithmetic.
126 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
127 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
128 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
129 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
131 // Double-precision floating-point arithmetic.
132 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
133 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
134 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
135 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
137 // Single-precision comparisons.
138 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
139 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
140 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
141 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
142 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
143 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
144 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
145 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
147 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
148 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
149 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
150 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
151 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
152 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
153 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
154 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
156 // Double-precision comparisons.
157 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
158 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
159 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
160 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
161 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
162 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
163 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
164 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
166 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
167 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
168 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
169 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
170 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
171 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
172 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
173 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
175 // Floating-point to integer conversions.
176 // i64 conversions are done via library routines even when generating VFP
177 // instructions, so use the same ones.
178 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
179 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
180 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
181 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
183 // Conversions between floating types.
184 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
185 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
187 // Integer to floating-point conversions.
188 // i64 conversions are done via library routines even when generating VFP
189 // instructions, so use the same ones.
190 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
191 // e.g., __floatunsidf vs. __floatunssidfvfp.
192 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
193 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
194 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
195 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
199 // These libcalls are not available in 32-bit.
200 setLibcallName(RTLIB::SHL_I128, 0);
201 setLibcallName(RTLIB::SRL_I128, 0);
202 setLibcallName(RTLIB::SRA_I128, 0);
204 if (Subtarget->isThumb1Only())
205 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
207 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
208 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
209 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
210 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
212 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
215 if (Subtarget->hasNEON()) {
216 addDRTypeForNEON(MVT::v2f32);
217 addDRTypeForNEON(MVT::v8i8);
218 addDRTypeForNEON(MVT::v4i16);
219 addDRTypeForNEON(MVT::v2i32);
220 addDRTypeForNEON(MVT::v1i64);
222 addQRTypeForNEON(MVT::v4f32);
223 addQRTypeForNEON(MVT::v2f64);
224 addQRTypeForNEON(MVT::v16i8);
225 addQRTypeForNEON(MVT::v8i16);
226 addQRTypeForNEON(MVT::v4i32);
227 addQRTypeForNEON(MVT::v2i64);
229 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
230 setTargetDAGCombine(ISD::SHL);
231 setTargetDAGCombine(ISD::SRL);
232 setTargetDAGCombine(ISD::SRA);
233 setTargetDAGCombine(ISD::SIGN_EXTEND);
234 setTargetDAGCombine(ISD::ZERO_EXTEND);
235 setTargetDAGCombine(ISD::ANY_EXTEND);
238 computeRegisterProperties();
240 // ARM does not have f32 extending load.
241 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
243 // ARM does not have i1 sign extending load.
244 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
246 // ARM supports all 4 flavors of integer indexed load / store.
247 if (!Subtarget->isThumb1Only()) {
248 for (unsigned im = (unsigned)ISD::PRE_INC;
249 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
250 setIndexedLoadAction(im, MVT::i1, Legal);
251 setIndexedLoadAction(im, MVT::i8, Legal);
252 setIndexedLoadAction(im, MVT::i16, Legal);
253 setIndexedLoadAction(im, MVT::i32, Legal);
254 setIndexedStoreAction(im, MVT::i1, Legal);
255 setIndexedStoreAction(im, MVT::i8, Legal);
256 setIndexedStoreAction(im, MVT::i16, Legal);
257 setIndexedStoreAction(im, MVT::i32, Legal);
261 // i64 operation support.
262 if (Subtarget->isThumb1Only()) {
263 setOperationAction(ISD::MUL, MVT::i64, Expand);
264 setOperationAction(ISD::MULHU, MVT::i32, Expand);
265 setOperationAction(ISD::MULHS, MVT::i32, Expand);
266 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
267 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
269 setOperationAction(ISD::MUL, MVT::i64, Expand);
270 setOperationAction(ISD::MULHU, MVT::i32, Expand);
271 if (!Subtarget->hasV6Ops())
272 setOperationAction(ISD::MULHS, MVT::i32, Expand);
274 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
275 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
276 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
277 setOperationAction(ISD::SRL, MVT::i64, Custom);
278 setOperationAction(ISD::SRA, MVT::i64, Custom);
280 // ARM does not have ROTL.
281 setOperationAction(ISD::ROTL, MVT::i32, Expand);
282 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
283 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
284 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
285 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
287 // Only ARMv6 has BSWAP.
288 if (!Subtarget->hasV6Ops())
289 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
291 // These are expanded into libcalls.
292 setOperationAction(ISD::SDIV, MVT::i32, Expand);
293 setOperationAction(ISD::UDIV, MVT::i32, Expand);
294 setOperationAction(ISD::SREM, MVT::i32, Expand);
295 setOperationAction(ISD::UREM, MVT::i32, Expand);
296 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
297 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
299 // Support label based line numbers.
300 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
301 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
303 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
304 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
305 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
306 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
308 // Use the default implementation.
309 setOperationAction(ISD::VASTART, MVT::Other, Custom);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
311 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
312 setOperationAction(ISD::VAEND, MVT::Other, Expand);
313 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
314 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
315 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
316 // FIXME: Shouldn't need this, since no register is used, but the legalizer
317 // doesn't yet know how to not do that for SjLj.
318 setExceptionSelectorRegister(ARM::R0);
319 if (Subtarget->isThumb())
320 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
322 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
323 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
325 if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
326 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
327 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
329 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
331 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
332 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
333 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
335 // We want to custom lower some of our intrinsics.
336 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
337 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
338 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
340 setOperationAction(ISD::SETCC, MVT::i32, Expand);
341 setOperationAction(ISD::SETCC, MVT::f32, Expand);
342 setOperationAction(ISD::SETCC, MVT::f64, Expand);
343 setOperationAction(ISD::SELECT, MVT::i32, Expand);
344 setOperationAction(ISD::SELECT, MVT::f32, Expand);
345 setOperationAction(ISD::SELECT, MVT::f64, Expand);
346 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
347 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
348 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
350 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
351 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
352 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
353 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
354 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
356 // We don't support sin/cos/fmod/copysign/pow
357 setOperationAction(ISD::FSIN, MVT::f64, Expand);
358 setOperationAction(ISD::FSIN, MVT::f32, Expand);
359 setOperationAction(ISD::FCOS, MVT::f32, Expand);
360 setOperationAction(ISD::FCOS, MVT::f64, Expand);
361 setOperationAction(ISD::FREM, MVT::f64, Expand);
362 setOperationAction(ISD::FREM, MVT::f32, Expand);
363 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
364 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
365 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
367 setOperationAction(ISD::FPOW, MVT::f64, Expand);
368 setOperationAction(ISD::FPOW, MVT::f32, Expand);
370 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
371 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
372 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
373 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
375 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
378 // We have target-specific dag combine patterns for the following nodes:
379 // ARMISD::FMRRD - No need to call setTargetDAGCombine
380 setTargetDAGCombine(ISD::ADD);
381 setTargetDAGCombine(ISD::SUB);
383 setStackPointerRegisterToSaveRestore(ARM::SP);
384 setSchedulingPreference(SchedulingForRegPressure);
385 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
386 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
388 if (!Subtarget->isThumb()) {
389 // Use branch latency information to determine if-conversion limits.
390 // FIXME: If-converter should use instruction latency of the branch being
391 // eliminated to compute the threshold. For ARMv6, the branch "latency"
392 // varies depending on whether it's dynamically or statically predicted
393 // and on whether the destination is in the prefetch buffer.
394 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
395 const InstrItineraryData &InstrItins = Subtarget->getInstrItineraryData();
396 unsigned Latency= InstrItins.getLatency(TII->get(ARM::Bcc).getSchedClass());
398 setIfCvtBlockSizeLimit(Latency-1);
400 setIfCvtDupBlockSizeLimit(Latency-2);
402 setIfCvtBlockSizeLimit(10);
403 setIfCvtDupBlockSizeLimit(2);
407 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
408 // Do not enable CodePlacementOpt for now: it currently runs after the
409 // ARMConstantIslandPass and messes up branch relaxation and placement
410 // of constant islands.
411 // benefitFromCodePlacementOpt = true;
414 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
417 case ARMISD::Wrapper: return "ARMISD::Wrapper";
418 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
419 case ARMISD::CALL: return "ARMISD::CALL";
420 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
421 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
422 case ARMISD::tCALL: return "ARMISD::tCALL";
423 case ARMISD::BRCOND: return "ARMISD::BRCOND";
424 case ARMISD::BR_JT: return "ARMISD::BR_JT";
425 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
426 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
427 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
428 case ARMISD::CMP: return "ARMISD::CMP";
429 case ARMISD::CMPZ: return "ARMISD::CMPZ";
430 case ARMISD::CMPFP: return "ARMISD::CMPFP";
431 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
432 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
433 case ARMISD::CMOV: return "ARMISD::CMOV";
434 case ARMISD::CNEG: return "ARMISD::CNEG";
436 case ARMISD::FTOSI: return "ARMISD::FTOSI";
437 case ARMISD::FTOUI: return "ARMISD::FTOUI";
438 case ARMISD::SITOF: return "ARMISD::SITOF";
439 case ARMISD::UITOF: return "ARMISD::UITOF";
441 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
442 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
443 case ARMISD::RRX: return "ARMISD::RRX";
445 case ARMISD::FMRRD: return "ARMISD::FMRRD";
446 case ARMISD::FMDRR: return "ARMISD::FMDRR";
448 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
450 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
452 case ARMISD::VCEQ: return "ARMISD::VCEQ";
453 case ARMISD::VCGE: return "ARMISD::VCGE";
454 case ARMISD::VCGEU: return "ARMISD::VCGEU";
455 case ARMISD::VCGT: return "ARMISD::VCGT";
456 case ARMISD::VCGTU: return "ARMISD::VCGTU";
457 case ARMISD::VTST: return "ARMISD::VTST";
459 case ARMISD::VSHL: return "ARMISD::VSHL";
460 case ARMISD::VSHRs: return "ARMISD::VSHRs";
461 case ARMISD::VSHRu: return "ARMISD::VSHRu";
462 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
463 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
464 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
465 case ARMISD::VSHRN: return "ARMISD::VSHRN";
466 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
467 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
468 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
469 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
470 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
471 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
472 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
473 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
474 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
475 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
476 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
477 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
478 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
479 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
480 case ARMISD::VDUPLANEQ: return "ARMISD::VDUPLANEQ";
481 case ARMISD::VLD2D: return "ARMISD::VLD2D";
482 case ARMISD::VLD3D: return "ARMISD::VLD3D";
483 case ARMISD::VLD4D: return "ARMISD::VLD4D";
484 case ARMISD::VST2D: return "ARMISD::VST2D";
485 case ARMISD::VST3D: return "ARMISD::VST3D";
486 case ARMISD::VST4D: return "ARMISD::VST4D";
487 case ARMISD::VREV64: return "ARMISD::VREV64";
488 case ARMISD::VREV32: return "ARMISD::VREV32";
489 case ARMISD::VREV16: return "ARMISD::VREV16";
493 /// getFunctionAlignment - Return the Log2 alignment of this function.
494 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
495 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
498 //===----------------------------------------------------------------------===//
500 //===----------------------------------------------------------------------===//
502 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
503 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
505 default: llvm_unreachable("Unknown condition code!");
506 case ISD::SETNE: return ARMCC::NE;
507 case ISD::SETEQ: return ARMCC::EQ;
508 case ISD::SETGT: return ARMCC::GT;
509 case ISD::SETGE: return ARMCC::GE;
510 case ISD::SETLT: return ARMCC::LT;
511 case ISD::SETLE: return ARMCC::LE;
512 case ISD::SETUGT: return ARMCC::HI;
513 case ISD::SETUGE: return ARMCC::HS;
514 case ISD::SETULT: return ARMCC::LO;
515 case ISD::SETULE: return ARMCC::LS;
519 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
520 /// returns true if the operands should be inverted to form the proper
522 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
523 ARMCC::CondCodes &CondCode2) {
525 CondCode2 = ARMCC::AL;
527 default: llvm_unreachable("Unknown FP condition!");
529 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
531 case ISD::SETOGT: CondCode = ARMCC::GT; break;
533 case ISD::SETOGE: CondCode = ARMCC::GE; break;
534 case ISD::SETOLT: CondCode = ARMCC::MI; break;
535 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
536 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
537 case ISD::SETO: CondCode = ARMCC::VC; break;
538 case ISD::SETUO: CondCode = ARMCC::VS; break;
539 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
540 case ISD::SETUGT: CondCode = ARMCC::HI; break;
541 case ISD::SETUGE: CondCode = ARMCC::PL; break;
543 case ISD::SETULT: CondCode = ARMCC::LT; break;
545 case ISD::SETULE: CondCode = ARMCC::LE; break;
547 case ISD::SETUNE: CondCode = ARMCC::NE; break;
552 //===----------------------------------------------------------------------===//
553 // Calling Convention Implementation
554 //===----------------------------------------------------------------------===//
556 #include "ARMGenCallingConv.inc"
558 // APCS f64 is in register pairs, possibly split to stack
559 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
560 CCValAssign::LocInfo &LocInfo,
561 CCState &State, bool CanFail) {
562 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
564 // Try to get the first register.
565 if (unsigned Reg = State.AllocateReg(RegList, 4))
566 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
568 // For the 2nd half of a v2f64, do not fail.
572 // Put the whole thing on the stack.
573 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
574 State.AllocateStack(8, 4),
579 // Try to get the second register.
580 if (unsigned Reg = State.AllocateReg(RegList, 4))
581 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
583 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
584 State.AllocateStack(4, 4),
589 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
590 CCValAssign::LocInfo &LocInfo,
591 ISD::ArgFlagsTy &ArgFlags,
593 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
595 if (LocVT == MVT::v2f64 &&
596 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
598 return true; // we handled it
601 // AAPCS f64 is in aligned register pairs
602 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
603 CCValAssign::LocInfo &LocInfo,
604 CCState &State, bool CanFail) {
605 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
606 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
608 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
610 // For the 2nd half of a v2f64, do not just fail.
614 // Put the whole thing on the stack.
615 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
616 State.AllocateStack(8, 8),
622 for (i = 0; i < 2; ++i)
623 if (HiRegList[i] == Reg)
626 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
627 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
632 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
633 CCValAssign::LocInfo &LocInfo,
634 ISD::ArgFlagsTy &ArgFlags,
636 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
638 if (LocVT == MVT::v2f64 &&
639 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
641 return true; // we handled it
644 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
645 CCValAssign::LocInfo &LocInfo, CCState &State) {
646 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
647 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
649 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
651 return false; // we didn't handle it
654 for (i = 0; i < 2; ++i)
655 if (HiRegList[i] == Reg)
658 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
659 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
664 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
665 CCValAssign::LocInfo &LocInfo,
666 ISD::ArgFlagsTy &ArgFlags,
668 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
670 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
672 return true; // we handled it
675 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
676 CCValAssign::LocInfo &LocInfo,
677 ISD::ArgFlagsTy &ArgFlags,
679 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
683 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
684 /// given CallingConvention value.
685 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
687 bool isVarArg) const {
690 llvm_unreachable("Unsupported calling convention");
692 case CallingConv::Fast:
693 // Use target triple & subtarget features to do actual dispatch.
694 if (Subtarget->isAAPCS_ABI()) {
695 if (Subtarget->hasVFP2() &&
696 FloatABIType == FloatABI::Hard && !isVarArg)
697 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
699 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
701 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
702 case CallingConv::ARM_AAPCS_VFP:
703 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
704 case CallingConv::ARM_AAPCS:
705 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
706 case CallingConv::ARM_APCS:
707 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
711 /// LowerCallResult - Lower the result values of a call into the
712 /// appropriate copies out of appropriate physical registers.
714 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
715 unsigned CallConv, bool isVarArg,
716 const SmallVectorImpl<ISD::InputArg> &Ins,
717 DebugLoc dl, SelectionDAG &DAG,
718 SmallVectorImpl<SDValue> &InVals) {
720 // Assign locations to each value returned by this call.
721 SmallVector<CCValAssign, 16> RVLocs;
722 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
723 RVLocs, *DAG.getContext());
724 CCInfo.AnalyzeCallResult(Ins,
725 CCAssignFnForNode(CallConv, /* Return*/ true,
728 // Copy all of the result registers out of their specified physreg.
729 for (unsigned i = 0; i != RVLocs.size(); ++i) {
730 CCValAssign VA = RVLocs[i];
733 if (VA.needsCustom()) {
734 // Handle f64 or half of a v2f64.
735 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
737 Chain = Lo.getValue(1);
738 InFlag = Lo.getValue(2);
739 VA = RVLocs[++i]; // skip ahead to next loc
740 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
742 Chain = Hi.getValue(1);
743 InFlag = Hi.getValue(2);
744 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
746 if (VA.getLocVT() == MVT::v2f64) {
747 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
748 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
749 DAG.getConstant(0, MVT::i32));
751 VA = RVLocs[++i]; // skip ahead to next loc
752 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
753 Chain = Lo.getValue(1);
754 InFlag = Lo.getValue(2);
755 VA = RVLocs[++i]; // skip ahead to next loc
756 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
757 Chain = Hi.getValue(1);
758 InFlag = Hi.getValue(2);
759 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
760 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
761 DAG.getConstant(1, MVT::i32));
764 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
766 Chain = Val.getValue(1);
767 InFlag = Val.getValue(2);
770 switch (VA.getLocInfo()) {
771 default: llvm_unreachable("Unknown loc info!");
772 case CCValAssign::Full: break;
773 case CCValAssign::BCvt:
774 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
778 InVals.push_back(Val);
784 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
785 /// by "Src" to address "Dst" of size "Size". Alignment information is
786 /// specified by the specific parameter attribute. The copy will be passed as
787 /// a byval function parameter.
788 /// Sometimes what we are copying is the end of a larger object, the part that
789 /// does not fit in registers.
791 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
792 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
794 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
795 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
796 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
799 /// LowerMemOpCallTo - Store the argument to the stack.
801 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
802 SDValue StackPtr, SDValue Arg,
803 DebugLoc dl, SelectionDAG &DAG,
804 const CCValAssign &VA,
805 ISD::ArgFlagsTy Flags) {
806 unsigned LocMemOffset = VA.getLocMemOffset();
807 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
808 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
809 if (Flags.isByVal()) {
810 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
812 return DAG.getStore(Chain, dl, Arg, PtrOff,
813 PseudoSourceValue::getStack(), LocMemOffset);
816 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
817 SDValue Chain, SDValue &Arg,
818 RegsToPassVector &RegsToPass,
819 CCValAssign &VA, CCValAssign &NextVA,
821 SmallVector<SDValue, 8> &MemOpChains,
822 ISD::ArgFlagsTy Flags) {
824 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
825 DAG.getVTList(MVT::i32, MVT::i32), Arg);
826 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
828 if (NextVA.isRegLoc())
829 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
831 assert(NextVA.isMemLoc());
832 if (StackPtr.getNode() == 0)
833 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
835 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
841 /// LowerCall - Lowering a call into a callseq_start <-
842 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
845 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
846 unsigned CallConv, bool isVarArg,
848 const SmallVectorImpl<ISD::OutputArg> &Outs,
849 const SmallVectorImpl<ISD::InputArg> &Ins,
850 DebugLoc dl, SelectionDAG &DAG,
851 SmallVectorImpl<SDValue> &InVals) {
853 // Analyze operands of the call, assigning locations to each operand.
854 SmallVector<CCValAssign, 16> ArgLocs;
855 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
857 CCInfo.AnalyzeCallOperands(Outs,
858 CCAssignFnForNode(CallConv, /* Return*/ false,
861 // Get a count of how many bytes are to be pushed on the stack.
862 unsigned NumBytes = CCInfo.getNextStackOffset();
864 // Adjust the stack pointer for the new arguments...
865 // These operations are automatically eliminated by the prolog/epilog pass
866 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
868 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
870 RegsToPassVector RegsToPass;
871 SmallVector<SDValue, 8> MemOpChains;
873 // Walk the register/memloc assignments, inserting copies/loads. In the case
874 // of tail call optimization, arguments are handled later.
875 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
878 CCValAssign &VA = ArgLocs[i];
879 SDValue Arg = Outs[realArgIdx].Val;
880 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
882 // Promote the value if needed.
883 switch (VA.getLocInfo()) {
884 default: llvm_unreachable("Unknown loc info!");
885 case CCValAssign::Full: break;
886 case CCValAssign::SExt:
887 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
889 case CCValAssign::ZExt:
890 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
892 case CCValAssign::AExt:
893 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
895 case CCValAssign::BCvt:
896 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
900 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
901 if (VA.needsCustom()) {
902 if (VA.getLocVT() == MVT::v2f64) {
903 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
904 DAG.getConstant(0, MVT::i32));
905 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
906 DAG.getConstant(1, MVT::i32));
908 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
909 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
911 VA = ArgLocs[++i]; // skip ahead to next loc
913 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
914 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
916 assert(VA.isMemLoc());
917 if (StackPtr.getNode() == 0)
918 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
920 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
921 dl, DAG, VA, Flags));
924 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
925 StackPtr, MemOpChains, Flags);
927 } else if (VA.isRegLoc()) {
928 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
930 assert(VA.isMemLoc());
931 if (StackPtr.getNode() == 0)
932 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
934 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
935 dl, DAG, VA, Flags));
939 if (!MemOpChains.empty())
940 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
941 &MemOpChains[0], MemOpChains.size());
943 // Build a sequence of copy-to-reg nodes chained together with token chain
944 // and flag operands which copy the outgoing args into the appropriate regs.
946 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
947 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
948 RegsToPass[i].second, InFlag);
949 InFlag = Chain.getValue(1);
952 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
953 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
954 // node so that legalize doesn't hack it.
955 bool isDirect = false;
956 bool isARMFunc = false;
957 bool isLocalARMFunc = false;
958 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
959 GlobalValue *GV = G->getGlobal();
961 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
962 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
963 getTargetMachine().getRelocationModel() != Reloc::Static;
964 isARMFunc = !Subtarget->isThumb() || isStub;
965 // ARM call to a local ARM function is predicable.
966 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
967 // tBX takes a register source operand.
968 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
969 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
971 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
972 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
973 Callee = DAG.getLoad(getPointerTy(), dl,
974 DAG.getEntryNode(), CPAddr, NULL, 0);
975 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
976 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
977 getPointerTy(), Callee, PICLabel);
979 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
980 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
982 bool isStub = Subtarget->isTargetDarwin() &&
983 getTargetMachine().getRelocationModel() != Reloc::Static;
984 isARMFunc = !Subtarget->isThumb() || isStub;
985 // tBX takes a register source operand.
986 const char *Sym = S->getSymbol();
987 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
988 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
990 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
991 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
992 Callee = DAG.getLoad(getPointerTy(), dl,
993 DAG.getEntryNode(), CPAddr, NULL, 0);
994 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
995 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
996 getPointerTy(), Callee, PICLabel);
998 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1001 // FIXME: handle tail calls differently.
1003 if (Subtarget->isThumb()) {
1004 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1005 CallOpc = ARMISD::CALL_NOLINK;
1007 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1009 CallOpc = (isDirect || Subtarget->hasV5TOps())
1010 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1011 : ARMISD::CALL_NOLINK;
1013 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1014 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1015 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1016 InFlag = Chain.getValue(1);
1019 std::vector<SDValue> Ops;
1020 Ops.push_back(Chain);
1021 Ops.push_back(Callee);
1023 // Add argument registers to the end of the list so that they are known live
1025 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1026 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1027 RegsToPass[i].second.getValueType()));
1029 if (InFlag.getNode())
1030 Ops.push_back(InFlag);
1031 // Returns a chain and a flag for retval copy to use.
1032 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1033 &Ops[0], Ops.size());
1034 InFlag = Chain.getValue(1);
1036 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1037 DAG.getIntPtrConstant(0, true), InFlag);
1039 InFlag = Chain.getValue(1);
1041 // Handle result values, copying them out of physregs into vregs that we
1043 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1048 ARMTargetLowering::LowerReturn(SDValue Chain,
1049 unsigned CallConv, bool isVarArg,
1050 const SmallVectorImpl<ISD::OutputArg> &Outs,
1051 DebugLoc dl, SelectionDAG &DAG) {
1053 // CCValAssign - represent the assignment of the return value to a location.
1054 SmallVector<CCValAssign, 16> RVLocs;
1056 // CCState - Info about the registers and stack slots.
1057 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1060 // Analyze outgoing return values.
1061 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1064 // If this is the first return lowered for this function, add
1065 // the regs to the liveout set for the function.
1066 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1067 for (unsigned i = 0; i != RVLocs.size(); ++i)
1068 if (RVLocs[i].isRegLoc())
1069 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1074 // Copy the result values into the output registers.
1075 for (unsigned i = 0, realRVLocIdx = 0;
1077 ++i, ++realRVLocIdx) {
1078 CCValAssign &VA = RVLocs[i];
1079 assert(VA.isRegLoc() && "Can only return in registers!");
1081 SDValue Arg = Outs[realRVLocIdx].Val;
1083 switch (VA.getLocInfo()) {
1084 default: llvm_unreachable("Unknown loc info!");
1085 case CCValAssign::Full: break;
1086 case CCValAssign::BCvt:
1087 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1091 if (VA.needsCustom()) {
1092 if (VA.getLocVT() == MVT::v2f64) {
1093 // Extract the first half and return it in two registers.
1094 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1095 DAG.getConstant(0, MVT::i32));
1096 SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
1097 DAG.getVTList(MVT::i32, MVT::i32), Half);
1099 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1100 Flag = Chain.getValue(1);
1101 VA = RVLocs[++i]; // skip ahead to next loc
1102 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1103 HalfGPRs.getValue(1), Flag);
1104 Flag = Chain.getValue(1);
1105 VA = RVLocs[++i]; // skip ahead to next loc
1107 // Extract the 2nd half and fall through to handle it as an f64 value.
1108 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1109 DAG.getConstant(1, MVT::i32));
1111 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1113 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
1114 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1115 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1116 Flag = Chain.getValue(1);
1117 VA = RVLocs[++i]; // skip ahead to next loc
1118 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1121 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1123 // Guarantee that all emitted copies are
1124 // stuck together, avoiding something bad.
1125 Flag = Chain.getValue(1);
1130 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1132 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1137 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1138 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1139 // one of the above mentioned nodes. It has to be wrapped because otherwise
1140 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1141 // be used to form addressing mode. These wrapped nodes will be selected
1143 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1144 EVT PtrVT = Op.getValueType();
1145 // FIXME there is no actual debug info here
1146 DebugLoc dl = Op.getDebugLoc();
1147 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1149 if (CP->isMachineConstantPoolEntry())
1150 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1151 CP->getAlignment());
1153 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1154 CP->getAlignment());
1155 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1158 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1160 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1161 SelectionDAG &DAG) {
1162 DebugLoc dl = GA->getDebugLoc();
1163 EVT PtrVT = getPointerTy();
1164 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1165 ARMConstantPoolValue *CPV =
1166 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1167 PCAdj, "tlsgd", true);
1168 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1169 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1170 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
1171 SDValue Chain = Argument.getValue(1);
1173 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1174 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1176 // call __tls_get_addr.
1179 Entry.Node = Argument;
1180 Entry.Ty = (const Type *) Type::Int32Ty;
1181 Args.push_back(Entry);
1182 // FIXME: is there useful debug info available here?
1183 std::pair<SDValue, SDValue> CallResult =
1184 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
1185 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1186 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1187 return CallResult.first;
1190 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1191 // "local exec" model.
1193 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1194 SelectionDAG &DAG) {
1195 GlobalValue *GV = GA->getGlobal();
1196 DebugLoc dl = GA->getDebugLoc();
1198 SDValue Chain = DAG.getEntryNode();
1199 EVT PtrVT = getPointerTy();
1200 // Get the Thread Pointer
1201 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1203 if (GV->isDeclaration()) {
1204 // initial exec model
1205 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1206 ARMConstantPoolValue *CPV =
1207 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1208 PCAdj, "gottpoff", true);
1209 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1210 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1211 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1212 Chain = Offset.getValue(1);
1214 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1215 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1217 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1220 ARMConstantPoolValue *CPV =
1221 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
1222 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1223 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1224 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1227 // The address of the thread local variable is the add of the thread
1228 // pointer with the offset of the variable.
1229 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1233 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1234 // TODO: implement the "local dynamic" model
1235 assert(Subtarget->isTargetELF() &&
1236 "TLS not implemented for non-ELF targets");
1237 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1238 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1239 // otherwise use the "Local Exec" TLS Model
1240 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1241 return LowerToTLSGeneralDynamicModel(GA, DAG);
1243 return LowerToTLSExecModels(GA, DAG);
1246 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1247 SelectionDAG &DAG) {
1248 EVT PtrVT = getPointerTy();
1249 DebugLoc dl = Op.getDebugLoc();
1250 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1251 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1252 if (RelocM == Reloc::PIC_) {
1253 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1254 ARMConstantPoolValue *CPV =
1255 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
1256 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1257 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1258 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1260 SDValue Chain = Result.getValue(1);
1261 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1262 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1264 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1267 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1268 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1269 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1273 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
1274 /// even in non-static mode.
1275 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
1276 // If symbol visibility is hidden, the extra load is not needed if
1277 // the symbol is definitely defined in the current translation unit.
1278 bool isDecl = GV->isDeclaration() || GV->hasAvailableExternallyLinkage();
1279 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
1281 return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker());
1284 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1285 SelectionDAG &DAG) {
1286 EVT PtrVT = getPointerTy();
1287 DebugLoc dl = Op.getDebugLoc();
1288 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1289 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1290 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
1292 if (RelocM == Reloc::Static)
1293 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1295 unsigned PCAdj = (RelocM != Reloc::PIC_)
1296 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1297 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
1299 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
1301 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1303 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1305 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1306 SDValue Chain = Result.getValue(1);
1308 if (RelocM == Reloc::PIC_) {
1309 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1310 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1313 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1318 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1320 assert(Subtarget->isTargetELF() &&
1321 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1322 EVT PtrVT = getPointerTy();
1323 DebugLoc dl = Op.getDebugLoc();
1324 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1325 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
1327 ARMCP::CPValue, PCAdj);
1328 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1329 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1330 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1331 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1332 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1335 static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
1337 SDNode *Node = Op.getNode();
1338 EVT VT = Node->getValueType(0);
1339 DebugLoc dl = Op.getDebugLoc();
1341 if (!VT.is64BitVector())
1342 return SDValue(); // unimplemented
1344 SDValue Ops[] = { Node->getOperand(0),
1345 Node->getOperand(2) };
1346 return DAG.getNode(Opcode, dl, Node->getVTList(), Ops, 2);
1349 static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG,
1350 unsigned Opcode, unsigned NumVecs) {
1351 SDNode *Node = Op.getNode();
1352 EVT VT = Node->getOperand(3).getValueType();
1353 DebugLoc dl = Op.getDebugLoc();
1355 if (!VT.is64BitVector())
1356 return SDValue(); // unimplemented
1358 SmallVector<SDValue, 6> Ops;
1359 Ops.push_back(Node->getOperand(0));
1360 Ops.push_back(Node->getOperand(2));
1361 for (unsigned N = 0; N < NumVecs; ++N)
1362 Ops.push_back(Node->getOperand(N + 3));
1363 return DAG.getNode(Opcode, dl, MVT::Other, Ops.data(), Ops.size());
1367 ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
1368 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1370 case Intrinsic::arm_neon_vld2:
1371 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD2D);
1372 case Intrinsic::arm_neon_vld3:
1373 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD3D);
1374 case Intrinsic::arm_neon_vld4:
1375 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD4D);
1376 case Intrinsic::arm_neon_vst2:
1377 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST2D, 2);
1378 case Intrinsic::arm_neon_vst3:
1379 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST3D, 3);
1380 case Intrinsic::arm_neon_vst4:
1381 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST4D, 4);
1382 default: return SDValue(); // Don't custom lower most intrinsics.
1387 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1388 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1389 DebugLoc dl = Op.getDebugLoc();
1391 default: return SDValue(); // Don't custom lower most intrinsics.
1392 case Intrinsic::arm_thread_pointer: {
1393 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1394 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1396 case Intrinsic::eh_sjlj_lsda: {
1397 // blah. horrible, horrible hack with the forced magic name.
1398 // really need to clean this up. It belongs in the target-independent
1399 // layer somehow that doesn't require the coupling with the asm
1401 MachineFunction &MF = DAG.getMachineFunction();
1402 EVT PtrVT = getPointerTy();
1403 DebugLoc dl = Op.getDebugLoc();
1404 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1406 unsigned PCAdj = (RelocM != Reloc::PIC_)
1407 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1408 ARMCP::ARMCPKind Kind = ARMCP::CPValue;
1409 // Save off the LSDA name for the AsmPrinter to use when it's time
1410 // to emit the table
1411 std::string LSDAName = "L_lsda_";
1412 LSDAName += MF.getFunction()->getName();
1413 ARMConstantPoolValue *CPV =
1414 new ARMConstantPoolValue(LSDAName.c_str(), ARMPCLabelIndex, Kind, PCAdj);
1415 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1416 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1418 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1419 SDValue Chain = Result.getValue(1);
1421 if (RelocM == Reloc::PIC_) {
1422 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1423 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1427 case Intrinsic::eh_sjlj_setjmp:
1428 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
1432 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1433 unsigned VarArgsFrameIndex) {
1434 // vastart just stores the address of the VarArgsFrameIndex slot into the
1435 // memory location argument.
1436 DebugLoc dl = Op.getDebugLoc();
1437 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1438 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1439 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1440 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1444 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1445 SDNode *Node = Op.getNode();
1446 DebugLoc dl = Node->getDebugLoc();
1447 EVT VT = Node->getValueType(0);
1448 SDValue Chain = Op.getOperand(0);
1449 SDValue Size = Op.getOperand(1);
1450 SDValue Align = Op.getOperand(2);
1452 // Chain the dynamic stack allocation so that it doesn't modify the stack
1453 // pointer when other instructions are using the stack.
1454 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1456 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1457 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1458 if (AlignVal > StackAlign)
1459 // Do this now since selection pass cannot introduce new target
1460 // independent node.
1461 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1463 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1464 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1465 // do even more horrible hack later.
1466 MachineFunction &MF = DAG.getMachineFunction();
1467 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1468 if (AFI->isThumb1OnlyFunction()) {
1470 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1472 uint32_t Val = C->getZExtValue();
1473 if (Val <= 508 && ((Val & 3) == 0))
1477 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1480 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1481 SDValue Ops1[] = { Chain, Size, Align };
1482 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1483 Chain = Res.getValue(1);
1484 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1485 DAG.getIntPtrConstant(0, true), SDValue());
1486 SDValue Ops2[] = { Res, Chain };
1487 return DAG.getMergeValues(Ops2, 2, dl);
1491 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1492 SDValue &Root, SelectionDAG &DAG,
1494 MachineFunction &MF = DAG.getMachineFunction();
1495 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1497 TargetRegisterClass *RC;
1498 if (AFI->isThumb1OnlyFunction())
1499 RC = ARM::tGPRRegisterClass;
1501 RC = ARM::GPRRegisterClass;
1503 // Transform the arguments stored in physical registers into virtual ones.
1504 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1505 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1508 if (NextVA.isMemLoc()) {
1509 unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1510 MachineFrameInfo *MFI = MF.getFrameInfo();
1511 int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset());
1513 // Create load node to retrieve arguments from the stack.
1514 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1515 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1517 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1518 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1521 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
1525 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1526 unsigned CallConv, bool isVarArg,
1527 const SmallVectorImpl<ISD::InputArg>
1529 DebugLoc dl, SelectionDAG &DAG,
1530 SmallVectorImpl<SDValue> &InVals) {
1532 MachineFunction &MF = DAG.getMachineFunction();
1533 MachineFrameInfo *MFI = MF.getFrameInfo();
1535 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1537 // Assign locations to all of the incoming arguments.
1538 SmallVector<CCValAssign, 16> ArgLocs;
1539 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1541 CCInfo.AnalyzeFormalArguments(Ins,
1542 CCAssignFnForNode(CallConv, /* Return*/ false,
1545 SmallVector<SDValue, 16> ArgValues;
1547 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1548 CCValAssign &VA = ArgLocs[i];
1550 // Arguments stored in registers.
1551 if (VA.isRegLoc()) {
1552 EVT RegVT = VA.getLocVT();
1555 if (VA.needsCustom()) {
1556 // f64 and vector types are split up into multiple registers or
1557 // combinations of registers and stack slots.
1560 if (VA.getLocVT() == MVT::v2f64) {
1561 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1563 VA = ArgLocs[++i]; // skip ahead to next loc
1564 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1566 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1567 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1568 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1569 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1570 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1572 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1575 TargetRegisterClass *RC;
1577 if (RegVT == MVT::f32)
1578 RC = ARM::SPRRegisterClass;
1579 else if (RegVT == MVT::f64)
1580 RC = ARM::DPRRegisterClass;
1581 else if (RegVT == MVT::v2f64)
1582 RC = ARM::QPRRegisterClass;
1583 else if (RegVT == MVT::i32)
1584 RC = (AFI->isThumb1OnlyFunction() ?
1585 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
1587 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1589 // Transform the arguments in physical registers into virtual ones.
1590 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1591 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1594 // If this is an 8 or 16-bit value, it is really passed promoted
1595 // to 32 bits. Insert an assert[sz]ext to capture this, then
1596 // truncate to the right size.
1597 switch (VA.getLocInfo()) {
1598 default: llvm_unreachable("Unknown loc info!");
1599 case CCValAssign::Full: break;
1600 case CCValAssign::BCvt:
1601 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1603 case CCValAssign::SExt:
1604 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1605 DAG.getValueType(VA.getValVT()));
1606 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1608 case CCValAssign::ZExt:
1609 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1610 DAG.getValueType(VA.getValVT()));
1611 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1615 InVals.push_back(ArgValue);
1617 } else { // VA.isRegLoc()
1620 assert(VA.isMemLoc());
1621 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1623 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1624 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1626 // Create load nodes to retrieve arguments from the stack.
1627 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1628 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1634 static const unsigned GPRArgRegs[] = {
1635 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1638 unsigned NumGPRs = CCInfo.getFirstUnallocated
1639 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1641 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1642 unsigned VARegSize = (4 - NumGPRs) * 4;
1643 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1644 unsigned ArgOffset = 0;
1645 if (VARegSaveSize) {
1646 // If this function is vararg, store any remaining integer argument regs
1647 // to their spots on the stack so that they may be loaded by deferencing
1648 // the result of va_next.
1649 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1650 ArgOffset = CCInfo.getNextStackOffset();
1651 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1652 VARegSaveSize - VARegSize);
1653 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1655 SmallVector<SDValue, 4> MemOps;
1656 for (; NumGPRs < 4; ++NumGPRs) {
1657 TargetRegisterClass *RC;
1658 if (AFI->isThumb1OnlyFunction())
1659 RC = ARM::tGPRRegisterClass;
1661 RC = ARM::GPRRegisterClass;
1663 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1664 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1665 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1666 MemOps.push_back(Store);
1667 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1668 DAG.getConstant(4, getPointerTy()));
1670 if (!MemOps.empty())
1671 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1672 &MemOps[0], MemOps.size());
1674 // This will point to the next argument passed via stack.
1675 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1681 /// isFloatingPointZero - Return true if this is +0.0.
1682 static bool isFloatingPointZero(SDValue Op) {
1683 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1684 return CFP->getValueAPF().isPosZero();
1685 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1686 // Maybe this has already been legalized into the constant pool?
1687 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1688 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1689 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1690 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1691 return CFP->getValueAPF().isPosZero();
1697 static bool isLegalCmpImmediate(unsigned C, bool isThumb1Only) {
1698 return ( isThumb1Only && (C & ~255U) == 0) ||
1699 (!isThumb1Only && ARM_AM::getSOImmVal(C) != -1);
1702 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1703 /// the given operands.
1704 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1705 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb1Only,
1707 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1708 unsigned C = RHSC->getZExtValue();
1709 if (!isLegalCmpImmediate(C, isThumb1Only)) {
1710 // Constant does not fit, try adjusting it by one?
1715 if (isLegalCmpImmediate(C-1, isThumb1Only)) {
1716 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1717 RHS = DAG.getConstant(C-1, MVT::i32);
1722 if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) {
1723 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1724 RHS = DAG.getConstant(C-1, MVT::i32);
1729 if (isLegalCmpImmediate(C+1, isThumb1Only)) {
1730 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1731 RHS = DAG.getConstant(C+1, MVT::i32);
1736 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) {
1737 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1738 RHS = DAG.getConstant(C+1, MVT::i32);
1745 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1746 ARMISD::NodeType CompareType;
1749 CompareType = ARMISD::CMP;
1754 CompareType = ARMISD::CMPZ;
1757 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1758 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1761 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1762 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1765 if (!isFloatingPointZero(RHS))
1766 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1768 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1769 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1772 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1773 const ARMSubtarget *ST) {
1774 EVT VT = Op.getValueType();
1775 SDValue LHS = Op.getOperand(0);
1776 SDValue RHS = Op.getOperand(1);
1777 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1778 SDValue TrueVal = Op.getOperand(2);
1779 SDValue FalseVal = Op.getOperand(3);
1780 DebugLoc dl = Op.getDebugLoc();
1782 if (LHS.getValueType() == MVT::i32) {
1784 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1785 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1786 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1789 ARMCC::CondCodes CondCode, CondCode2;
1790 if (FPCCToARMCC(CC, CondCode, CondCode2))
1791 std::swap(TrueVal, FalseVal);
1793 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1794 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1795 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1796 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1798 if (CondCode2 != ARMCC::AL) {
1799 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1800 // FIXME: Needs another CMP because flag can have but one use.
1801 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1802 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1803 Result, TrueVal, ARMCC2, CCR, Cmp2);
1808 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1809 const ARMSubtarget *ST) {
1810 SDValue Chain = Op.getOperand(0);
1811 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1812 SDValue LHS = Op.getOperand(2);
1813 SDValue RHS = Op.getOperand(3);
1814 SDValue Dest = Op.getOperand(4);
1815 DebugLoc dl = Op.getDebugLoc();
1817 if (LHS.getValueType() == MVT::i32) {
1819 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1820 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1821 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1822 Chain, Dest, ARMCC, CCR,Cmp);
1825 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1826 ARMCC::CondCodes CondCode, CondCode2;
1827 if (FPCCToARMCC(CC, CondCode, CondCode2))
1828 // Swap the LHS/RHS of the comparison if needed.
1829 std::swap(LHS, RHS);
1831 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1832 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1833 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1834 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1835 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1836 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1837 if (CondCode2 != ARMCC::AL) {
1838 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1839 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1840 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1845 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1846 SDValue Chain = Op.getOperand(0);
1847 SDValue Table = Op.getOperand(1);
1848 SDValue Index = Op.getOperand(2);
1849 DebugLoc dl = Op.getDebugLoc();
1851 EVT PTy = getPointerTy();
1852 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1853 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1854 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1855 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1856 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1857 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1858 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1859 if (Subtarget->isThumb2()) {
1860 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
1861 // which does another jump to the destination. This also makes it easier
1862 // to translate it to TBB / TBH later.
1863 // FIXME: This might not work if the function is extremely large.
1864 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
1865 Addr, Op.getOperand(2), JTI, UId);
1867 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1868 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, NULL, 0);
1869 Chain = Addr.getValue(1);
1870 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1871 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1873 Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0);
1874 Chain = Addr.getValue(1);
1875 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1879 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1880 DebugLoc dl = Op.getDebugLoc();
1882 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1883 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1884 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1887 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1888 EVT VT = Op.getValueType();
1889 DebugLoc dl = Op.getDebugLoc();
1891 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1893 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1894 return DAG.getNode(Opc, dl, VT, Op);
1897 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1898 // Implement fcopysign with a fabs and a conditional fneg.
1899 SDValue Tmp0 = Op.getOperand(0);
1900 SDValue Tmp1 = Op.getOperand(1);
1901 DebugLoc dl = Op.getDebugLoc();
1902 EVT VT = Op.getValueType();
1903 EVT SrcVT = Tmp1.getValueType();
1904 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1905 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1906 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1907 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1908 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1911 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1912 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1913 MFI->setFrameAddressIsTaken(true);
1914 EVT VT = Op.getValueType();
1915 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1916 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1917 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1918 ? ARM::R7 : ARM::R11;
1919 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1921 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1926 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1928 SDValue Dst, SDValue Src,
1929 SDValue Size, unsigned Align,
1931 const Value *DstSV, uint64_t DstSVOff,
1932 const Value *SrcSV, uint64_t SrcSVOff){
1933 // Do repeated 4-byte loads and stores. To be improved.
1934 // This requires 4-byte alignment.
1935 if ((Align & 3) != 0)
1937 // This requires the copy size to be a constant, preferrably
1938 // within a subtarget-specific limit.
1939 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1942 uint64_t SizeVal = ConstantSize->getZExtValue();
1943 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1946 unsigned BytesLeft = SizeVal & 3;
1947 unsigned NumMemOps = SizeVal >> 2;
1948 unsigned EmittedNumMemOps = 0;
1950 unsigned VTSize = 4;
1952 const unsigned MAX_LOADS_IN_LDM = 6;
1953 SDValue TFOps[MAX_LOADS_IN_LDM];
1954 SDValue Loads[MAX_LOADS_IN_LDM];
1955 uint64_t SrcOff = 0, DstOff = 0;
1957 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1958 // same number of stores. The loads and stores will get combined into
1959 // ldm/stm later on.
1960 while (EmittedNumMemOps < NumMemOps) {
1962 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1963 Loads[i] = DAG.getLoad(VT, dl, Chain,
1964 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1965 DAG.getConstant(SrcOff, MVT::i32)),
1966 SrcSV, SrcSVOff + SrcOff);
1967 TFOps[i] = Loads[i].getValue(1);
1970 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1973 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1974 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1975 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1976 DAG.getConstant(DstOff, MVT::i32)),
1977 DstSV, DstSVOff + DstOff);
1980 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1982 EmittedNumMemOps += i;
1988 // Issue loads / stores for the trailing (1 - 3) bytes.
1989 unsigned BytesLeftSave = BytesLeft;
1992 if (BytesLeft >= 2) {
2000 Loads[i] = DAG.getLoad(VT, dl, Chain,
2001 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2002 DAG.getConstant(SrcOff, MVT::i32)),
2003 SrcSV, SrcSVOff + SrcOff);
2004 TFOps[i] = Loads[i].getValue(1);
2007 BytesLeft -= VTSize;
2009 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2012 BytesLeft = BytesLeftSave;
2014 if (BytesLeft >= 2) {
2022 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2023 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2024 DAG.getConstant(DstOff, MVT::i32)),
2025 DstSV, DstSVOff + DstOff);
2028 BytesLeft -= VTSize;
2030 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2033 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2034 SDValue Op = N->getOperand(0);
2035 DebugLoc dl = N->getDebugLoc();
2036 if (N->getValueType(0) == MVT::f64) {
2037 // Turn i64->f64 into FMDRR.
2038 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2039 DAG.getConstant(0, MVT::i32));
2040 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2041 DAG.getConstant(1, MVT::i32));
2042 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
2045 // Turn f64->i64 into FMRRD.
2046 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
2047 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2049 // Merge the pieces into a single i64 value.
2050 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2053 /// getZeroVector - Returns a vector of specified type with all zero elements.
2055 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2056 assert(VT.isVector() && "Expected a vector type");
2058 // Zero vectors are used to represent vector negation and in those cases
2059 // will be implemented with the NEON VNEG instruction. However, VNEG does
2060 // not support i64 elements, so sometimes the zero vectors will need to be
2061 // explicitly constructed. For those cases, and potentially other uses in
2062 // the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
2063 // to their dest type. This ensures they get CSE'd.
2065 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2066 if (VT.getSizeInBits() == 64)
2067 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2071 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2074 /// getOnesVector - Returns a vector of specified type with all bits set.
2076 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2077 assert(VT.isVector() && "Expected a vector type");
2079 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2080 // type. This ensures they get CSE'd.
2082 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2083 if (VT.getSizeInBits() == 64)
2084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2086 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2088 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2091 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2092 const ARMSubtarget *ST) {
2093 EVT VT = N->getValueType(0);
2094 DebugLoc dl = N->getDebugLoc();
2096 // Lower vector shifts on NEON to use VSHL.
2097 if (VT.isVector()) {
2098 assert(ST->hasNEON() && "unexpected vector shift");
2100 // Left shifts translate directly to the vshiftu intrinsic.
2101 if (N->getOpcode() == ISD::SHL)
2102 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2103 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2104 N->getOperand(0), N->getOperand(1));
2106 assert((N->getOpcode() == ISD::SRA ||
2107 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2109 // NEON uses the same intrinsics for both left and right shifts. For
2110 // right shifts, the shift amounts are negative, so negate the vector of
2112 EVT ShiftVT = N->getOperand(1).getValueType();
2113 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2114 getZeroVector(ShiftVT, DAG, dl),
2116 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2117 Intrinsic::arm_neon_vshifts :
2118 Intrinsic::arm_neon_vshiftu);
2119 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2120 DAG.getConstant(vshiftInt, MVT::i32),
2121 N->getOperand(0), NegatedCount);
2124 assert(VT == MVT::i64 &&
2125 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2126 "Unknown shift to lower!");
2128 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2129 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2130 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2133 // If we are in thumb mode, we don't have RRX.
2134 if (ST->isThumb1Only()) return SDValue();
2136 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2137 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2138 DAG.getConstant(0, MVT::i32));
2139 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2140 DAG.getConstant(1, MVT::i32));
2142 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2143 // captures the result into a carry flag.
2144 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2145 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2147 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2148 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2150 // Merge the pieces into a single i64 value.
2151 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2154 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2155 SDValue TmpOp0, TmpOp1;
2156 bool Invert = false;
2160 SDValue Op0 = Op.getOperand(0);
2161 SDValue Op1 = Op.getOperand(1);
2162 SDValue CC = Op.getOperand(2);
2163 EVT VT = Op.getValueType();
2164 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2165 DebugLoc dl = Op.getDebugLoc();
2167 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2168 switch (SetCCOpcode) {
2169 default: llvm_unreachable("Illegal FP comparison"); break;
2171 case ISD::SETNE: Invert = true; // Fallthrough
2173 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2175 case ISD::SETLT: Swap = true; // Fallthrough
2177 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2179 case ISD::SETLE: Swap = true; // Fallthrough
2181 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2182 case ISD::SETUGE: Swap = true; // Fallthrough
2183 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2184 case ISD::SETUGT: Swap = true; // Fallthrough
2185 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2186 case ISD::SETUEQ: Invert = true; // Fallthrough
2188 // Expand this to (OLT | OGT).
2192 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2193 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2195 case ISD::SETUO: Invert = true; // Fallthrough
2197 // Expand this to (OLT | OGE).
2201 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2202 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2206 // Integer comparisons.
2207 switch (SetCCOpcode) {
2208 default: llvm_unreachable("Illegal integer comparison"); break;
2209 case ISD::SETNE: Invert = true;
2210 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2211 case ISD::SETLT: Swap = true;
2212 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2213 case ISD::SETLE: Swap = true;
2214 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2215 case ISD::SETULT: Swap = true;
2216 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2217 case ISD::SETULE: Swap = true;
2218 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2221 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2222 if (Opc == ARMISD::VCEQ) {
2225 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2227 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2230 // Ignore bitconvert.
2231 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2232 AndOp = AndOp.getOperand(0);
2234 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2236 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2237 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2244 std::swap(Op0, Op1);
2246 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2249 Result = DAG.getNOT(dl, Result, VT);
2254 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2255 /// VMOV instruction, and if so, return the constant being splatted.
2256 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2257 unsigned SplatBitSize, SelectionDAG &DAG) {
2258 switch (SplatBitSize) {
2260 // Any 1-byte value is OK.
2261 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2262 return DAG.getTargetConstant(SplatBits, MVT::i8);
2265 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2266 if ((SplatBits & ~0xff) == 0 ||
2267 (SplatBits & ~0xff00) == 0)
2268 return DAG.getTargetConstant(SplatBits, MVT::i16);
2272 // NEON's 32-bit VMOV supports splat values where:
2273 // * only one byte is nonzero, or
2274 // * the least significant byte is 0xff and the second byte is nonzero, or
2275 // * the least significant 2 bytes are 0xff and the third is nonzero.
2276 if ((SplatBits & ~0xff) == 0 ||
2277 (SplatBits & ~0xff00) == 0 ||
2278 (SplatBits & ~0xff0000) == 0 ||
2279 (SplatBits & ~0xff000000) == 0)
2280 return DAG.getTargetConstant(SplatBits, MVT::i32);
2282 if ((SplatBits & ~0xffff) == 0 &&
2283 ((SplatBits | SplatUndef) & 0xff) == 0xff)
2284 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2286 if ((SplatBits & ~0xffffff) == 0 &&
2287 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2288 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2290 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2291 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2292 // VMOV.I32. A (very) minor optimization would be to replicate the value
2293 // and fall through here to test for a valid 64-bit splat. But, then the
2294 // caller would also need to check and handle the change in size.
2298 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2299 uint64_t BitMask = 0xff;
2301 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2302 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2304 else if ((SplatBits & BitMask) != 0)
2308 return DAG.getTargetConstant(Val, MVT::i64);
2312 llvm_unreachable("unexpected size for isVMOVSplat");
2319 /// getVMOVImm - If this is a build_vector of constants which can be
2320 /// formed by using a VMOV instruction of the specified element size,
2321 /// return the constant being splatted. The ByteSize field indicates the
2322 /// number of bytes of each element [1248].
2323 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2324 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2325 APInt SplatBits, SplatUndef;
2326 unsigned SplatBitSize;
2328 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2329 HasAnyUndefs, ByteSize * 8))
2332 if (SplatBitSize > ByteSize * 8)
2335 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2339 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2340 /// instruction with the specified blocksize. (The order of the elements
2341 /// within each block of the vector is reversed.)
2342 static bool isVREVMask(ShuffleVectorSDNode *N, unsigned BlockSize) {
2343 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2344 "Only possible block sizes for VREV are: 16, 32, 64");
2346 EVT VT = N->getValueType(0);
2347 unsigned NumElts = VT.getVectorNumElements();
2348 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2349 unsigned BlockElts = N->getMaskElt(0) + 1;
2351 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2354 for (unsigned i = 0; i < NumElts; ++i) {
2355 if ((unsigned) N->getMaskElt(i) !=
2356 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2363 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2364 // Canonicalize all-zeros and all-ones vectors.
2365 ConstantSDNode *ConstVal = dyn_cast<ConstantSDNode>(Val.getNode());
2366 if (ConstVal->isNullValue())
2367 return getZeroVector(VT, DAG, dl);
2368 if (ConstVal->isAllOnesValue())
2369 return getOnesVector(VT, DAG, dl);
2372 if (VT.is64BitVector()) {
2373 switch (Val.getValueType().getSizeInBits()) {
2374 case 8: CanonicalVT = MVT::v8i8; break;
2375 case 16: CanonicalVT = MVT::v4i16; break;
2376 case 32: CanonicalVT = MVT::v2i32; break;
2377 case 64: CanonicalVT = MVT::v1i64; break;
2378 default: llvm_unreachable("unexpected splat element type"); break;
2381 assert(VT.is128BitVector() && "unknown splat vector size");
2382 switch (Val.getValueType().getSizeInBits()) {
2383 case 8: CanonicalVT = MVT::v16i8; break;
2384 case 16: CanonicalVT = MVT::v8i16; break;
2385 case 32: CanonicalVT = MVT::v4i32; break;
2386 case 64: CanonicalVT = MVT::v2i64; break;
2387 default: llvm_unreachable("unexpected splat element type"); break;
2391 // Build a canonical splat for this value.
2392 SmallVector<SDValue, 8> Ops;
2393 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2394 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2396 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2399 // If this is a case we can't handle, return null and let the default
2400 // expansion code take care of it.
2401 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2402 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
2403 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
2404 DebugLoc dl = Op.getDebugLoc();
2405 EVT VT = Op.getValueType();
2407 APInt SplatBits, SplatUndef;
2408 unsigned SplatBitSize;
2410 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2411 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2412 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2414 return BuildSplat(Val, VT, DAG, dl);
2417 // If there are only 2 elements in a 128-bit vector, insert them into an
2418 // undef vector. This handles the common case for 128-bit vector argument
2419 // passing, where the insertions should be translated to subreg accesses
2420 // with no real instructions.
2421 if (VT.is128BitVector() && Op.getNumOperands() == 2) {
2422 SDValue Val = DAG.getUNDEF(VT);
2423 SDValue Op0 = Op.getOperand(0);
2424 SDValue Op1 = Op.getOperand(1);
2425 if (Op0.getOpcode() != ISD::UNDEF)
2426 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
2427 DAG.getIntPtrConstant(0));
2428 if (Op1.getOpcode() != ISD::UNDEF)
2429 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
2430 DAG.getIntPtrConstant(1));
2437 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2438 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Op.getNode());
2439 assert(SVN != 0 && "Expected a ShuffleVectorSDNode in LowerVECTOR_SHUFFLE");
2440 DebugLoc dl = Op.getDebugLoc();
2441 EVT VT = Op.getValueType();
2443 if (isVREVMask(SVN, 64))
2444 return DAG.getNode(ARMISD::VREV64, dl, VT, SVN->getOperand(0));
2445 if (isVREVMask(SVN, 32))
2446 return DAG.getNode(ARMISD::VREV32, dl, VT, SVN->getOperand(0));
2447 if (isVREVMask(SVN, 16))
2448 return DAG.getNode(ARMISD::VREV16, dl, VT, SVN->getOperand(0));
2453 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
2457 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2458 EVT VT = Op.getValueType();
2459 DebugLoc dl = Op.getDebugLoc();
2460 assert((VT == MVT::i8 || VT == MVT::i16) &&
2461 "unexpected type for custom-lowering vector extract");
2462 SDValue Vec = Op.getOperand(0);
2463 SDValue Lane = Op.getOperand(1);
2464 Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2465 Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
2466 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
2469 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2470 // The only time a CONCAT_VECTORS operation can have legal types is when
2471 // two 64-bit vectors are concatenated to a 128-bit vector.
2472 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2473 "unexpected CONCAT_VECTORS");
2474 DebugLoc dl = Op.getDebugLoc();
2475 SDValue Val = DAG.getUNDEF(MVT::v2f64);
2476 SDValue Op0 = Op.getOperand(0);
2477 SDValue Op1 = Op.getOperand(1);
2478 if (Op0.getOpcode() != ISD::UNDEF)
2479 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2480 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
2481 DAG.getIntPtrConstant(0));
2482 if (Op1.getOpcode() != ISD::UNDEF)
2483 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2484 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
2485 DAG.getIntPtrConstant(1));
2486 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
2489 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
2490 switch (Op.getOpcode()) {
2491 default: llvm_unreachable("Don't know how to custom lower this!");
2492 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2493 case ISD::GlobalAddress:
2494 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2495 LowerGlobalAddressELF(Op, DAG);
2496 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2497 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
2498 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
2499 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2500 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2501 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2502 case ISD::SINT_TO_FP:
2503 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
2504 case ISD::FP_TO_SINT:
2505 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
2506 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
2507 case ISD::RETURNADDR: break;
2508 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2509 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2510 case ISD::INTRINSIC_VOID:
2511 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
2512 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2513 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
2516 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
2517 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
2518 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2519 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2520 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2521 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2522 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2527 /// ReplaceNodeResults - Replace the results of node with an illegal result
2528 /// type with new values built out of custom code.
2529 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
2530 SmallVectorImpl<SDValue>&Results,
2531 SelectionDAG &DAG) {
2532 switch (N->getOpcode()) {
2534 llvm_unreachable("Don't know how to custom expand this!");
2536 case ISD::BIT_CONVERT:
2537 Results.push_back(ExpandBIT_CONVERT(N, DAG));
2541 SDValue Res = LowerShift(N, DAG, Subtarget);
2543 Results.push_back(Res);
2549 //===----------------------------------------------------------------------===//
2550 // ARM Scheduler Hooks
2551 //===----------------------------------------------------------------------===//
2554 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2555 MachineBasicBlock *BB) const {
2556 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2557 DebugLoc dl = MI->getDebugLoc();
2558 switch (MI->getOpcode()) {
2560 llvm_unreachable("Unexpected instr type to insert");
2561 case ARM::tMOVCCr_pseudo: {
2562 // To "insert" a SELECT_CC instruction, we actually have to insert the
2563 // diamond control-flow pattern. The incoming instruction knows the
2564 // destination vreg to set, the condition code register to branch on, the
2565 // true/false values to select between, and a branch opcode to use.
2566 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2567 MachineFunction::iterator It = BB;
2573 // cmpTY ccX, r1, r2
2575 // fallthrough --> copy0MBB
2576 MachineBasicBlock *thisMBB = BB;
2577 MachineFunction *F = BB->getParent();
2578 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2579 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2580 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
2581 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
2582 F->insert(It, copy0MBB);
2583 F->insert(It, sinkMBB);
2584 // Update machine-CFG edges by first adding all successors of the current
2585 // block to the new block which will contain the Phi node for the select.
2586 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2587 e = BB->succ_end(); i != e; ++i)
2588 sinkMBB->addSuccessor(*i);
2589 // Next, remove all successors of the current block, and add the true
2590 // and fallthrough blocks as its successors.
2591 while(!BB->succ_empty())
2592 BB->removeSuccessor(BB->succ_begin());
2593 BB->addSuccessor(copy0MBB);
2594 BB->addSuccessor(sinkMBB);
2597 // %FalseValue = ...
2598 // # fallthrough to sinkMBB
2601 // Update machine-CFG edges
2602 BB->addSuccessor(sinkMBB);
2605 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2608 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
2609 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
2610 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2612 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2619 case ARM::t2SUBrSPi_:
2620 case ARM::t2SUBrSPi12_:
2621 case ARM::t2SUBrSPs_: {
2622 MachineFunction *MF = BB->getParent();
2623 unsigned DstReg = MI->getOperand(0).getReg();
2624 unsigned SrcReg = MI->getOperand(1).getReg();
2625 bool DstIsDead = MI->getOperand(0).isDead();
2626 bool SrcIsKill = MI->getOperand(1).isKill();
2628 if (SrcReg != ARM::SP) {
2629 // Copy the source to SP from virtual register.
2630 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
2631 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2632 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
2633 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
2634 .addReg(SrcReg, getKillRegState(SrcIsKill));
2638 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
2639 switch (MI->getOpcode()) {
2641 llvm_unreachable("Unexpected pseudo instruction!");
2647 OpOpc = ARM::tADDspr;
2650 OpOpc = ARM::tSUBspi;
2652 case ARM::t2SUBrSPi_:
2653 OpOpc = ARM::t2SUBrSPi;
2654 NeedPred = true; NeedCC = true;
2656 case ARM::t2SUBrSPi12_:
2657 OpOpc = ARM::t2SUBrSPi12;
2660 case ARM::t2SUBrSPs_:
2661 OpOpc = ARM::t2SUBrSPs;
2662 NeedPred = true; NeedCC = true; NeedOp3 = true;
2665 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
2666 if (OpOpc == ARM::tAND)
2667 AddDefaultT1CC(MIB);
2668 MIB.addReg(ARM::SP);
2669 MIB.addOperand(MI->getOperand(2));
2671 MIB.addOperand(MI->getOperand(3));
2673 AddDefaultPred(MIB);
2677 // Copy the result from SP to virtual register.
2678 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
2679 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2680 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
2681 BuildMI(BB, dl, TII->get(CopyOpc))
2682 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
2684 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2690 //===----------------------------------------------------------------------===//
2691 // ARM Optimization Hooks
2692 //===----------------------------------------------------------------------===//
2695 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
2696 TargetLowering::DAGCombinerInfo &DCI) {
2697 SelectionDAG &DAG = DCI.DAG;
2698 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2699 EVT VT = N->getValueType(0);
2700 unsigned Opc = N->getOpcode();
2701 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
2702 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
2703 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
2704 ISD::CondCode CC = ISD::SETCC_INVALID;
2707 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
2709 SDValue CCOp = Slct.getOperand(0);
2710 if (CCOp.getOpcode() == ISD::SETCC)
2711 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
2714 bool DoXform = false;
2716 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
2719 if (LHS.getOpcode() == ISD::Constant &&
2720 cast<ConstantSDNode>(LHS)->isNullValue()) {
2722 } else if (CC != ISD::SETCC_INVALID &&
2723 RHS.getOpcode() == ISD::Constant &&
2724 cast<ConstantSDNode>(RHS)->isNullValue()) {
2725 std::swap(LHS, RHS);
2726 SDValue Op0 = Slct.getOperand(0);
2727 EVT OpVT = isSlctCC ? Op0.getValueType() :
2728 Op0.getOperand(0).getValueType();
2729 bool isInt = OpVT.isInteger();
2730 CC = ISD::getSetCCInverse(CC, isInt);
2732 if (!TLI.isCondCodeLegal(CC, OpVT))
2733 return SDValue(); // Inverse operator isn't legal.
2740 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
2742 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
2743 Slct.getOperand(0), Slct.getOperand(1), CC);
2744 SDValue CCOp = Slct.getOperand(0);
2746 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
2747 CCOp.getOperand(0), CCOp.getOperand(1), CC);
2748 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
2749 CCOp, OtherOp, Result);
2754 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
2755 static SDValue PerformADDCombine(SDNode *N,
2756 TargetLowering::DAGCombinerInfo &DCI) {
2757 // added by evan in r37685 with no testcase.
2758 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2760 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
2761 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
2762 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
2763 if (Result.getNode()) return Result;
2765 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2766 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2767 if (Result.getNode()) return Result;
2773 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
2774 static SDValue PerformSUBCombine(SDNode *N,
2775 TargetLowering::DAGCombinerInfo &DCI) {
2776 // added by evan in r37685 with no testcase.
2777 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2779 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
2780 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2781 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2782 if (Result.getNode()) return Result;
2789 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
2790 static SDValue PerformFMRRDCombine(SDNode *N,
2791 TargetLowering::DAGCombinerInfo &DCI) {
2792 // fmrrd(fmdrr x, y) -> x,y
2793 SDValue InDouble = N->getOperand(0);
2794 if (InDouble.getOpcode() == ARMISD::FMDRR)
2795 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
2799 /// getVShiftImm - Check if this is a valid build_vector for the immediate
2800 /// operand of a vector shift operation, where all the elements of the
2801 /// build_vector must have the same constant integer value.
2802 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
2803 // Ignore bit_converts.
2804 while (Op.getOpcode() == ISD::BIT_CONVERT)
2805 Op = Op.getOperand(0);
2806 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
2807 APInt SplatBits, SplatUndef;
2808 unsigned SplatBitSize;
2810 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2811 HasAnyUndefs, ElementBits) ||
2812 SplatBitSize > ElementBits)
2814 Cnt = SplatBits.getSExtValue();
2818 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
2819 /// operand of a vector shift left operation. That value must be in the range:
2820 /// 0 <= Value < ElementBits for a left shift; or
2821 /// 0 <= Value <= ElementBits for a long left shift.
2822 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
2823 assert(VT.isVector() && "vector shift count is not a vector type");
2824 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2825 if (! getVShiftImm(Op, ElementBits, Cnt))
2827 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
2830 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
2831 /// operand of a vector shift right operation. For a shift opcode, the value
2832 /// is positive, but for an intrinsic the value count must be negative. The
2833 /// absolute value must be in the range:
2834 /// 1 <= |Value| <= ElementBits for a right shift; or
2835 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
2836 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
2838 assert(VT.isVector() && "vector shift count is not a vector type");
2839 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2840 if (! getVShiftImm(Op, ElementBits, Cnt))
2844 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
2847 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
2848 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
2849 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2852 // Don't do anything for most intrinsics.
2855 // Vector shifts: check for immediate versions and lower them.
2856 // Note: This is done during DAG combining instead of DAG legalizing because
2857 // the build_vectors for 64-bit vector element shift counts are generally
2858 // not legal, and it is hard to see their values after they get legalized to
2859 // loads from a constant pool.
2860 case Intrinsic::arm_neon_vshifts:
2861 case Intrinsic::arm_neon_vshiftu:
2862 case Intrinsic::arm_neon_vshiftls:
2863 case Intrinsic::arm_neon_vshiftlu:
2864 case Intrinsic::arm_neon_vshiftn:
2865 case Intrinsic::arm_neon_vrshifts:
2866 case Intrinsic::arm_neon_vrshiftu:
2867 case Intrinsic::arm_neon_vrshiftn:
2868 case Intrinsic::arm_neon_vqshifts:
2869 case Intrinsic::arm_neon_vqshiftu:
2870 case Intrinsic::arm_neon_vqshiftsu:
2871 case Intrinsic::arm_neon_vqshiftns:
2872 case Intrinsic::arm_neon_vqshiftnu:
2873 case Intrinsic::arm_neon_vqshiftnsu:
2874 case Intrinsic::arm_neon_vqrshiftns:
2875 case Intrinsic::arm_neon_vqrshiftnu:
2876 case Intrinsic::arm_neon_vqrshiftnsu: {
2877 EVT VT = N->getOperand(1).getValueType();
2879 unsigned VShiftOpc = 0;
2882 case Intrinsic::arm_neon_vshifts:
2883 case Intrinsic::arm_neon_vshiftu:
2884 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
2885 VShiftOpc = ARMISD::VSHL;
2888 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
2889 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
2890 ARMISD::VSHRs : ARMISD::VSHRu);
2895 case Intrinsic::arm_neon_vshiftls:
2896 case Intrinsic::arm_neon_vshiftlu:
2897 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
2899 llvm_unreachable("invalid shift count for vshll intrinsic");
2901 case Intrinsic::arm_neon_vrshifts:
2902 case Intrinsic::arm_neon_vrshiftu:
2903 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
2907 case Intrinsic::arm_neon_vqshifts:
2908 case Intrinsic::arm_neon_vqshiftu:
2909 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2913 case Intrinsic::arm_neon_vqshiftsu:
2914 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2916 llvm_unreachable("invalid shift count for vqshlu intrinsic");
2918 case Intrinsic::arm_neon_vshiftn:
2919 case Intrinsic::arm_neon_vrshiftn:
2920 case Intrinsic::arm_neon_vqshiftns:
2921 case Intrinsic::arm_neon_vqshiftnu:
2922 case Intrinsic::arm_neon_vqshiftnsu:
2923 case Intrinsic::arm_neon_vqrshiftns:
2924 case Intrinsic::arm_neon_vqrshiftnu:
2925 case Intrinsic::arm_neon_vqrshiftnsu:
2926 // Narrowing shifts require an immediate right shift.
2927 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
2929 llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
2932 llvm_unreachable("unhandled vector shift");
2936 case Intrinsic::arm_neon_vshifts:
2937 case Intrinsic::arm_neon_vshiftu:
2938 // Opcode already set above.
2940 case Intrinsic::arm_neon_vshiftls:
2941 case Intrinsic::arm_neon_vshiftlu:
2942 if (Cnt == VT.getVectorElementType().getSizeInBits())
2943 VShiftOpc = ARMISD::VSHLLi;
2945 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
2946 ARMISD::VSHLLs : ARMISD::VSHLLu);
2948 case Intrinsic::arm_neon_vshiftn:
2949 VShiftOpc = ARMISD::VSHRN; break;
2950 case Intrinsic::arm_neon_vrshifts:
2951 VShiftOpc = ARMISD::VRSHRs; break;
2952 case Intrinsic::arm_neon_vrshiftu:
2953 VShiftOpc = ARMISD::VRSHRu; break;
2954 case Intrinsic::arm_neon_vrshiftn:
2955 VShiftOpc = ARMISD::VRSHRN; break;
2956 case Intrinsic::arm_neon_vqshifts:
2957 VShiftOpc = ARMISD::VQSHLs; break;
2958 case Intrinsic::arm_neon_vqshiftu:
2959 VShiftOpc = ARMISD::VQSHLu; break;
2960 case Intrinsic::arm_neon_vqshiftsu:
2961 VShiftOpc = ARMISD::VQSHLsu; break;
2962 case Intrinsic::arm_neon_vqshiftns:
2963 VShiftOpc = ARMISD::VQSHRNs; break;
2964 case Intrinsic::arm_neon_vqshiftnu:
2965 VShiftOpc = ARMISD::VQSHRNu; break;
2966 case Intrinsic::arm_neon_vqshiftnsu:
2967 VShiftOpc = ARMISD::VQSHRNsu; break;
2968 case Intrinsic::arm_neon_vqrshiftns:
2969 VShiftOpc = ARMISD::VQRSHRNs; break;
2970 case Intrinsic::arm_neon_vqrshiftnu:
2971 VShiftOpc = ARMISD::VQRSHRNu; break;
2972 case Intrinsic::arm_neon_vqrshiftnsu:
2973 VShiftOpc = ARMISD::VQRSHRNsu; break;
2976 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
2977 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
2980 case Intrinsic::arm_neon_vshiftins: {
2981 EVT VT = N->getOperand(1).getValueType();
2983 unsigned VShiftOpc = 0;
2985 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
2986 VShiftOpc = ARMISD::VSLI;
2987 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
2988 VShiftOpc = ARMISD::VSRI;
2990 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
2993 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
2994 N->getOperand(1), N->getOperand(2),
2995 DAG.getConstant(Cnt, MVT::i32));
2998 case Intrinsic::arm_neon_vqrshifts:
2999 case Intrinsic::arm_neon_vqrshiftu:
3000 // No immediate versions of these to check for.
3007 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
3008 /// lowers them. As with the vector shift intrinsics, this is done during DAG
3009 /// combining instead of DAG legalizing because the build_vectors for 64-bit
3010 /// vector element shift counts are generally not legal, and it is hard to see
3011 /// their values after they get legalized to loads from a constant pool.
3012 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
3013 const ARMSubtarget *ST) {
3014 EVT VT = N->getValueType(0);
3016 // Nothing to be done for scalar shifts.
3017 if (! VT.isVector())
3020 assert(ST->hasNEON() && "unexpected vector shift");
3023 switch (N->getOpcode()) {
3024 default: llvm_unreachable("unexpected shift opcode");
3027 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
3028 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
3029 DAG.getConstant(Cnt, MVT::i32));
3034 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
3035 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
3036 ARMISD::VSHRs : ARMISD::VSHRu);
3037 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
3038 DAG.getConstant(Cnt, MVT::i32));
3044 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
3045 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
3046 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
3047 const ARMSubtarget *ST) {
3048 SDValue N0 = N->getOperand(0);
3050 // Check for sign- and zero-extensions of vector extract operations of 8-
3051 // and 16-bit vector elements. NEON supports these directly. They are
3052 // handled during DAG combining because type legalization will promote them
3053 // to 32-bit types and it is messy to recognize the operations after that.
3054 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
3055 SDValue Vec = N0.getOperand(0);
3056 SDValue Lane = N0.getOperand(1);
3057 EVT VT = N->getValueType(0);
3058 EVT EltVT = N0.getValueType();
3059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3061 if (VT == MVT::i32 &&
3062 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
3063 TLI.isTypeLegal(Vec.getValueType())) {
3066 switch (N->getOpcode()) {
3067 default: llvm_unreachable("unexpected opcode");
3068 case ISD::SIGN_EXTEND:
3069 Opc = ARMISD::VGETLANEs;
3071 case ISD::ZERO_EXTEND:
3072 case ISD::ANY_EXTEND:
3073 Opc = ARMISD::VGETLANEu;
3076 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
3083 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
3084 DAGCombinerInfo &DCI) const {
3085 switch (N->getOpcode()) {
3087 case ISD::ADD: return PerformADDCombine(N, DCI);
3088 case ISD::SUB: return PerformSUBCombine(N, DCI);
3089 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
3090 case ISD::INTRINSIC_WO_CHAIN:
3091 return PerformIntrinsicCombine(N, DCI.DAG);
3095 return PerformShiftCombine(N, DCI.DAG, Subtarget);
3096 case ISD::SIGN_EXTEND:
3097 case ISD::ZERO_EXTEND:
3098 case ISD::ANY_EXTEND:
3099 return PerformExtendCombine(N, DCI.DAG, Subtarget);
3104 /// isLegalAddressImmediate - Return true if the integer value can be used
3105 /// as the offset of the target addressing mode for load / store of the
3107 static bool isLegalAddressImmediate(int64_t V, EVT VT,
3108 const ARMSubtarget *Subtarget) {
3115 if (Subtarget->isThumb()) { // FIXME for thumb2
3120 switch (VT.getSimpleVT().SimpleTy) {
3121 default: return false;
3136 if ((V & (Scale - 1)) != 0)
3139 return V == (V & ((1LL << 5) - 1));
3144 switch (VT.getSimpleVT().SimpleTy) {
3145 default: return false;
3150 return V == (V & ((1LL << 12) - 1));
3153 return V == (V & ((1LL << 8) - 1));
3156 if (!Subtarget->hasVFP2())
3161 return V == (V & ((1LL << 8) - 1));
3165 /// isLegalAddressingMode - Return true if the addressing mode represented
3166 /// by AM is legal for this target, for a load/store of the specified type.
3167 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3168 const Type *Ty) const {
3169 EVT VT = getValueType(Ty, true);
3170 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
3173 // Can never fold addr of global into load/store.
3178 case 0: // no scale reg, must be "r+i" or "r", or "i".
3181 if (Subtarget->isThumb()) // FIXME for thumb2
3185 // ARM doesn't support any R+R*scale+imm addr modes.
3192 int Scale = AM.Scale;
3193 switch (VT.getSimpleVT().SimpleTy) {
3194 default: return false;
3199 // This assumes i64 is legalized to a pair of i32. If not (i.e.
3200 // ldrd / strd are used, then its address mode is same as i16.
3202 if (Scale < 0) Scale = -Scale;
3206 return isPowerOf2_32(Scale & ~1);
3209 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3214 // Note, we allow "void" uses (basically, uses that aren't loads or
3215 // stores), because arm allows folding a scale into many arithmetic
3216 // operations. This should be made more precise and revisited later.
3218 // Allow r << imm, but the imm has to be a multiple of two.
3219 if (AM.Scale & 1) return false;
3220 return isPowerOf2_32(AM.Scale);
3227 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
3228 bool isSEXTLoad, SDValue &Base,
3229 SDValue &Offset, bool &isInc,
3230 SelectionDAG &DAG) {
3231 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3234 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
3236 Base = Ptr->getOperand(0);
3237 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3238 int RHSC = (int)RHS->getZExtValue();
3239 if (RHSC < 0 && RHSC > -256) {
3240 assert(Ptr->getOpcode() == ISD::ADD);
3242 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3246 isInc = (Ptr->getOpcode() == ISD::ADD);
3247 Offset = Ptr->getOperand(1);
3249 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
3251 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3252 int RHSC = (int)RHS->getZExtValue();
3253 if (RHSC < 0 && RHSC > -0x1000) {
3254 assert(Ptr->getOpcode() == ISD::ADD);
3256 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3257 Base = Ptr->getOperand(0);
3262 if (Ptr->getOpcode() == ISD::ADD) {
3264 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
3265 if (ShOpcVal != ARM_AM::no_shift) {
3266 Base = Ptr->getOperand(1);
3267 Offset = Ptr->getOperand(0);
3269 Base = Ptr->getOperand(0);
3270 Offset = Ptr->getOperand(1);
3275 isInc = (Ptr->getOpcode() == ISD::ADD);
3276 Base = Ptr->getOperand(0);
3277 Offset = Ptr->getOperand(1);
3281 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
3285 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
3286 bool isSEXTLoad, SDValue &Base,
3287 SDValue &Offset, bool &isInc,
3288 SelectionDAG &DAG) {
3289 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3292 Base = Ptr->getOperand(0);
3293 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3294 int RHSC = (int)RHS->getZExtValue();
3295 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
3296 assert(Ptr->getOpcode() == ISD::ADD);
3298 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3300 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
3301 isInc = Ptr->getOpcode() == ISD::ADD;
3302 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
3310 /// getPreIndexedAddressParts - returns true by value, base pointer and
3311 /// offset pointer and addressing mode by reference if the node's address
3312 /// can be legally represented as pre-indexed load / store address.
3314 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
3316 ISD::MemIndexedMode &AM,
3317 SelectionDAG &DAG) const {
3318 if (Subtarget->isThumb1Only())
3323 bool isSEXTLoad = false;
3324 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3325 Ptr = LD->getBasePtr();
3326 VT = LD->getMemoryVT();
3327 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3328 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3329 Ptr = ST->getBasePtr();
3330 VT = ST->getMemoryVT();
3335 bool isLegal = false;
3336 if (Subtarget->isThumb() && Subtarget->hasThumb2())
3337 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3338 Offset, isInc, DAG);
3340 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3341 Offset, isInc, DAG);
3345 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
3349 /// getPostIndexedAddressParts - returns true by value, base pointer and
3350 /// offset pointer and addressing mode by reference if this node can be
3351 /// combined with a load / store to form a post-indexed load / store.
3352 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
3355 ISD::MemIndexedMode &AM,
3356 SelectionDAG &DAG) const {
3357 if (Subtarget->isThumb1Only())
3362 bool isSEXTLoad = false;
3363 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3364 VT = LD->getMemoryVT();
3365 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3366 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3367 VT = ST->getMemoryVT();
3372 bool isLegal = false;
3373 if (Subtarget->isThumb() && Subtarget->hasThumb2())
3374 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3377 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3382 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
3386 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3390 const SelectionDAG &DAG,
3391 unsigned Depth) const {
3392 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3393 switch (Op.getOpcode()) {
3395 case ARMISD::CMOV: {
3396 // Bits are known zero/one if known on the LHS and RHS.
3397 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
3398 if (KnownZero == 0 && KnownOne == 0) return;
3400 APInt KnownZeroRHS, KnownOneRHS;
3401 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
3402 KnownZeroRHS, KnownOneRHS, Depth+1);
3403 KnownZero &= KnownZeroRHS;
3404 KnownOne &= KnownOneRHS;
3410 //===----------------------------------------------------------------------===//
3411 // ARM Inline Assembly Support
3412 //===----------------------------------------------------------------------===//
3414 /// getConstraintType - Given a constraint letter, return the type of
3415 /// constraint it is for this target.
3416 ARMTargetLowering::ConstraintType
3417 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
3418 if (Constraint.size() == 1) {
3419 switch (Constraint[0]) {
3421 case 'l': return C_RegisterClass;
3422 case 'w': return C_RegisterClass;
3425 return TargetLowering::getConstraintType(Constraint);
3428 std::pair<unsigned, const TargetRegisterClass*>
3429 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3431 if (Constraint.size() == 1) {
3432 // GCC RS6000 Constraint Letters
3433 switch (Constraint[0]) {
3435 if (Subtarget->isThumb1Only())
3436 return std::make_pair(0U, ARM::tGPRRegisterClass);
3438 return std::make_pair(0U, ARM::GPRRegisterClass);
3440 return std::make_pair(0U, ARM::GPRRegisterClass);
3443 return std::make_pair(0U, ARM::SPRRegisterClass);
3445 return std::make_pair(0U, ARM::DPRRegisterClass);
3449 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3452 std::vector<unsigned> ARMTargetLowering::
3453 getRegClassForInlineAsmConstraint(const std::string &Constraint,
3455 if (Constraint.size() != 1)
3456 return std::vector<unsigned>();
3458 switch (Constraint[0]) { // GCC ARM Constraint Letters
3461 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3462 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3465 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3466 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3467 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
3468 ARM::R12, ARM::LR, 0);
3471 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
3472 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
3473 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
3474 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
3475 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
3476 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
3477 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
3478 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
3480 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
3481 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
3482 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
3483 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
3487 return std::vector<unsigned>();
3490 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3491 /// vector. If it is invalid, don't add anything to Ops.
3492 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3495 std::vector<SDValue>&Ops,
3496 SelectionDAG &DAG) const {
3497 SDValue Result(0, 0);
3499 switch (Constraint) {
3501 case 'I': case 'J': case 'K': case 'L':
3502 case 'M': case 'N': case 'O':
3503 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3507 int64_t CVal64 = C->getSExtValue();
3508 int CVal = (int) CVal64;
3509 // None of these constraints allow values larger than 32 bits. Check
3510 // that the value fits in an int.
3514 switch (Constraint) {
3516 if (Subtarget->isThumb1Only()) {
3517 // This must be a constant between 0 and 255, for ADD
3519 if (CVal >= 0 && CVal <= 255)
3521 } else if (Subtarget->isThumb2()) {
3522 // A constant that can be used as an immediate value in a
3523 // data-processing instruction.
3524 if (ARM_AM::getT2SOImmVal(CVal) != -1)
3527 // A constant that can be used as an immediate value in a
3528 // data-processing instruction.
3529 if (ARM_AM::getSOImmVal(CVal) != -1)
3535 if (Subtarget->isThumb()) { // FIXME thumb2
3536 // This must be a constant between -255 and -1, for negated ADD
3537 // immediates. This can be used in GCC with an "n" modifier that
3538 // prints the negated value, for use with SUB instructions. It is
3539 // not useful otherwise but is implemented for compatibility.
3540 if (CVal >= -255 && CVal <= -1)
3543 // This must be a constant between -4095 and 4095. It is not clear
3544 // what this constraint is intended for. Implemented for
3545 // compatibility with GCC.
3546 if (CVal >= -4095 && CVal <= 4095)
3552 if (Subtarget->isThumb1Only()) {
3553 // A 32-bit value where only one byte has a nonzero value. Exclude
3554 // zero to match GCC. This constraint is used by GCC internally for
3555 // constants that can be loaded with a move/shift combination.
3556 // It is not useful otherwise but is implemented for compatibility.
3557 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
3559 } else if (Subtarget->isThumb2()) {
3560 // A constant whose bitwise inverse can be used as an immediate
3561 // value in a data-processing instruction. This can be used in GCC
3562 // with a "B" modifier that prints the inverted value, for use with
3563 // BIC and MVN instructions. It is not useful otherwise but is
3564 // implemented for compatibility.
3565 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
3568 // A constant whose bitwise inverse can be used as an immediate
3569 // value in a data-processing instruction. This can be used in GCC
3570 // with a "B" modifier that prints the inverted value, for use with
3571 // BIC and MVN instructions. It is not useful otherwise but is
3572 // implemented for compatibility.
3573 if (ARM_AM::getSOImmVal(~CVal) != -1)
3579 if (Subtarget->isThumb1Only()) {
3580 // This must be a constant between -7 and 7,
3581 // for 3-operand ADD/SUB immediate instructions.
3582 if (CVal >= -7 && CVal < 7)
3584 } else if (Subtarget->isThumb2()) {
3585 // A constant whose negation can be used as an immediate value in a
3586 // data-processing instruction. This can be used in GCC with an "n"
3587 // modifier that prints the negated value, for use with SUB
3588 // instructions. It is not useful otherwise but is implemented for
3590 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
3593 // A constant whose negation can be used as an immediate value in a
3594 // data-processing instruction. This can be used in GCC with an "n"
3595 // modifier that prints the negated value, for use with SUB
3596 // instructions. It is not useful otherwise but is implemented for
3598 if (ARM_AM::getSOImmVal(-CVal) != -1)
3604 if (Subtarget->isThumb()) { // FIXME thumb2
3605 // This must be a multiple of 4 between 0 and 1020, for
3606 // ADD sp + immediate.
3607 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
3610 // A power of two or a constant between 0 and 32. This is used in
3611 // GCC for the shift amount on shifted register operands, but it is
3612 // useful in general for any shift amounts.
3613 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
3619 if (Subtarget->isThumb()) { // FIXME thumb2
3620 // This must be a constant between 0 and 31, for shift amounts.
3621 if (CVal >= 0 && CVal <= 31)
3627 if (Subtarget->isThumb()) { // FIXME thumb2
3628 // This must be a multiple of 4 between -508 and 508, for
3629 // ADD/SUB sp = sp + immediate.
3630 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
3635 Result = DAG.getTargetConstant(CVal, Op.getValueType());
3639 if (Result.getNode()) {
3640 Ops.push_back(Result);
3643 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,