1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMCallingConv.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "MCTargetDesc/ARMAddressingModes.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineModuleInfo.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/PseudoSourceValue.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/ADT/Statistic.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
57 STATISTIC(NumTailCalls, "Number of tail calls");
58 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
60 // This option should go away when tail calls fully work.
62 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
63 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
67 EnableARMLongCalls("arm-long-calls", cl::Hidden,
68 cl::desc("Generate calls via indirect call instructions"),
72 ARMInterworking("arm-interworking", cl::Hidden,
73 cl::desc("Enable / disable ARM interworking (for debugging only)"),
77 class ARMCCState : public CCState {
79 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
80 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,
81 LLVMContext &C, ParmContext PC)
82 : CCState(CC, isVarArg, MF, TM, locs, C) {
83 assert(((PC == Call) || (PC == Prologue)) &&
84 "ARMCCState users must specify whether their context is call"
85 "or prologue generation.");
91 // The APCS parameter registers.
92 static const unsigned GPRArgRegs[] = {
93 ARM::R0, ARM::R1, ARM::R2, ARM::R3
96 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
97 EVT PromotedBitwiseVT) {
98 if (VT != PromotedLdStVT) {
99 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
100 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
101 PromotedLdStVT.getSimpleVT());
103 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
104 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
105 PromotedLdStVT.getSimpleVT());
108 EVT ElemTy = VT.getVectorElementType();
109 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
110 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
111 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
112 if (ElemTy != MVT::i32) {
113 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
114 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
116 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
118 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
119 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
120 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
121 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
122 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
123 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
124 if (VT.isInteger()) {
125 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
126 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
127 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
128 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
129 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
130 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
131 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
132 setTruncStoreAction(VT.getSimpleVT(),
133 (MVT::SimpleValueType)InnerVT, Expand);
135 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
137 // Promote all bit-wise operations.
138 if (VT.isInteger() && VT != PromotedBitwiseVT) {
139 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
140 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
141 PromotedBitwiseVT.getSimpleVT());
142 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
143 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
144 PromotedBitwiseVT.getSimpleVT());
145 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
146 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
147 PromotedBitwiseVT.getSimpleVT());
150 // Neon does not support vector divide/remainder operations.
151 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
152 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
153 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
154 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
155 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
156 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
159 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
160 addRegisterClass(VT, ARM::DPRRegisterClass);
161 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
164 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
165 addRegisterClass(VT, ARM::QPRRegisterClass);
166 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
169 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
170 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
171 return new TargetLoweringObjectFileMachO();
173 return new ARMElfTargetObjectFile();
176 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
177 : TargetLowering(TM, createTLOF(TM)) {
178 Subtarget = &TM.getSubtarget<ARMSubtarget>();
179 RegInfo = TM.getRegisterInfo();
180 Itins = TM.getInstrItineraryData();
182 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
184 if (Subtarget->isTargetDarwin()) {
185 // Uses VFP for Thumb libfuncs if available.
186 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
187 // Single-precision floating-point arithmetic.
188 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
189 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
190 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
191 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
193 // Double-precision floating-point arithmetic.
194 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
195 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
196 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
197 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
199 // Single-precision comparisons.
200 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
201 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
202 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
203 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
204 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
205 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
206 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
207 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
209 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
218 // Double-precision comparisons.
219 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
220 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
221 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
222 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
223 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
224 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
225 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
226 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
228 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
229 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
230 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
231 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
232 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
233 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
234 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
235 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
237 // Floating-point to integer conversions.
238 // i64 conversions are done via library routines even when generating VFP
239 // instructions, so use the same ones.
240 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
241 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
242 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
243 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
245 // Conversions between floating types.
246 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
247 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
249 // Integer to floating-point conversions.
250 // i64 conversions are done via library routines even when generating VFP
251 // instructions, so use the same ones.
252 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
253 // e.g., __floatunsidf vs. __floatunssidfvfp.
254 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
255 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
256 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
257 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
261 // These libcalls are not available in 32-bit.
262 setLibcallName(RTLIB::SHL_I128, 0);
263 setLibcallName(RTLIB::SRL_I128, 0);
264 setLibcallName(RTLIB::SRA_I128, 0);
266 if (Subtarget->isAAPCS_ABI()) {
267 // Double-precision floating-point arithmetic helper functions
268 // RTABI chapter 4.1.2, Table 2
269 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
270 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
271 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
272 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
273 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
278 // Double-precision floating-point comparison helper functions
279 // RTABI chapter 4.1.2, Table 3
280 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
281 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
282 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
283 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
284 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
285 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
286 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
287 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
288 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
289 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
290 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
291 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
292 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
293 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
294 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
295 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
296 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
297 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
298 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
299 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
300 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
301 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
302 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
303 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
305 // Single-precision floating-point arithmetic helper functions
306 // RTABI chapter 4.1.2, Table 4
307 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
308 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
309 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
310 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
311 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
316 // Single-precision floating-point comparison helper functions
317 // RTABI chapter 4.1.2, Table 5
318 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
319 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
320 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
321 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
322 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
323 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
324 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
325 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
326 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
327 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
328 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
329 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
330 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
331 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
332 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
333 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
334 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
338 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
339 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
340 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
341 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
343 // Floating-point to integer conversions.
344 // RTABI chapter 4.1.2, Table 6
345 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
346 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
347 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
348 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
349 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
350 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
351 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
352 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
353 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
362 // Conversions between floating types.
363 // RTABI chapter 4.1.2, Table 7
364 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
365 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
366 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
367 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
369 // Integer to floating-point conversions.
370 // RTABI chapter 4.1.2, Table 8
371 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
372 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
373 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
374 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
375 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
376 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
377 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
378 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
379 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
380 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
381 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
382 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
383 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
384 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
385 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
386 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
388 // Long long helper functions
389 // RTABI chapter 4.2, Table 9
390 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
391 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
392 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
393 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
394 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
395 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
396 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
397 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
398 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
399 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
400 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
401 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
403 // Integer division functions
404 // RTABI chapter 4.3.1
405 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
406 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
407 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
408 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
409 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
410 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
411 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
412 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
413 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
414 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
415 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
416 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
419 // RTABI chapter 4.3.4
420 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
421 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
422 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
425 if (Subtarget->isThumb1Only())
426 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
428 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
429 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
430 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
431 if (!Subtarget->isFPOnlySP())
432 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
434 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
437 if (Subtarget->hasNEON()) {
438 addDRTypeForNEON(MVT::v2f32);
439 addDRTypeForNEON(MVT::v8i8);
440 addDRTypeForNEON(MVT::v4i16);
441 addDRTypeForNEON(MVT::v2i32);
442 addDRTypeForNEON(MVT::v1i64);
444 addQRTypeForNEON(MVT::v4f32);
445 addQRTypeForNEON(MVT::v2f64);
446 addQRTypeForNEON(MVT::v16i8);
447 addQRTypeForNEON(MVT::v8i16);
448 addQRTypeForNEON(MVT::v4i32);
449 addQRTypeForNEON(MVT::v2i64);
451 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
452 // neither Neon nor VFP support any arithmetic operations on it.
453 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
454 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
455 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
456 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
457 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
458 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
459 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
460 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
461 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
462 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
463 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
464 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
465 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
466 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
467 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
468 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
469 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
470 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
471 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
472 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
473 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
474 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
475 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
476 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
478 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
480 // Neon does not support some operations on v1i64 and v2i64 types.
481 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
482 // Custom handling for some quad-vector types to detect VMULL.
483 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
484 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
485 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
486 // Custom handling for some vector types to avoid expensive expansions
487 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
488 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
489 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
490 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
491 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
492 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
493 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
494 // a destination type that is wider than the source.
495 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
496 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
498 setTargetDAGCombine(ISD::INTRINSIC_VOID);
499 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
500 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
501 setTargetDAGCombine(ISD::SHL);
502 setTargetDAGCombine(ISD::SRL);
503 setTargetDAGCombine(ISD::SRA);
504 setTargetDAGCombine(ISD::SIGN_EXTEND);
505 setTargetDAGCombine(ISD::ZERO_EXTEND);
506 setTargetDAGCombine(ISD::ANY_EXTEND);
507 setTargetDAGCombine(ISD::SELECT_CC);
508 setTargetDAGCombine(ISD::BUILD_VECTOR);
509 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
510 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
511 setTargetDAGCombine(ISD::STORE);
512 setTargetDAGCombine(ISD::FP_TO_SINT);
513 setTargetDAGCombine(ISD::FP_TO_UINT);
514 setTargetDAGCombine(ISD::FDIV);
517 computeRegisterProperties();
519 // ARM does not have f32 extending load.
520 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
522 // ARM does not have i1 sign extending load.
523 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
525 // ARM supports all 4 flavors of integer indexed load / store.
526 if (!Subtarget->isThumb1Only()) {
527 for (unsigned im = (unsigned)ISD::PRE_INC;
528 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
529 setIndexedLoadAction(im, MVT::i1, Legal);
530 setIndexedLoadAction(im, MVT::i8, Legal);
531 setIndexedLoadAction(im, MVT::i16, Legal);
532 setIndexedLoadAction(im, MVT::i32, Legal);
533 setIndexedStoreAction(im, MVT::i1, Legal);
534 setIndexedStoreAction(im, MVT::i8, Legal);
535 setIndexedStoreAction(im, MVT::i16, Legal);
536 setIndexedStoreAction(im, MVT::i32, Legal);
540 // i64 operation support.
541 setOperationAction(ISD::MUL, MVT::i64, Expand);
542 setOperationAction(ISD::MULHU, MVT::i32, Expand);
543 if (Subtarget->isThumb1Only()) {
544 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
545 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
547 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
548 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
549 setOperationAction(ISD::MULHS, MVT::i32, Expand);
551 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
552 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
553 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
554 setOperationAction(ISD::SRL, MVT::i64, Custom);
555 setOperationAction(ISD::SRA, MVT::i64, Custom);
557 if (!Subtarget->isThumb1Only()) {
558 // FIXME: We should do this for Thumb1 as well.
559 setOperationAction(ISD::ADDC, MVT::i32, Custom);
560 setOperationAction(ISD::ADDE, MVT::i32, Custom);
561 setOperationAction(ISD::SUBC, MVT::i32, Custom);
562 setOperationAction(ISD::SUBE, MVT::i32, Custom);
565 // ARM does not have ROTL.
566 setOperationAction(ISD::ROTL, MVT::i32, Expand);
567 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
568 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
569 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
570 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
572 // Only ARMv6 has BSWAP.
573 if (!Subtarget->hasV6Ops())
574 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
576 // These are expanded into libcalls.
577 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
578 // v7M has a hardware divider
579 setOperationAction(ISD::SDIV, MVT::i32, Expand);
580 setOperationAction(ISD::UDIV, MVT::i32, Expand);
582 setOperationAction(ISD::SREM, MVT::i32, Expand);
583 setOperationAction(ISD::UREM, MVT::i32, Expand);
584 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
585 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
587 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
588 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
589 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
590 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
591 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
593 setOperationAction(ISD::TRAP, MVT::Other, Legal);
595 // Use the default implementation.
596 setOperationAction(ISD::VASTART, MVT::Other, Custom);
597 setOperationAction(ISD::VAARG, MVT::Other, Expand);
598 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
599 setOperationAction(ISD::VAEND, MVT::Other, Expand);
600 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
601 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
602 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
603 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
604 setExceptionPointerRegister(ARM::R0);
605 setExceptionSelectorRegister(ARM::R1);
607 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
608 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
609 // the default expansion.
610 // FIXME: This should be checking for v6k, not just v6.
611 if (Subtarget->hasDataBarrier() ||
612 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
613 // membarrier needs custom lowering; the rest are legal and handled
615 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
616 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
617 // Custom lowering for 64-bit ops
618 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
619 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
621 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
622 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
623 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
624 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
625 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
626 setInsertFencesForAtomic(true);
628 // Set them all for expansion, which will force libcalls.
629 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
630 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
631 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
632 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
633 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
634 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
635 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
636 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
637 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
638 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
639 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
640 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
641 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
642 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
643 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
644 // Unordered/Monotonic case.
645 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
646 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
647 // Since the libcalls include locking, fold in the fences
648 setShouldFoldAtomicFences(true);
651 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
653 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
654 if (!Subtarget->hasV6Ops()) {
655 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
656 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
658 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
660 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
661 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
662 // iff target supports vfp2.
663 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
664 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
667 // We want to custom lower some of our intrinsics.
668 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
669 if (Subtarget->isTargetDarwin()) {
670 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
671 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
672 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
673 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
676 setOperationAction(ISD::SETCC, MVT::i32, Expand);
677 setOperationAction(ISD::SETCC, MVT::f32, Expand);
678 setOperationAction(ISD::SETCC, MVT::f64, Expand);
679 setOperationAction(ISD::SELECT, MVT::i32, Custom);
680 setOperationAction(ISD::SELECT, MVT::f32, Custom);
681 setOperationAction(ISD::SELECT, MVT::f64, Custom);
682 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
683 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
684 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
686 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
687 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
688 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
689 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
690 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
692 // We don't support sin/cos/fmod/copysign/pow
693 setOperationAction(ISD::FSIN, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN, MVT::f32, Expand);
695 setOperationAction(ISD::FCOS, MVT::f32, Expand);
696 setOperationAction(ISD::FCOS, MVT::f64, Expand);
697 setOperationAction(ISD::FREM, MVT::f64, Expand);
698 setOperationAction(ISD::FREM, MVT::f32, Expand);
699 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
700 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
701 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
703 setOperationAction(ISD::FPOW, MVT::f64, Expand);
704 setOperationAction(ISD::FPOW, MVT::f32, Expand);
706 setOperationAction(ISD::FMA, MVT::f64, Expand);
707 setOperationAction(ISD::FMA, MVT::f32, Expand);
709 // Various VFP goodness
710 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
711 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
712 if (Subtarget->hasVFP2()) {
713 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
714 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
715 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
716 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
718 // Special handling for half-precision FP.
719 if (!Subtarget->hasFP16()) {
720 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
721 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
725 // We have target-specific dag combine patterns for the following nodes:
726 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
727 setTargetDAGCombine(ISD::ADD);
728 setTargetDAGCombine(ISD::SUB);
729 setTargetDAGCombine(ISD::MUL);
731 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
732 setTargetDAGCombine(ISD::OR);
733 if (Subtarget->hasNEON())
734 setTargetDAGCombine(ISD::AND);
736 setStackPointerRegisterToSaveRestore(ARM::SP);
738 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
739 setSchedulingPreference(Sched::RegPressure);
741 setSchedulingPreference(Sched::Hybrid);
743 //// temporary - rewrite interface to use type
744 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
746 // On ARM arguments smaller than 4 bytes are extended, so all arguments
747 // are at least 4 bytes aligned.
748 setMinStackArgumentAlignment(4);
750 benefitFromCodePlacementOpt = true;
752 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
755 // FIXME: It might make sense to define the representative register class as the
756 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
757 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
758 // SPR's representative would be DPR_VFP2. This should work well if register
759 // pressure tracking were modified such that a register use would increment the
760 // pressure of the register class's representative and all of it's super
761 // classes' representatives transitively. We have not implemented this because
762 // of the difficulty prior to coalescing of modeling operand register classes
763 // due to the common occurrence of cross class copies and subregister insertions
765 std::pair<const TargetRegisterClass*, uint8_t>
766 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
767 const TargetRegisterClass *RRC = 0;
769 switch (VT.getSimpleVT().SimpleTy) {
771 return TargetLowering::findRepresentativeClass(VT);
772 // Use DPR as representative register class for all floating point
773 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
774 // the cost is 1 for both f32 and f64.
775 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
776 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
777 RRC = ARM::DPRRegisterClass;
778 // When NEON is used for SP, only half of the register file is available
779 // because operations that define both SP and DP results will be constrained
780 // to the VFP2 class (D0-D15). We currently model this constraint prior to
781 // coalescing by double-counting the SP regs. See the FIXME above.
782 if (Subtarget->useNEONForSinglePrecisionFP())
785 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
786 case MVT::v4f32: case MVT::v2f64:
787 RRC = ARM::DPRRegisterClass;
791 RRC = ARM::DPRRegisterClass;
795 RRC = ARM::DPRRegisterClass;
799 return std::make_pair(RRC, Cost);
802 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
805 case ARMISD::Wrapper: return "ARMISD::Wrapper";
806 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
807 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
808 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
809 case ARMISD::CALL: return "ARMISD::CALL";
810 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
811 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
812 case ARMISD::tCALL: return "ARMISD::tCALL";
813 case ARMISD::BRCOND: return "ARMISD::BRCOND";
814 case ARMISD::BR_JT: return "ARMISD::BR_JT";
815 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
816 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
817 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
818 case ARMISD::CMP: return "ARMISD::CMP";
819 case ARMISD::CMPZ: return "ARMISD::CMPZ";
820 case ARMISD::CMPFP: return "ARMISD::CMPFP";
821 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
822 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
823 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
824 case ARMISD::CMOV: return "ARMISD::CMOV";
826 case ARMISD::RBIT: return "ARMISD::RBIT";
828 case ARMISD::FTOSI: return "ARMISD::FTOSI";
829 case ARMISD::FTOUI: return "ARMISD::FTOUI";
830 case ARMISD::SITOF: return "ARMISD::SITOF";
831 case ARMISD::UITOF: return "ARMISD::UITOF";
833 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
834 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
835 case ARMISD::RRX: return "ARMISD::RRX";
837 case ARMISD::ADDC: return "ARMISD::ADDC";
838 case ARMISD::ADDE: return "ARMISD::ADDE";
839 case ARMISD::SUBC: return "ARMISD::SUBC";
840 case ARMISD::SUBE: return "ARMISD::SUBE";
842 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
843 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
845 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
846 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
847 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
849 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
851 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
853 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
855 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
856 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
858 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
860 case ARMISD::VCEQ: return "ARMISD::VCEQ";
861 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
862 case ARMISD::VCGE: return "ARMISD::VCGE";
863 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
864 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
865 case ARMISD::VCGEU: return "ARMISD::VCGEU";
866 case ARMISD::VCGT: return "ARMISD::VCGT";
867 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
868 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
869 case ARMISD::VCGTU: return "ARMISD::VCGTU";
870 case ARMISD::VTST: return "ARMISD::VTST";
872 case ARMISD::VSHL: return "ARMISD::VSHL";
873 case ARMISD::VSHRs: return "ARMISD::VSHRs";
874 case ARMISD::VSHRu: return "ARMISD::VSHRu";
875 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
876 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
877 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
878 case ARMISD::VSHRN: return "ARMISD::VSHRN";
879 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
880 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
881 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
882 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
883 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
884 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
885 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
886 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
887 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
888 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
889 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
890 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
891 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
892 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
893 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
894 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
895 case ARMISD::VDUP: return "ARMISD::VDUP";
896 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
897 case ARMISD::VEXT: return "ARMISD::VEXT";
898 case ARMISD::VREV64: return "ARMISD::VREV64";
899 case ARMISD::VREV32: return "ARMISD::VREV32";
900 case ARMISD::VREV16: return "ARMISD::VREV16";
901 case ARMISD::VZIP: return "ARMISD::VZIP";
902 case ARMISD::VUZP: return "ARMISD::VUZP";
903 case ARMISD::VTRN: return "ARMISD::VTRN";
904 case ARMISD::VTBL1: return "ARMISD::VTBL1";
905 case ARMISD::VTBL2: return "ARMISD::VTBL2";
906 case ARMISD::VMULLs: return "ARMISD::VMULLs";
907 case ARMISD::VMULLu: return "ARMISD::VMULLu";
908 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
909 case ARMISD::FMAX: return "ARMISD::FMAX";
910 case ARMISD::FMIN: return "ARMISD::FMIN";
911 case ARMISD::BFI: return "ARMISD::BFI";
912 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
913 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
914 case ARMISD::VBSL: return "ARMISD::VBSL";
915 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
916 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
917 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
918 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
919 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
920 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
921 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
922 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
923 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
924 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
925 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
926 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
927 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
928 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
929 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
930 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
931 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
932 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
933 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
934 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
938 EVT ARMTargetLowering::getSetCCResultType(EVT VT) const {
939 if (!VT.isVector()) return getPointerTy();
940 return VT.changeVectorElementTypeToInteger();
943 /// getRegClassFor - Return the register class that should be used for the
944 /// specified value type.
945 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
946 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
947 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
948 // load / store 4 to 8 consecutive D registers.
949 if (Subtarget->hasNEON()) {
950 if (VT == MVT::v4i64)
951 return ARM::QQPRRegisterClass;
952 else if (VT == MVT::v8i64)
953 return ARM::QQQQPRRegisterClass;
955 return TargetLowering::getRegClassFor(VT);
958 // Create a fast isel object.
960 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
961 return ARM::createFastISel(funcInfo);
964 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
965 /// be used for loads / stores from the global.
966 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
967 return (Subtarget->isThumb1Only() ? 127 : 4095);
970 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
971 unsigned NumVals = N->getNumValues();
973 return Sched::RegPressure;
975 for (unsigned i = 0; i != NumVals; ++i) {
976 EVT VT = N->getValueType(i);
977 if (VT == MVT::Glue || VT == MVT::Other)
979 if (VT.isFloatingPoint() || VT.isVector())
980 return Sched::Latency;
983 if (!N->isMachineOpcode())
984 return Sched::RegPressure;
986 // Load are scheduled for latency even if there instruction itinerary
988 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
989 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
991 if (MCID.getNumDefs() == 0)
992 return Sched::RegPressure;
993 if (!Itins->isEmpty() &&
994 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
995 return Sched::Latency;
997 return Sched::RegPressure;
1000 //===----------------------------------------------------------------------===//
1002 //===----------------------------------------------------------------------===//
1004 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1005 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1007 default: llvm_unreachable("Unknown condition code!");
1008 case ISD::SETNE: return ARMCC::NE;
1009 case ISD::SETEQ: return ARMCC::EQ;
1010 case ISD::SETGT: return ARMCC::GT;
1011 case ISD::SETGE: return ARMCC::GE;
1012 case ISD::SETLT: return ARMCC::LT;
1013 case ISD::SETLE: return ARMCC::LE;
1014 case ISD::SETUGT: return ARMCC::HI;
1015 case ISD::SETUGE: return ARMCC::HS;
1016 case ISD::SETULT: return ARMCC::LO;
1017 case ISD::SETULE: return ARMCC::LS;
1021 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1022 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1023 ARMCC::CondCodes &CondCode2) {
1024 CondCode2 = ARMCC::AL;
1026 default: llvm_unreachable("Unknown FP condition!");
1028 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1030 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1032 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1033 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1034 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1035 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1036 case ISD::SETO: CondCode = ARMCC::VC; break;
1037 case ISD::SETUO: CondCode = ARMCC::VS; break;
1038 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1039 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1040 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1042 case ISD::SETULT: CondCode = ARMCC::LT; break;
1044 case ISD::SETULE: CondCode = ARMCC::LE; break;
1046 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1050 //===----------------------------------------------------------------------===//
1051 // Calling Convention Implementation
1052 //===----------------------------------------------------------------------===//
1054 #include "ARMGenCallingConv.inc"
1056 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1057 /// given CallingConvention value.
1058 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1060 bool isVarArg) const {
1063 llvm_unreachable("Unsupported calling convention");
1064 case CallingConv::Fast:
1065 if (Subtarget->hasVFP2() && !isVarArg) {
1066 if (!Subtarget->isAAPCS_ABI())
1067 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1068 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1069 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1072 case CallingConv::C: {
1073 // Use target triple & subtarget features to do actual dispatch.
1074 if (!Subtarget->isAAPCS_ABI())
1075 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1076 else if (Subtarget->hasVFP2() &&
1077 FloatABIType == FloatABI::Hard && !isVarArg)
1078 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1079 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1081 case CallingConv::ARM_AAPCS_VFP:
1082 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1083 case CallingConv::ARM_AAPCS:
1084 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1085 case CallingConv::ARM_APCS:
1086 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1090 /// LowerCallResult - Lower the result values of a call into the
1091 /// appropriate copies out of appropriate physical registers.
1093 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1094 CallingConv::ID CallConv, bool isVarArg,
1095 const SmallVectorImpl<ISD::InputArg> &Ins,
1096 DebugLoc dl, SelectionDAG &DAG,
1097 SmallVectorImpl<SDValue> &InVals) const {
1099 // Assign locations to each value returned by this call.
1100 SmallVector<CCValAssign, 16> RVLocs;
1101 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1102 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1103 CCInfo.AnalyzeCallResult(Ins,
1104 CCAssignFnForNode(CallConv, /* Return*/ true,
1107 // Copy all of the result registers out of their specified physreg.
1108 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1109 CCValAssign VA = RVLocs[i];
1112 if (VA.needsCustom()) {
1113 // Handle f64 or half of a v2f64.
1114 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1116 Chain = Lo.getValue(1);
1117 InFlag = Lo.getValue(2);
1118 VA = RVLocs[++i]; // skip ahead to next loc
1119 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1121 Chain = Hi.getValue(1);
1122 InFlag = Hi.getValue(2);
1123 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1125 if (VA.getLocVT() == MVT::v2f64) {
1126 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1127 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1128 DAG.getConstant(0, MVT::i32));
1130 VA = RVLocs[++i]; // skip ahead to next loc
1131 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1132 Chain = Lo.getValue(1);
1133 InFlag = Lo.getValue(2);
1134 VA = RVLocs[++i]; // skip ahead to next loc
1135 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1136 Chain = Hi.getValue(1);
1137 InFlag = Hi.getValue(2);
1138 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1139 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1140 DAG.getConstant(1, MVT::i32));
1143 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1145 Chain = Val.getValue(1);
1146 InFlag = Val.getValue(2);
1149 switch (VA.getLocInfo()) {
1150 default: llvm_unreachable("Unknown loc info!");
1151 case CCValAssign::Full: break;
1152 case CCValAssign::BCvt:
1153 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1157 InVals.push_back(Val);
1163 /// LowerMemOpCallTo - Store the argument to the stack.
1165 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1166 SDValue StackPtr, SDValue Arg,
1167 DebugLoc dl, SelectionDAG &DAG,
1168 const CCValAssign &VA,
1169 ISD::ArgFlagsTy Flags) const {
1170 unsigned LocMemOffset = VA.getLocMemOffset();
1171 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1172 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1173 return DAG.getStore(Chain, dl, Arg, PtrOff,
1174 MachinePointerInfo::getStack(LocMemOffset),
1178 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1179 SDValue Chain, SDValue &Arg,
1180 RegsToPassVector &RegsToPass,
1181 CCValAssign &VA, CCValAssign &NextVA,
1183 SmallVector<SDValue, 8> &MemOpChains,
1184 ISD::ArgFlagsTy Flags) const {
1186 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1187 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1188 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1190 if (NextVA.isRegLoc())
1191 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1193 assert(NextVA.isMemLoc());
1194 if (StackPtr.getNode() == 0)
1195 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1197 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1203 /// LowerCall - Lowering a call into a callseq_start <-
1204 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1207 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1208 CallingConv::ID CallConv, bool isVarArg,
1210 const SmallVectorImpl<ISD::OutputArg> &Outs,
1211 const SmallVectorImpl<SDValue> &OutVals,
1212 const SmallVectorImpl<ISD::InputArg> &Ins,
1213 DebugLoc dl, SelectionDAG &DAG,
1214 SmallVectorImpl<SDValue> &InVals) const {
1215 MachineFunction &MF = DAG.getMachineFunction();
1216 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1217 bool IsSibCall = false;
1218 // Temporarily disable tail calls so things don't break.
1219 if (!EnableARMTailCalls)
1222 // Check if it's really possible to do a tail call.
1223 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1224 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1225 Outs, OutVals, Ins, DAG);
1226 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1227 // detected sibcalls.
1234 // Analyze operands of the call, assigning locations to each operand.
1235 SmallVector<CCValAssign, 16> ArgLocs;
1236 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1237 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1238 CCInfo.AnalyzeCallOperands(Outs,
1239 CCAssignFnForNode(CallConv, /* Return*/ false,
1242 // Get a count of how many bytes are to be pushed on the stack.
1243 unsigned NumBytes = CCInfo.getNextStackOffset();
1245 // For tail calls, memory operands are available in our caller's stack.
1249 // Adjust the stack pointer for the new arguments...
1250 // These operations are automatically eliminated by the prolog/epilog pass
1252 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1254 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1256 RegsToPassVector RegsToPass;
1257 SmallVector<SDValue, 8> MemOpChains;
1259 // Walk the register/memloc assignments, inserting copies/loads. In the case
1260 // of tail call optimization, arguments are handled later.
1261 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1263 ++i, ++realArgIdx) {
1264 CCValAssign &VA = ArgLocs[i];
1265 SDValue Arg = OutVals[realArgIdx];
1266 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1267 bool isByVal = Flags.isByVal();
1269 // Promote the value if needed.
1270 switch (VA.getLocInfo()) {
1271 default: llvm_unreachable("Unknown loc info!");
1272 case CCValAssign::Full: break;
1273 case CCValAssign::SExt:
1274 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1276 case CCValAssign::ZExt:
1277 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1279 case CCValAssign::AExt:
1280 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1282 case CCValAssign::BCvt:
1283 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1287 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1288 if (VA.needsCustom()) {
1289 if (VA.getLocVT() == MVT::v2f64) {
1290 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1291 DAG.getConstant(0, MVT::i32));
1292 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1293 DAG.getConstant(1, MVT::i32));
1295 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1296 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1298 VA = ArgLocs[++i]; // skip ahead to next loc
1299 if (VA.isRegLoc()) {
1300 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1301 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1303 assert(VA.isMemLoc());
1305 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1306 dl, DAG, VA, Flags));
1309 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1310 StackPtr, MemOpChains, Flags);
1312 } else if (VA.isRegLoc()) {
1313 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1314 } else if (isByVal) {
1315 assert(VA.isMemLoc());
1316 unsigned offset = 0;
1318 // True if this byval aggregate will be split between registers
1320 if (CCInfo.isFirstByValRegValid()) {
1321 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1323 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) {
1324 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1325 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1326 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1327 MachinePointerInfo(),
1329 MemOpChains.push_back(Load.getValue(1));
1330 RegsToPass.push_back(std::make_pair(j, Load));
1332 offset = ARM::R4 - CCInfo.getFirstByValReg();
1333 CCInfo.clearFirstByValReg();
1336 unsigned LocMemOffset = VA.getLocMemOffset();
1337 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1338 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1340 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1341 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1342 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1344 // TODO: Disable AlwaysInline when it becomes possible
1345 // to emit a nested call sequence.
1346 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
1347 Flags.getByValAlign(),
1348 /*isVolatile=*/false,
1349 /*AlwaysInline=*/true,
1350 MachinePointerInfo(0),
1351 MachinePointerInfo(0)));
1353 } else if (!IsSibCall) {
1354 assert(VA.isMemLoc());
1356 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1357 dl, DAG, VA, Flags));
1361 if (!MemOpChains.empty())
1362 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1363 &MemOpChains[0], MemOpChains.size());
1365 // Build a sequence of copy-to-reg nodes chained together with token chain
1366 // and flag operands which copy the outgoing args into the appropriate regs.
1368 // Tail call byval lowering might overwrite argument registers so in case of
1369 // tail call optimization the copies to registers are lowered later.
1371 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1372 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1373 RegsToPass[i].second, InFlag);
1374 InFlag = Chain.getValue(1);
1377 // For tail calls lower the arguments to the 'real' stack slot.
1379 // Force all the incoming stack arguments to be loaded from the stack
1380 // before any new outgoing arguments are stored to the stack, because the
1381 // outgoing stack slots may alias the incoming argument stack slots, and
1382 // the alias isn't otherwise explicit. This is slightly more conservative
1383 // than necessary, because it means that each store effectively depends
1384 // on every argument instead of just those arguments it would clobber.
1386 // Do not flag preceding copytoreg stuff together with the following stuff.
1388 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1389 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1390 RegsToPass[i].second, InFlag);
1391 InFlag = Chain.getValue(1);
1396 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1397 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1398 // node so that legalize doesn't hack it.
1399 bool isDirect = false;
1400 bool isARMFunc = false;
1401 bool isLocalARMFunc = false;
1402 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1404 if (EnableARMLongCalls) {
1405 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1406 && "long-calls with non-static relocation model!");
1407 // Handle a global address or an external symbol. If it's not one of
1408 // those, the target's already in a register, so we don't need to do
1410 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1411 const GlobalValue *GV = G->getGlobal();
1412 // Create a constant pool entry for the callee address
1413 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1414 ARMConstantPoolValue *CPV =
1415 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1417 // Get the address of the callee into a register
1418 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1419 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1420 Callee = DAG.getLoad(getPointerTy(), dl,
1421 DAG.getEntryNode(), CPAddr,
1422 MachinePointerInfo::getConstantPool(),
1424 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1425 const char *Sym = S->getSymbol();
1427 // Create a constant pool entry for the callee address
1428 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1429 ARMConstantPoolValue *CPV =
1430 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1431 ARMPCLabelIndex, 0);
1432 // Get the address of the callee into a register
1433 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1434 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1435 Callee = DAG.getLoad(getPointerTy(), dl,
1436 DAG.getEntryNode(), CPAddr,
1437 MachinePointerInfo::getConstantPool(),
1440 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1441 const GlobalValue *GV = G->getGlobal();
1443 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1444 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1445 getTargetMachine().getRelocationModel() != Reloc::Static;
1446 isARMFunc = !Subtarget->isThumb() || isStub;
1447 // ARM call to a local ARM function is predicable.
1448 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1449 // tBX takes a register source operand.
1450 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1451 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1452 ARMConstantPoolValue *CPV =
1453 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4);
1454 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1455 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1456 Callee = DAG.getLoad(getPointerTy(), dl,
1457 DAG.getEntryNode(), CPAddr,
1458 MachinePointerInfo::getConstantPool(),
1460 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1461 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1462 getPointerTy(), Callee, PICLabel);
1464 // On ELF targets for PIC code, direct calls should go through the PLT
1465 unsigned OpFlags = 0;
1466 if (Subtarget->isTargetELF() &&
1467 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1468 OpFlags = ARMII::MO_PLT;
1469 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1471 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1473 bool isStub = Subtarget->isTargetDarwin() &&
1474 getTargetMachine().getRelocationModel() != Reloc::Static;
1475 isARMFunc = !Subtarget->isThumb() || isStub;
1476 // tBX takes a register source operand.
1477 const char *Sym = S->getSymbol();
1478 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1479 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1480 ARMConstantPoolValue *CPV =
1481 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1482 ARMPCLabelIndex, 4);
1483 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1484 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1485 Callee = DAG.getLoad(getPointerTy(), dl,
1486 DAG.getEntryNode(), CPAddr,
1487 MachinePointerInfo::getConstantPool(),
1489 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1490 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1491 getPointerTy(), Callee, PICLabel);
1493 unsigned OpFlags = 0;
1494 // On ELF targets for PIC code, direct calls should go through the PLT
1495 if (Subtarget->isTargetELF() &&
1496 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1497 OpFlags = ARMII::MO_PLT;
1498 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1502 // FIXME: handle tail calls differently.
1504 if (Subtarget->isThumb()) {
1505 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1506 CallOpc = ARMISD::CALL_NOLINK;
1508 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1510 CallOpc = (isDirect || Subtarget->hasV5TOps())
1511 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1512 : ARMISD::CALL_NOLINK;
1515 std::vector<SDValue> Ops;
1516 Ops.push_back(Chain);
1517 Ops.push_back(Callee);
1519 // Add argument registers to the end of the list so that they are known live
1521 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1522 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1523 RegsToPass[i].second.getValueType()));
1525 if (InFlag.getNode())
1526 Ops.push_back(InFlag);
1528 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1530 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1532 // Returns a chain and a flag for retval copy to use.
1533 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1534 InFlag = Chain.getValue(1);
1536 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1537 DAG.getIntPtrConstant(0, true), InFlag);
1539 InFlag = Chain.getValue(1);
1541 // Handle result values, copying them out of physregs into vregs that we
1543 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1547 /// HandleByVal - Every parameter *after* a byval parameter is passed
1548 /// on the stack. Remember the next parameter register to allocate,
1549 /// and then confiscate the rest of the parameter registers to insure
1552 llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const {
1553 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1554 assert((State->getCallOrPrologue() == Prologue ||
1555 State->getCallOrPrologue() == Call) &&
1556 "unhandled ParmContext");
1557 if ((!State->isFirstByValRegValid()) &&
1558 (ARM::R0 <= reg) && (reg <= ARM::R3)) {
1559 State->setFirstByValReg(reg);
1560 // At a call site, a byval parameter that is split between
1561 // registers and memory needs its size truncated here. In a
1562 // function prologue, such byval parameters are reassembled in
1563 // memory, and are not truncated.
1564 if (State->getCallOrPrologue() == Call) {
1565 unsigned excess = 4 * (ARM::R4 - reg);
1566 assert(size >= excess && "expected larger existing stack allocation");
1570 // Confiscate any remaining parameter registers to preclude their
1571 // assignment to subsequent parameters.
1572 while (State->AllocateReg(GPRArgRegs, 4))
1576 /// MatchingStackOffset - Return true if the given stack call argument is
1577 /// already available in the same position (relatively) of the caller's
1578 /// incoming argument stack.
1580 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1581 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1582 const ARMInstrInfo *TII) {
1583 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1585 if (Arg.getOpcode() == ISD::CopyFromReg) {
1586 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1587 if (!TargetRegisterInfo::isVirtualRegister(VR))
1589 MachineInstr *Def = MRI->getVRegDef(VR);
1592 if (!Flags.isByVal()) {
1593 if (!TII->isLoadFromStackSlot(Def, FI))
1598 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1599 if (Flags.isByVal())
1600 // ByVal argument is passed in as a pointer but it's now being
1601 // dereferenced. e.g.
1602 // define @foo(%struct.X* %A) {
1603 // tail call @bar(%struct.X* byval %A)
1606 SDValue Ptr = Ld->getBasePtr();
1607 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1610 FI = FINode->getIndex();
1614 assert(FI != INT_MAX);
1615 if (!MFI->isFixedObjectIndex(FI))
1617 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1620 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1621 /// for tail call optimization. Targets which want to do tail call
1622 /// optimization should implement this function.
1624 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1625 CallingConv::ID CalleeCC,
1627 bool isCalleeStructRet,
1628 bool isCallerStructRet,
1629 const SmallVectorImpl<ISD::OutputArg> &Outs,
1630 const SmallVectorImpl<SDValue> &OutVals,
1631 const SmallVectorImpl<ISD::InputArg> &Ins,
1632 SelectionDAG& DAG) const {
1633 const Function *CallerF = DAG.getMachineFunction().getFunction();
1634 CallingConv::ID CallerCC = CallerF->getCallingConv();
1635 bool CCMatch = CallerCC == CalleeCC;
1637 // Look for obvious safe cases to perform tail call optimization that do not
1638 // require ABI changes. This is what gcc calls sibcall.
1640 // Do not sibcall optimize vararg calls unless the call site is not passing
1642 if (isVarArg && !Outs.empty())
1645 // Also avoid sibcall optimization if either caller or callee uses struct
1646 // return semantics.
1647 if (isCalleeStructRet || isCallerStructRet)
1650 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1651 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1652 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1653 // support in the assembler and linker to be used. This would need to be
1654 // fixed to fully support tail calls in Thumb1.
1656 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1657 // LR. This means if we need to reload LR, it takes an extra instructions,
1658 // which outweighs the value of the tail call; but here we don't know yet
1659 // whether LR is going to be used. Probably the right approach is to
1660 // generate the tail call here and turn it back into CALL/RET in
1661 // emitEpilogue if LR is used.
1663 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1664 // but we need to make sure there are enough registers; the only valid
1665 // registers are the 4 used for parameters. We don't currently do this
1667 if (Subtarget->isThumb1Only())
1670 // If the calling conventions do not match, then we'd better make sure the
1671 // results are returned in the same way as what the caller expects.
1673 SmallVector<CCValAssign, 16> RVLocs1;
1674 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1675 getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
1676 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1678 SmallVector<CCValAssign, 16> RVLocs2;
1679 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1680 getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
1681 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1683 if (RVLocs1.size() != RVLocs2.size())
1685 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1686 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1688 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1690 if (RVLocs1[i].isRegLoc()) {
1691 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1694 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1700 // If the callee takes no arguments then go on to check the results of the
1702 if (!Outs.empty()) {
1703 // Check if stack adjustment is needed. For now, do not do this if any
1704 // argument is passed on the stack.
1705 SmallVector<CCValAssign, 16> ArgLocs;
1706 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
1707 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1708 CCInfo.AnalyzeCallOperands(Outs,
1709 CCAssignFnForNode(CalleeCC, false, isVarArg));
1710 if (CCInfo.getNextStackOffset()) {
1711 MachineFunction &MF = DAG.getMachineFunction();
1713 // Check if the arguments are already laid out in the right way as
1714 // the caller's fixed stack objects.
1715 MachineFrameInfo *MFI = MF.getFrameInfo();
1716 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1717 const ARMInstrInfo *TII =
1718 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1719 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1721 ++i, ++realArgIdx) {
1722 CCValAssign &VA = ArgLocs[i];
1723 EVT RegVT = VA.getLocVT();
1724 SDValue Arg = OutVals[realArgIdx];
1725 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1726 if (VA.getLocInfo() == CCValAssign::Indirect)
1728 if (VA.needsCustom()) {
1729 // f64 and vector types are split into multiple registers or
1730 // register/stack-slot combinations. The types will not match
1731 // the registers; give up on memory f64 refs until we figure
1732 // out what to do about this.
1735 if (!ArgLocs[++i].isRegLoc())
1737 if (RegVT == MVT::v2f64) {
1738 if (!ArgLocs[++i].isRegLoc())
1740 if (!ArgLocs[++i].isRegLoc())
1743 } else if (!VA.isRegLoc()) {
1744 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1756 ARMTargetLowering::LowerReturn(SDValue Chain,
1757 CallingConv::ID CallConv, bool isVarArg,
1758 const SmallVectorImpl<ISD::OutputArg> &Outs,
1759 const SmallVectorImpl<SDValue> &OutVals,
1760 DebugLoc dl, SelectionDAG &DAG) const {
1762 // CCValAssign - represent the assignment of the return value to a location.
1763 SmallVector<CCValAssign, 16> RVLocs;
1765 // CCState - Info about the registers and stack slots.
1766 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1767 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1769 // Analyze outgoing return values.
1770 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1773 // If this is the first return lowered for this function, add
1774 // the regs to the liveout set for the function.
1775 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1776 for (unsigned i = 0; i != RVLocs.size(); ++i)
1777 if (RVLocs[i].isRegLoc())
1778 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1783 // Copy the result values into the output registers.
1784 for (unsigned i = 0, realRVLocIdx = 0;
1786 ++i, ++realRVLocIdx) {
1787 CCValAssign &VA = RVLocs[i];
1788 assert(VA.isRegLoc() && "Can only return in registers!");
1790 SDValue Arg = OutVals[realRVLocIdx];
1792 switch (VA.getLocInfo()) {
1793 default: llvm_unreachable("Unknown loc info!");
1794 case CCValAssign::Full: break;
1795 case CCValAssign::BCvt:
1796 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1800 if (VA.needsCustom()) {
1801 if (VA.getLocVT() == MVT::v2f64) {
1802 // Extract the first half and return it in two registers.
1803 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1804 DAG.getConstant(0, MVT::i32));
1805 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1806 DAG.getVTList(MVT::i32, MVT::i32), Half);
1808 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1809 Flag = Chain.getValue(1);
1810 VA = RVLocs[++i]; // skip ahead to next loc
1811 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1812 HalfGPRs.getValue(1), Flag);
1813 Flag = Chain.getValue(1);
1814 VA = RVLocs[++i]; // skip ahead to next loc
1816 // Extract the 2nd half and fall through to handle it as an f64 value.
1817 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1818 DAG.getConstant(1, MVT::i32));
1820 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1822 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1823 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1824 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1825 Flag = Chain.getValue(1);
1826 VA = RVLocs[++i]; // skip ahead to next loc
1827 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1830 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1832 // Guarantee that all emitted copies are
1833 // stuck together, avoiding something bad.
1834 Flag = Chain.getValue(1);
1839 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1841 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1846 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1847 if (N->getNumValues() != 1)
1849 if (!N->hasNUsesOfValue(1, 0))
1852 unsigned NumCopies = 0;
1854 SDNode *Use = *N->use_begin();
1855 if (Use->getOpcode() == ISD::CopyToReg) {
1856 Copies[NumCopies++] = Use;
1857 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1858 // f64 returned in a pair of GPRs.
1859 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1861 if (UI->getOpcode() != ISD::CopyToReg)
1863 Copies[UI.getUse().getResNo()] = *UI;
1866 } else if (Use->getOpcode() == ISD::BITCAST) {
1867 // f32 returned in a single GPR.
1868 if (!Use->hasNUsesOfValue(1, 0))
1870 Use = *Use->use_begin();
1871 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1873 Copies[NumCopies++] = Use;
1878 if (NumCopies != 1 && NumCopies != 2)
1881 bool HasRet = false;
1882 for (unsigned i = 0; i < NumCopies; ++i) {
1883 SDNode *Copy = Copies[i];
1884 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1886 if (UI->getOpcode() == ISD::CopyToReg) {
1888 if (Use == Copies[0] || Use == Copies[1])
1892 if (UI->getOpcode() != ARMISD::RET_FLAG)
1901 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1902 if (!EnableARMTailCalls)
1905 if (!CI->isTailCall())
1908 return !Subtarget->isThumb1Only();
1911 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1912 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1913 // one of the above mentioned nodes. It has to be wrapped because otherwise
1914 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1915 // be used to form addressing mode. These wrapped nodes will be selected
1917 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1918 EVT PtrVT = Op.getValueType();
1919 // FIXME there is no actual debug info here
1920 DebugLoc dl = Op.getDebugLoc();
1921 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1923 if (CP->isMachineConstantPoolEntry())
1924 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1925 CP->getAlignment());
1927 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1928 CP->getAlignment());
1929 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1932 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1933 return MachineJumpTableInfo::EK_Inline;
1936 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1937 SelectionDAG &DAG) const {
1938 MachineFunction &MF = DAG.getMachineFunction();
1939 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1940 unsigned ARMPCLabelIndex = 0;
1941 DebugLoc DL = Op.getDebugLoc();
1942 EVT PtrVT = getPointerTy();
1943 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1944 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1946 if (RelocM == Reloc::Static) {
1947 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1949 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1950 ARMPCLabelIndex = AFI->createPICLabelUId();
1951 ARMConstantPoolValue *CPV =
1952 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
1953 ARMCP::CPBlockAddress, PCAdj);
1954 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1956 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1957 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1958 MachinePointerInfo::getConstantPool(),
1960 if (RelocM == Reloc::Static)
1962 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1963 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1966 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1968 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1969 SelectionDAG &DAG) const {
1970 DebugLoc dl = GA->getDebugLoc();
1971 EVT PtrVT = getPointerTy();
1972 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1973 MachineFunction &MF = DAG.getMachineFunction();
1974 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1975 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1976 ARMConstantPoolValue *CPV =
1977 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
1978 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1979 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1980 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1981 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1982 MachinePointerInfo::getConstantPool(),
1984 SDValue Chain = Argument.getValue(1);
1986 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1987 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1989 // call __tls_get_addr.
1992 Entry.Node = Argument;
1993 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
1994 Args.push_back(Entry);
1995 // FIXME: is there useful debug info available here?
1996 std::pair<SDValue, SDValue> CallResult =
1997 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()),
1998 false, false, false, false,
1999 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
2000 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
2001 return CallResult.first;
2004 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2005 // "local exec" model.
2007 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2008 SelectionDAG &DAG) const {
2009 const GlobalValue *GV = GA->getGlobal();
2010 DebugLoc dl = GA->getDebugLoc();
2012 SDValue Chain = DAG.getEntryNode();
2013 EVT PtrVT = getPointerTy();
2014 // Get the Thread Pointer
2015 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2017 if (GV->isDeclaration()) {
2018 MachineFunction &MF = DAG.getMachineFunction();
2019 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2020 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2021 // Initial exec model.
2022 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2023 ARMConstantPoolValue *CPV =
2024 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2025 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2027 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2028 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2029 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2030 MachinePointerInfo::getConstantPool(),
2032 Chain = Offset.getValue(1);
2034 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2035 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2037 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2038 MachinePointerInfo::getConstantPool(),
2042 ARMConstantPoolValue *CPV =
2043 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2044 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2045 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2046 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2047 MachinePointerInfo::getConstantPool(),
2051 // The address of the thread local variable is the add of the thread
2052 // pointer with the offset of the variable.
2053 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2057 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2058 // TODO: implement the "local dynamic" model
2059 assert(Subtarget->isTargetELF() &&
2060 "TLS not implemented for non-ELF targets");
2061 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2062 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
2063 // otherwise use the "Local Exec" TLS Model
2064 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
2065 return LowerToTLSGeneralDynamicModel(GA, DAG);
2067 return LowerToTLSExecModels(GA, DAG);
2070 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2071 SelectionDAG &DAG) const {
2072 EVT PtrVT = getPointerTy();
2073 DebugLoc dl = Op.getDebugLoc();
2074 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2075 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2076 if (RelocM == Reloc::PIC_) {
2077 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2078 ARMConstantPoolValue *CPV =
2079 ARMConstantPoolConstant::Create(GV,
2080 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2081 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2082 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2083 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2085 MachinePointerInfo::getConstantPool(),
2087 SDValue Chain = Result.getValue(1);
2088 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2089 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2091 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2092 MachinePointerInfo::getGOT(), false, false, 0);
2096 // If we have T2 ops, we can materialize the address directly via movt/movw
2097 // pair. This is always cheaper.
2098 if (Subtarget->useMovt()) {
2100 // FIXME: Once remat is capable of dealing with instructions with register
2101 // operands, expand this into two nodes.
2102 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2103 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2105 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2106 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2107 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2108 MachinePointerInfo::getConstantPool(),
2113 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2114 SelectionDAG &DAG) const {
2115 EVT PtrVT = getPointerTy();
2116 DebugLoc dl = Op.getDebugLoc();
2117 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2118 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2119 MachineFunction &MF = DAG.getMachineFunction();
2120 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2122 // FIXME: Enable this for static codegen when tool issues are fixed.
2123 if (Subtarget->useMovt() && RelocM != Reloc::Static) {
2125 // FIXME: Once remat is capable of dealing with instructions with register
2126 // operands, expand this into two nodes.
2127 if (RelocM == Reloc::Static)
2128 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2129 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2131 unsigned Wrapper = (RelocM == Reloc::PIC_)
2132 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2133 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2134 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2135 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2136 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2137 MachinePointerInfo::getGOT(), false, false, 0);
2141 unsigned ARMPCLabelIndex = 0;
2143 if (RelocM == Reloc::Static) {
2144 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2146 ARMPCLabelIndex = AFI->createPICLabelUId();
2147 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2148 ARMConstantPoolValue *CPV =
2149 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue,
2151 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2153 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2155 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2156 MachinePointerInfo::getConstantPool(),
2158 SDValue Chain = Result.getValue(1);
2160 if (RelocM == Reloc::PIC_) {
2161 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2162 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2165 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2166 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2172 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2173 SelectionDAG &DAG) const {
2174 assert(Subtarget->isTargetELF() &&
2175 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2176 MachineFunction &MF = DAG.getMachineFunction();
2177 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2178 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2179 EVT PtrVT = getPointerTy();
2180 DebugLoc dl = Op.getDebugLoc();
2181 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2182 ARMConstantPoolValue *CPV =
2183 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2184 ARMPCLabelIndex, PCAdj);
2185 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2186 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2187 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2188 MachinePointerInfo::getConstantPool(),
2190 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2191 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2195 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2197 DebugLoc dl = Op.getDebugLoc();
2198 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2199 Op.getOperand(0), Op.getOperand(1));
2203 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2204 DebugLoc dl = Op.getDebugLoc();
2205 SDValue Val = DAG.getConstant(0, MVT::i32);
2206 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2207 Op.getOperand(1), Val);
2211 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2212 DebugLoc dl = Op.getDebugLoc();
2213 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2214 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2218 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2219 const ARMSubtarget *Subtarget) const {
2220 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2221 DebugLoc dl = Op.getDebugLoc();
2223 default: return SDValue(); // Don't custom lower most intrinsics.
2224 case Intrinsic::arm_thread_pointer: {
2225 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2226 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2228 case Intrinsic::eh_sjlj_lsda: {
2229 MachineFunction &MF = DAG.getMachineFunction();
2230 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2231 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2232 EVT PtrVT = getPointerTy();
2233 DebugLoc dl = Op.getDebugLoc();
2234 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2236 unsigned PCAdj = (RelocM != Reloc::PIC_)
2237 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2238 ARMConstantPoolValue *CPV =
2239 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2240 ARMCP::CPLSDA, PCAdj);
2241 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2242 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2244 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2245 MachinePointerInfo::getConstantPool(),
2248 if (RelocM == Reloc::PIC_) {
2249 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2250 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2254 case Intrinsic::arm_neon_vmulls:
2255 case Intrinsic::arm_neon_vmullu: {
2256 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2257 ? ARMISD::VMULLs : ARMISD::VMULLu;
2258 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2259 Op.getOperand(1), Op.getOperand(2));
2264 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2265 const ARMSubtarget *Subtarget) {
2266 DebugLoc dl = Op.getDebugLoc();
2267 if (!Subtarget->hasDataBarrier()) {
2268 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2269 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2271 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2272 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2273 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2274 DAG.getConstant(0, MVT::i32));
2277 SDValue Op5 = Op.getOperand(5);
2278 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2279 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2280 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2281 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2283 ARM_MB::MemBOpt DMBOpt;
2284 if (isDeviceBarrier)
2285 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2287 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2288 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2289 DAG.getConstant(DMBOpt, MVT::i32));
2293 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2294 const ARMSubtarget *Subtarget) {
2295 // FIXME: handle "fence singlethread" more efficiently.
2296 DebugLoc dl = Op.getDebugLoc();
2297 if (!Subtarget->hasDataBarrier()) {
2298 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2299 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2301 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2302 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2303 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2304 DAG.getConstant(0, MVT::i32));
2307 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2308 DAG.getConstant(ARM_MB::ISH, MVT::i32));
2311 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2312 const ARMSubtarget *Subtarget) {
2313 // ARM pre v5TE and Thumb1 does not have preload instructions.
2314 if (!(Subtarget->isThumb2() ||
2315 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2316 // Just preserve the chain.
2317 return Op.getOperand(0);
2319 DebugLoc dl = Op.getDebugLoc();
2320 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2322 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2323 // ARMv7 with MP extension has PLDW.
2324 return Op.getOperand(0);
2326 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2327 if (Subtarget->isThumb()) {
2329 isRead = ~isRead & 1;
2330 isData = ~isData & 1;
2333 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2334 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2335 DAG.getConstant(isData, MVT::i32));
2338 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2339 MachineFunction &MF = DAG.getMachineFunction();
2340 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2342 // vastart just stores the address of the VarArgsFrameIndex slot into the
2343 // memory location argument.
2344 DebugLoc dl = Op.getDebugLoc();
2345 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2346 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2347 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2348 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2349 MachinePointerInfo(SV), false, false, 0);
2353 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2354 SDValue &Root, SelectionDAG &DAG,
2355 DebugLoc dl) const {
2356 MachineFunction &MF = DAG.getMachineFunction();
2357 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2359 TargetRegisterClass *RC;
2360 if (AFI->isThumb1OnlyFunction())
2361 RC = ARM::tGPRRegisterClass;
2363 RC = ARM::GPRRegisterClass;
2365 // Transform the arguments stored in physical registers into virtual ones.
2366 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2367 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2370 if (NextVA.isMemLoc()) {
2371 MachineFrameInfo *MFI = MF.getFrameInfo();
2372 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2374 // Create load node to retrieve arguments from the stack.
2375 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2376 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2377 MachinePointerInfo::getFixedStack(FI),
2380 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2381 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2384 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2388 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2389 unsigned &VARegSize, unsigned &VARegSaveSize)
2392 if (CCInfo.isFirstByValRegValid())
2393 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
2395 unsigned int firstUnalloced;
2396 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2397 sizeof(GPRArgRegs) /
2398 sizeof(GPRArgRegs[0]));
2399 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2402 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2403 VARegSize = NumGPRs * 4;
2404 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2407 // The remaining GPRs hold either the beginning of variable-argument
2408 // data, or the beginning of an aggregate passed by value (usuall
2409 // byval). Either way, we allocate stack slots adjacent to the data
2410 // provided by our caller, and store the unallocated registers there.
2411 // If this is a variadic function, the va_list pointer will begin with
2412 // these values; otherwise, this reassembles a (byval) structure that
2413 // was split between registers and memory.
2415 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2416 DebugLoc dl, SDValue &Chain,
2417 unsigned ArgOffset) const {
2418 MachineFunction &MF = DAG.getMachineFunction();
2419 MachineFrameInfo *MFI = MF.getFrameInfo();
2420 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2421 unsigned firstRegToSaveIndex;
2422 if (CCInfo.isFirstByValRegValid())
2423 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
2425 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2426 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2429 unsigned VARegSize, VARegSaveSize;
2430 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2431 if (VARegSaveSize) {
2432 // If this function is vararg, store any remaining integer argument regs
2433 // to their spots on the stack so that they may be loaded by deferencing
2434 // the result of va_next.
2435 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2436 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize,
2437 ArgOffset + VARegSaveSize
2440 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2443 SmallVector<SDValue, 4> MemOps;
2444 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) {
2445 TargetRegisterClass *RC;
2446 if (AFI->isThumb1OnlyFunction())
2447 RC = ARM::tGPRRegisterClass;
2449 RC = ARM::GPRRegisterClass;
2451 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2452 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2454 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2455 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2457 MemOps.push_back(Store);
2458 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2459 DAG.getConstant(4, getPointerTy()));
2461 if (!MemOps.empty())
2462 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2463 &MemOps[0], MemOps.size());
2465 // This will point to the next argument passed via stack.
2466 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2470 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2471 CallingConv::ID CallConv, bool isVarArg,
2472 const SmallVectorImpl<ISD::InputArg>
2474 DebugLoc dl, SelectionDAG &DAG,
2475 SmallVectorImpl<SDValue> &InVals)
2477 MachineFunction &MF = DAG.getMachineFunction();
2478 MachineFrameInfo *MFI = MF.getFrameInfo();
2480 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2482 // Assign locations to all of the incoming arguments.
2483 SmallVector<CCValAssign, 16> ArgLocs;
2484 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2485 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2486 CCInfo.AnalyzeFormalArguments(Ins,
2487 CCAssignFnForNode(CallConv, /* Return*/ false,
2490 SmallVector<SDValue, 16> ArgValues;
2491 int lastInsIndex = -1;
2494 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2495 CCValAssign &VA = ArgLocs[i];
2497 // Arguments stored in registers.
2498 if (VA.isRegLoc()) {
2499 EVT RegVT = VA.getLocVT();
2501 if (VA.needsCustom()) {
2502 // f64 and vector types are split up into multiple registers or
2503 // combinations of registers and stack slots.
2504 if (VA.getLocVT() == MVT::v2f64) {
2505 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2507 VA = ArgLocs[++i]; // skip ahead to next loc
2509 if (VA.isMemLoc()) {
2510 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2511 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2512 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2513 MachinePointerInfo::getFixedStack(FI),
2516 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2519 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2520 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2521 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2522 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2523 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2525 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2528 TargetRegisterClass *RC;
2530 if (RegVT == MVT::f32)
2531 RC = ARM::SPRRegisterClass;
2532 else if (RegVT == MVT::f64)
2533 RC = ARM::DPRRegisterClass;
2534 else if (RegVT == MVT::v2f64)
2535 RC = ARM::QPRRegisterClass;
2536 else if (RegVT == MVT::i32)
2537 RC = (AFI->isThumb1OnlyFunction() ?
2538 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2540 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2542 // Transform the arguments in physical registers into virtual ones.
2543 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2544 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2547 // If this is an 8 or 16-bit value, it is really passed promoted
2548 // to 32 bits. Insert an assert[sz]ext to capture this, then
2549 // truncate to the right size.
2550 switch (VA.getLocInfo()) {
2551 default: llvm_unreachable("Unknown loc info!");
2552 case CCValAssign::Full: break;
2553 case CCValAssign::BCvt:
2554 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2556 case CCValAssign::SExt:
2557 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2558 DAG.getValueType(VA.getValVT()));
2559 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2561 case CCValAssign::ZExt:
2562 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2563 DAG.getValueType(VA.getValVT()));
2564 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2568 InVals.push_back(ArgValue);
2570 } else { // VA.isRegLoc()
2573 assert(VA.isMemLoc());
2574 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2576 int index = ArgLocs[i].getValNo();
2578 // Some Ins[] entries become multiple ArgLoc[] entries.
2579 // Process them only once.
2580 if (index != lastInsIndex)
2582 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2583 // FIXME: For now, all byval parameter objects are marked mutable.
2584 // This can be changed with more analysis.
2585 // In case of tail call optimization mark all arguments mutable.
2586 // Since they could be overwritten by lowering of arguments in case of
2588 if (Flags.isByVal()) {
2589 unsigned VARegSize, VARegSaveSize;
2590 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2591 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0);
2592 unsigned Bytes = Flags.getByValSize() - VARegSize;
2593 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2594 int FI = MFI->CreateFixedObject(Bytes,
2595 VA.getLocMemOffset(), false);
2596 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2598 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2599 VA.getLocMemOffset(), true);
2601 // Create load nodes to retrieve arguments from the stack.
2602 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2603 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2604 MachinePointerInfo::getFixedStack(FI),
2607 lastInsIndex = index;
2614 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset());
2619 /// isFloatingPointZero - Return true if this is +0.0.
2620 static bool isFloatingPointZero(SDValue Op) {
2621 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2622 return CFP->getValueAPF().isPosZero();
2623 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2624 // Maybe this has already been legalized into the constant pool?
2625 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2626 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2627 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2628 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2629 return CFP->getValueAPF().isPosZero();
2635 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2636 /// the given operands.
2638 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2639 SDValue &ARMcc, SelectionDAG &DAG,
2640 DebugLoc dl) const {
2641 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2642 unsigned C = RHSC->getZExtValue();
2643 if (!isLegalICmpImmediate(C)) {
2644 // Constant does not fit, try adjusting it by one?
2649 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2650 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2651 RHS = DAG.getConstant(C-1, MVT::i32);
2656 if (C != 0 && isLegalICmpImmediate(C-1)) {
2657 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2658 RHS = DAG.getConstant(C-1, MVT::i32);
2663 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2664 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2665 RHS = DAG.getConstant(C+1, MVT::i32);
2670 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2671 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2672 RHS = DAG.getConstant(C+1, MVT::i32);
2679 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2680 ARMISD::NodeType CompareType;
2683 CompareType = ARMISD::CMP;
2688 CompareType = ARMISD::CMPZ;
2691 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2692 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2695 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2697 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2698 DebugLoc dl) const {
2700 if (!isFloatingPointZero(RHS))
2701 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2703 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2704 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2707 /// duplicateCmp - Glue values can have only one use, so this function
2708 /// duplicates a comparison node.
2710 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2711 unsigned Opc = Cmp.getOpcode();
2712 DebugLoc DL = Cmp.getDebugLoc();
2713 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2714 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2716 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2717 Cmp = Cmp.getOperand(0);
2718 Opc = Cmp.getOpcode();
2719 if (Opc == ARMISD::CMPFP)
2720 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2722 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2723 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2725 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2728 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2729 SDValue Cond = Op.getOperand(0);
2730 SDValue SelectTrue = Op.getOperand(1);
2731 SDValue SelectFalse = Op.getOperand(2);
2732 DebugLoc dl = Op.getDebugLoc();
2736 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2737 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2739 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2740 const ConstantSDNode *CMOVTrue =
2741 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2742 const ConstantSDNode *CMOVFalse =
2743 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2745 if (CMOVTrue && CMOVFalse) {
2746 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2747 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2751 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2753 False = SelectFalse;
2754 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2759 if (True.getNode() && False.getNode()) {
2760 EVT VT = Op.getValueType();
2761 SDValue ARMcc = Cond.getOperand(2);
2762 SDValue CCR = Cond.getOperand(3);
2763 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2764 assert(True.getValueType() == VT);
2765 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2770 return DAG.getSelectCC(dl, Cond,
2771 DAG.getConstant(0, Cond.getValueType()),
2772 SelectTrue, SelectFalse, ISD::SETNE);
2775 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2776 EVT VT = Op.getValueType();
2777 SDValue LHS = Op.getOperand(0);
2778 SDValue RHS = Op.getOperand(1);
2779 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2780 SDValue TrueVal = Op.getOperand(2);
2781 SDValue FalseVal = Op.getOperand(3);
2782 DebugLoc dl = Op.getDebugLoc();
2784 if (LHS.getValueType() == MVT::i32) {
2786 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2787 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2788 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2791 ARMCC::CondCodes CondCode, CondCode2;
2792 FPCCToARMCC(CC, CondCode, CondCode2);
2794 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2795 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2796 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2797 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2799 if (CondCode2 != ARMCC::AL) {
2800 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2801 // FIXME: Needs another CMP because flag can have but one use.
2802 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2803 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2804 Result, TrueVal, ARMcc2, CCR, Cmp2);
2809 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2810 /// to morph to an integer compare sequence.
2811 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2812 const ARMSubtarget *Subtarget) {
2813 SDNode *N = Op.getNode();
2814 if (!N->hasOneUse())
2815 // Otherwise it requires moving the value from fp to integer registers.
2817 if (!N->getNumValues())
2819 EVT VT = Op.getValueType();
2820 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2821 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2822 // vmrs are very slow, e.g. cortex-a8.
2825 if (isFloatingPointZero(Op)) {
2829 return ISD::isNormalLoad(N);
2832 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2833 if (isFloatingPointZero(Op))
2834 return DAG.getConstant(0, MVT::i32);
2836 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2837 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2838 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2839 Ld->isVolatile(), Ld->isNonTemporal(),
2840 Ld->getAlignment());
2842 llvm_unreachable("Unknown VFP cmp argument!");
2845 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2846 SDValue &RetVal1, SDValue &RetVal2) {
2847 if (isFloatingPointZero(Op)) {
2848 RetVal1 = DAG.getConstant(0, MVT::i32);
2849 RetVal2 = DAG.getConstant(0, MVT::i32);
2853 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2854 SDValue Ptr = Ld->getBasePtr();
2855 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2856 Ld->getChain(), Ptr,
2857 Ld->getPointerInfo(),
2858 Ld->isVolatile(), Ld->isNonTemporal(),
2859 Ld->getAlignment());
2861 EVT PtrType = Ptr.getValueType();
2862 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2863 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2864 PtrType, Ptr, DAG.getConstant(4, PtrType));
2865 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2866 Ld->getChain(), NewPtr,
2867 Ld->getPointerInfo().getWithOffset(4),
2868 Ld->isVolatile(), Ld->isNonTemporal(),
2873 llvm_unreachable("Unknown VFP cmp argument!");
2876 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2877 /// f32 and even f64 comparisons to integer ones.
2879 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2880 SDValue Chain = Op.getOperand(0);
2881 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2882 SDValue LHS = Op.getOperand(2);
2883 SDValue RHS = Op.getOperand(3);
2884 SDValue Dest = Op.getOperand(4);
2885 DebugLoc dl = Op.getDebugLoc();
2887 bool SeenZero = false;
2888 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2889 canChangeToInt(RHS, SeenZero, Subtarget) &&
2890 // If one of the operand is zero, it's safe to ignore the NaN case since
2891 // we only care about equality comparisons.
2892 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2893 // If unsafe fp math optimization is enabled and there are no other uses of
2894 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2895 // to an integer comparison.
2896 if (CC == ISD::SETOEQ)
2898 else if (CC == ISD::SETUNE)
2902 if (LHS.getValueType() == MVT::f32) {
2903 LHS = bitcastf32Toi32(LHS, DAG);
2904 RHS = bitcastf32Toi32(RHS, DAG);
2905 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2906 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2907 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2908 Chain, Dest, ARMcc, CCR, Cmp);
2913 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2914 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2915 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2916 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2917 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2918 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2919 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2925 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2926 SDValue Chain = Op.getOperand(0);
2927 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2928 SDValue LHS = Op.getOperand(2);
2929 SDValue RHS = Op.getOperand(3);
2930 SDValue Dest = Op.getOperand(4);
2931 DebugLoc dl = Op.getDebugLoc();
2933 if (LHS.getValueType() == MVT::i32) {
2935 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2936 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2937 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2938 Chain, Dest, ARMcc, CCR, Cmp);
2941 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2944 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2945 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2946 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2947 if (Result.getNode())
2951 ARMCC::CondCodes CondCode, CondCode2;
2952 FPCCToARMCC(CC, CondCode, CondCode2);
2954 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2955 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2956 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2957 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2958 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2959 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2960 if (CondCode2 != ARMCC::AL) {
2961 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2962 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2963 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2968 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2969 SDValue Chain = Op.getOperand(0);
2970 SDValue Table = Op.getOperand(1);
2971 SDValue Index = Op.getOperand(2);
2972 DebugLoc dl = Op.getDebugLoc();
2974 EVT PTy = getPointerTy();
2975 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2976 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2977 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2978 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2979 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2980 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2981 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2982 if (Subtarget->isThumb2()) {
2983 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2984 // which does another jump to the destination. This also makes it easier
2985 // to translate it to TBB / TBH later.
2986 // FIXME: This might not work if the function is extremely large.
2987 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2988 Addr, Op.getOperand(2), JTI, UId);
2990 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2991 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2992 MachinePointerInfo::getJumpTable(),
2994 Chain = Addr.getValue(1);
2995 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2996 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2998 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2999 MachinePointerInfo::getJumpTable(), false, false, 0);
3000 Chain = Addr.getValue(1);
3001 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3005 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3006 DebugLoc dl = Op.getDebugLoc();
3009 switch (Op.getOpcode()) {
3011 assert(0 && "Invalid opcode!");
3012 case ISD::FP_TO_SINT:
3013 Opc = ARMISD::FTOSI;
3015 case ISD::FP_TO_UINT:
3016 Opc = ARMISD::FTOUI;
3019 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3020 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3023 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3024 EVT VT = Op.getValueType();
3025 DebugLoc dl = Op.getDebugLoc();
3027 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3028 "Invalid type for custom lowering!");
3029 if (VT != MVT::v4f32)
3030 return DAG.UnrollVectorOp(Op.getNode());
3034 switch (Op.getOpcode()) {
3036 assert(0 && "Invalid opcode!");
3037 case ISD::SINT_TO_FP:
3038 CastOpc = ISD::SIGN_EXTEND;
3039 Opc = ISD::SINT_TO_FP;
3041 case ISD::UINT_TO_FP:
3042 CastOpc = ISD::ZERO_EXTEND;
3043 Opc = ISD::UINT_TO_FP;
3047 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3048 return DAG.getNode(Opc, dl, VT, Op);
3051 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3052 EVT VT = Op.getValueType();
3054 return LowerVectorINT_TO_FP(Op, DAG);
3056 DebugLoc dl = Op.getDebugLoc();
3059 switch (Op.getOpcode()) {
3061 assert(0 && "Invalid opcode!");
3062 case ISD::SINT_TO_FP:
3063 Opc = ARMISD::SITOF;
3065 case ISD::UINT_TO_FP:
3066 Opc = ARMISD::UITOF;
3070 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3071 return DAG.getNode(Opc, dl, VT, Op);
3074 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3075 // Implement fcopysign with a fabs and a conditional fneg.
3076 SDValue Tmp0 = Op.getOperand(0);
3077 SDValue Tmp1 = Op.getOperand(1);
3078 DebugLoc dl = Op.getDebugLoc();
3079 EVT VT = Op.getValueType();
3080 EVT SrcVT = Tmp1.getValueType();
3081 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3082 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3083 bool UseNEON = !InGPR && Subtarget->hasNEON();
3086 // Use VBSL to copy the sign bit.
3087 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3088 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3089 DAG.getTargetConstant(EncodedVal, MVT::i32));
3090 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3092 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3093 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3094 DAG.getConstant(32, MVT::i32));
3095 else /*if (VT == MVT::f32)*/
3096 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3097 if (SrcVT == MVT::f32) {
3098 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3100 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3101 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3102 DAG.getConstant(32, MVT::i32));
3103 } else if (VT == MVT::f32)
3104 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3105 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3106 DAG.getConstant(32, MVT::i32));
3107 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3108 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3110 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3112 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3113 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3114 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3116 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3117 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3118 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3119 if (VT == MVT::f32) {
3120 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3121 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3122 DAG.getConstant(0, MVT::i32));
3124 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3130 // Bitcast operand 1 to i32.
3131 if (SrcVT == MVT::f64)
3132 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3133 &Tmp1, 1).getValue(1);
3134 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3136 // Or in the signbit with integer operations.
3137 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3138 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3139 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3140 if (VT == MVT::f32) {
3141 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3142 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3143 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3144 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3147 // f64: Or the high part with signbit and then combine two parts.
3148 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3150 SDValue Lo = Tmp0.getValue(0);
3151 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3152 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3153 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3156 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3157 MachineFunction &MF = DAG.getMachineFunction();
3158 MachineFrameInfo *MFI = MF.getFrameInfo();
3159 MFI->setReturnAddressIsTaken(true);
3161 EVT VT = Op.getValueType();
3162 DebugLoc dl = Op.getDebugLoc();
3163 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3165 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3166 SDValue Offset = DAG.getConstant(4, MVT::i32);
3167 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3168 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3169 MachinePointerInfo(), false, false, 0);
3172 // Return LR, which contains the return address. Mark it an implicit live-in.
3173 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3174 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3177 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3178 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3179 MFI->setFrameAddressIsTaken(true);
3181 EVT VT = Op.getValueType();
3182 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3183 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3184 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3185 ? ARM::R7 : ARM::R11;
3186 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3188 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3189 MachinePointerInfo(),
3194 /// ExpandBITCAST - If the target supports VFP, this function is called to
3195 /// expand a bit convert where either the source or destination type is i64 to
3196 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3197 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3198 /// vectors), since the legalizer won't know what to do with that.
3199 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3201 DebugLoc dl = N->getDebugLoc();
3202 SDValue Op = N->getOperand(0);
3204 // This function is only supposed to be called for i64 types, either as the
3205 // source or destination of the bit convert.
3206 EVT SrcVT = Op.getValueType();
3207 EVT DstVT = N->getValueType(0);
3208 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3209 "ExpandBITCAST called for non-i64 type");
3211 // Turn i64->f64 into VMOVDRR.
3212 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3213 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3214 DAG.getConstant(0, MVT::i32));
3215 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3216 DAG.getConstant(1, MVT::i32));
3217 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3218 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3221 // Turn f64->i64 into VMOVRRD.
3222 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3223 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3224 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3225 // Merge the pieces into a single i64 value.
3226 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3232 /// getZeroVector - Returns a vector of specified type with all zero elements.
3233 /// Zero vectors are used to represent vector negation and in those cases
3234 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3235 /// not support i64 elements, so sometimes the zero vectors will need to be
3236 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3238 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3239 assert(VT.isVector() && "Expected a vector type");
3240 // The canonical modified immediate encoding of a zero vector is....0!
3241 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3242 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3243 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3244 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3247 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3248 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3249 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3250 SelectionDAG &DAG) const {
3251 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3252 EVT VT = Op.getValueType();
3253 unsigned VTBits = VT.getSizeInBits();
3254 DebugLoc dl = Op.getDebugLoc();
3255 SDValue ShOpLo = Op.getOperand(0);
3256 SDValue ShOpHi = Op.getOperand(1);
3257 SDValue ShAmt = Op.getOperand(2);
3259 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3261 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3263 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3264 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3265 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3266 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3267 DAG.getConstant(VTBits, MVT::i32));
3268 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3269 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3270 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3272 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3273 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3275 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3276 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3279 SDValue Ops[2] = { Lo, Hi };
3280 return DAG.getMergeValues(Ops, 2, dl);
3283 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3284 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3285 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3286 SelectionDAG &DAG) const {
3287 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3288 EVT VT = Op.getValueType();
3289 unsigned VTBits = VT.getSizeInBits();
3290 DebugLoc dl = Op.getDebugLoc();
3291 SDValue ShOpLo = Op.getOperand(0);
3292 SDValue ShOpHi = Op.getOperand(1);
3293 SDValue ShAmt = Op.getOperand(2);
3296 assert(Op.getOpcode() == ISD::SHL_PARTS);
3297 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3298 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3299 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3300 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3301 DAG.getConstant(VTBits, MVT::i32));
3302 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3303 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3305 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3306 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3307 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3309 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3310 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3313 SDValue Ops[2] = { Lo, Hi };
3314 return DAG.getMergeValues(Ops, 2, dl);
3317 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3318 SelectionDAG &DAG) const {
3319 // The rounding mode is in bits 23:22 of the FPSCR.
3320 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3321 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3322 // so that the shift + and get folded into a bitfield extract.
3323 DebugLoc dl = Op.getDebugLoc();
3324 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3325 DAG.getConstant(Intrinsic::arm_get_fpscr,
3327 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3328 DAG.getConstant(1U << 22, MVT::i32));
3329 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3330 DAG.getConstant(22, MVT::i32));
3331 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3332 DAG.getConstant(3, MVT::i32));
3335 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3336 const ARMSubtarget *ST) {
3337 EVT VT = N->getValueType(0);
3338 DebugLoc dl = N->getDebugLoc();
3340 if (!ST->hasV6T2Ops())
3343 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3344 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3347 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3348 const ARMSubtarget *ST) {
3349 EVT VT = N->getValueType(0);
3350 DebugLoc dl = N->getDebugLoc();
3355 // Lower vector shifts on NEON to use VSHL.
3356 assert(ST->hasNEON() && "unexpected vector shift");
3358 // Left shifts translate directly to the vshiftu intrinsic.
3359 if (N->getOpcode() == ISD::SHL)
3360 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3361 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3362 N->getOperand(0), N->getOperand(1));
3364 assert((N->getOpcode() == ISD::SRA ||
3365 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3367 // NEON uses the same intrinsics for both left and right shifts. For
3368 // right shifts, the shift amounts are negative, so negate the vector of
3370 EVT ShiftVT = N->getOperand(1).getValueType();
3371 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3372 getZeroVector(ShiftVT, DAG, dl),
3374 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3375 Intrinsic::arm_neon_vshifts :
3376 Intrinsic::arm_neon_vshiftu);
3377 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3378 DAG.getConstant(vshiftInt, MVT::i32),
3379 N->getOperand(0), NegatedCount);
3382 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3383 const ARMSubtarget *ST) {
3384 EVT VT = N->getValueType(0);
3385 DebugLoc dl = N->getDebugLoc();
3387 // We can get here for a node like i32 = ISD::SHL i32, i64
3391 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3392 "Unknown shift to lower!");
3394 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3395 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3396 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3399 // If we are in thumb mode, we don't have RRX.
3400 if (ST->isThumb1Only()) return SDValue();
3402 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3403 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3404 DAG.getConstant(0, MVT::i32));
3405 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3406 DAG.getConstant(1, MVT::i32));
3408 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3409 // captures the result into a carry flag.
3410 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3411 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3413 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3414 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3416 // Merge the pieces into a single i64 value.
3417 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3420 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3421 SDValue TmpOp0, TmpOp1;
3422 bool Invert = false;
3426 SDValue Op0 = Op.getOperand(0);
3427 SDValue Op1 = Op.getOperand(1);
3428 SDValue CC = Op.getOperand(2);
3429 EVT VT = Op.getValueType();
3430 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3431 DebugLoc dl = Op.getDebugLoc();
3433 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3434 switch (SetCCOpcode) {
3435 default: llvm_unreachable("Illegal FP comparison"); break;
3437 case ISD::SETNE: Invert = true; // Fallthrough
3439 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3441 case ISD::SETLT: Swap = true; // Fallthrough
3443 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3445 case ISD::SETLE: Swap = true; // Fallthrough
3447 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3448 case ISD::SETUGE: Swap = true; // Fallthrough
3449 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3450 case ISD::SETUGT: Swap = true; // Fallthrough
3451 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3452 case ISD::SETUEQ: Invert = true; // Fallthrough
3454 // Expand this to (OLT | OGT).
3458 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3459 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3461 case ISD::SETUO: Invert = true; // Fallthrough
3463 // Expand this to (OLT | OGE).
3467 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3468 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3472 // Integer comparisons.
3473 switch (SetCCOpcode) {
3474 default: llvm_unreachable("Illegal integer comparison"); break;
3475 case ISD::SETNE: Invert = true;
3476 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3477 case ISD::SETLT: Swap = true;
3478 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3479 case ISD::SETLE: Swap = true;
3480 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3481 case ISD::SETULT: Swap = true;
3482 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3483 case ISD::SETULE: Swap = true;
3484 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3487 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3488 if (Opc == ARMISD::VCEQ) {
3491 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3493 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3496 // Ignore bitconvert.
3497 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3498 AndOp = AndOp.getOperand(0);
3500 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3502 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3503 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3510 std::swap(Op0, Op1);
3512 // If one of the operands is a constant vector zero, attempt to fold the
3513 // comparison to a specialized compare-against-zero form.
3515 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3517 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3518 if (Opc == ARMISD::VCGE)
3519 Opc = ARMISD::VCLEZ;
3520 else if (Opc == ARMISD::VCGT)
3521 Opc = ARMISD::VCLTZ;
3526 if (SingleOp.getNode()) {
3529 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3531 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3533 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3535 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3537 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3539 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3542 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3546 Result = DAG.getNOT(dl, Result, VT);
3551 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3552 /// valid vector constant for a NEON instruction with a "modified immediate"
3553 /// operand (e.g., VMOV). If so, return the encoded value.
3554 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3555 unsigned SplatBitSize, SelectionDAG &DAG,
3556 EVT &VT, bool is128Bits, NEONModImmType type) {
3557 unsigned OpCmode, Imm;
3559 // SplatBitSize is set to the smallest size that splats the vector, so a
3560 // zero vector will always have SplatBitSize == 8. However, NEON modified
3561 // immediate instructions others than VMOV do not support the 8-bit encoding
3562 // of a zero vector, and the default encoding of zero is supposed to be the
3567 switch (SplatBitSize) {
3569 if (type != VMOVModImm)
3571 // Any 1-byte value is OK. Op=0, Cmode=1110.
3572 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3575 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3579 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3580 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3581 if ((SplatBits & ~0xff) == 0) {
3582 // Value = 0x00nn: Op=x, Cmode=100x.
3587 if ((SplatBits & ~0xff00) == 0) {
3588 // Value = 0xnn00: Op=x, Cmode=101x.
3590 Imm = SplatBits >> 8;
3596 // NEON's 32-bit VMOV supports splat values where:
3597 // * only one byte is nonzero, or
3598 // * the least significant byte is 0xff and the second byte is nonzero, or
3599 // * the least significant 2 bytes are 0xff and the third is nonzero.
3600 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3601 if ((SplatBits & ~0xff) == 0) {
3602 // Value = 0x000000nn: Op=x, Cmode=000x.
3607 if ((SplatBits & ~0xff00) == 0) {
3608 // Value = 0x0000nn00: Op=x, Cmode=001x.
3610 Imm = SplatBits >> 8;
3613 if ((SplatBits & ~0xff0000) == 0) {
3614 // Value = 0x00nn0000: Op=x, Cmode=010x.
3616 Imm = SplatBits >> 16;
3619 if ((SplatBits & ~0xff000000) == 0) {
3620 // Value = 0xnn000000: Op=x, Cmode=011x.
3622 Imm = SplatBits >> 24;
3626 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3627 if (type == OtherModImm) return SDValue();
3629 if ((SplatBits & ~0xffff) == 0 &&
3630 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3631 // Value = 0x0000nnff: Op=x, Cmode=1100.
3633 Imm = SplatBits >> 8;
3638 if ((SplatBits & ~0xffffff) == 0 &&
3639 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3640 // Value = 0x00nnffff: Op=x, Cmode=1101.
3642 Imm = SplatBits >> 16;
3643 SplatBits |= 0xffff;
3647 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3648 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3649 // VMOV.I32. A (very) minor optimization would be to replicate the value
3650 // and fall through here to test for a valid 64-bit splat. But, then the
3651 // caller would also need to check and handle the change in size.
3655 if (type != VMOVModImm)
3657 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3658 uint64_t BitMask = 0xff;
3660 unsigned ImmMask = 1;
3662 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3663 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3666 } else if ((SplatBits & BitMask) != 0) {
3672 // Op=1, Cmode=1110.
3675 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3680 llvm_unreachable("unexpected size for isNEONModifiedImm");
3684 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3685 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3688 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3689 bool &ReverseVEXT, unsigned &Imm) {
3690 unsigned NumElts = VT.getVectorNumElements();
3691 ReverseVEXT = false;
3693 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3699 // If this is a VEXT shuffle, the immediate value is the index of the first
3700 // element. The other shuffle indices must be the successive elements after
3702 unsigned ExpectedElt = Imm;
3703 for (unsigned i = 1; i < NumElts; ++i) {
3704 // Increment the expected index. If it wraps around, it may still be
3705 // a VEXT but the source vectors must be swapped.
3707 if (ExpectedElt == NumElts * 2) {
3712 if (M[i] < 0) continue; // ignore UNDEF indices
3713 if (ExpectedElt != static_cast<unsigned>(M[i]))
3717 // Adjust the index value if the source operands will be swapped.
3724 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3725 /// instruction with the specified blocksize. (The order of the elements
3726 /// within each block of the vector is reversed.)
3727 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3728 unsigned BlockSize) {
3729 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3730 "Only possible block sizes for VREV are: 16, 32, 64");
3732 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3736 unsigned NumElts = VT.getVectorNumElements();
3737 unsigned BlockElts = M[0] + 1;
3738 // If the first shuffle index is UNDEF, be optimistic.
3740 BlockElts = BlockSize / EltSz;
3742 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3745 for (unsigned i = 0; i < NumElts; ++i) {
3746 if (M[i] < 0) continue; // ignore UNDEF indices
3747 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3754 static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) {
3755 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3756 // range, then 0 is placed into the resulting vector. So pretty much any mask
3757 // of 8 elements can work here.
3758 return VT == MVT::v8i8 && M.size() == 8;
3761 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3762 unsigned &WhichResult) {
3763 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3767 unsigned NumElts = VT.getVectorNumElements();
3768 WhichResult = (M[0] == 0 ? 0 : 1);
3769 for (unsigned i = 0; i < NumElts; i += 2) {
3770 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3771 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3777 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3778 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3779 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3780 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3781 unsigned &WhichResult) {
3782 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3786 unsigned NumElts = VT.getVectorNumElements();
3787 WhichResult = (M[0] == 0 ? 0 : 1);
3788 for (unsigned i = 0; i < NumElts; i += 2) {
3789 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3790 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3796 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3797 unsigned &WhichResult) {
3798 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3802 unsigned NumElts = VT.getVectorNumElements();
3803 WhichResult = (M[0] == 0 ? 0 : 1);
3804 for (unsigned i = 0; i != NumElts; ++i) {
3805 if (M[i] < 0) continue; // ignore UNDEF indices
3806 if ((unsigned) M[i] != 2 * i + WhichResult)
3810 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3811 if (VT.is64BitVector() && EltSz == 32)
3817 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3818 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3819 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3820 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3821 unsigned &WhichResult) {
3822 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3826 unsigned Half = VT.getVectorNumElements() / 2;
3827 WhichResult = (M[0] == 0 ? 0 : 1);
3828 for (unsigned j = 0; j != 2; ++j) {
3829 unsigned Idx = WhichResult;
3830 for (unsigned i = 0; i != Half; ++i) {
3831 int MIdx = M[i + j * Half];
3832 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3838 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3839 if (VT.is64BitVector() && EltSz == 32)
3845 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3846 unsigned &WhichResult) {
3847 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3851 unsigned NumElts = VT.getVectorNumElements();
3852 WhichResult = (M[0] == 0 ? 0 : 1);
3853 unsigned Idx = WhichResult * NumElts / 2;
3854 for (unsigned i = 0; i != NumElts; i += 2) {
3855 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3856 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3861 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3862 if (VT.is64BitVector() && EltSz == 32)
3868 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3869 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3870 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3871 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3872 unsigned &WhichResult) {
3873 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3877 unsigned NumElts = VT.getVectorNumElements();
3878 WhichResult = (M[0] == 0 ? 0 : 1);
3879 unsigned Idx = WhichResult * NumElts / 2;
3880 for (unsigned i = 0; i != NumElts; i += 2) {
3881 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3882 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3887 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3888 if (VT.is64BitVector() && EltSz == 32)
3894 // If N is an integer constant that can be moved into a register in one
3895 // instruction, return an SDValue of such a constant (will become a MOV
3896 // instruction). Otherwise return null.
3897 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3898 const ARMSubtarget *ST, DebugLoc dl) {
3900 if (!isa<ConstantSDNode>(N))
3902 Val = cast<ConstantSDNode>(N)->getZExtValue();
3904 if (ST->isThumb1Only()) {
3905 if (Val <= 255 || ~Val <= 255)
3906 return DAG.getConstant(Val, MVT::i32);
3908 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3909 return DAG.getConstant(Val, MVT::i32);
3914 // If this is a case we can't handle, return null and let the default
3915 // expansion code take care of it.
3916 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3917 const ARMSubtarget *ST) const {
3918 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3919 DebugLoc dl = Op.getDebugLoc();
3920 EVT VT = Op.getValueType();
3922 APInt SplatBits, SplatUndef;
3923 unsigned SplatBitSize;
3925 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3926 if (SplatBitSize <= 64) {
3927 // Check if an immediate VMOV works.
3929 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3930 SplatUndef.getZExtValue(), SplatBitSize,
3931 DAG, VmovVT, VT.is128BitVector(),
3933 if (Val.getNode()) {
3934 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3935 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3938 // Try an immediate VMVN.
3939 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3940 ((1LL << SplatBitSize) - 1));
3941 Val = isNEONModifiedImm(NegatedImm,
3942 SplatUndef.getZExtValue(), SplatBitSize,
3943 DAG, VmovVT, VT.is128BitVector(),
3945 if (Val.getNode()) {
3946 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3947 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3952 // Scan through the operands to see if only one value is used.
3953 unsigned NumElts = VT.getVectorNumElements();
3954 bool isOnlyLowElement = true;
3955 bool usesOnlyOneValue = true;
3956 bool isConstant = true;
3958 for (unsigned i = 0; i < NumElts; ++i) {
3959 SDValue V = Op.getOperand(i);
3960 if (V.getOpcode() == ISD::UNDEF)
3963 isOnlyLowElement = false;
3964 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3967 if (!Value.getNode())
3969 else if (V != Value)
3970 usesOnlyOneValue = false;
3973 if (!Value.getNode())
3974 return DAG.getUNDEF(VT);
3976 if (isOnlyLowElement)
3977 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3979 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3981 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3982 // i32 and try again.
3983 if (usesOnlyOneValue && EltSize <= 32) {
3985 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3986 if (VT.getVectorElementType().isFloatingPoint()) {
3987 SmallVector<SDValue, 8> Ops;
3988 for (unsigned i = 0; i < NumElts; ++i)
3989 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3991 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3992 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3993 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3995 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3997 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3999 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
4002 // If all elements are constants and the case above didn't get hit, fall back
4003 // to the default expansion, which will generate a load from the constant
4008 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
4010 SDValue shuffle = ReconstructShuffle(Op, DAG);
4011 if (shuffle != SDValue())
4015 // Vectors with 32- or 64-bit elements can be built by directly assigning
4016 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
4017 // will be legalized.
4018 if (EltSize >= 32) {
4019 // Do the expansion with floating-point types, since that is what the VFP
4020 // registers are defined to use, and since i64 is not legal.
4021 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4022 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4023 SmallVector<SDValue, 8> Ops;
4024 for (unsigned i = 0; i < NumElts; ++i)
4025 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
4026 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4027 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4033 // Gather data to see if the operation can be modelled as a
4034 // shuffle in combination with VEXTs.
4035 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
4036 SelectionDAG &DAG) const {
4037 DebugLoc dl = Op.getDebugLoc();
4038 EVT VT = Op.getValueType();
4039 unsigned NumElts = VT.getVectorNumElements();
4041 SmallVector<SDValue, 2> SourceVecs;
4042 SmallVector<unsigned, 2> MinElts;
4043 SmallVector<unsigned, 2> MaxElts;
4045 for (unsigned i = 0; i < NumElts; ++i) {
4046 SDValue V = Op.getOperand(i);
4047 if (V.getOpcode() == ISD::UNDEF)
4049 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4050 // A shuffle can only come from building a vector from various
4051 // elements of other vectors.
4055 // Record this extraction against the appropriate vector if possible...
4056 SDValue SourceVec = V.getOperand(0);
4057 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4058 bool FoundSource = false;
4059 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4060 if (SourceVecs[j] == SourceVec) {
4061 if (MinElts[j] > EltNo)
4063 if (MaxElts[j] < EltNo)
4070 // Or record a new source if not...
4072 SourceVecs.push_back(SourceVec);
4073 MinElts.push_back(EltNo);
4074 MaxElts.push_back(EltNo);
4078 // Currently only do something sane when at most two source vectors
4080 if (SourceVecs.size() > 2)
4083 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4084 int VEXTOffsets[2] = {0, 0};
4086 // This loop extracts the usage patterns of the source vectors
4087 // and prepares appropriate SDValues for a shuffle if possible.
4088 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4089 if (SourceVecs[i].getValueType() == VT) {
4090 // No VEXT necessary
4091 ShuffleSrcs[i] = SourceVecs[i];
4094 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4095 // It probably isn't worth padding out a smaller vector just to
4096 // break it down again in a shuffle.
4100 // Since only 64-bit and 128-bit vectors are legal on ARM and
4101 // we've eliminated the other cases...
4102 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
4103 "unexpected vector sizes in ReconstructShuffle");
4105 if (MaxElts[i] - MinElts[i] >= NumElts) {
4106 // Span too large for a VEXT to cope
4110 if (MinElts[i] >= NumElts) {
4111 // The extraction can just take the second half
4112 VEXTOffsets[i] = NumElts;
4113 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4115 DAG.getIntPtrConstant(NumElts));
4116 } else if (MaxElts[i] < NumElts) {
4117 // The extraction can just take the first half
4119 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4121 DAG.getIntPtrConstant(0));
4123 // An actual VEXT is needed
4124 VEXTOffsets[i] = MinElts[i];
4125 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4127 DAG.getIntPtrConstant(0));
4128 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4130 DAG.getIntPtrConstant(NumElts));
4131 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4132 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4136 SmallVector<int, 8> Mask;
4138 for (unsigned i = 0; i < NumElts; ++i) {
4139 SDValue Entry = Op.getOperand(i);
4140 if (Entry.getOpcode() == ISD::UNDEF) {
4145 SDValue ExtractVec = Entry.getOperand(0);
4146 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
4147 .getOperand(1))->getSExtValue();
4148 if (ExtractVec == SourceVecs[0]) {
4149 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4151 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4155 // Final check before we try to produce nonsense...
4156 if (isShuffleMaskLegal(Mask, VT))
4157 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4163 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4164 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4165 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4166 /// are assumed to be legal.
4168 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4170 if (VT.getVectorNumElements() == 4 &&
4171 (VT.is128BitVector() || VT.is64BitVector())) {
4172 unsigned PFIndexes[4];
4173 for (unsigned i = 0; i != 4; ++i) {
4177 PFIndexes[i] = M[i];
4180 // Compute the index in the perfect shuffle table.
4181 unsigned PFTableIndex =
4182 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4183 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4184 unsigned Cost = (PFEntry >> 30);
4191 unsigned Imm, WhichResult;
4193 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4194 return (EltSize >= 32 ||
4195 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4196 isVREVMask(M, VT, 64) ||
4197 isVREVMask(M, VT, 32) ||
4198 isVREVMask(M, VT, 16) ||
4199 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4200 isVTBLMask(M, VT) ||
4201 isVTRNMask(M, VT, WhichResult) ||
4202 isVUZPMask(M, VT, WhichResult) ||
4203 isVZIPMask(M, VT, WhichResult) ||
4204 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4205 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4206 isVZIP_v_undef_Mask(M, VT, WhichResult));
4209 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4210 /// the specified operations to build the shuffle.
4211 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4212 SDValue RHS, SelectionDAG &DAG,
4214 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4215 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4216 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4219 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4228 OP_VUZPL, // VUZP, left result
4229 OP_VUZPR, // VUZP, right result
4230 OP_VZIPL, // VZIP, left result
4231 OP_VZIPR, // VZIP, right result
4232 OP_VTRNL, // VTRN, left result
4233 OP_VTRNR // VTRN, right result
4236 if (OpNum == OP_COPY) {
4237 if (LHSID == (1*9+2)*9+3) return LHS;
4238 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4242 SDValue OpLHS, OpRHS;
4243 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4244 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4245 EVT VT = OpLHS.getValueType();
4248 default: llvm_unreachable("Unknown shuffle opcode!");
4250 // VREV divides the vector in half and swaps within the half.
4251 if (VT.getVectorElementType() == MVT::i32 ||
4252 VT.getVectorElementType() == MVT::f32)
4253 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4254 // vrev <4 x i16> -> VREV32
4255 if (VT.getVectorElementType() == MVT::i16)
4256 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4257 // vrev <4 x i8> -> VREV16
4258 assert(VT.getVectorElementType() == MVT::i8);
4259 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4264 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4265 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4269 return DAG.getNode(ARMISD::VEXT, dl, VT,
4271 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4274 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4275 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4278 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4279 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4282 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4283 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4287 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4288 SmallVectorImpl<int> &ShuffleMask,
4289 SelectionDAG &DAG) {
4290 // Check to see if we can use the VTBL instruction.
4291 SDValue V1 = Op.getOperand(0);
4292 SDValue V2 = Op.getOperand(1);
4293 DebugLoc DL = Op.getDebugLoc();
4295 SmallVector<SDValue, 8> VTBLMask;
4296 for (SmallVectorImpl<int>::iterator
4297 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4298 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4300 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4301 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4302 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4305 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4306 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4310 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4311 SDValue V1 = Op.getOperand(0);
4312 SDValue V2 = Op.getOperand(1);
4313 DebugLoc dl = Op.getDebugLoc();
4314 EVT VT = Op.getValueType();
4315 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4316 SmallVector<int, 8> ShuffleMask;
4318 // Convert shuffles that are directly supported on NEON to target-specific
4319 // DAG nodes, instead of keeping them as shuffles and matching them again
4320 // during code selection. This is more efficient and avoids the possibility
4321 // of inconsistencies between legalization and selection.
4322 // FIXME: floating-point vectors should be canonicalized to integer vectors
4323 // of the same time so that they get CSEd properly.
4324 SVN->getMask(ShuffleMask);
4326 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4327 if (EltSize <= 32) {
4328 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4329 int Lane = SVN->getSplatIndex();
4330 // If this is undef splat, generate it via "just" vdup, if possible.
4331 if (Lane == -1) Lane = 0;
4333 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4334 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4336 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4337 DAG.getConstant(Lane, MVT::i32));
4342 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4345 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4346 DAG.getConstant(Imm, MVT::i32));
4349 if (isVREVMask(ShuffleMask, VT, 64))
4350 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4351 if (isVREVMask(ShuffleMask, VT, 32))
4352 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4353 if (isVREVMask(ShuffleMask, VT, 16))
4354 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4356 // Check for Neon shuffles that modify both input vectors in place.
4357 // If both results are used, i.e., if there are two shuffles with the same
4358 // source operands and with masks corresponding to both results of one of
4359 // these operations, DAG memoization will ensure that a single node is
4360 // used for both shuffles.
4361 unsigned WhichResult;
4362 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4363 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4364 V1, V2).getValue(WhichResult);
4365 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4366 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4367 V1, V2).getValue(WhichResult);
4368 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4369 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4370 V1, V2).getValue(WhichResult);
4372 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4373 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4374 V1, V1).getValue(WhichResult);
4375 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4376 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4377 V1, V1).getValue(WhichResult);
4378 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4379 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4380 V1, V1).getValue(WhichResult);
4383 // If the shuffle is not directly supported and it has 4 elements, use
4384 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4385 unsigned NumElts = VT.getVectorNumElements();
4387 unsigned PFIndexes[4];
4388 for (unsigned i = 0; i != 4; ++i) {
4389 if (ShuffleMask[i] < 0)
4392 PFIndexes[i] = ShuffleMask[i];
4395 // Compute the index in the perfect shuffle table.
4396 unsigned PFTableIndex =
4397 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4398 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4399 unsigned Cost = (PFEntry >> 30);
4402 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4405 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4406 if (EltSize >= 32) {
4407 // Do the expansion with floating-point types, since that is what the VFP
4408 // registers are defined to use, and since i64 is not legal.
4409 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4410 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4411 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4412 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4413 SmallVector<SDValue, 8> Ops;
4414 for (unsigned i = 0; i < NumElts; ++i) {
4415 if (ShuffleMask[i] < 0)
4416 Ops.push_back(DAG.getUNDEF(EltVT));
4418 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4419 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4420 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4423 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4424 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4427 if (VT == MVT::v8i8) {
4428 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4429 if (NewOp.getNode())
4436 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4437 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4438 SDValue Lane = Op.getOperand(1);
4439 if (!isa<ConstantSDNode>(Lane))
4442 SDValue Vec = Op.getOperand(0);
4443 if (Op.getValueType() == MVT::i32 &&
4444 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4445 DebugLoc dl = Op.getDebugLoc();
4446 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4452 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4453 // The only time a CONCAT_VECTORS operation can have legal types is when
4454 // two 64-bit vectors are concatenated to a 128-bit vector.
4455 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4456 "unexpected CONCAT_VECTORS");
4457 DebugLoc dl = Op.getDebugLoc();
4458 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4459 SDValue Op0 = Op.getOperand(0);
4460 SDValue Op1 = Op.getOperand(1);
4461 if (Op0.getOpcode() != ISD::UNDEF)
4462 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4463 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4464 DAG.getIntPtrConstant(0));
4465 if (Op1.getOpcode() != ISD::UNDEF)
4466 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4467 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4468 DAG.getIntPtrConstant(1));
4469 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4472 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4473 /// element has been zero/sign-extended, depending on the isSigned parameter,
4474 /// from an integer type half its size.
4475 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4477 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4478 EVT VT = N->getValueType(0);
4479 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4480 SDNode *BVN = N->getOperand(0).getNode();
4481 if (BVN->getValueType(0) != MVT::v4i32 ||
4482 BVN->getOpcode() != ISD::BUILD_VECTOR)
4484 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4485 unsigned HiElt = 1 - LoElt;
4486 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4487 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4488 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4489 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4490 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4493 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4494 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4497 if (Hi0->isNullValue() && Hi1->isNullValue())
4503 if (N->getOpcode() != ISD::BUILD_VECTOR)
4506 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4507 SDNode *Elt = N->getOperand(i).getNode();
4508 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4509 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4510 unsigned HalfSize = EltSize / 2;
4512 int64_t SExtVal = C->getSExtValue();
4513 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
4516 if ((C->getZExtValue() >> HalfSize) != 0)
4527 /// isSignExtended - Check if a node is a vector value that is sign-extended
4528 /// or a constant BUILD_VECTOR with sign-extended elements.
4529 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4530 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4532 if (isExtendedBUILD_VECTOR(N, DAG, true))
4537 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4538 /// or a constant BUILD_VECTOR with zero-extended elements.
4539 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4540 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4542 if (isExtendedBUILD_VECTOR(N, DAG, false))
4547 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4548 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4549 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4550 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4551 return N->getOperand(0);
4552 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4553 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4554 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4555 LD->isNonTemporal(), LD->getAlignment());
4556 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4557 // have been legalized as a BITCAST from v4i32.
4558 if (N->getOpcode() == ISD::BITCAST) {
4559 SDNode *BVN = N->getOperand(0).getNode();
4560 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4561 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4562 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4563 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4564 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4566 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4567 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4568 EVT VT = N->getValueType(0);
4569 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4570 unsigned NumElts = VT.getVectorNumElements();
4571 MVT TruncVT = MVT::getIntegerVT(EltSize);
4572 SmallVector<SDValue, 8> Ops;
4573 for (unsigned i = 0; i != NumElts; ++i) {
4574 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4575 const APInt &CInt = C->getAPIntValue();
4576 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4578 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4579 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4582 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4583 unsigned Opcode = N->getOpcode();
4584 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4585 SDNode *N0 = N->getOperand(0).getNode();
4586 SDNode *N1 = N->getOperand(1).getNode();
4587 return N0->hasOneUse() && N1->hasOneUse() &&
4588 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4593 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4594 unsigned Opcode = N->getOpcode();
4595 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4596 SDNode *N0 = N->getOperand(0).getNode();
4597 SDNode *N1 = N->getOperand(1).getNode();
4598 return N0->hasOneUse() && N1->hasOneUse() &&
4599 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4604 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4605 // Multiplications are only custom-lowered for 128-bit vectors so that
4606 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4607 EVT VT = Op.getValueType();
4608 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4609 SDNode *N0 = Op.getOperand(0).getNode();
4610 SDNode *N1 = Op.getOperand(1).getNode();
4611 unsigned NewOpc = 0;
4613 bool isN0SExt = isSignExtended(N0, DAG);
4614 bool isN1SExt = isSignExtended(N1, DAG);
4615 if (isN0SExt && isN1SExt)
4616 NewOpc = ARMISD::VMULLs;
4618 bool isN0ZExt = isZeroExtended(N0, DAG);
4619 bool isN1ZExt = isZeroExtended(N1, DAG);
4620 if (isN0ZExt && isN1ZExt)
4621 NewOpc = ARMISD::VMULLu;
4622 else if (isN1SExt || isN1ZExt) {
4623 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4624 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4625 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4626 NewOpc = ARMISD::VMULLs;
4628 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4629 NewOpc = ARMISD::VMULLu;
4631 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4633 NewOpc = ARMISD::VMULLu;
4639 if (VT == MVT::v2i64)
4640 // Fall through to expand this. It is not legal.
4643 // Other vector multiplications are legal.
4648 // Legalize to a VMULL instruction.
4649 DebugLoc DL = Op.getDebugLoc();
4651 SDValue Op1 = SkipExtension(N1, DAG);
4653 Op0 = SkipExtension(N0, DAG);
4654 assert(Op0.getValueType().is64BitVector() &&
4655 Op1.getValueType().is64BitVector() &&
4656 "unexpected types for extended operands to VMULL");
4657 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4660 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
4661 // isel lowering to take advantage of no-stall back to back vmul + vmla.
4668 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4669 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4670 EVT Op1VT = Op1.getValueType();
4671 return DAG.getNode(N0->getOpcode(), DL, VT,
4672 DAG.getNode(NewOpc, DL, VT,
4673 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
4674 DAG.getNode(NewOpc, DL, VT,
4675 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
4679 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4681 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4682 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4683 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4684 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4685 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4686 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4687 // Get reciprocal estimate.
4688 // float4 recip = vrecpeq_f32(yf);
4689 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4690 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4691 // Because char has a smaller range than uchar, we can actually get away
4692 // without any newton steps. This requires that we use a weird bias
4693 // of 0xb000, however (again, this has been exhaustively tested).
4694 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4695 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4696 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4697 Y = DAG.getConstant(0xb000, MVT::i32);
4698 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4699 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4700 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4701 // Convert back to short.
4702 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4703 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4708 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4710 // Convert to float.
4711 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4712 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4713 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4714 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4715 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4716 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4718 // Use reciprocal estimate and one refinement step.
4719 // float4 recip = vrecpeq_f32(yf);
4720 // recip *= vrecpsq_f32(yf, recip);
4721 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4722 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4723 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4724 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4726 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4727 // Because short has a smaller range than ushort, we can actually get away
4728 // with only a single newton step. This requires that we use a weird bias
4729 // of 89, however (again, this has been exhaustively tested).
4730 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
4731 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4732 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4733 N1 = DAG.getConstant(0x89, MVT::i32);
4734 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4735 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4736 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4737 // Convert back to integer and return.
4738 // return vmovn_s32(vcvt_s32_f32(result));
4739 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4740 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4744 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4745 EVT VT = Op.getValueType();
4746 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4747 "unexpected type for custom-lowering ISD::SDIV");
4749 DebugLoc dl = Op.getDebugLoc();
4750 SDValue N0 = Op.getOperand(0);
4751 SDValue N1 = Op.getOperand(1);
4754 if (VT == MVT::v8i8) {
4755 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4756 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4758 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4759 DAG.getIntPtrConstant(4));
4760 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4761 DAG.getIntPtrConstant(4));
4762 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4763 DAG.getIntPtrConstant(0));
4764 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4765 DAG.getIntPtrConstant(0));
4767 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4768 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4770 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4771 N0 = LowerCONCAT_VECTORS(N0, DAG);
4773 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4776 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4779 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4780 EVT VT = Op.getValueType();
4781 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4782 "unexpected type for custom-lowering ISD::UDIV");
4784 DebugLoc dl = Op.getDebugLoc();
4785 SDValue N0 = Op.getOperand(0);
4786 SDValue N1 = Op.getOperand(1);
4789 if (VT == MVT::v8i8) {
4790 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4791 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4793 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4794 DAG.getIntPtrConstant(4));
4795 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4796 DAG.getIntPtrConstant(4));
4797 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4798 DAG.getIntPtrConstant(0));
4799 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4800 DAG.getIntPtrConstant(0));
4802 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4803 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4805 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4806 N0 = LowerCONCAT_VECTORS(N0, DAG);
4808 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4809 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4814 // v4i16 sdiv ... Convert to float.
4815 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4816 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4817 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4818 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4819 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4820 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4822 // Use reciprocal estimate and two refinement steps.
4823 // float4 recip = vrecpeq_f32(yf);
4824 // recip *= vrecpsq_f32(yf, recip);
4825 // recip *= vrecpsq_f32(yf, recip);
4826 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4827 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
4828 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4829 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4831 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4832 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4833 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4835 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4836 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4837 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4838 // and that it will never cause us to return an answer too large).
4839 // float4 result = as_float4(as_int4(xf*recip) + 2);
4840 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4841 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4842 N1 = DAG.getConstant(2, MVT::i32);
4843 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4844 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4845 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4846 // Convert back to integer and return.
4847 // return vmovn_u32(vcvt_s32_f32(result));
4848 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4849 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4853 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
4854 EVT VT = Op.getNode()->getValueType(0);
4855 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4858 bool ExtraOp = false;
4859 switch (Op.getOpcode()) {
4860 default: assert(0 && "Invalid code");
4861 case ISD::ADDC: Opc = ARMISD::ADDC; break;
4862 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
4863 case ISD::SUBC: Opc = ARMISD::SUBC; break;
4864 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
4868 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
4870 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
4871 Op.getOperand(1), Op.getOperand(2));
4874 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
4875 // Monotonic load/store is legal for all targets
4876 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
4879 // Aquire/Release load/store is not legal for targets without a
4880 // dmb or equivalent available.
4886 ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results,
4887 SelectionDAG &DAG, unsigned NewOp) {
4888 EVT T = Node->getValueType(0);
4889 DebugLoc dl = Node->getDebugLoc();
4890 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
4892 SmallVector<SDValue, 6> Ops;
4893 Ops.push_back(Node->getOperand(0)); // Chain
4894 Ops.push_back(Node->getOperand(1)); // Ptr
4896 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4897 Node->getOperand(2), DAG.getIntPtrConstant(0)));
4898 // High part of Val1
4899 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4900 Node->getOperand(2), DAG.getIntPtrConstant(1)));
4901 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) {
4902 // High part of Val1
4903 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4904 Node->getOperand(3), DAG.getIntPtrConstant(0)));
4905 // High part of Val2
4906 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4907 Node->getOperand(3), DAG.getIntPtrConstant(1)));
4909 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
4911 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64,
4912 cast<MemSDNode>(Node)->getMemOperand());
4913 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) };
4914 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
4915 Results.push_back(Result.getValue(2));
4918 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4919 switch (Op.getOpcode()) {
4920 default: llvm_unreachable("Don't know how to custom lower this!");
4921 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4922 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4923 case ISD::GlobalAddress:
4924 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4925 LowerGlobalAddressELF(Op, DAG);
4926 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4927 case ISD::SELECT: return LowerSELECT(Op, DAG);
4928 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4929 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4930 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4931 case ISD::VASTART: return LowerVASTART(Op, DAG);
4932 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4933 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
4934 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4935 case ISD::SINT_TO_FP:
4936 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4937 case ISD::FP_TO_SINT:
4938 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4939 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4940 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4941 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4942 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4943 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4944 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4945 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4946 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4948 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4951 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4952 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4953 case ISD::SRL_PARTS:
4954 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4955 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4956 case ISD::SETCC: return LowerVSETCC(Op, DAG);
4957 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4958 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4959 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4960 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4961 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4962 case ISD::MUL: return LowerMUL(Op, DAG);
4963 case ISD::SDIV: return LowerSDIV(Op, DAG);
4964 case ISD::UDIV: return LowerUDIV(Op, DAG);
4968 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
4969 case ISD::ATOMIC_LOAD:
4970 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
4975 /// ReplaceNodeResults - Replace the results of node with an illegal result
4976 /// type with new values built out of custom code.
4977 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4978 SmallVectorImpl<SDValue>&Results,
4979 SelectionDAG &DAG) const {
4981 switch (N->getOpcode()) {
4983 llvm_unreachable("Don't know how to custom expand this!");
4986 Res = ExpandBITCAST(N, DAG);
4990 Res = Expand64BitShift(N, DAG, Subtarget);
4992 case ISD::ATOMIC_LOAD_ADD:
4993 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG);
4995 case ISD::ATOMIC_LOAD_AND:
4996 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG);
4998 case ISD::ATOMIC_LOAD_NAND:
4999 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG);
5001 case ISD::ATOMIC_LOAD_OR:
5002 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG);
5004 case ISD::ATOMIC_LOAD_SUB:
5005 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG);
5007 case ISD::ATOMIC_LOAD_XOR:
5008 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG);
5010 case ISD::ATOMIC_SWAP:
5011 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG);
5013 case ISD::ATOMIC_CMP_SWAP:
5014 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG);
5018 Results.push_back(Res);
5021 //===----------------------------------------------------------------------===//
5022 // ARM Scheduler Hooks
5023 //===----------------------------------------------------------------------===//
5026 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
5027 MachineBasicBlock *BB,
5028 unsigned Size) const {
5029 unsigned dest = MI->getOperand(0).getReg();
5030 unsigned ptr = MI->getOperand(1).getReg();
5031 unsigned oldval = MI->getOperand(2).getReg();
5032 unsigned newval = MI->getOperand(3).getReg();
5033 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5034 DebugLoc dl = MI->getDebugLoc();
5035 bool isThumb2 = Subtarget->isThumb2();
5037 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5039 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass
5040 : ARM::GPRRegisterClass);
5043 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5044 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass);
5045 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass);
5048 unsigned ldrOpc, strOpc;
5050 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5052 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5053 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5056 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5057 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5060 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5061 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5065 MachineFunction *MF = BB->getParent();
5066 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5067 MachineFunction::iterator It = BB;
5068 ++It; // insert the new blocks after the current block
5070 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5071 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5072 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5073 MF->insert(It, loop1MBB);
5074 MF->insert(It, loop2MBB);
5075 MF->insert(It, exitMBB);
5077 // Transfer the remainder of BB and its successor edges to exitMBB.
5078 exitMBB->splice(exitMBB->begin(), BB,
5079 llvm::next(MachineBasicBlock::iterator(MI)),
5081 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5085 // fallthrough --> loop1MBB
5086 BB->addSuccessor(loop1MBB);
5089 // ldrex dest, [ptr]
5093 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5094 if (ldrOpc == ARM::t2LDREX)
5096 AddDefaultPred(MIB);
5097 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5098 .addReg(dest).addReg(oldval));
5099 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5100 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5101 BB->addSuccessor(loop2MBB);
5102 BB->addSuccessor(exitMBB);
5105 // strex scratch, newval, [ptr]
5109 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr);
5110 if (strOpc == ARM::t2STREX)
5112 AddDefaultPred(MIB);
5113 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5114 .addReg(scratch).addImm(0));
5115 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5116 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5117 BB->addSuccessor(loop1MBB);
5118 BB->addSuccessor(exitMBB);
5124 MI->eraseFromParent(); // The instruction is gone now.
5130 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5131 unsigned Size, unsigned BinOpcode) const {
5132 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5133 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5135 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5136 MachineFunction *MF = BB->getParent();
5137 MachineFunction::iterator It = BB;
5140 unsigned dest = MI->getOperand(0).getReg();
5141 unsigned ptr = MI->getOperand(1).getReg();
5142 unsigned incr = MI->getOperand(2).getReg();
5143 DebugLoc dl = MI->getDebugLoc();
5144 bool isThumb2 = Subtarget->isThumb2();
5146 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5148 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5149 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5152 unsigned ldrOpc, strOpc;
5154 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5156 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5157 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5160 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5161 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5164 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5165 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5169 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5170 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5171 MF->insert(It, loopMBB);
5172 MF->insert(It, exitMBB);
5174 // Transfer the remainder of BB and its successor edges to exitMBB.
5175 exitMBB->splice(exitMBB->begin(), BB,
5176 llvm::next(MachineBasicBlock::iterator(MI)),
5178 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5180 TargetRegisterClass *TRC =
5181 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5182 unsigned scratch = MRI.createVirtualRegister(TRC);
5183 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
5187 // fallthrough --> loopMBB
5188 BB->addSuccessor(loopMBB);
5192 // <binop> scratch2, dest, incr
5193 // strex scratch, scratch2, ptr
5196 // fallthrough --> exitMBB
5198 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5199 if (ldrOpc == ARM::t2LDREX)
5201 AddDefaultPred(MIB);
5203 // operand order needs to go the other way for NAND
5204 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
5205 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5206 addReg(incr).addReg(dest)).addReg(0);
5208 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5209 addReg(dest).addReg(incr)).addReg(0);
5212 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5213 if (strOpc == ARM::t2STREX)
5215 AddDefaultPred(MIB);
5216 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5217 .addReg(scratch).addImm(0));
5218 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5219 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5221 BB->addSuccessor(loopMBB);
5222 BB->addSuccessor(exitMBB);
5228 MI->eraseFromParent(); // The instruction is gone now.
5234 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
5235 MachineBasicBlock *BB,
5238 ARMCC::CondCodes Cond) const {
5239 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5241 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5242 MachineFunction *MF = BB->getParent();
5243 MachineFunction::iterator It = BB;
5246 unsigned dest = MI->getOperand(0).getReg();
5247 unsigned ptr = MI->getOperand(1).getReg();
5248 unsigned incr = MI->getOperand(2).getReg();
5249 unsigned oldval = dest;
5250 DebugLoc dl = MI->getDebugLoc();
5251 bool isThumb2 = Subtarget->isThumb2();
5253 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5255 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5256 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5259 unsigned ldrOpc, strOpc, extendOpc;
5261 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5263 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5264 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5265 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
5268 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5269 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5270 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
5273 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5274 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5279 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5280 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5281 MF->insert(It, loopMBB);
5282 MF->insert(It, exitMBB);
5284 // Transfer the remainder of BB and its successor edges to exitMBB.
5285 exitMBB->splice(exitMBB->begin(), BB,
5286 llvm::next(MachineBasicBlock::iterator(MI)),
5288 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5290 TargetRegisterClass *TRC =
5291 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5292 unsigned scratch = MRI.createVirtualRegister(TRC);
5293 unsigned scratch2 = MRI.createVirtualRegister(TRC);
5297 // fallthrough --> loopMBB
5298 BB->addSuccessor(loopMBB);
5302 // (sign extend dest, if required)
5304 // cmov.cond scratch2, dest, incr
5305 // strex scratch, scratch2, ptr
5308 // fallthrough --> exitMBB
5310 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5311 if (ldrOpc == ARM::t2LDREX)
5313 AddDefaultPred(MIB);
5315 // Sign extend the value, if necessary.
5316 if (signExtend && extendOpc) {
5317 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass);
5318 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
5323 // Build compare and cmov instructions.
5324 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5325 .addReg(oldval).addReg(incr));
5326 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
5327 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR);
5329 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5330 if (strOpc == ARM::t2STREX)
5332 AddDefaultPred(MIB);
5333 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5334 .addReg(scratch).addImm(0));
5335 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5336 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5338 BB->addSuccessor(loopMBB);
5339 BB->addSuccessor(exitMBB);
5345 MI->eraseFromParent(); // The instruction is gone now.
5351 ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
5352 unsigned Op1, unsigned Op2,
5353 bool NeedsCarry, bool IsCmpxchg) const {
5354 // This also handles ATOMIC_SWAP, indicated by Op1==0.
5355 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5357 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5358 MachineFunction *MF = BB->getParent();
5359 MachineFunction::iterator It = BB;
5362 unsigned destlo = MI->getOperand(0).getReg();
5363 unsigned desthi = MI->getOperand(1).getReg();
5364 unsigned ptr = MI->getOperand(2).getReg();
5365 unsigned vallo = MI->getOperand(3).getReg();
5366 unsigned valhi = MI->getOperand(4).getReg();
5367 DebugLoc dl = MI->getDebugLoc();
5368 bool isThumb2 = Subtarget->isThumb2();
5370 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5372 MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass);
5373 MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass);
5374 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5377 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD;
5378 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD;
5380 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5381 MachineBasicBlock *contBB = 0, *cont2BB = 0;
5383 contBB = MF->CreateMachineBasicBlock(LLVM_BB);
5384 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB);
5386 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5387 MF->insert(It, loopMBB);
5389 MF->insert(It, contBB);
5390 MF->insert(It, cont2BB);
5392 MF->insert(It, exitMBB);
5394 // Transfer the remainder of BB and its successor edges to exitMBB.
5395 exitMBB->splice(exitMBB->begin(), BB,
5396 llvm::next(MachineBasicBlock::iterator(MI)),
5398 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5400 TargetRegisterClass *TRC =
5401 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5402 unsigned storesuccess = MRI.createVirtualRegister(TRC);
5406 // fallthrough --> loopMBB
5407 BB->addSuccessor(loopMBB);
5410 // ldrexd r2, r3, ptr
5411 // <binopa> r0, r2, incr
5412 // <binopb> r1, r3, incr
5413 // strexd storesuccess, r0, r1, ptr
5414 // cmp storesuccess, #0
5416 // fallthrough --> exitMBB
5418 // Note that the registers are explicitly specified because there is not any
5419 // way to force the register allocator to allocate a register pair.
5421 // FIXME: The hardcoded registers are not necessary for Thumb2, but we
5422 // need to properly enforce the restriction that the two output registers
5423 // for ldrexd must be different.
5426 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
5427 .addReg(ARM::R2, RegState::Define)
5428 .addReg(ARM::R3, RegState::Define).addReg(ptr));
5429 // Copy r2/r3 into dest. (This copy will normally be coalesced.)
5430 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2);
5431 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3);
5435 for (unsigned i = 0; i < 2; i++) {
5436 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr :
5438 .addReg(i == 0 ? destlo : desthi)
5439 .addReg(i == 0 ? vallo : valhi));
5440 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5441 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5442 BB->addSuccessor(exitMBB);
5443 BB->addSuccessor(i == 0 ? contBB : cont2BB);
5444 BB = (i == 0 ? contBB : cont2BB);
5447 // Copy to physregs for strexd
5448 unsigned setlo = MI->getOperand(5).getReg();
5449 unsigned sethi = MI->getOperand(6).getReg();
5450 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo);
5451 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi);
5453 // Perform binary operation
5454 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0)
5455 .addReg(destlo).addReg(vallo))
5456 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry));
5457 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1)
5458 .addReg(desthi).addReg(valhi)).addReg(0);
5460 // Copy to physregs for strexd
5461 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo);
5462 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi);
5466 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
5467 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr));
5469 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5470 .addReg(storesuccess).addImm(0));
5471 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5472 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5474 BB->addSuccessor(loopMBB);
5475 BB->addSuccessor(exitMBB);
5481 MI->eraseFromParent(); // The instruction is gone now.
5486 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
5487 /// registers the function context.
5488 void ARMTargetLowering::
5489 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
5490 MachineBasicBlock *DispatchBB, int FI) const {
5491 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5492 DebugLoc dl = MI->getDebugLoc();
5493 MachineFunction *MF = MBB->getParent();
5494 MachineRegisterInfo *MRI = &MF->getRegInfo();
5495 MachineConstantPool *MCP = MF->getConstantPool();
5496 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
5497 const Function *F = MF->getFunction();
5499 bool isThumb = Subtarget->isThumb();
5500 bool isThumb2 = Subtarget->isThumb2();
5502 unsigned PCLabelId = AFI->createPICLabelUId();
5503 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
5504 ARMConstantPoolValue *CPV =
5505 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
5506 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
5508 const TargetRegisterClass *TRC =
5509 isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5511 // Grab constant pool and fixed stack memory operands.
5512 MachineMemOperand *CPMMO =
5513 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
5514 MachineMemOperand::MOLoad, 4, 4);
5516 MachineMemOperand *FIMMOSt =
5517 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
5518 MachineMemOperand::MOStore, 4, 4);
5520 // Load the address of the dispatch MBB into the jump buffer.
5522 // Incoming value: jbuf
5523 // ldr.n r5, LCPI1_1
5526 // str r5, [$jbuf, #+4] ; &jbuf[1]
5527 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5528 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
5529 .addConstantPoolIndex(CPI)
5530 .addMemOperand(CPMMO));
5531 // Set the low bit because of thumb mode.
5532 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5534 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
5535 .addReg(NewVReg1, RegState::Kill)
5537 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5538 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
5539 .addReg(NewVReg2, RegState::Kill)
5541 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
5542 .addReg(NewVReg3, RegState::Kill)
5544 .addImm(36) // &jbuf[1] :: pc
5545 .addMemOperand(FIMMOSt));
5546 } else if (isThumb) {
5547 // Incoming value: jbuf
5548 // ldr.n r1, LCPI1_4
5552 // add r2, $jbuf, #+4 ; &jbuf[1]
5554 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5555 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
5556 .addConstantPoolIndex(CPI)
5557 .addMemOperand(CPMMO));
5558 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5559 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
5560 .addReg(NewVReg1, RegState::Kill)
5562 // Set the low bit because of thumb mode.
5563 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5564 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
5565 .addReg(ARM::CPSR, RegState::Define)
5567 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5568 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
5569 .addReg(ARM::CPSR, RegState::Define)
5570 .addReg(NewVReg2, RegState::Kill)
5571 .addReg(NewVReg3, RegState::Kill));
5572 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
5573 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
5575 .addImm(36)); // &jbuf[1] :: pc
5576 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
5577 .addReg(NewVReg4, RegState::Kill)
5578 .addReg(NewVReg5, RegState::Kill)
5580 .addMemOperand(FIMMOSt));
5582 // Incoming value: jbuf
5585 // str r1, [$jbuf, #+4] ; &jbuf[1]
5586 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5587 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
5588 .addConstantPoolIndex(CPI)
5590 .addMemOperand(CPMMO));
5591 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5592 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
5593 .addReg(NewVReg1, RegState::Kill)
5594 .addImm(PCLabelId));
5595 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
5596 .addReg(NewVReg2, RegState::Kill)
5598 .addImm(36) // &jbuf[1] :: pc
5599 .addMemOperand(FIMMOSt));
5603 MachineBasicBlock *ARMTargetLowering::
5604 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
5605 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5606 DebugLoc dl = MI->getDebugLoc();
5607 MachineFunction *MF = MBB->getParent();
5608 MachineRegisterInfo *MRI = &MF->getRegInfo();
5609 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
5610 MachineFrameInfo *MFI = MF->getFrameInfo();
5611 int FI = MFI->getFunctionContextIndex();
5613 const TargetRegisterClass *TRC =
5614 Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5616 // Get a mapping of the call site numbers to all of the landing pads they're
5618 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
5619 unsigned MaxCSNum = 0;
5620 MachineModuleInfo &MMI = MF->getMMI();
5621 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E; ++BB) {
5622 if (!BB->isLandingPad()) continue;
5624 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
5626 for (MachineBasicBlock::iterator
5627 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
5628 if (!II->isEHLabel()) continue;
5630 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
5631 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
5633 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
5634 for (SmallVectorImpl<unsigned>::iterator
5635 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
5636 CSI != CSE; ++CSI) {
5637 CallSiteNumToLPad[*CSI].push_back(BB);
5638 MaxCSNum = std::max(MaxCSNum, *CSI);
5644 // Get an ordered list of the machine basic blocks for the jump table.
5645 std::vector<MachineBasicBlock*> LPadList;
5646 LPadList.reserve(CallSiteNumToLPad.size());
5647 for (unsigned I = 1; I <= MaxCSNum; ++I) {
5648 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
5649 for (SmallVectorImpl<MachineBasicBlock*>::iterator
5650 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II)
5651 LPadList.push_back(*II);
5654 assert(!LPadList.empty() &&
5655 "No landing pad destinations for the dispatch jump table!");
5657 // Create the jump table and associated information.
5658 MachineJumpTableInfo *JTI =
5659 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
5660 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
5661 unsigned UId = AFI->createJumpTableUId();
5663 // Create the MBBs for the dispatch code.
5665 // Shove the dispatch's address into the return slot in the function context.
5666 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
5667 DispatchBB->setIsLandingPad();
5668 MBB->addSuccessor(DispatchBB);
5670 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
5671 BuildMI(TrapBB, dl, TII->get(ARM::TRAP));
5672 DispatchBB->addSuccessor(TrapBB);
5674 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
5675 DispatchBB->addSuccessor(DispContBB);
5677 // Insert and renumber MBBs.
5678 MachineBasicBlock *Last = &MF->back();
5679 MF->insert(MF->end(), DispatchBB);
5680 MF->insert(MF->end(), DispContBB);
5681 MF->insert(MF->end(), TrapBB);
5682 MF->RenumberBlocks(Last);
5684 // Insert code into the entry block that creates and registers the function
5686 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
5688 // Grab constant pool and fixed stack memory operands.
5689 MachineMemOperand *FIMMOLd =
5690 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
5691 MachineMemOperand::MOLoad, 4, 4);
5693 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5694 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
5697 .addMemOperand(FIMMOLd));
5698 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
5700 .addImm(LPadList.size()));
5701 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
5706 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5707 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT), NewVReg2)
5708 .addJumpTableIndex(MJTI)
5711 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5714 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg3)
5715 .addReg(NewVReg2, RegState::Kill)
5717 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
5719 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
5720 .addReg(NewVReg3, RegState::Kill)
5722 .addJumpTableIndex(MJTI)
5725 // Add the jump table entries as successors to the MBB.
5726 for (std::vector<MachineBasicBlock*>::iterator
5727 I = LPadList.begin(), E = LPadList.end(); I != E; ++I)
5728 DispContBB->addSuccessor(*I);
5730 // The instruction is gone now.
5731 MI->eraseFromParent();
5737 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
5738 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
5739 E = MBB->succ_end(); I != E; ++I)
5742 llvm_unreachable("Expecting a BB with two successors!");
5746 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
5747 MachineBasicBlock *BB) const {
5748 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5749 DebugLoc dl = MI->getDebugLoc();
5750 bool isThumb2 = Subtarget->isThumb2();
5751 switch (MI->getOpcode()) {
5754 llvm_unreachable("Unexpected instr type to insert");
5756 // The Thumb2 pre-indexed stores have the same MI operands, they just
5757 // define them differently in the .td files from the isel patterns, so
5758 // they need pseudos.
5759 case ARM::t2STR_preidx:
5760 MI->setDesc(TII->get(ARM::t2STR_PRE));
5762 case ARM::t2STRB_preidx:
5763 MI->setDesc(TII->get(ARM::t2STRB_PRE));
5765 case ARM::t2STRH_preidx:
5766 MI->setDesc(TII->get(ARM::t2STRH_PRE));
5769 case ARM::STRi_preidx:
5770 case ARM::STRBi_preidx: {
5771 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
5772 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
5773 // Decode the offset.
5774 unsigned Offset = MI->getOperand(4).getImm();
5775 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
5776 Offset = ARM_AM::getAM2Offset(Offset);
5780 MachineMemOperand *MMO = *MI->memoperands_begin();
5781 BuildMI(*BB, MI, dl, TII->get(NewOpc))
5782 .addOperand(MI->getOperand(0)) // Rn_wb
5783 .addOperand(MI->getOperand(1)) // Rt
5784 .addOperand(MI->getOperand(2)) // Rn
5785 .addImm(Offset) // offset (skip GPR==zero_reg)
5786 .addOperand(MI->getOperand(5)) // pred
5787 .addOperand(MI->getOperand(6))
5788 .addMemOperand(MMO);
5789 MI->eraseFromParent();
5792 case ARM::STRr_preidx:
5793 case ARM::STRBr_preidx:
5794 case ARM::STRH_preidx: {
5796 switch (MI->getOpcode()) {
5797 default: llvm_unreachable("unexpected opcode!");
5798 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
5799 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
5800 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
5802 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
5803 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
5804 MIB.addOperand(MI->getOperand(i));
5805 MI->eraseFromParent();
5808 case ARM::ATOMIC_LOAD_ADD_I8:
5809 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5810 case ARM::ATOMIC_LOAD_ADD_I16:
5811 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5812 case ARM::ATOMIC_LOAD_ADD_I32:
5813 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5815 case ARM::ATOMIC_LOAD_AND_I8:
5816 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5817 case ARM::ATOMIC_LOAD_AND_I16:
5818 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5819 case ARM::ATOMIC_LOAD_AND_I32:
5820 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5822 case ARM::ATOMIC_LOAD_OR_I8:
5823 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5824 case ARM::ATOMIC_LOAD_OR_I16:
5825 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5826 case ARM::ATOMIC_LOAD_OR_I32:
5827 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5829 case ARM::ATOMIC_LOAD_XOR_I8:
5830 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5831 case ARM::ATOMIC_LOAD_XOR_I16:
5832 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5833 case ARM::ATOMIC_LOAD_XOR_I32:
5834 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5836 case ARM::ATOMIC_LOAD_NAND_I8:
5837 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5838 case ARM::ATOMIC_LOAD_NAND_I16:
5839 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5840 case ARM::ATOMIC_LOAD_NAND_I32:
5841 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5843 case ARM::ATOMIC_LOAD_SUB_I8:
5844 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5845 case ARM::ATOMIC_LOAD_SUB_I16:
5846 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5847 case ARM::ATOMIC_LOAD_SUB_I32:
5848 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5850 case ARM::ATOMIC_LOAD_MIN_I8:
5851 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
5852 case ARM::ATOMIC_LOAD_MIN_I16:
5853 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
5854 case ARM::ATOMIC_LOAD_MIN_I32:
5855 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
5857 case ARM::ATOMIC_LOAD_MAX_I8:
5858 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
5859 case ARM::ATOMIC_LOAD_MAX_I16:
5860 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
5861 case ARM::ATOMIC_LOAD_MAX_I32:
5862 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
5864 case ARM::ATOMIC_LOAD_UMIN_I8:
5865 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
5866 case ARM::ATOMIC_LOAD_UMIN_I16:
5867 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
5868 case ARM::ATOMIC_LOAD_UMIN_I32:
5869 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
5871 case ARM::ATOMIC_LOAD_UMAX_I8:
5872 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
5873 case ARM::ATOMIC_LOAD_UMAX_I16:
5874 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
5875 case ARM::ATOMIC_LOAD_UMAX_I32:
5876 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
5878 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
5879 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
5880 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
5882 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
5883 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
5884 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
5887 case ARM::ATOMADD6432:
5888 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr,
5889 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr,
5890 /*NeedsCarry*/ true);
5891 case ARM::ATOMSUB6432:
5892 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
5893 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
5894 /*NeedsCarry*/ true);
5895 case ARM::ATOMOR6432:
5896 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr,
5897 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5898 case ARM::ATOMXOR6432:
5899 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr,
5900 isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5901 case ARM::ATOMAND6432:
5902 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr,
5903 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5904 case ARM::ATOMSWAP6432:
5905 return EmitAtomicBinary64(MI, BB, 0, 0, false);
5906 case ARM::ATOMCMPXCHG6432:
5907 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
5908 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
5909 /*NeedsCarry*/ false, /*IsCmpxchg*/true);
5911 case ARM::tMOVCCr_pseudo: {
5912 // To "insert" a SELECT_CC instruction, we actually have to insert the
5913 // diamond control-flow pattern. The incoming instruction knows the
5914 // destination vreg to set, the condition code register to branch on, the
5915 // true/false values to select between, and a branch opcode to use.
5916 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5917 MachineFunction::iterator It = BB;
5923 // cmpTY ccX, r1, r2
5925 // fallthrough --> copy0MBB
5926 MachineBasicBlock *thisMBB = BB;
5927 MachineFunction *F = BB->getParent();
5928 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
5929 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
5930 F->insert(It, copy0MBB);
5931 F->insert(It, sinkMBB);
5933 // Transfer the remainder of BB and its successor edges to sinkMBB.
5934 sinkMBB->splice(sinkMBB->begin(), BB,
5935 llvm::next(MachineBasicBlock::iterator(MI)),
5937 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
5939 BB->addSuccessor(copy0MBB);
5940 BB->addSuccessor(sinkMBB);
5942 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
5943 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
5946 // %FalseValue = ...
5947 // # fallthrough to sinkMBB
5950 // Update machine-CFG edges
5951 BB->addSuccessor(sinkMBB);
5954 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5957 BuildMI(*BB, BB->begin(), dl,
5958 TII->get(ARM::PHI), MI->getOperand(0).getReg())
5959 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5960 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5962 MI->eraseFromParent(); // The pseudo instruction is gone now.
5967 case ARM::BCCZi64: {
5968 // If there is an unconditional branch to the other successor, remove it.
5969 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
5971 // Compare both parts that make up the double comparison separately for
5973 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
5975 unsigned LHS1 = MI->getOperand(1).getReg();
5976 unsigned LHS2 = MI->getOperand(2).getReg();
5978 AddDefaultPred(BuildMI(BB, dl,
5979 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5980 .addReg(LHS1).addImm(0));
5981 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5982 .addReg(LHS2).addImm(0)
5983 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5985 unsigned RHS1 = MI->getOperand(3).getReg();
5986 unsigned RHS2 = MI->getOperand(4).getReg();
5987 AddDefaultPred(BuildMI(BB, dl,
5988 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5989 .addReg(LHS1).addReg(RHS1));
5990 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5991 .addReg(LHS2).addReg(RHS2)
5992 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5995 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
5996 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
5997 if (MI->getOperand(0).getImm() == ARMCC::NE)
5998 std::swap(destMBB, exitMBB);
6000 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6001 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
6003 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
6005 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
6007 MI->eraseFromParent(); // The pseudo instruction is gone now.
6013 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
6014 SDNode *Node) const {
6015 const MCInstrDesc &MCID = MI->getDesc();
6016 if (!MCID.hasPostISelHook()) {
6017 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
6018 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
6022 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
6023 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
6024 // operand is still set to noreg. If needed, set the optional operand's
6025 // register to CPSR, and remove the redundant implicit def.
6027 // e.g. ADCS (...opt:%noreg, CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
6029 // Rename pseudo opcodes.
6030 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
6032 const ARMBaseInstrInfo *TII =
6033 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
6034 MI->setDesc(TII->get(NewOpc));
6036 unsigned ccOutIdx = MCID.getNumOperands() - 1;
6038 // Any ARM instruction that sets the 's' bit should specify an optional
6039 // "cc_out" operand in the last operand position.
6040 if (!MCID.hasOptionalDef() || !MCID.OpInfo[ccOutIdx].isOptionalDef()) {
6041 assert(!NewOpc && "Optional cc_out operand required");
6044 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
6045 // since we already have an optional CPSR def.
6046 bool definesCPSR = false;
6047 bool deadCPSR = false;
6048 for (unsigned i = MCID.getNumOperands(), e = MI->getNumOperands();
6050 const MachineOperand &MO = MI->getOperand(i);
6051 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
6055 MI->RemoveOperand(i);
6060 assert(!NewOpc && "Optional cc_out operand required");
6063 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
6065 assert(!MI->getOperand(ccOutIdx).getReg() &&
6066 "expect uninitialized optional cc_out operand");
6070 // If this instruction was defined with an optional CPSR def and its dag node
6071 // had a live implicit CPSR def, then activate the optional CPSR def.
6072 MachineOperand &MO = MI->getOperand(ccOutIdx);
6073 MO.setReg(ARM::CPSR);
6077 //===----------------------------------------------------------------------===//
6078 // ARM Optimization Hooks
6079 //===----------------------------------------------------------------------===//
6082 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
6083 TargetLowering::DAGCombinerInfo &DCI) {
6084 SelectionDAG &DAG = DCI.DAG;
6085 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6086 EVT VT = N->getValueType(0);
6087 unsigned Opc = N->getOpcode();
6088 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
6089 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
6090 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
6091 ISD::CondCode CC = ISD::SETCC_INVALID;
6094 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
6096 SDValue CCOp = Slct.getOperand(0);
6097 if (CCOp.getOpcode() == ISD::SETCC)
6098 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
6101 bool DoXform = false;
6103 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
6106 if (LHS.getOpcode() == ISD::Constant &&
6107 cast<ConstantSDNode>(LHS)->isNullValue()) {
6109 } else if (CC != ISD::SETCC_INVALID &&
6110 RHS.getOpcode() == ISD::Constant &&
6111 cast<ConstantSDNode>(RHS)->isNullValue()) {
6112 std::swap(LHS, RHS);
6113 SDValue Op0 = Slct.getOperand(0);
6114 EVT OpVT = isSlctCC ? Op0.getValueType() :
6115 Op0.getOperand(0).getValueType();
6116 bool isInt = OpVT.isInteger();
6117 CC = ISD::getSetCCInverse(CC, isInt);
6119 if (!TLI.isCondCodeLegal(CC, OpVT))
6120 return SDValue(); // Inverse operator isn't legal.
6127 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
6129 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
6130 Slct.getOperand(0), Slct.getOperand(1), CC);
6131 SDValue CCOp = Slct.getOperand(0);
6133 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
6134 CCOp.getOperand(0), CCOp.getOperand(1), CC);
6135 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
6136 CCOp, OtherOp, Result);
6141 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
6142 // (only after legalization).
6143 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
6144 TargetLowering::DAGCombinerInfo &DCI,
6145 const ARMSubtarget *Subtarget) {
6147 // Only perform optimization if after legalize, and if NEON is available. We
6148 // also expected both operands to be BUILD_VECTORs.
6149 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
6150 || N0.getOpcode() != ISD::BUILD_VECTOR
6151 || N1.getOpcode() != ISD::BUILD_VECTOR)
6154 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
6155 EVT VT = N->getValueType(0);
6156 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
6159 // Check that the vector operands are of the right form.
6160 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
6161 // operands, where N is the size of the formed vector.
6162 // Each EXTRACT_VECTOR should have the same input vector and odd or even
6163 // index such that we have a pair wise add pattern.
6165 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
6166 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6168 SDValue Vec = N0->getOperand(0)->getOperand(0);
6169 SDNode *V = Vec.getNode();
6170 unsigned nextIndex = 0;
6172 // For each operands to the ADD which are BUILD_VECTORs,
6173 // check to see if each of their operands are an EXTRACT_VECTOR with
6174 // the same vector and appropriate index.
6175 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
6176 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
6177 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6179 SDValue ExtVec0 = N0->getOperand(i);
6180 SDValue ExtVec1 = N1->getOperand(i);
6182 // First operand is the vector, verify its the same.
6183 if (V != ExtVec0->getOperand(0).getNode() ||
6184 V != ExtVec1->getOperand(0).getNode())
6187 // Second is the constant, verify its correct.
6188 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
6189 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
6191 // For the constant, we want to see all the even or all the odd.
6192 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
6193 || C1->getZExtValue() != nextIndex+1)
6202 // Create VPADDL node.
6203 SelectionDAG &DAG = DCI.DAG;
6204 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6206 // Build operand list.
6207 SmallVector<SDValue, 8> Ops;
6208 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
6209 TLI.getPointerTy()));
6211 // Input is the vector.
6214 // Get widened type and narrowed type.
6216 unsigned numElem = VT.getVectorNumElements();
6217 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
6218 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
6219 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
6220 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
6222 assert(0 && "Invalid vector element type for padd optimization.");
6225 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
6226 widenType, &Ops[0], Ops.size());
6227 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp);
6230 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
6231 /// operands N0 and N1. This is a helper for PerformADDCombine that is
6232 /// called with the default operands, and if that fails, with commuted
6234 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
6235 TargetLowering::DAGCombinerInfo &DCI,
6236 const ARMSubtarget *Subtarget){
6238 // Attempt to create vpaddl for this add.
6239 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
6240 if (Result.getNode())
6243 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
6244 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
6245 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
6246 if (Result.getNode()) return Result;
6251 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
6253 static SDValue PerformADDCombine(SDNode *N,
6254 TargetLowering::DAGCombinerInfo &DCI,
6255 const ARMSubtarget *Subtarget) {
6256 SDValue N0 = N->getOperand(0);
6257 SDValue N1 = N->getOperand(1);
6259 // First try with the default operand order.
6260 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
6261 if (Result.getNode())
6264 // If that didn't work, try again with the operands commuted.
6265 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
6268 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
6270 static SDValue PerformSUBCombine(SDNode *N,
6271 TargetLowering::DAGCombinerInfo &DCI) {
6272 SDValue N0 = N->getOperand(0);
6273 SDValue N1 = N->getOperand(1);
6275 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
6276 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
6277 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
6278 if (Result.getNode()) return Result;
6284 /// PerformVMULCombine
6285 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
6286 /// special multiplier accumulator forwarding.
6292 static SDValue PerformVMULCombine(SDNode *N,
6293 TargetLowering::DAGCombinerInfo &DCI,
6294 const ARMSubtarget *Subtarget) {
6295 if (!Subtarget->hasVMLxForwarding())
6298 SelectionDAG &DAG = DCI.DAG;
6299 SDValue N0 = N->getOperand(0);
6300 SDValue N1 = N->getOperand(1);
6301 unsigned Opcode = N0.getOpcode();
6302 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
6303 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
6304 Opcode = N1.getOpcode();
6305 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
6306 Opcode != ISD::FADD && Opcode != ISD::FSUB)
6311 EVT VT = N->getValueType(0);
6312 DebugLoc DL = N->getDebugLoc();
6313 SDValue N00 = N0->getOperand(0);
6314 SDValue N01 = N0->getOperand(1);
6315 return DAG.getNode(Opcode, DL, VT,
6316 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
6317 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
6320 static SDValue PerformMULCombine(SDNode *N,
6321 TargetLowering::DAGCombinerInfo &DCI,
6322 const ARMSubtarget *Subtarget) {
6323 SelectionDAG &DAG = DCI.DAG;
6325 if (Subtarget->isThumb1Only())
6328 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
6331 EVT VT = N->getValueType(0);
6332 if (VT.is64BitVector() || VT.is128BitVector())
6333 return PerformVMULCombine(N, DCI, Subtarget);
6337 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
6341 uint64_t MulAmt = C->getZExtValue();
6342 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
6343 ShiftAmt = ShiftAmt & (32 - 1);
6344 SDValue V = N->getOperand(0);
6345 DebugLoc DL = N->getDebugLoc();
6348 MulAmt >>= ShiftAmt;
6349 if (isPowerOf2_32(MulAmt - 1)) {
6350 // (mul x, 2^N + 1) => (add (shl x, N), x)
6351 Res = DAG.getNode(ISD::ADD, DL, VT,
6352 V, DAG.getNode(ISD::SHL, DL, VT,
6353 V, DAG.getConstant(Log2_32(MulAmt-1),
6355 } else if (isPowerOf2_32(MulAmt + 1)) {
6356 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6357 Res = DAG.getNode(ISD::SUB, DL, VT,
6358 DAG.getNode(ISD::SHL, DL, VT,
6359 V, DAG.getConstant(Log2_32(MulAmt+1),
6366 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
6367 DAG.getConstant(ShiftAmt, MVT::i32));
6369 // Do not add new nodes to DAG combiner worklist.
6370 DCI.CombineTo(N, Res, false);
6374 static SDValue PerformANDCombine(SDNode *N,
6375 TargetLowering::DAGCombinerInfo &DCI) {
6377 // Attempt to use immediate-form VBIC
6378 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
6379 DebugLoc dl = N->getDebugLoc();
6380 EVT VT = N->getValueType(0);
6381 SelectionDAG &DAG = DCI.DAG;
6383 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6386 APInt SplatBits, SplatUndef;
6387 unsigned SplatBitSize;
6390 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
6391 if (SplatBitSize <= 64) {
6393 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
6394 SplatUndef.getZExtValue(), SplatBitSize,
6395 DAG, VbicVT, VT.is128BitVector(),
6397 if (Val.getNode()) {
6399 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
6400 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
6401 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
6409 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
6410 static SDValue PerformORCombine(SDNode *N,
6411 TargetLowering::DAGCombinerInfo &DCI,
6412 const ARMSubtarget *Subtarget) {
6413 // Attempt to use immediate-form VORR
6414 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
6415 DebugLoc dl = N->getDebugLoc();
6416 EVT VT = N->getValueType(0);
6417 SelectionDAG &DAG = DCI.DAG;
6419 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6422 APInt SplatBits, SplatUndef;
6423 unsigned SplatBitSize;
6425 if (BVN && Subtarget->hasNEON() &&
6426 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
6427 if (SplatBitSize <= 64) {
6429 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
6430 SplatUndef.getZExtValue(), SplatBitSize,
6431 DAG, VorrVT, VT.is128BitVector(),
6433 if (Val.getNode()) {
6435 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
6436 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
6437 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
6442 SDValue N0 = N->getOperand(0);
6443 if (N0.getOpcode() != ISD::AND)
6445 SDValue N1 = N->getOperand(1);
6447 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
6448 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
6449 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
6451 unsigned SplatBitSize;
6454 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
6456 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
6457 HasAnyUndefs) && !HasAnyUndefs) {
6458 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
6460 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
6461 HasAnyUndefs) && !HasAnyUndefs &&
6462 SplatBits0 == ~SplatBits1) {
6463 // Canonicalize the vector type to make instruction selection simpler.
6464 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
6465 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
6466 N0->getOperand(1), N0->getOperand(0),
6468 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
6473 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
6476 // BFI is only available on V6T2+
6477 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
6480 DebugLoc DL = N->getDebugLoc();
6481 // 1) or (and A, mask), val => ARMbfi A, val, mask
6482 // iff (val & mask) == val
6484 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
6485 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
6486 // && mask == ~mask2
6487 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
6488 // && ~mask == mask2
6489 // (i.e., copy a bitfield value into another bitfield of the same width)
6494 SDValue N00 = N0.getOperand(0);
6496 // The value and the mask need to be constants so we can verify this is
6497 // actually a bitfield set. If the mask is 0xffff, we can do better
6498 // via a movt instruction, so don't use BFI in that case.
6499 SDValue MaskOp = N0.getOperand(1);
6500 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
6503 unsigned Mask = MaskC->getZExtValue();
6507 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
6508 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
6510 unsigned Val = N1C->getZExtValue();
6511 if ((Val & ~Mask) != Val)
6514 if (ARM::isBitFieldInvertedMask(Mask)) {
6515 Val >>= CountTrailingZeros_32(~Mask);
6517 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
6518 DAG.getConstant(Val, MVT::i32),
6519 DAG.getConstant(Mask, MVT::i32));
6521 // Do not add new nodes to DAG combiner worklist.
6522 DCI.CombineTo(N, Res, false);
6525 } else if (N1.getOpcode() == ISD::AND) {
6526 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
6527 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
6530 unsigned Mask2 = N11C->getZExtValue();
6532 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
6534 if (ARM::isBitFieldInvertedMask(Mask) &&
6536 // The pack halfword instruction works better for masks that fit it,
6537 // so use that when it's available.
6538 if (Subtarget->hasT2ExtractPack() &&
6539 (Mask == 0xffff || Mask == 0xffff0000))
6542 unsigned amt = CountTrailingZeros_32(Mask2);
6543 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
6544 DAG.getConstant(amt, MVT::i32));
6545 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
6546 DAG.getConstant(Mask, MVT::i32));
6547 // Do not add new nodes to DAG combiner worklist.
6548 DCI.CombineTo(N, Res, false);
6550 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
6552 // The pack halfword instruction works better for masks that fit it,
6553 // so use that when it's available.
6554 if (Subtarget->hasT2ExtractPack() &&
6555 (Mask2 == 0xffff || Mask2 == 0xffff0000))
6558 unsigned lsb = CountTrailingZeros_32(Mask);
6559 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
6560 DAG.getConstant(lsb, MVT::i32));
6561 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
6562 DAG.getConstant(Mask2, MVT::i32));
6563 // Do not add new nodes to DAG combiner worklist.
6564 DCI.CombineTo(N, Res, false);
6569 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
6570 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
6571 ARM::isBitFieldInvertedMask(~Mask)) {
6572 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
6573 // where lsb(mask) == #shamt and masked bits of B are known zero.
6574 SDValue ShAmt = N00.getOperand(1);
6575 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
6576 unsigned LSB = CountTrailingZeros_32(Mask);
6580 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
6581 DAG.getConstant(~Mask, MVT::i32));
6583 // Do not add new nodes to DAG combiner worklist.
6584 DCI.CombineTo(N, Res, false);
6590 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
6591 /// the bits being cleared by the AND are not demanded by the BFI.
6592 static SDValue PerformBFICombine(SDNode *N,
6593 TargetLowering::DAGCombinerInfo &DCI) {
6594 SDValue N1 = N->getOperand(1);
6595 if (N1.getOpcode() == ISD::AND) {
6596 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
6599 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
6600 unsigned LSB = CountTrailingZeros_32(~InvMask);
6601 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB;
6602 unsigned Mask = (1 << Width)-1;
6603 unsigned Mask2 = N11C->getZExtValue();
6604 if ((Mask & (~Mask2)) == 0)
6605 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
6606 N->getOperand(0), N1.getOperand(0),
6612 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
6613 /// ARMISD::VMOVRRD.
6614 static SDValue PerformVMOVRRDCombine(SDNode *N,
6615 TargetLowering::DAGCombinerInfo &DCI) {
6616 // vmovrrd(vmovdrr x, y) -> x,y
6617 SDValue InDouble = N->getOperand(0);
6618 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
6619 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
6621 // vmovrrd(load f64) -> (load i32), (load i32)
6622 SDNode *InNode = InDouble.getNode();
6623 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
6624 InNode->getValueType(0) == MVT::f64 &&
6625 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
6626 !cast<LoadSDNode>(InNode)->isVolatile()) {
6627 // TODO: Should this be done for non-FrameIndex operands?
6628 LoadSDNode *LD = cast<LoadSDNode>(InNode);
6630 SelectionDAG &DAG = DCI.DAG;
6631 DebugLoc DL = LD->getDebugLoc();
6632 SDValue BasePtr = LD->getBasePtr();
6633 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
6634 LD->getPointerInfo(), LD->isVolatile(),
6635 LD->isNonTemporal(), LD->getAlignment());
6637 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
6638 DAG.getConstant(4, MVT::i32));
6639 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
6640 LD->getPointerInfo(), LD->isVolatile(),
6641 LD->isNonTemporal(),
6642 std::min(4U, LD->getAlignment() / 2));
6644 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
6645 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
6646 DCI.RemoveFromWorklist(LD);
6654 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
6655 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
6656 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
6657 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
6658 SDValue Op0 = N->getOperand(0);
6659 SDValue Op1 = N->getOperand(1);
6660 if (Op0.getOpcode() == ISD::BITCAST)
6661 Op0 = Op0.getOperand(0);
6662 if (Op1.getOpcode() == ISD::BITCAST)
6663 Op1 = Op1.getOperand(0);
6664 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
6665 Op0.getNode() == Op1.getNode() &&
6666 Op0.getResNo() == 0 && Op1.getResNo() == 1)
6667 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6668 N->getValueType(0), Op0.getOperand(0));
6672 /// PerformSTORECombine - Target-specific dag combine xforms for
6674 static SDValue PerformSTORECombine(SDNode *N,
6675 TargetLowering::DAGCombinerInfo &DCI) {
6676 // Bitcast an i64 store extracted from a vector to f64.
6677 // Otherwise, the i64 value will be legalized to a pair of i32 values.
6678 StoreSDNode *St = cast<StoreSDNode>(N);
6679 SDValue StVal = St->getValue();
6680 if (!ISD::isNormalStore(St) || St->isVolatile())
6683 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
6684 StVal.getNode()->hasOneUse() && !St->isVolatile()) {
6685 SelectionDAG &DAG = DCI.DAG;
6686 DebugLoc DL = St->getDebugLoc();
6687 SDValue BasePtr = St->getBasePtr();
6688 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
6689 StVal.getNode()->getOperand(0), BasePtr,
6690 St->getPointerInfo(), St->isVolatile(),
6691 St->isNonTemporal(), St->getAlignment());
6693 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
6694 DAG.getConstant(4, MVT::i32));
6695 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
6696 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
6697 St->isNonTemporal(),
6698 std::min(4U, St->getAlignment() / 2));
6701 if (StVal.getValueType() != MVT::i64 ||
6702 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6705 SelectionDAG &DAG = DCI.DAG;
6706 DebugLoc dl = StVal.getDebugLoc();
6707 SDValue IntVec = StVal.getOperand(0);
6708 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
6709 IntVec.getValueType().getVectorNumElements());
6710 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
6711 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6712 Vec, StVal.getOperand(1));
6713 dl = N->getDebugLoc();
6714 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
6715 // Make the DAGCombiner fold the bitcasts.
6716 DCI.AddToWorklist(Vec.getNode());
6717 DCI.AddToWorklist(ExtElt.getNode());
6718 DCI.AddToWorklist(V.getNode());
6719 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
6720 St->getPointerInfo(), St->isVolatile(),
6721 St->isNonTemporal(), St->getAlignment(),
6725 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
6726 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
6727 /// i64 vector to have f64 elements, since the value can then be loaded
6728 /// directly into a VFP register.
6729 static bool hasNormalLoadOperand(SDNode *N) {
6730 unsigned NumElts = N->getValueType(0).getVectorNumElements();
6731 for (unsigned i = 0; i < NumElts; ++i) {
6732 SDNode *Elt = N->getOperand(i).getNode();
6733 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
6739 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
6740 /// ISD::BUILD_VECTOR.
6741 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
6742 TargetLowering::DAGCombinerInfo &DCI){
6743 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
6744 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
6745 // into a pair of GPRs, which is fine when the value is used as a scalar,
6746 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
6747 SelectionDAG &DAG = DCI.DAG;
6748 if (N->getNumOperands() == 2) {
6749 SDValue RV = PerformVMOVDRRCombine(N, DAG);
6754 // Load i64 elements as f64 values so that type legalization does not split
6755 // them up into i32 values.
6756 EVT VT = N->getValueType(0);
6757 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
6759 DebugLoc dl = N->getDebugLoc();
6760 SmallVector<SDValue, 8> Ops;
6761 unsigned NumElts = VT.getVectorNumElements();
6762 for (unsigned i = 0; i < NumElts; ++i) {
6763 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
6765 // Make the DAGCombiner fold the bitcast.
6766 DCI.AddToWorklist(V.getNode());
6768 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
6769 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
6770 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
6773 /// PerformInsertEltCombine - Target-specific dag combine xforms for
6774 /// ISD::INSERT_VECTOR_ELT.
6775 static SDValue PerformInsertEltCombine(SDNode *N,
6776 TargetLowering::DAGCombinerInfo &DCI) {
6777 // Bitcast an i64 load inserted into a vector to f64.
6778 // Otherwise, the i64 value will be legalized to a pair of i32 values.
6779 EVT VT = N->getValueType(0);
6780 SDNode *Elt = N->getOperand(1).getNode();
6781 if (VT.getVectorElementType() != MVT::i64 ||
6782 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
6785 SelectionDAG &DAG = DCI.DAG;
6786 DebugLoc dl = N->getDebugLoc();
6787 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
6788 VT.getVectorNumElements());
6789 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
6790 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
6791 // Make the DAGCombiner fold the bitcasts.
6792 DCI.AddToWorklist(Vec.getNode());
6793 DCI.AddToWorklist(V.getNode());
6794 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
6795 Vec, V, N->getOperand(2));
6796 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
6799 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
6800 /// ISD::VECTOR_SHUFFLE.
6801 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
6802 // The LLVM shufflevector instruction does not require the shuffle mask
6803 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
6804 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
6805 // operands do not match the mask length, they are extended by concatenating
6806 // them with undef vectors. That is probably the right thing for other
6807 // targets, but for NEON it is better to concatenate two double-register
6808 // size vector operands into a single quad-register size vector. Do that
6809 // transformation here:
6810 // shuffle(concat(v1, undef), concat(v2, undef)) ->
6811 // shuffle(concat(v1, v2), undef)
6812 SDValue Op0 = N->getOperand(0);
6813 SDValue Op1 = N->getOperand(1);
6814 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
6815 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
6816 Op0.getNumOperands() != 2 ||
6817 Op1.getNumOperands() != 2)
6819 SDValue Concat0Op1 = Op0.getOperand(1);
6820 SDValue Concat1Op1 = Op1.getOperand(1);
6821 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
6822 Concat1Op1.getOpcode() != ISD::UNDEF)
6824 // Skip the transformation if any of the types are illegal.
6825 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6826 EVT VT = N->getValueType(0);
6827 if (!TLI.isTypeLegal(VT) ||
6828 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
6829 !TLI.isTypeLegal(Concat1Op1.getValueType()))
6832 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
6833 Op0.getOperand(0), Op1.getOperand(0));
6834 // Translate the shuffle mask.
6835 SmallVector<int, 16> NewMask;
6836 unsigned NumElts = VT.getVectorNumElements();
6837 unsigned HalfElts = NumElts/2;
6838 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
6839 for (unsigned n = 0; n < NumElts; ++n) {
6840 int MaskElt = SVN->getMaskElt(n);
6842 if (MaskElt < (int)HalfElts)
6844 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
6845 NewElt = HalfElts + MaskElt - NumElts;
6846 NewMask.push_back(NewElt);
6848 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
6849 DAG.getUNDEF(VT), NewMask.data());
6852 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
6853 /// NEON load/store intrinsics to merge base address updates.
6854 static SDValue CombineBaseUpdate(SDNode *N,
6855 TargetLowering::DAGCombinerInfo &DCI) {
6856 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
6859 SelectionDAG &DAG = DCI.DAG;
6860 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
6861 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
6862 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
6863 SDValue Addr = N->getOperand(AddrOpIdx);
6865 // Search for a use of the address operand that is an increment.
6866 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
6867 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
6869 if (User->getOpcode() != ISD::ADD ||
6870 UI.getUse().getResNo() != Addr.getResNo())
6873 // Check that the add is independent of the load/store. Otherwise, folding
6874 // it would create a cycle.
6875 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
6878 // Find the new opcode for the updating load/store.
6880 bool isLaneOp = false;
6881 unsigned NewOpc = 0;
6882 unsigned NumVecs = 0;
6884 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
6886 default: assert(0 && "unexpected intrinsic for Neon base update");
6887 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
6889 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
6891 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
6893 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
6895 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
6896 NumVecs = 2; isLaneOp = true; break;
6897 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
6898 NumVecs = 3; isLaneOp = true; break;
6899 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
6900 NumVecs = 4; isLaneOp = true; break;
6901 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
6902 NumVecs = 1; isLoad = false; break;
6903 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
6904 NumVecs = 2; isLoad = false; break;
6905 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
6906 NumVecs = 3; isLoad = false; break;
6907 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
6908 NumVecs = 4; isLoad = false; break;
6909 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
6910 NumVecs = 2; isLoad = false; isLaneOp = true; break;
6911 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
6912 NumVecs = 3; isLoad = false; isLaneOp = true; break;
6913 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
6914 NumVecs = 4; isLoad = false; isLaneOp = true; break;
6918 switch (N->getOpcode()) {
6919 default: assert(0 && "unexpected opcode for Neon base update");
6920 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
6921 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
6922 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
6926 // Find the size of memory referenced by the load/store.
6929 VecTy = N->getValueType(0);
6931 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
6932 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
6934 NumBytes /= VecTy.getVectorNumElements();
6936 // If the increment is a constant, it must match the memory ref size.
6937 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
6938 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
6939 uint64_t IncVal = CInc->getZExtValue();
6940 if (IncVal != NumBytes)
6942 } else if (NumBytes >= 3 * 16) {
6943 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
6944 // separate instructions that make it harder to use a non-constant update.
6948 // Create the new updating load/store node.
6950 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
6952 for (n = 0; n < NumResultVecs; ++n)
6954 Tys[n++] = MVT::i32;
6955 Tys[n] = MVT::Other;
6956 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
6957 SmallVector<SDValue, 8> Ops;
6958 Ops.push_back(N->getOperand(0)); // incoming chain
6959 Ops.push_back(N->getOperand(AddrOpIdx));
6961 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
6962 Ops.push_back(N->getOperand(i));
6964 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
6965 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
6966 Ops.data(), Ops.size(),
6967 MemInt->getMemoryVT(),
6968 MemInt->getMemOperand());
6971 std::vector<SDValue> NewResults;
6972 for (unsigned i = 0; i < NumResultVecs; ++i) {
6973 NewResults.push_back(SDValue(UpdN.getNode(), i));
6975 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
6976 DCI.CombineTo(N, NewResults);
6977 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
6984 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
6985 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
6986 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
6988 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
6989 SelectionDAG &DAG = DCI.DAG;
6990 EVT VT = N->getValueType(0);
6991 // vldN-dup instructions only support 64-bit vectors for N > 1.
6992 if (!VT.is64BitVector())
6995 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
6996 SDNode *VLD = N->getOperand(0).getNode();
6997 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
6999 unsigned NumVecs = 0;
7000 unsigned NewOpc = 0;
7001 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
7002 if (IntNo == Intrinsic::arm_neon_vld2lane) {
7004 NewOpc = ARMISD::VLD2DUP;
7005 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
7007 NewOpc = ARMISD::VLD3DUP;
7008 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
7010 NewOpc = ARMISD::VLD4DUP;
7015 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
7016 // numbers match the load.
7017 unsigned VLDLaneNo =
7018 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
7019 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
7021 // Ignore uses of the chain result.
7022 if (UI.getUse().getResNo() == NumVecs)
7025 if (User->getOpcode() != ARMISD::VDUPLANE ||
7026 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
7030 // Create the vldN-dup node.
7033 for (n = 0; n < NumVecs; ++n)
7035 Tys[n] = MVT::Other;
7036 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
7037 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
7038 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
7039 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
7040 Ops, 2, VLDMemInt->getMemoryVT(),
7041 VLDMemInt->getMemOperand());
7044 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
7046 unsigned ResNo = UI.getUse().getResNo();
7047 // Ignore uses of the chain result.
7048 if (ResNo == NumVecs)
7051 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
7054 // Now the vldN-lane intrinsic is dead except for its chain result.
7055 // Update uses of the chain.
7056 std::vector<SDValue> VLDDupResults;
7057 for (unsigned n = 0; n < NumVecs; ++n)
7058 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
7059 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
7060 DCI.CombineTo(VLD, VLDDupResults);
7065 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
7066 /// ARMISD::VDUPLANE.
7067 static SDValue PerformVDUPLANECombine(SDNode *N,
7068 TargetLowering::DAGCombinerInfo &DCI) {
7069 SDValue Op = N->getOperand(0);
7071 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
7072 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
7073 if (CombineVLDDUP(N, DCI))
7074 return SDValue(N, 0);
7076 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
7077 // redundant. Ignore bit_converts for now; element sizes are checked below.
7078 while (Op.getOpcode() == ISD::BITCAST)
7079 Op = Op.getOperand(0);
7080 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
7083 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
7084 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
7085 // The canonical VMOV for a zero vector uses a 32-bit element size.
7086 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7088 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
7090 EVT VT = N->getValueType(0);
7091 if (EltSize > VT.getVectorElementType().getSizeInBits())
7094 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
7097 // isConstVecPow2 - Return true if each vector element is a power of 2, all
7098 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
7099 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
7103 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
7105 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
7110 APFloat APF = C->getValueAPF();
7111 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
7112 != APFloat::opOK || !isExact)
7115 c0 = (I == 0) ? cN : c0;
7116 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
7123 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
7124 /// can replace combinations of VMUL and VCVT (floating-point to integer)
7125 /// when the VMUL has a constant operand that is a power of 2.
7127 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
7128 /// vmul.f32 d16, d17, d16
7129 /// vcvt.s32.f32 d16, d16
7131 /// vcvt.s32.f32 d16, d16, #3
7132 static SDValue PerformVCVTCombine(SDNode *N,
7133 TargetLowering::DAGCombinerInfo &DCI,
7134 const ARMSubtarget *Subtarget) {
7135 SelectionDAG &DAG = DCI.DAG;
7136 SDValue Op = N->getOperand(0);
7138 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
7139 Op.getOpcode() != ISD::FMUL)
7143 SDValue N0 = Op->getOperand(0);
7144 SDValue ConstVec = Op->getOperand(1);
7145 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
7147 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7148 !isConstVecPow2(ConstVec, isSigned, C))
7151 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
7152 Intrinsic::arm_neon_vcvtfp2fxu;
7153 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
7155 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
7156 DAG.getConstant(Log2_64(C), MVT::i32));
7159 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
7160 /// can replace combinations of VCVT (integer to floating-point) and VDIV
7161 /// when the VDIV has a constant operand that is a power of 2.
7163 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
7164 /// vcvt.f32.s32 d16, d16
7165 /// vdiv.f32 d16, d17, d16
7167 /// vcvt.f32.s32 d16, d16, #3
7168 static SDValue PerformVDIVCombine(SDNode *N,
7169 TargetLowering::DAGCombinerInfo &DCI,
7170 const ARMSubtarget *Subtarget) {
7171 SelectionDAG &DAG = DCI.DAG;
7172 SDValue Op = N->getOperand(0);
7173 unsigned OpOpcode = Op.getNode()->getOpcode();
7175 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
7176 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
7180 SDValue ConstVec = N->getOperand(1);
7181 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
7183 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7184 !isConstVecPow2(ConstVec, isSigned, C))
7187 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
7188 Intrinsic::arm_neon_vcvtfxu2fp;
7189 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
7191 DAG.getConstant(IntrinsicOpcode, MVT::i32),
7192 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32));
7195 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
7196 /// operand of a vector shift operation, where all the elements of the
7197 /// build_vector must have the same constant integer value.
7198 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
7199 // Ignore bit_converts.
7200 while (Op.getOpcode() == ISD::BITCAST)
7201 Op = Op.getOperand(0);
7202 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
7203 APInt SplatBits, SplatUndef;
7204 unsigned SplatBitSize;
7206 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
7207 HasAnyUndefs, ElementBits) ||
7208 SplatBitSize > ElementBits)
7210 Cnt = SplatBits.getSExtValue();
7214 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
7215 /// operand of a vector shift left operation. That value must be in the range:
7216 /// 0 <= Value < ElementBits for a left shift; or
7217 /// 0 <= Value <= ElementBits for a long left shift.
7218 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
7219 assert(VT.isVector() && "vector shift count is not a vector type");
7220 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
7221 if (! getVShiftImm(Op, ElementBits, Cnt))
7223 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
7226 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
7227 /// operand of a vector shift right operation. For a shift opcode, the value
7228 /// is positive, but for an intrinsic the value count must be negative. The
7229 /// absolute value must be in the range:
7230 /// 1 <= |Value| <= ElementBits for a right shift; or
7231 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
7232 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
7234 assert(VT.isVector() && "vector shift count is not a vector type");
7235 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
7236 if (! getVShiftImm(Op, ElementBits, Cnt))
7240 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
7243 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
7244 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
7245 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
7248 // Don't do anything for most intrinsics.
7251 // Vector shifts: check for immediate versions and lower them.
7252 // Note: This is done during DAG combining instead of DAG legalizing because
7253 // the build_vectors for 64-bit vector element shift counts are generally
7254 // not legal, and it is hard to see their values after they get legalized to
7255 // loads from a constant pool.
7256 case Intrinsic::arm_neon_vshifts:
7257 case Intrinsic::arm_neon_vshiftu:
7258 case Intrinsic::arm_neon_vshiftls:
7259 case Intrinsic::arm_neon_vshiftlu:
7260 case Intrinsic::arm_neon_vshiftn:
7261 case Intrinsic::arm_neon_vrshifts:
7262 case Intrinsic::arm_neon_vrshiftu:
7263 case Intrinsic::arm_neon_vrshiftn:
7264 case Intrinsic::arm_neon_vqshifts:
7265 case Intrinsic::arm_neon_vqshiftu:
7266 case Intrinsic::arm_neon_vqshiftsu:
7267 case Intrinsic::arm_neon_vqshiftns:
7268 case Intrinsic::arm_neon_vqshiftnu:
7269 case Intrinsic::arm_neon_vqshiftnsu:
7270 case Intrinsic::arm_neon_vqrshiftns:
7271 case Intrinsic::arm_neon_vqrshiftnu:
7272 case Intrinsic::arm_neon_vqrshiftnsu: {
7273 EVT VT = N->getOperand(1).getValueType();
7275 unsigned VShiftOpc = 0;
7278 case Intrinsic::arm_neon_vshifts:
7279 case Intrinsic::arm_neon_vshiftu:
7280 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
7281 VShiftOpc = ARMISD::VSHL;
7284 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
7285 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
7286 ARMISD::VSHRs : ARMISD::VSHRu);
7291 case Intrinsic::arm_neon_vshiftls:
7292 case Intrinsic::arm_neon_vshiftlu:
7293 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
7295 llvm_unreachable("invalid shift count for vshll intrinsic");
7297 case Intrinsic::arm_neon_vrshifts:
7298 case Intrinsic::arm_neon_vrshiftu:
7299 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
7303 case Intrinsic::arm_neon_vqshifts:
7304 case Intrinsic::arm_neon_vqshiftu:
7305 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
7309 case Intrinsic::arm_neon_vqshiftsu:
7310 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
7312 llvm_unreachable("invalid shift count for vqshlu intrinsic");
7314 case Intrinsic::arm_neon_vshiftn:
7315 case Intrinsic::arm_neon_vrshiftn:
7316 case Intrinsic::arm_neon_vqshiftns:
7317 case Intrinsic::arm_neon_vqshiftnu:
7318 case Intrinsic::arm_neon_vqshiftnsu:
7319 case Intrinsic::arm_neon_vqrshiftns:
7320 case Intrinsic::arm_neon_vqrshiftnu:
7321 case Intrinsic::arm_neon_vqrshiftnsu:
7322 // Narrowing shifts require an immediate right shift.
7323 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
7325 llvm_unreachable("invalid shift count for narrowing vector shift "
7329 llvm_unreachable("unhandled vector shift");
7333 case Intrinsic::arm_neon_vshifts:
7334 case Intrinsic::arm_neon_vshiftu:
7335 // Opcode already set above.
7337 case Intrinsic::arm_neon_vshiftls:
7338 case Intrinsic::arm_neon_vshiftlu:
7339 if (Cnt == VT.getVectorElementType().getSizeInBits())
7340 VShiftOpc = ARMISD::VSHLLi;
7342 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
7343 ARMISD::VSHLLs : ARMISD::VSHLLu);
7345 case Intrinsic::arm_neon_vshiftn:
7346 VShiftOpc = ARMISD::VSHRN; break;
7347 case Intrinsic::arm_neon_vrshifts:
7348 VShiftOpc = ARMISD::VRSHRs; break;
7349 case Intrinsic::arm_neon_vrshiftu:
7350 VShiftOpc = ARMISD::VRSHRu; break;
7351 case Intrinsic::arm_neon_vrshiftn:
7352 VShiftOpc = ARMISD::VRSHRN; break;
7353 case Intrinsic::arm_neon_vqshifts:
7354 VShiftOpc = ARMISD::VQSHLs; break;
7355 case Intrinsic::arm_neon_vqshiftu:
7356 VShiftOpc = ARMISD::VQSHLu; break;
7357 case Intrinsic::arm_neon_vqshiftsu:
7358 VShiftOpc = ARMISD::VQSHLsu; break;
7359 case Intrinsic::arm_neon_vqshiftns:
7360 VShiftOpc = ARMISD::VQSHRNs; break;
7361 case Intrinsic::arm_neon_vqshiftnu:
7362 VShiftOpc = ARMISD::VQSHRNu; break;
7363 case Intrinsic::arm_neon_vqshiftnsu:
7364 VShiftOpc = ARMISD::VQSHRNsu; break;
7365 case Intrinsic::arm_neon_vqrshiftns:
7366 VShiftOpc = ARMISD::VQRSHRNs; break;
7367 case Intrinsic::arm_neon_vqrshiftnu:
7368 VShiftOpc = ARMISD::VQRSHRNu; break;
7369 case Intrinsic::arm_neon_vqrshiftnsu:
7370 VShiftOpc = ARMISD::VQRSHRNsu; break;
7373 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
7374 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
7377 case Intrinsic::arm_neon_vshiftins: {
7378 EVT VT = N->getOperand(1).getValueType();
7380 unsigned VShiftOpc = 0;
7382 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
7383 VShiftOpc = ARMISD::VSLI;
7384 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
7385 VShiftOpc = ARMISD::VSRI;
7387 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
7390 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
7391 N->getOperand(1), N->getOperand(2),
7392 DAG.getConstant(Cnt, MVT::i32));
7395 case Intrinsic::arm_neon_vqrshifts:
7396 case Intrinsic::arm_neon_vqrshiftu:
7397 // No immediate versions of these to check for.
7404 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
7405 /// lowers them. As with the vector shift intrinsics, this is done during DAG
7406 /// combining instead of DAG legalizing because the build_vectors for 64-bit
7407 /// vector element shift counts are generally not legal, and it is hard to see
7408 /// their values after they get legalized to loads from a constant pool.
7409 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
7410 const ARMSubtarget *ST) {
7411 EVT VT = N->getValueType(0);
7413 // Nothing to be done for scalar shifts.
7414 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7415 if (!VT.isVector() || !TLI.isTypeLegal(VT))
7418 assert(ST->hasNEON() && "unexpected vector shift");
7421 switch (N->getOpcode()) {
7422 default: llvm_unreachable("unexpected shift opcode");
7425 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
7426 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
7427 DAG.getConstant(Cnt, MVT::i32));
7432 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
7433 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
7434 ARMISD::VSHRs : ARMISD::VSHRu);
7435 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
7436 DAG.getConstant(Cnt, MVT::i32));
7442 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
7443 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
7444 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
7445 const ARMSubtarget *ST) {
7446 SDValue N0 = N->getOperand(0);
7448 // Check for sign- and zero-extensions of vector extract operations of 8-
7449 // and 16-bit vector elements. NEON supports these directly. They are
7450 // handled during DAG combining because type legalization will promote them
7451 // to 32-bit types and it is messy to recognize the operations after that.
7452 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7453 SDValue Vec = N0.getOperand(0);
7454 SDValue Lane = N0.getOperand(1);
7455 EVT VT = N->getValueType(0);
7456 EVT EltVT = N0.getValueType();
7457 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7459 if (VT == MVT::i32 &&
7460 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
7461 TLI.isTypeLegal(Vec.getValueType()) &&
7462 isa<ConstantSDNode>(Lane)) {
7465 switch (N->getOpcode()) {
7466 default: llvm_unreachable("unexpected opcode");
7467 case ISD::SIGN_EXTEND:
7468 Opc = ARMISD::VGETLANEs;
7470 case ISD::ZERO_EXTEND:
7471 case ISD::ANY_EXTEND:
7472 Opc = ARMISD::VGETLANEu;
7475 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
7482 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
7483 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
7484 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
7485 const ARMSubtarget *ST) {
7486 // If the target supports NEON, try to use vmax/vmin instructions for f32
7487 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
7488 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
7489 // a NaN; only do the transformation when it matches that behavior.
7491 // For now only do this when using NEON for FP operations; if using VFP, it
7492 // is not obvious that the benefit outweighs the cost of switching to the
7494 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
7495 N->getValueType(0) != MVT::f32)
7498 SDValue CondLHS = N->getOperand(0);
7499 SDValue CondRHS = N->getOperand(1);
7500 SDValue LHS = N->getOperand(2);
7501 SDValue RHS = N->getOperand(3);
7502 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
7504 unsigned Opcode = 0;
7506 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
7507 IsReversed = false; // x CC y ? x : y
7508 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
7509 IsReversed = true ; // x CC y ? y : x
7523 // If LHS is NaN, an ordered comparison will be false and the result will
7524 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
7525 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
7526 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
7527 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
7529 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
7530 // will return -0, so vmin can only be used for unsafe math or if one of
7531 // the operands is known to be nonzero.
7532 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
7534 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
7536 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
7545 // If LHS is NaN, an ordered comparison will be false and the result will
7546 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
7547 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
7548 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
7549 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
7551 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
7552 // will return +0, so vmax can only be used for unsafe math or if one of
7553 // the operands is known to be nonzero.
7554 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
7556 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
7558 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
7564 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
7567 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
7569 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
7570 SDValue Cmp = N->getOperand(4);
7571 if (Cmp.getOpcode() != ARMISD::CMPZ)
7572 // Only looking at EQ and NE cases.
7575 EVT VT = N->getValueType(0);
7576 DebugLoc dl = N->getDebugLoc();
7577 SDValue LHS = Cmp.getOperand(0);
7578 SDValue RHS = Cmp.getOperand(1);
7579 SDValue FalseVal = N->getOperand(0);
7580 SDValue TrueVal = N->getOperand(1);
7581 SDValue ARMcc = N->getOperand(2);
7582 ARMCC::CondCodes CC =
7583 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
7601 /// FIXME: Turn this into a target neutral optimization?
7603 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
7604 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
7605 N->getOperand(3), Cmp);
7606 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
7608 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
7609 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
7610 N->getOperand(3), NewCmp);
7613 if (Res.getNode()) {
7614 APInt KnownZero, KnownOne;
7615 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
7616 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne);
7617 // Capture demanded bits information that would be otherwise lost.
7618 if (KnownZero == 0xfffffffe)
7619 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7620 DAG.getValueType(MVT::i1));
7621 else if (KnownZero == 0xffffff00)
7622 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7623 DAG.getValueType(MVT::i8));
7624 else if (KnownZero == 0xffff0000)
7625 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7626 DAG.getValueType(MVT::i16));
7632 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
7633 DAGCombinerInfo &DCI) const {
7634 switch (N->getOpcode()) {
7636 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
7637 case ISD::SUB: return PerformSUBCombine(N, DCI);
7638 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
7639 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
7640 case ISD::AND: return PerformANDCombine(N, DCI);
7641 case ARMISD::BFI: return PerformBFICombine(N, DCI);
7642 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
7643 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
7644 case ISD::STORE: return PerformSTORECombine(N, DCI);
7645 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
7646 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
7647 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
7648 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
7649 case ISD::FP_TO_SINT:
7650 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
7651 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
7652 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
7655 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
7656 case ISD::SIGN_EXTEND:
7657 case ISD::ZERO_EXTEND:
7658 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
7659 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
7660 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
7661 case ARMISD::VLD2DUP:
7662 case ARMISD::VLD3DUP:
7663 case ARMISD::VLD4DUP:
7664 return CombineBaseUpdate(N, DCI);
7665 case ISD::INTRINSIC_VOID:
7666 case ISD::INTRINSIC_W_CHAIN:
7667 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7668 case Intrinsic::arm_neon_vld1:
7669 case Intrinsic::arm_neon_vld2:
7670 case Intrinsic::arm_neon_vld3:
7671 case Intrinsic::arm_neon_vld4:
7672 case Intrinsic::arm_neon_vld2lane:
7673 case Intrinsic::arm_neon_vld3lane:
7674 case Intrinsic::arm_neon_vld4lane:
7675 case Intrinsic::arm_neon_vst1:
7676 case Intrinsic::arm_neon_vst2:
7677 case Intrinsic::arm_neon_vst3:
7678 case Intrinsic::arm_neon_vst4:
7679 case Intrinsic::arm_neon_vst2lane:
7680 case Intrinsic::arm_neon_vst3lane:
7681 case Intrinsic::arm_neon_vst4lane:
7682 return CombineBaseUpdate(N, DCI);
7690 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
7692 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
7695 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
7696 if (!Subtarget->allowsUnalignedMem())
7699 switch (VT.getSimpleVT().SimpleTy) {
7706 // FIXME: VLD1 etc with standard alignment is legal.
7710 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
7715 switch (VT.getSimpleVT().SimpleTy) {
7716 default: return false;
7731 if ((V & (Scale - 1)) != 0)
7734 return V == (V & ((1LL << 5) - 1));
7737 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
7738 const ARMSubtarget *Subtarget) {
7745 switch (VT.getSimpleVT().SimpleTy) {
7746 default: return false;
7751 // + imm12 or - imm8
7753 return V == (V & ((1LL << 8) - 1));
7754 return V == (V & ((1LL << 12) - 1));
7757 // Same as ARM mode. FIXME: NEON?
7758 if (!Subtarget->hasVFP2())
7763 return V == (V & ((1LL << 8) - 1));
7767 /// isLegalAddressImmediate - Return true if the integer value can be used
7768 /// as the offset of the target addressing mode for load / store of the
7770 static bool isLegalAddressImmediate(int64_t V, EVT VT,
7771 const ARMSubtarget *Subtarget) {
7778 if (Subtarget->isThumb1Only())
7779 return isLegalT1AddressImmediate(V, VT);
7780 else if (Subtarget->isThumb2())
7781 return isLegalT2AddressImmediate(V, VT, Subtarget);
7786 switch (VT.getSimpleVT().SimpleTy) {
7787 default: return false;
7792 return V == (V & ((1LL << 12) - 1));
7795 return V == (V & ((1LL << 8) - 1));
7798 if (!Subtarget->hasVFP2()) // FIXME: NEON?
7803 return V == (V & ((1LL << 8) - 1));
7807 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
7809 int Scale = AM.Scale;
7813 switch (VT.getSimpleVT().SimpleTy) {
7814 default: return false;
7823 return Scale == 2 || Scale == 4 || Scale == 8;
7826 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
7830 // Note, we allow "void" uses (basically, uses that aren't loads or
7831 // stores), because arm allows folding a scale into many arithmetic
7832 // operations. This should be made more precise and revisited later.
7834 // Allow r << imm, but the imm has to be a multiple of two.
7835 if (Scale & 1) return false;
7836 return isPowerOf2_32(Scale);
7840 /// isLegalAddressingMode - Return true if the addressing mode represented
7841 /// by AM is legal for this target, for a load/store of the specified type.
7842 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7844 EVT VT = getValueType(Ty, true);
7845 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
7848 // Can never fold addr of global into load/store.
7853 case 0: // no scale reg, must be "r+i" or "r", or "i".
7856 if (Subtarget->isThumb1Only())
7860 // ARM doesn't support any R+R*scale+imm addr modes.
7867 if (Subtarget->isThumb2())
7868 return isLegalT2ScaledAddressingMode(AM, VT);
7870 int Scale = AM.Scale;
7871 switch (VT.getSimpleVT().SimpleTy) {
7872 default: return false;
7876 if (Scale < 0) Scale = -Scale;
7880 return isPowerOf2_32(Scale & ~1);
7884 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
7889 // Note, we allow "void" uses (basically, uses that aren't loads or
7890 // stores), because arm allows folding a scale into many arithmetic
7891 // operations. This should be made more precise and revisited later.
7893 // Allow r << imm, but the imm has to be a multiple of two.
7894 if (Scale & 1) return false;
7895 return isPowerOf2_32(Scale);
7902 /// isLegalICmpImmediate - Return true if the specified immediate is legal
7903 /// icmp immediate, that is the target has icmp instructions which can compare
7904 /// a register against the immediate without having to materialize the
7905 /// immediate into a register.
7906 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
7907 if (!Subtarget->isThumb())
7908 return ARM_AM::getSOImmVal(Imm) != -1;
7909 if (Subtarget->isThumb2())
7910 return ARM_AM::getT2SOImmVal(Imm) != -1;
7911 return Imm >= 0 && Imm <= 255;
7914 /// isLegalAddImmediate - Return true if the specified immediate is legal
7915 /// add immediate, that is the target has add instructions which can add
7916 /// a register with the immediate without having to materialize the
7917 /// immediate into a register.
7918 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
7919 return ARM_AM::getSOImmVal(Imm) != -1;
7922 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
7923 bool isSEXTLoad, SDValue &Base,
7924 SDValue &Offset, bool &isInc,
7925 SelectionDAG &DAG) {
7926 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
7929 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
7931 Base = Ptr->getOperand(0);
7932 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7933 int RHSC = (int)RHS->getZExtValue();
7934 if (RHSC < 0 && RHSC > -256) {
7935 assert(Ptr->getOpcode() == ISD::ADD);
7937 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7941 isInc = (Ptr->getOpcode() == ISD::ADD);
7942 Offset = Ptr->getOperand(1);
7944 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
7946 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7947 int RHSC = (int)RHS->getZExtValue();
7948 if (RHSC < 0 && RHSC > -0x1000) {
7949 assert(Ptr->getOpcode() == ISD::ADD);
7951 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7952 Base = Ptr->getOperand(0);
7957 if (Ptr->getOpcode() == ISD::ADD) {
7959 ARM_AM::ShiftOpc ShOpcVal=
7960 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
7961 if (ShOpcVal != ARM_AM::no_shift) {
7962 Base = Ptr->getOperand(1);
7963 Offset = Ptr->getOperand(0);
7965 Base = Ptr->getOperand(0);
7966 Offset = Ptr->getOperand(1);
7971 isInc = (Ptr->getOpcode() == ISD::ADD);
7972 Base = Ptr->getOperand(0);
7973 Offset = Ptr->getOperand(1);
7977 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
7981 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
7982 bool isSEXTLoad, SDValue &Base,
7983 SDValue &Offset, bool &isInc,
7984 SelectionDAG &DAG) {
7985 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
7988 Base = Ptr->getOperand(0);
7989 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7990 int RHSC = (int)RHS->getZExtValue();
7991 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
7992 assert(Ptr->getOpcode() == ISD::ADD);
7994 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7996 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
7997 isInc = Ptr->getOpcode() == ISD::ADD;
7998 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
8006 /// getPreIndexedAddressParts - returns true by value, base pointer and
8007 /// offset pointer and addressing mode by reference if the node's address
8008 /// can be legally represented as pre-indexed load / store address.
8010 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8012 ISD::MemIndexedMode &AM,
8013 SelectionDAG &DAG) const {
8014 if (Subtarget->isThumb1Only())
8019 bool isSEXTLoad = false;
8020 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8021 Ptr = LD->getBasePtr();
8022 VT = LD->getMemoryVT();
8023 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
8024 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8025 Ptr = ST->getBasePtr();
8026 VT = ST->getMemoryVT();
8031 bool isLegal = false;
8032 if (Subtarget->isThumb2())
8033 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
8034 Offset, isInc, DAG);
8036 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
8037 Offset, isInc, DAG);
8041 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
8045 /// getPostIndexedAddressParts - returns true by value, base pointer and
8046 /// offset pointer and addressing mode by reference if this node can be
8047 /// combined with a load / store to form a post-indexed load / store.
8048 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
8051 ISD::MemIndexedMode &AM,
8052 SelectionDAG &DAG) const {
8053 if (Subtarget->isThumb1Only())
8058 bool isSEXTLoad = false;
8059 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8060 VT = LD->getMemoryVT();
8061 Ptr = LD->getBasePtr();
8062 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
8063 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8064 VT = ST->getMemoryVT();
8065 Ptr = ST->getBasePtr();
8070 bool isLegal = false;
8071 if (Subtarget->isThumb2())
8072 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
8075 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
8081 // Swap base ptr and offset to catch more post-index load / store when
8082 // it's legal. In Thumb2 mode, offset must be an immediate.
8083 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
8084 !Subtarget->isThumb2())
8085 std::swap(Base, Offset);
8087 // Post-indexed load / store update the base pointer.
8092 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
8096 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8100 const SelectionDAG &DAG,
8101 unsigned Depth) const {
8102 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
8103 switch (Op.getOpcode()) {
8105 case ARMISD::CMOV: {
8106 // Bits are known zero/one if known on the LHS and RHS.
8107 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
8108 if (KnownZero == 0 && KnownOne == 0) return;
8110 APInt KnownZeroRHS, KnownOneRHS;
8111 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
8112 KnownZeroRHS, KnownOneRHS, Depth+1);
8113 KnownZero &= KnownZeroRHS;
8114 KnownOne &= KnownOneRHS;
8120 //===----------------------------------------------------------------------===//
8121 // ARM Inline Assembly Support
8122 //===----------------------------------------------------------------------===//
8124 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
8125 // Looking for "rev" which is V6+.
8126 if (!Subtarget->hasV6Ops())
8129 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
8130 std::string AsmStr = IA->getAsmString();
8131 SmallVector<StringRef, 4> AsmPieces;
8132 SplitString(AsmStr, AsmPieces, ";\n");
8134 switch (AsmPieces.size()) {
8135 default: return false;
8137 AsmStr = AsmPieces[0];
8139 SplitString(AsmStr, AsmPieces, " \t,");
8142 if (AsmPieces.size() == 3 &&
8143 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
8144 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
8145 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
8146 if (Ty && Ty->getBitWidth() == 32)
8147 return IntrinsicLowering::LowerToByteSwap(CI);
8155 /// getConstraintType - Given a constraint letter, return the type of
8156 /// constraint it is for this target.
8157 ARMTargetLowering::ConstraintType
8158 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
8159 if (Constraint.size() == 1) {
8160 switch (Constraint[0]) {
8162 case 'l': return C_RegisterClass;
8163 case 'w': return C_RegisterClass;
8164 case 'h': return C_RegisterClass;
8165 case 'x': return C_RegisterClass;
8166 case 't': return C_RegisterClass;
8167 case 'j': return C_Other; // Constant for movw.
8168 // An address with a single base register. Due to the way we
8169 // currently handle addresses it is the same as an 'r' memory constraint.
8170 case 'Q': return C_Memory;
8172 } else if (Constraint.size() == 2) {
8173 switch (Constraint[0]) {
8175 // All 'U+' constraints are addresses.
8176 case 'U': return C_Memory;
8179 return TargetLowering::getConstraintType(Constraint);
8182 /// Examine constraint type and operand type and determine a weight value.
8183 /// This object must already have been set up with the operand type
8184 /// and the current alternative constraint selected.
8185 TargetLowering::ConstraintWeight
8186 ARMTargetLowering::getSingleConstraintMatchWeight(
8187 AsmOperandInfo &info, const char *constraint) const {
8188 ConstraintWeight weight = CW_Invalid;
8189 Value *CallOperandVal = info.CallOperandVal;
8190 // If we don't have a value, we can't do a match,
8191 // but allow it at the lowest weight.
8192 if (CallOperandVal == NULL)
8194 Type *type = CallOperandVal->getType();
8195 // Look at the constraint type.
8196 switch (*constraint) {
8198 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8201 if (type->isIntegerTy()) {
8202 if (Subtarget->isThumb())
8203 weight = CW_SpecificReg;
8205 weight = CW_Register;
8209 if (type->isFloatingPointTy())
8210 weight = CW_Register;
8216 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
8218 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8220 if (Constraint.size() == 1) {
8221 // GCC ARM Constraint Letters
8222 switch (Constraint[0]) {
8223 case 'l': // Low regs or general regs.
8224 if (Subtarget->isThumb())
8225 return RCPair(0U, ARM::tGPRRegisterClass);
8227 return RCPair(0U, ARM::GPRRegisterClass);
8228 case 'h': // High regs or no regs.
8229 if (Subtarget->isThumb())
8230 return RCPair(0U, ARM::hGPRRegisterClass);
8233 return RCPair(0U, ARM::GPRRegisterClass);
8236 return RCPair(0U, ARM::SPRRegisterClass);
8237 if (VT.getSizeInBits() == 64)
8238 return RCPair(0U, ARM::DPRRegisterClass);
8239 if (VT.getSizeInBits() == 128)
8240 return RCPair(0U, ARM::QPRRegisterClass);
8244 return RCPair(0U, ARM::SPR_8RegisterClass);
8245 if (VT.getSizeInBits() == 64)
8246 return RCPair(0U, ARM::DPR_8RegisterClass);
8247 if (VT.getSizeInBits() == 128)
8248 return RCPair(0U, ARM::QPR_8RegisterClass);
8252 return RCPair(0U, ARM::SPRRegisterClass);
8256 if (StringRef("{cc}").equals_lower(Constraint))
8257 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
8259 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8262 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8263 /// vector. If it is invalid, don't add anything to Ops.
8264 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8265 std::string &Constraint,
8266 std::vector<SDValue>&Ops,
8267 SelectionDAG &DAG) const {
8268 SDValue Result(0, 0);
8270 // Currently only support length 1 constraints.
8271 if (Constraint.length() != 1) return;
8273 char ConstraintLetter = Constraint[0];
8274 switch (ConstraintLetter) {
8277 case 'I': case 'J': case 'K': case 'L':
8278 case 'M': case 'N': case 'O':
8279 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
8283 int64_t CVal64 = C->getSExtValue();
8284 int CVal = (int) CVal64;
8285 // None of these constraints allow values larger than 32 bits. Check
8286 // that the value fits in an int.
8290 switch (ConstraintLetter) {
8292 // Constant suitable for movw, must be between 0 and
8294 if (Subtarget->hasV6T2Ops())
8295 if (CVal >= 0 && CVal <= 65535)
8299 if (Subtarget->isThumb1Only()) {
8300 // This must be a constant between 0 and 255, for ADD
8302 if (CVal >= 0 && CVal <= 255)
8304 } else if (Subtarget->isThumb2()) {
8305 // A constant that can be used as an immediate value in a
8306 // data-processing instruction.
8307 if (ARM_AM::getT2SOImmVal(CVal) != -1)
8310 // A constant that can be used as an immediate value in a
8311 // data-processing instruction.
8312 if (ARM_AM::getSOImmVal(CVal) != -1)
8318 if (Subtarget->isThumb()) { // FIXME thumb2
8319 // This must be a constant between -255 and -1, for negated ADD
8320 // immediates. This can be used in GCC with an "n" modifier that
8321 // prints the negated value, for use with SUB instructions. It is
8322 // not useful otherwise but is implemented for compatibility.
8323 if (CVal >= -255 && CVal <= -1)
8326 // This must be a constant between -4095 and 4095. It is not clear
8327 // what this constraint is intended for. Implemented for
8328 // compatibility with GCC.
8329 if (CVal >= -4095 && CVal <= 4095)
8335 if (Subtarget->isThumb1Only()) {
8336 // A 32-bit value where only one byte has a nonzero value. Exclude
8337 // zero to match GCC. This constraint is used by GCC internally for
8338 // constants that can be loaded with a move/shift combination.
8339 // It is not useful otherwise but is implemented for compatibility.
8340 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
8342 } else if (Subtarget->isThumb2()) {
8343 // A constant whose bitwise inverse can be used as an immediate
8344 // value in a data-processing instruction. This can be used in GCC
8345 // with a "B" modifier that prints the inverted value, for use with
8346 // BIC and MVN instructions. It is not useful otherwise but is
8347 // implemented for compatibility.
8348 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
8351 // A constant whose bitwise inverse can be used as an immediate
8352 // value in a data-processing instruction. This can be used in GCC
8353 // with a "B" modifier that prints the inverted value, for use with
8354 // BIC and MVN instructions. It is not useful otherwise but is
8355 // implemented for compatibility.
8356 if (ARM_AM::getSOImmVal(~CVal) != -1)
8362 if (Subtarget->isThumb1Only()) {
8363 // This must be a constant between -7 and 7,
8364 // for 3-operand ADD/SUB immediate instructions.
8365 if (CVal >= -7 && CVal < 7)
8367 } else if (Subtarget->isThumb2()) {
8368 // A constant whose negation can be used as an immediate value in a
8369 // data-processing instruction. This can be used in GCC with an "n"
8370 // modifier that prints the negated value, for use with SUB
8371 // instructions. It is not useful otherwise but is implemented for
8373 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
8376 // A constant whose negation can be used as an immediate value in a
8377 // data-processing instruction. This can be used in GCC with an "n"
8378 // modifier that prints the negated value, for use with SUB
8379 // instructions. It is not useful otherwise but is implemented for
8381 if (ARM_AM::getSOImmVal(-CVal) != -1)
8387 if (Subtarget->isThumb()) { // FIXME thumb2
8388 // This must be a multiple of 4 between 0 and 1020, for
8389 // ADD sp + immediate.
8390 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
8393 // A power of two or a constant between 0 and 32. This is used in
8394 // GCC for the shift amount on shifted register operands, but it is
8395 // useful in general for any shift amounts.
8396 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
8402 if (Subtarget->isThumb()) { // FIXME thumb2
8403 // This must be a constant between 0 and 31, for shift amounts.
8404 if (CVal >= 0 && CVal <= 31)
8410 if (Subtarget->isThumb()) { // FIXME thumb2
8411 // This must be a multiple of 4 between -508 and 508, for
8412 // ADD/SUB sp = sp + immediate.
8413 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
8418 Result = DAG.getTargetConstant(CVal, Op.getValueType());
8422 if (Result.getNode()) {
8423 Ops.push_back(Result);
8426 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8430 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8431 // The ARM target isn't yet aware of offsets.
8435 bool ARM::isBitFieldInvertedMask(unsigned v) {
8436 if (v == 0xffffffff)
8438 // there can be 1's on either or both "outsides", all the "inside"
8440 unsigned int lsb = 0, msb = 31;
8441 while (v & (1 << msb)) --msb;
8442 while (v & (1 << lsb)) ++lsb;
8443 for (unsigned int i = lsb; i <= msb; ++i) {
8450 /// isFPImmLegal - Returns true if the target can instruction select the
8451 /// specified FP immediate natively. If false, the legalizer will
8452 /// materialize the FP immediate as a load from a constant pool.
8453 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
8454 if (!Subtarget->hasVFP3())
8457 return ARM_AM::getFP32Imm(Imm) != -1;
8459 return ARM_AM::getFP64Imm(Imm) != -1;
8463 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
8464 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
8465 /// specified in the intrinsic calls.
8466 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
8468 unsigned Intrinsic) const {
8469 switch (Intrinsic) {
8470 case Intrinsic::arm_neon_vld1:
8471 case Intrinsic::arm_neon_vld2:
8472 case Intrinsic::arm_neon_vld3:
8473 case Intrinsic::arm_neon_vld4:
8474 case Intrinsic::arm_neon_vld2lane:
8475 case Intrinsic::arm_neon_vld3lane:
8476 case Intrinsic::arm_neon_vld4lane: {
8477 Info.opc = ISD::INTRINSIC_W_CHAIN;
8478 // Conservatively set memVT to the entire set of vectors loaded.
8479 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
8480 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
8481 Info.ptrVal = I.getArgOperand(0);
8483 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
8484 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
8485 Info.vol = false; // volatile loads with NEON intrinsics not supported
8486 Info.readMem = true;
8487 Info.writeMem = false;
8490 case Intrinsic::arm_neon_vst1:
8491 case Intrinsic::arm_neon_vst2:
8492 case Intrinsic::arm_neon_vst3:
8493 case Intrinsic::arm_neon_vst4:
8494 case Intrinsic::arm_neon_vst2lane:
8495 case Intrinsic::arm_neon_vst3lane:
8496 case Intrinsic::arm_neon_vst4lane: {
8497 Info.opc = ISD::INTRINSIC_VOID;
8498 // Conservatively set memVT to the entire set of vectors stored.
8499 unsigned NumElts = 0;
8500 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
8501 Type *ArgTy = I.getArgOperand(ArgI)->getType();
8502 if (!ArgTy->isVectorTy())
8504 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
8506 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
8507 Info.ptrVal = I.getArgOperand(0);
8509 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
8510 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
8511 Info.vol = false; // volatile stores with NEON intrinsics not supported
8512 Info.readMem = false;
8513 Info.writeMem = true;
8516 case Intrinsic::arm_strexd: {
8517 Info.opc = ISD::INTRINSIC_W_CHAIN;
8518 Info.memVT = MVT::i64;
8519 Info.ptrVal = I.getArgOperand(2);
8523 Info.readMem = false;
8524 Info.writeMem = true;
8527 case Intrinsic::arm_ldrexd: {
8528 Info.opc = ISD::INTRINSIC_W_CHAIN;
8529 Info.memVT = MVT::i64;
8530 Info.ptrVal = I.getArgOperand(0);
8534 Info.readMem = true;
8535 Info.writeMem = false;