1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Instruction.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineBasicBlock.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/VectorExtras.h"
39 #include "llvm/Support/MathExtras.h"
42 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
43 CCValAssign::LocInfo &LocInfo,
44 ISD::ArgFlagsTy &ArgFlags,
46 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
50 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
51 CCValAssign::LocInfo &LocInfo,
52 ISD::ArgFlagsTy &ArgFlags,
54 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
55 CCValAssign::LocInfo &LocInfo,
56 ISD::ArgFlagsTy &ArgFlags,
59 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
60 : TargetLowering(TM), ARMPCLabelIndex(0) {
61 Subtarget = &TM.getSubtarget<ARMSubtarget>();
63 if (Subtarget->isTargetDarwin()) {
64 // Uses VFP for Thumb libfuncs if available.
65 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
66 // Single-precision floating-point arithmetic.
67 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
68 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
69 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
70 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
72 // Double-precision floating-point arithmetic.
73 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
74 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
75 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
76 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
78 // Single-precision comparisons.
79 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
80 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
81 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
82 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
83 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
84 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
85 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
86 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
88 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
89 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
90 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
91 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
92 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
93 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
94 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
95 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
97 // Double-precision comparisons.
98 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
99 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
100 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
101 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
102 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
103 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
104 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
105 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
107 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
108 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
109 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
110 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
111 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
112 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
113 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
114 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
116 // Floating-point to integer conversions.
117 // i64 conversions are done via library routines even when generating VFP
118 // instructions, so use the same ones.
119 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
120 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
121 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
122 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
124 // Conversions between floating types.
125 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
126 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
128 // Integer to floating-point conversions.
129 // i64 conversions are done via library routines even when generating VFP
130 // instructions, so use the same ones.
131 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
132 // e.g., __floatunsidf vs. __floatunssidfvfp.
133 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
134 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
135 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
136 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
140 if (Subtarget->isThumb())
141 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
143 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
144 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
145 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
146 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
148 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
150 computeRegisterProperties();
152 // ARM does not have f32 extending load.
153 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
155 // ARM does not have i1 sign extending load.
156 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
158 // ARM supports all 4 flavors of integer indexed load / store.
159 for (unsigned im = (unsigned)ISD::PRE_INC;
160 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
161 setIndexedLoadAction(im, MVT::i1, Legal);
162 setIndexedLoadAction(im, MVT::i8, Legal);
163 setIndexedLoadAction(im, MVT::i16, Legal);
164 setIndexedLoadAction(im, MVT::i32, Legal);
165 setIndexedStoreAction(im, MVT::i1, Legal);
166 setIndexedStoreAction(im, MVT::i8, Legal);
167 setIndexedStoreAction(im, MVT::i16, Legal);
168 setIndexedStoreAction(im, MVT::i32, Legal);
171 // i64 operation support.
172 if (Subtarget->isThumb()) {
173 setOperationAction(ISD::MUL, MVT::i64, Expand);
174 setOperationAction(ISD::MULHU, MVT::i32, Expand);
175 setOperationAction(ISD::MULHS, MVT::i32, Expand);
176 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
177 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
179 setOperationAction(ISD::MUL, MVT::i64, Expand);
180 setOperationAction(ISD::MULHU, MVT::i32, Expand);
181 if (!Subtarget->hasV6Ops())
182 setOperationAction(ISD::MULHS, MVT::i32, Expand);
184 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
185 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
186 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
187 setOperationAction(ISD::SRL, MVT::i64, Custom);
188 setOperationAction(ISD::SRA, MVT::i64, Custom);
190 // ARM does not have ROTL.
191 setOperationAction(ISD::ROTL, MVT::i32, Expand);
192 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
193 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
194 if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
195 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
197 // Only ARMv6 has BSWAP.
198 if (!Subtarget->hasV6Ops())
199 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
201 // These are expanded into libcalls.
202 setOperationAction(ISD::SDIV, MVT::i32, Expand);
203 setOperationAction(ISD::UDIV, MVT::i32, Expand);
204 setOperationAction(ISD::SREM, MVT::i32, Expand);
205 setOperationAction(ISD::UREM, MVT::i32, Expand);
206 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
207 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
209 // Support label based line numbers.
210 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
211 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
213 setOperationAction(ISD::RET, MVT::Other, Custom);
214 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
215 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
216 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
217 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
219 // Use the default implementation.
220 setOperationAction(ISD::VASTART, MVT::Other, Custom);
221 setOperationAction(ISD::VAARG, MVT::Other, Expand);
222 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
223 setOperationAction(ISD::VAEND, MVT::Other, Expand);
224 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
225 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
226 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
227 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
229 if (!Subtarget->hasV6Ops()) {
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
233 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
235 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
236 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
237 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
239 // We want to custom lower some of our intrinsics.
240 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
242 setOperationAction(ISD::SETCC, MVT::i32, Expand);
243 setOperationAction(ISD::SETCC, MVT::f32, Expand);
244 setOperationAction(ISD::SETCC, MVT::f64, Expand);
245 setOperationAction(ISD::SELECT, MVT::i32, Expand);
246 setOperationAction(ISD::SELECT, MVT::f32, Expand);
247 setOperationAction(ISD::SELECT, MVT::f64, Expand);
248 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
249 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
250 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
252 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
253 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
254 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
255 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
256 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
258 // We don't support sin/cos/fmod/copysign/pow
259 setOperationAction(ISD::FSIN, MVT::f64, Expand);
260 setOperationAction(ISD::FSIN, MVT::f32, Expand);
261 setOperationAction(ISD::FCOS, MVT::f32, Expand);
262 setOperationAction(ISD::FCOS, MVT::f64, Expand);
263 setOperationAction(ISD::FREM, MVT::f64, Expand);
264 setOperationAction(ISD::FREM, MVT::f32, Expand);
265 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
266 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
267 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
269 setOperationAction(ISD::FPOW, MVT::f64, Expand);
270 setOperationAction(ISD::FPOW, MVT::f32, Expand);
272 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
273 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
274 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
275 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
276 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
277 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
280 // We have target-specific dag combine patterns for the following nodes:
281 // ARMISD::FMRRD - No need to call setTargetDAGCombine
282 setTargetDAGCombine(ISD::ADD);
283 setTargetDAGCombine(ISD::SUB);
285 setStackPointerRegisterToSaveRestore(ARM::SP);
286 setSchedulingPreference(SchedulingForRegPressure);
287 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
288 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
290 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
293 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
296 case ARMISD::Wrapper: return "ARMISD::Wrapper";
297 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
298 case ARMISD::CALL: return "ARMISD::CALL";
299 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
300 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
301 case ARMISD::tCALL: return "ARMISD::tCALL";
302 case ARMISD::BRCOND: return "ARMISD::BRCOND";
303 case ARMISD::BR_JT: return "ARMISD::BR_JT";
304 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
305 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
306 case ARMISD::CMP: return "ARMISD::CMP";
307 case ARMISD::CMPNZ: return "ARMISD::CMPNZ";
308 case ARMISD::CMPFP: return "ARMISD::CMPFP";
309 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
310 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
311 case ARMISD::CMOV: return "ARMISD::CMOV";
312 case ARMISD::CNEG: return "ARMISD::CNEG";
314 case ARMISD::FTOSI: return "ARMISD::FTOSI";
315 case ARMISD::FTOUI: return "ARMISD::FTOUI";
316 case ARMISD::SITOF: return "ARMISD::SITOF";
317 case ARMISD::UITOF: return "ARMISD::UITOF";
319 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
320 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
321 case ARMISD::RRX: return "ARMISD::RRX";
323 case ARMISD::FMRRD: return "ARMISD::FMRRD";
324 case ARMISD::FMDRR: return "ARMISD::FMDRR";
326 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
330 //===----------------------------------------------------------------------===//
332 //===----------------------------------------------------------------------===//
334 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
335 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
337 default: assert(0 && "Unknown condition code!");
338 case ISD::SETNE: return ARMCC::NE;
339 case ISD::SETEQ: return ARMCC::EQ;
340 case ISD::SETGT: return ARMCC::GT;
341 case ISD::SETGE: return ARMCC::GE;
342 case ISD::SETLT: return ARMCC::LT;
343 case ISD::SETLE: return ARMCC::LE;
344 case ISD::SETUGT: return ARMCC::HI;
345 case ISD::SETUGE: return ARMCC::HS;
346 case ISD::SETULT: return ARMCC::LO;
347 case ISD::SETULE: return ARMCC::LS;
351 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
352 /// returns true if the operands should be inverted to form the proper
354 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
355 ARMCC::CondCodes &CondCode2) {
357 CondCode2 = ARMCC::AL;
359 default: assert(0 && "Unknown FP condition!");
361 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
363 case ISD::SETOGT: CondCode = ARMCC::GT; break;
365 case ISD::SETOGE: CondCode = ARMCC::GE; break;
366 case ISD::SETOLT: CondCode = ARMCC::MI; break;
367 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
368 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
369 case ISD::SETO: CondCode = ARMCC::VC; break;
370 case ISD::SETUO: CondCode = ARMCC::VS; break;
371 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
372 case ISD::SETUGT: CondCode = ARMCC::HI; break;
373 case ISD::SETUGE: CondCode = ARMCC::PL; break;
375 case ISD::SETULT: CondCode = ARMCC::LT; break;
377 case ISD::SETULE: CondCode = ARMCC::LE; break;
379 case ISD::SETUNE: CondCode = ARMCC::NE; break;
384 //===----------------------------------------------------------------------===//
385 // Calling Convention Implementation
387 // The lower operations present on calling convention works on this order:
388 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
389 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
390 // LowerRET (virt regs --> phys regs)
391 // LowerCALL (phys regs --> virt regs)
393 //===----------------------------------------------------------------------===//
395 #include "ARMGenCallingConv.inc"
397 // APCS f64 is in register pairs, possibly split to stack
398 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
399 CCValAssign::LocInfo &LocInfo,
400 ISD::ArgFlagsTy &ArgFlags,
402 static const unsigned HiRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
403 static const unsigned LoRegList[] = { ARM::R1,
408 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 4);
410 return false; // we didn't handle it
413 for (i = 0; i < 4; ++i)
414 if (HiRegList[i] == Reg)
417 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
418 if (LoRegList[i] != ARM::NoRegister)
419 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
422 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
423 State.AllocateStack(4, 4),
425 return true; // we handled it
428 // AAPCS f64 is in aligned register pairs
429 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
430 CCValAssign::LocInfo &LocInfo,
431 ISD::ArgFlagsTy &ArgFlags,
433 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
434 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
436 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
438 return false; // we didn't handle it
441 for (i = 0; i < 2; ++i)
442 if (HiRegList[i] == Reg)
445 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
446 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
448 return true; // we handled it
451 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
452 CCValAssign::LocInfo &LocInfo,
453 ISD::ArgFlagsTy &ArgFlags,
455 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
456 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
458 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
460 return false; // we didn't handle it
463 for (i = 0; i < 2; ++i)
464 if (HiRegList[i] == Reg)
467 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
468 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
470 return true; // we handled it
473 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
474 CCValAssign::LocInfo &LocInfo,
475 ISD::ArgFlagsTy &ArgFlags,
477 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
481 /// AddLiveIn - This helper function adds the specified physical register to the
482 /// MachineFunction as a live in value. It also creates a corresponding virtual
484 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
485 const TargetRegisterClass *RC) {
486 assert(RC->contains(PReg) && "Not the correct regclass!");
487 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
488 MF.getRegInfo().addLiveIn(PReg, VReg);
492 /// LowerCallResult - Lower the result values of an ISD::CALL into the
493 /// appropriate copies out of appropriate physical registers. This assumes that
494 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
495 /// being lowered. The returns a SDNode with the same number of values as the
497 SDNode *ARMTargetLowering::
498 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
499 unsigned CallingConv, SelectionDAG &DAG) {
501 DebugLoc dl = TheCall->getDebugLoc();
502 // Assign locations to each value returned by this call.
503 SmallVector<CCValAssign, 16> RVLocs;
504 bool isVarArg = TheCall->isVarArg();
505 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
506 CCInfo.AnalyzeCallResult(TheCall, RetCC_ARM);
508 SmallVector<SDValue, 8> ResultVals;
510 // Copy all of the result registers out of their specified physreg.
511 for (unsigned i = 0; i != RVLocs.size(); ++i) {
512 CCValAssign VA = RVLocs[i];
514 // handle f64 as custom
515 if (VA.needsCustom()) {
516 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
518 VA = RVLocs[++i]; // skip ahead to next loc
519 SDValue Hi = DAG.getCopyFromReg(Lo, dl, VA.getLocReg(), VA.getLocVT(),
521 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, dl, VA.getValVT(), Lo,
524 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
526 SDValue Val = Chain.getValue(0);
527 InFlag = Chain.getValue(2);
529 switch (VA.getLocInfo()) {
530 default: assert(0 && "Unknown loc info!");
531 case CCValAssign::Full: break;
532 case CCValAssign::BCvt:
533 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(),
538 ResultVals.push_back(Val);
542 // Merge everything together with a MERGE_VALUES node.
543 ResultVals.push_back(Chain);
544 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
545 &ResultVals[0], ResultVals.size()).getNode();
548 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
549 /// by "Src" to address "Dst" of size "Size". Alignment information is
550 /// specified by the specific parameter attribute. The copy will be passed as
551 /// a byval function parameter.
552 /// Sometimes what we are copying is the end of a larger object, the part that
553 /// does not fit in registers.
555 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
556 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
558 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
559 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
560 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
563 /// LowerMemOpCallTo - Store the argument to the stack.
565 ARMTargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
566 const SDValue &StackPtr,
567 const CCValAssign &VA, SDValue Chain,
568 SDValue Arg, ISD::ArgFlagsTy Flags) {
569 DebugLoc dl = TheCall->getDebugLoc();
570 unsigned LocMemOffset = VA.getLocMemOffset();
571 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
572 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
573 if (Flags.isByVal()) {
574 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
576 return DAG.getStore(Chain, dl, Arg, PtrOff,
577 PseudoSourceValue::getStack(), LocMemOffset);
580 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
581 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
583 SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
584 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
585 MVT RetVT = TheCall->getRetValType(0);
586 SDValue Chain = TheCall->getChain();
587 unsigned CC = TheCall->getCallingConv();
588 assert((CC == CallingConv::C ||
589 CC == CallingConv::Fast) && "unknown calling convention");
590 bool isVarArg = TheCall->isVarArg();
591 SDValue Callee = TheCall->getCallee();
592 DebugLoc dl = TheCall->getDebugLoc();
594 // Analyze operands of the call, assigning locations to each operand.
595 SmallVector<CCValAssign, 16> ArgLocs;
596 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
597 CCInfo.AnalyzeCallOperands(TheCall, CC_ARM);
599 // Get a count of how many bytes are to be pushed on the stack.
600 unsigned NumBytes = CCInfo.getNextStackOffset();
602 // Adjust the stack pointer for the new arguments...
603 // These operations are automatically eliminated by the prolog/epilog pass
604 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
606 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
608 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
609 SmallVector<SDValue, 8> MemOpChains;
611 // Walk the register/memloc assignments, inserting copies/loads. In the case
612 // of tail call optimization, arguments are handled later.
613 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
616 CCValAssign &VA = ArgLocs[i];
617 SDValue Arg = TheCall->getArg(realArgIdx);
618 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(realArgIdx);
620 // Promote the value if needed.
621 switch (VA.getLocInfo()) {
622 default: assert(0 && "Unknown loc info!");
623 case CCValAssign::Full: break;
624 case CCValAssign::SExt:
625 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
627 case CCValAssign::ZExt:
628 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
630 case CCValAssign::AExt:
631 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
633 case CCValAssign::BCvt:
634 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
638 // f64 is passed in i32 pairs and must be combined
639 if (VA.needsCustom()) {
640 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
641 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
642 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
643 VA = ArgLocs[++i]; // skip ahead to next loc
645 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(1)));
647 assert(VA.isMemLoc());
648 if (StackPtr.getNode() == 0)
649 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
651 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
652 Chain, fmrrd.getValue(1),
655 } else if (VA.isRegLoc()) {
656 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
658 assert(VA.isMemLoc());
659 if (StackPtr.getNode() == 0)
660 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
662 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
667 if (!MemOpChains.empty())
668 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
669 &MemOpChains[0], MemOpChains.size());
671 // Build a sequence of copy-to-reg nodes chained together with token chain
672 // and flag operands which copy the outgoing args into the appropriate regs.
674 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
675 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
676 RegsToPass[i].second, InFlag);
677 InFlag = Chain.getValue(1);
680 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
681 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
682 // node so that legalize doesn't hack it.
683 bool isDirect = false;
684 bool isARMFunc = false;
685 bool isLocalARMFunc = false;
686 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
687 GlobalValue *GV = G->getGlobal();
689 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
690 GV->hasLinkOnceLinkage());
691 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
692 getTargetMachine().getRelocationModel() != Reloc::Static;
693 isARMFunc = !Subtarget->isThumb() || isStub;
694 // ARM call to a local ARM function is predicable.
695 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
696 // tBX takes a register source operand.
697 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
698 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
700 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
701 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
702 Callee = DAG.getLoad(getPointerTy(), dl,
703 DAG.getEntryNode(), CPAddr, NULL, 0);
704 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
705 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
706 getPointerTy(), Callee, PICLabel);
708 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
709 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
711 bool isStub = Subtarget->isTargetDarwin() &&
712 getTargetMachine().getRelocationModel() != Reloc::Static;
713 isARMFunc = !Subtarget->isThumb() || isStub;
714 // tBX takes a register source operand.
715 const char *Sym = S->getSymbol();
716 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
717 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
719 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
720 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
721 Callee = DAG.getLoad(getPointerTy(), dl,
722 DAG.getEntryNode(), CPAddr, NULL, 0);
723 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
724 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
725 getPointerTy(), Callee, PICLabel);
727 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
730 // FIXME: handle tail calls differently.
732 if (Subtarget->isThumb()) {
733 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
734 CallOpc = ARMISD::CALL_NOLINK;
736 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
738 CallOpc = (isDirect || Subtarget->hasV5TOps())
739 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
740 : ARMISD::CALL_NOLINK;
742 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
743 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
744 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
745 InFlag = Chain.getValue(1);
748 std::vector<SDValue> Ops;
749 Ops.push_back(Chain);
750 Ops.push_back(Callee);
752 // Add argument registers to the end of the list so that they are known live
754 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
755 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
756 RegsToPass[i].second.getValueType()));
758 if (InFlag.getNode())
759 Ops.push_back(InFlag);
760 // Returns a chain and a flag for retval copy to use.
761 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
762 &Ops[0], Ops.size());
763 InFlag = Chain.getValue(1);
765 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
766 DAG.getIntPtrConstant(0, true), InFlag);
767 if (RetVT != MVT::Other)
768 InFlag = Chain.getValue(1);
770 // Handle result values, copying them out of physregs into vregs that we
772 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
776 SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
777 // The chain is always operand #0
778 SDValue Chain = Op.getOperand(0);
779 DebugLoc dl = Op.getDebugLoc();
781 // CCValAssign - represent the assignment of the return value to a location.
782 SmallVector<CCValAssign, 16> RVLocs;
783 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
784 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
786 // CCState - Info about the registers and stack slots.
787 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
789 // Analyze return values of ISD::RET.
790 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_ARM);
792 // If this is the first return lowered for this function, add
793 // the regs to the liveout set for the function.
794 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
795 for (unsigned i = 0; i != RVLocs.size(); ++i)
796 if (RVLocs[i].isRegLoc())
797 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
802 // Copy the result values into the output registers.
803 for (unsigned i = 0, realRVLocIdx = 0;
805 ++i, ++realRVLocIdx) {
806 CCValAssign &VA = RVLocs[i];
807 assert(VA.isRegLoc() && "Can only return in registers!");
809 // ISD::RET => ret chain, (regnum1,val1), ...
810 // So i*2+1 index only the regnums
811 SDValue Arg = Op.getOperand(realRVLocIdx*2+1);
813 switch (VA.getLocInfo()) {
814 default: assert(0 && "Unknown loc info!");
815 case CCValAssign::Full: break;
816 case CCValAssign::BCvt:
817 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
821 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
823 if (VA.needsCustom()) {
824 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
825 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
826 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
827 VA = RVLocs[++i]; // skip ahead to next loc
828 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
831 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
833 // Guarantee that all emitted copies are
834 // stuck together, avoiding something bad.
835 Flag = Chain.getValue(1);
840 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
842 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
847 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
848 // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
849 // one of the above mentioned nodes. It has to be wrapped because otherwise
850 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
851 // be used to form addressing mode. These wrapped nodes will be selected
853 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
854 MVT PtrVT = Op.getValueType();
855 // FIXME there is no actual debug info here
856 DebugLoc dl = Op.getDebugLoc();
857 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
859 if (CP->isMachineConstantPoolEntry())
860 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
863 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
865 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
868 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
870 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
872 DebugLoc dl = GA->getDebugLoc();
873 MVT PtrVT = getPointerTy();
874 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
875 ARMConstantPoolValue *CPV =
876 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
877 PCAdj, "tlsgd", true);
878 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
879 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
880 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
881 SDValue Chain = Argument.getValue(1);
883 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
884 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
886 // call __tls_get_addr.
889 Entry.Node = Argument;
890 Entry.Ty = (const Type *) Type::Int32Ty;
891 Args.push_back(Entry);
892 // FIXME: is there useful debug info available here?
893 std::pair<SDValue, SDValue> CallResult =
894 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
895 CallingConv::C, false,
896 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
897 return CallResult.first;
900 // Lower ISD::GlobalTLSAddress using the "initial exec" or
901 // "local exec" model.
903 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
905 GlobalValue *GV = GA->getGlobal();
906 DebugLoc dl = GA->getDebugLoc();
908 SDValue Chain = DAG.getEntryNode();
909 MVT PtrVT = getPointerTy();
910 // Get the Thread Pointer
911 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
913 if (GV->isDeclaration()){
914 // initial exec model
915 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
916 ARMConstantPoolValue *CPV =
917 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
918 PCAdj, "gottpoff", true);
919 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
920 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
921 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
922 Chain = Offset.getValue(1);
924 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
925 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
927 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
930 ARMConstantPoolValue *CPV =
931 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
932 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
933 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
934 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
937 // The address of the thread local variable is the add of the thread
938 // pointer with the offset of the variable.
939 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
943 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
944 // TODO: implement the "local dynamic" model
945 assert(Subtarget->isTargetELF() &&
946 "TLS not implemented for non-ELF targets");
947 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
948 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
949 // otherwise use the "Local Exec" TLS Model
950 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
951 return LowerToTLSGeneralDynamicModel(GA, DAG);
953 return LowerToTLSExecModels(GA, DAG);
956 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
958 MVT PtrVT = getPointerTy();
959 DebugLoc dl = Op.getDebugLoc();
960 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
961 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
962 if (RelocM == Reloc::PIC_) {
963 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
964 ARMConstantPoolValue *CPV =
965 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
966 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
967 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
968 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
970 SDValue Chain = Result.getValue(1);
971 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
972 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
974 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
977 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
978 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
979 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
983 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
984 /// even in non-static mode.
985 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
986 // If symbol visibility is hidden, the extra load is not needed if
987 // the symbol is definitely defined in the current translation unit.
988 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
989 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
991 return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker());
994 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
996 MVT PtrVT = getPointerTy();
997 DebugLoc dl = Op.getDebugLoc();
998 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
999 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1000 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
1002 if (RelocM == Reloc::Static)
1003 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1005 unsigned PCAdj = (RelocM != Reloc::PIC_)
1006 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1007 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
1009 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
1011 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1013 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1015 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1016 SDValue Chain = Result.getValue(1);
1018 if (RelocM == Reloc::PIC_) {
1019 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1020 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1023 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1028 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1030 assert(Subtarget->isTargetELF() &&
1031 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1032 MVT PtrVT = getPointerTy();
1033 DebugLoc dl = Op.getDebugLoc();
1034 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1035 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
1037 ARMCP::CPValue, PCAdj);
1038 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1039 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1040 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1041 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1042 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1045 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1046 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1047 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1049 default: return SDValue(); // Don't custom lower most intrinsics.
1050 case Intrinsic::arm_thread_pointer:
1051 return DAG.getNode(ARMISD::THREAD_POINTER, DebugLoc::getUnknownLoc(),
1056 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1057 unsigned VarArgsFrameIndex) {
1058 // vastart just stores the address of the VarArgsFrameIndex slot into the
1059 // memory location argument.
1060 DebugLoc dl = Op.getDebugLoc();
1061 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1062 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1063 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1064 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1068 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1069 MachineFunction &MF = DAG.getMachineFunction();
1070 MachineFrameInfo *MFI = MF.getFrameInfo();
1072 SDValue Root = Op.getOperand(0);
1073 DebugLoc dl = Op.getDebugLoc();
1074 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1075 unsigned CC = MF.getFunction()->getCallingConv();
1076 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1078 // Assign locations to all of the incoming arguments.
1079 SmallVector<CCValAssign, 16> ArgLocs;
1080 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1081 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_ARM);
1083 SmallVector<SDValue, 16> ArgValues;
1085 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1086 CCValAssign &VA = ArgLocs[i];
1088 // Arguments stored in registers.
1089 if (VA.isRegLoc()) {
1090 MVT RegVT = VA.getLocVT();
1091 TargetRegisterClass *RC;
1092 if (AFI->isThumbFunction())
1093 RC = ARM::tGPRRegisterClass;
1095 RC = ARM::GPRRegisterClass;
1097 if (RegVT == MVT::f64) {
1098 // f64 is passed in pairs of GPRs and must be combined.
1100 } else if (!((RegVT == MVT::i32) || (RegVT == MVT::f32)))
1101 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
1103 // Transform the arguments stored in physical registers into virtual ones.
1104 unsigned Reg = AddLiveIn(MF, VA.getLocReg(), RC);
1105 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1107 // f64 is passed in i32 pairs and must be combined.
1108 if (VA.needsCustom()) {
1111 VA = ArgLocs[++i]; // skip ahead to next loc
1112 if (VA.isMemLoc()) {
1113 // must be APCS and older than V5T to split like this
1114 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1115 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1117 // Create load node to retrieve arguments from the stack.
1118 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1119 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1121 Reg = AddLiveIn(MF, VA.getLocReg(), RC);
1122 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1125 ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64,
1126 ArgValue, ArgValue2);
1129 // If this is an 8 or 16-bit value, it is really passed promoted
1130 // to 32 bits. Insert an assert[sz]ext to capture this, then
1131 // truncate to the right size.
1132 switch (VA.getLocInfo()) {
1133 default: assert(0 && "Unknown loc info!");
1134 case CCValAssign::Full: break;
1135 case CCValAssign::BCvt:
1136 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1138 case CCValAssign::SExt:
1139 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1140 DAG.getValueType(VA.getValVT()));
1141 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1143 case CCValAssign::ZExt:
1144 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1145 DAG.getValueType(VA.getValVT()));
1146 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1150 ArgValues.push_back(ArgValue);
1152 } else { // VA.isRegLoc()
1155 assert(VA.isMemLoc());
1156 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1158 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1159 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1161 // Create load nodes to retrieve arguments from the stack.
1162 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1163 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1169 static const unsigned GPRArgRegs[] = {
1170 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1173 unsigned NumGPRs = CCInfo.getFirstUnallocated
1174 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1176 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1177 unsigned VARegSize = (4 - NumGPRs) * 4;
1178 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1179 unsigned ArgOffset = 0;
1180 if (VARegSaveSize) {
1181 // If this function is vararg, store any remaining integer argument regs
1182 // to their spots on the stack so that they may be loaded by deferencing
1183 // the result of va_next.
1184 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1185 ArgOffset = CCInfo.getNextStackOffset();
1186 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1187 VARegSaveSize - VARegSize);
1188 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1190 SmallVector<SDValue, 4> MemOps;
1191 for (; NumGPRs < 4; ++NumGPRs) {
1192 TargetRegisterClass *RC;
1193 if (AFI->isThumbFunction())
1194 RC = ARM::tGPRRegisterClass;
1196 RC = ARM::GPRRegisterClass;
1198 unsigned VReg = AddLiveIn(MF, GPRArgRegs[NumGPRs], RC);
1199 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
1200 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1201 MemOps.push_back(Store);
1202 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1203 DAG.getConstant(4, getPointerTy()));
1205 if (!MemOps.empty())
1206 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1207 &MemOps[0], MemOps.size());
1209 // This will point to the next argument passed via stack.
1210 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1213 ArgValues.push_back(Root);
1215 // Return the new list of results.
1216 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1217 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1220 /// isFloatingPointZero - Return true if this is +0.0.
1221 static bool isFloatingPointZero(SDValue Op) {
1222 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1223 return CFP->getValueAPF().isPosZero();
1224 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1225 // Maybe this has already been legalized into the constant pool?
1226 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1227 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1228 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1229 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1230 return CFP->getValueAPF().isPosZero();
1236 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1237 return ( isThumb && (C & ~255U) == 0) ||
1238 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1241 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1242 /// the given operands.
1243 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1244 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb,
1246 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1247 unsigned C = RHSC->getZExtValue();
1248 if (!isLegalCmpImmediate(C, isThumb)) {
1249 // Constant does not fit, try adjusting it by one?
1254 if (isLegalCmpImmediate(C-1, isThumb)) {
1255 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1256 RHS = DAG.getConstant(C-1, MVT::i32);
1261 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1262 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1263 RHS = DAG.getConstant(C-1, MVT::i32);
1268 if (isLegalCmpImmediate(C+1, isThumb)) {
1269 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1270 RHS = DAG.getConstant(C+1, MVT::i32);
1275 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1276 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1277 RHS = DAG.getConstant(C+1, MVT::i32);
1284 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1285 ARMISD::NodeType CompareType;
1288 CompareType = ARMISD::CMP;
1294 // Uses only N and Z Flags
1295 CompareType = ARMISD::CMPNZ;
1298 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1299 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1302 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1303 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1306 if (!isFloatingPointZero(RHS))
1307 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1309 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1310 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1313 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1314 const ARMSubtarget *ST) {
1315 MVT VT = Op.getValueType();
1316 SDValue LHS = Op.getOperand(0);
1317 SDValue RHS = Op.getOperand(1);
1318 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1319 SDValue TrueVal = Op.getOperand(2);
1320 SDValue FalseVal = Op.getOperand(3);
1321 DebugLoc dl = Op.getDebugLoc();
1323 if (LHS.getValueType() == MVT::i32) {
1325 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1326 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1327 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1330 ARMCC::CondCodes CondCode, CondCode2;
1331 if (FPCCToARMCC(CC, CondCode, CondCode2))
1332 std::swap(TrueVal, FalseVal);
1334 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1335 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1336 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1337 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1339 if (CondCode2 != ARMCC::AL) {
1340 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1341 // FIXME: Needs another CMP because flag can have but one use.
1342 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1343 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1344 Result, TrueVal, ARMCC2, CCR, Cmp2);
1349 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1350 const ARMSubtarget *ST) {
1351 SDValue Chain = Op.getOperand(0);
1352 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1353 SDValue LHS = Op.getOperand(2);
1354 SDValue RHS = Op.getOperand(3);
1355 SDValue Dest = Op.getOperand(4);
1356 DebugLoc dl = Op.getDebugLoc();
1358 if (LHS.getValueType() == MVT::i32) {
1360 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1361 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1362 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1363 Chain, Dest, ARMCC, CCR,Cmp);
1366 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1367 ARMCC::CondCodes CondCode, CondCode2;
1368 if (FPCCToARMCC(CC, CondCode, CondCode2))
1369 // Swap the LHS/RHS of the comparison if needed.
1370 std::swap(LHS, RHS);
1372 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1373 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1374 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1375 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1376 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1377 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1378 if (CondCode2 != ARMCC::AL) {
1379 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1380 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1381 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1386 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1387 SDValue Chain = Op.getOperand(0);
1388 SDValue Table = Op.getOperand(1);
1389 SDValue Index = Op.getOperand(2);
1390 DebugLoc dl = Op.getDebugLoc();
1392 MVT PTy = getPointerTy();
1393 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1394 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1395 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1396 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1397 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1398 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1399 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1400 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1401 Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, dl,
1402 Chain, Addr, NULL, 0);
1403 Chain = Addr.getValue(1);
1405 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1406 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1409 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1410 DebugLoc dl = Op.getDebugLoc();
1412 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1413 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1414 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1417 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1418 MVT VT = Op.getValueType();
1419 DebugLoc dl = Op.getDebugLoc();
1421 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1423 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1424 return DAG.getNode(Opc, dl, VT, Op);
1427 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1428 // Implement fcopysign with a fabs and a conditional fneg.
1429 SDValue Tmp0 = Op.getOperand(0);
1430 SDValue Tmp1 = Op.getOperand(1);
1431 DebugLoc dl = Op.getDebugLoc();
1432 MVT VT = Op.getValueType();
1433 MVT SrcVT = Tmp1.getValueType();
1434 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1435 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1436 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1437 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1438 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1442 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1444 SDValue Dst, SDValue Src,
1445 SDValue Size, unsigned Align,
1447 const Value *DstSV, uint64_t DstSVOff,
1448 const Value *SrcSV, uint64_t SrcSVOff){
1449 // Do repeated 4-byte loads and stores. To be improved.
1450 // This requires 4-byte alignment.
1451 if ((Align & 3) != 0)
1453 // This requires the copy size to be a constant, preferrably
1454 // within a subtarget-specific limit.
1455 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1458 uint64_t SizeVal = ConstantSize->getZExtValue();
1459 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1462 unsigned BytesLeft = SizeVal & 3;
1463 unsigned NumMemOps = SizeVal >> 2;
1464 unsigned EmittedNumMemOps = 0;
1466 unsigned VTSize = 4;
1468 const unsigned MAX_LOADS_IN_LDM = 6;
1469 SDValue TFOps[MAX_LOADS_IN_LDM];
1470 SDValue Loads[MAX_LOADS_IN_LDM];
1471 uint64_t SrcOff = 0, DstOff = 0;
1473 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1474 // same number of stores. The loads and stores will get combined into
1475 // ldm/stm later on.
1476 while (EmittedNumMemOps < NumMemOps) {
1478 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1479 Loads[i] = DAG.getLoad(VT, dl, Chain,
1480 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1481 DAG.getConstant(SrcOff, MVT::i32)),
1482 SrcSV, SrcSVOff + SrcOff);
1483 TFOps[i] = Loads[i].getValue(1);
1486 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1489 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1490 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1491 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1492 DAG.getConstant(DstOff, MVT::i32)),
1493 DstSV, DstSVOff + DstOff);
1496 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1498 EmittedNumMemOps += i;
1504 // Issue loads / stores for the trailing (1 - 3) bytes.
1505 unsigned BytesLeftSave = BytesLeft;
1508 if (BytesLeft >= 2) {
1516 Loads[i] = DAG.getLoad(VT, dl, Chain,
1517 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1518 DAG.getConstant(SrcOff, MVT::i32)),
1519 SrcSV, SrcSVOff + SrcOff);
1520 TFOps[i] = Loads[i].getValue(1);
1523 BytesLeft -= VTSize;
1525 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1528 BytesLeft = BytesLeftSave;
1530 if (BytesLeft >= 2) {
1538 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1539 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1540 DAG.getConstant(DstOff, MVT::i32)),
1541 DstSV, DstSVOff + DstOff);
1544 BytesLeft -= VTSize;
1546 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1549 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1550 SDValue Op = N->getOperand(0);
1551 DebugLoc dl = N->getDebugLoc();
1552 if (N->getValueType(0) == MVT::f64) {
1553 // Turn i64->f64 into FMDRR.
1554 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1555 DAG.getConstant(0, MVT::i32));
1556 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1557 DAG.getConstant(1, MVT::i32));
1558 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
1561 // Turn f64->i64 into FMRRD.
1562 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
1563 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
1565 // Merge the pieces into a single i64 value.
1566 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
1569 static SDValue ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
1570 assert(N->getValueType(0) == MVT::i64 &&
1571 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1572 "Unknown shift to lower!");
1574 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1575 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1576 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
1579 // If we are in thumb mode, we don't have RRX.
1580 if (ST->isThumb()) return SDValue();
1582 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1583 DebugLoc dl = N->getDebugLoc();
1584 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1585 DAG.getConstant(0, MVT::i32));
1586 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1587 DAG.getConstant(1, MVT::i32));
1589 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1590 // captures the result into a carry flag.
1591 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1592 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1594 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1595 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
1597 // Merge the pieces into a single i64 value.
1598 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1601 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1602 switch (Op.getOpcode()) {
1603 default: assert(0 && "Don't know how to custom lower this!"); abort();
1604 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1605 case ISD::GlobalAddress:
1606 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1607 LowerGlobalAddressELF(Op, DAG);
1608 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1609 case ISD::CALL: return LowerCALL(Op, DAG);
1610 case ISD::RET: return LowerRET(Op, DAG);
1611 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
1612 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
1613 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1614 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1615 case ISD::SINT_TO_FP:
1616 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
1617 case ISD::FP_TO_SINT:
1618 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
1619 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1620 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
1621 case ISD::RETURNADDR: break;
1622 case ISD::FRAMEADDR: break;
1623 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1624 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1625 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
1627 case ISD::SRA: return ExpandSRx(Op.getNode(), DAG,Subtarget);
1632 /// ReplaceNodeResults - Replace the results of node with an illegal result
1633 /// type with new values built out of custom code.
1634 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
1635 SmallVectorImpl<SDValue>&Results,
1636 SelectionDAG &DAG) {
1637 switch (N->getOpcode()) {
1639 assert(0 && "Don't know how to custom expand this!");
1641 case ISD::BIT_CONVERT:
1642 Results.push_back(ExpandBIT_CONVERT(N, DAG));
1646 SDValue Res = ExpandSRx(N, DAG, Subtarget);
1648 Results.push_back(Res);
1654 //===----------------------------------------------------------------------===//
1655 // ARM Scheduler Hooks
1656 //===----------------------------------------------------------------------===//
1659 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1660 MachineBasicBlock *BB) const {
1661 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1662 DebugLoc dl = MI->getDebugLoc();
1663 switch (MI->getOpcode()) {
1664 default: assert(false && "Unexpected instr type to insert");
1665 case ARM::tMOVCCr: {
1666 // To "insert" a SELECT_CC instruction, we actually have to insert the
1667 // diamond control-flow pattern. The incoming instruction knows the
1668 // destination vreg to set, the condition code register to branch on, the
1669 // true/false values to select between, and a branch opcode to use.
1670 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1671 MachineFunction::iterator It = BB;
1677 // cmpTY ccX, r1, r2
1679 // fallthrough --> copy0MBB
1680 MachineBasicBlock *thisMBB = BB;
1681 MachineFunction *F = BB->getParent();
1682 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1683 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1684 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1685 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
1686 F->insert(It, copy0MBB);
1687 F->insert(It, sinkMBB);
1688 // Update machine-CFG edges by first adding all successors of the current
1689 // block to the new block which will contain the Phi node for the select.
1690 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1691 e = BB->succ_end(); i != e; ++i)
1692 sinkMBB->addSuccessor(*i);
1693 // Next, remove all successors of the current block, and add the true
1694 // and fallthrough blocks as its successors.
1695 while(!BB->succ_empty())
1696 BB->removeSuccessor(BB->succ_begin());
1697 BB->addSuccessor(copy0MBB);
1698 BB->addSuccessor(sinkMBB);
1701 // %FalseValue = ...
1702 // # fallthrough to sinkMBB
1705 // Update machine-CFG edges
1706 BB->addSuccessor(sinkMBB);
1709 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1712 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1713 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1714 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1716 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1722 //===----------------------------------------------------------------------===//
1723 // ARM Optimization Hooks
1724 //===----------------------------------------------------------------------===//
1727 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
1728 TargetLowering::DAGCombinerInfo &DCI) {
1729 SelectionDAG &DAG = DCI.DAG;
1730 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1731 MVT VT = N->getValueType(0);
1732 unsigned Opc = N->getOpcode();
1733 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
1734 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
1735 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
1736 ISD::CondCode CC = ISD::SETCC_INVALID;
1739 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
1741 SDValue CCOp = Slct.getOperand(0);
1742 if (CCOp.getOpcode() == ISD::SETCC)
1743 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
1746 bool DoXform = false;
1748 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
1751 if (LHS.getOpcode() == ISD::Constant &&
1752 cast<ConstantSDNode>(LHS)->isNullValue()) {
1754 } else if (CC != ISD::SETCC_INVALID &&
1755 RHS.getOpcode() == ISD::Constant &&
1756 cast<ConstantSDNode>(RHS)->isNullValue()) {
1757 std::swap(LHS, RHS);
1758 SDValue Op0 = Slct.getOperand(0);
1759 MVT OpVT = isSlctCC ? Op0.getValueType() :
1760 Op0.getOperand(0).getValueType();
1761 bool isInt = OpVT.isInteger();
1762 CC = ISD::getSetCCInverse(CC, isInt);
1764 if (!TLI.isCondCodeLegal(CC, OpVT))
1765 return SDValue(); // Inverse operator isn't legal.
1772 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
1774 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
1775 Slct.getOperand(0), Slct.getOperand(1), CC);
1776 SDValue CCOp = Slct.getOperand(0);
1778 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
1779 CCOp.getOperand(0), CCOp.getOperand(1), CC);
1780 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
1781 CCOp, OtherOp, Result);
1786 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
1787 static SDValue PerformADDCombine(SDNode *N,
1788 TargetLowering::DAGCombinerInfo &DCI) {
1789 // added by evan in r37685 with no testcase.
1790 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1792 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1793 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
1794 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
1795 if (Result.getNode()) return Result;
1797 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1798 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
1799 if (Result.getNode()) return Result;
1805 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1806 static SDValue PerformSUBCombine(SDNode *N,
1807 TargetLowering::DAGCombinerInfo &DCI) {
1808 // added by evan in r37685 with no testcase.
1809 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1811 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1812 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1813 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
1814 if (Result.getNode()) return Result;
1821 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
1822 static SDValue PerformFMRRDCombine(SDNode *N,
1823 TargetLowering::DAGCombinerInfo &DCI) {
1824 // fmrrd(fmdrr x, y) -> x,y
1825 SDValue InDouble = N->getOperand(0);
1826 if (InDouble.getOpcode() == ARMISD::FMDRR)
1827 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
1831 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
1832 DAGCombinerInfo &DCI) const {
1833 switch (N->getOpcode()) {
1835 case ISD::ADD: return PerformADDCombine(N, DCI);
1836 case ISD::SUB: return PerformSUBCombine(N, DCI);
1837 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
1843 /// isLegalAddressImmediate - Return true if the integer value can be used
1844 /// as the offset of the target addressing mode for load / store of the
1846 static bool isLegalAddressImmediate(int64_t V, MVT VT,
1847 const ARMSubtarget *Subtarget) {
1854 if (Subtarget->isThumb()) {
1859 switch (VT.getSimpleVT()) {
1860 default: return false;
1875 if ((V & (Scale - 1)) != 0)
1878 return V == (V & ((1LL << 5) - 1));
1883 switch (VT.getSimpleVT()) {
1884 default: return false;
1889 return V == (V & ((1LL << 12) - 1));
1892 return V == (V & ((1LL << 8) - 1));
1895 if (!Subtarget->hasVFP2())
1900 return V == (V & ((1LL << 8) - 1));
1904 /// isLegalAddressingMode - Return true if the addressing mode represented
1905 /// by AM is legal for this target, for a load/store of the specified type.
1906 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1907 const Type *Ty) const {
1908 MVT VT = getValueType(Ty, true);
1909 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
1912 // Can never fold addr of global into load/store.
1917 case 0: // no scale reg, must be "r+i" or "r", or "i".
1920 if (Subtarget->isThumb())
1924 // ARM doesn't support any R+R*scale+imm addr modes.
1931 int Scale = AM.Scale;
1932 switch (VT.getSimpleVT()) {
1933 default: return false;
1938 // This assumes i64 is legalized to a pair of i32. If not (i.e.
1939 // ldrd / strd are used, then its address mode is same as i16.
1941 if (Scale < 0) Scale = -Scale;
1945 return isPowerOf2_32(Scale & ~1);
1948 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1953 // Note, we allow "void" uses (basically, uses that aren't loads or
1954 // stores), because arm allows folding a scale into many arithmetic
1955 // operations. This should be made more precise and revisited later.
1957 // Allow r << imm, but the imm has to be a multiple of two.
1958 if (AM.Scale & 1) return false;
1959 return isPowerOf2_32(AM.Scale);
1966 static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
1967 bool isSEXTLoad, SDValue &Base,
1968 SDValue &Offset, bool &isInc,
1969 SelectionDAG &DAG) {
1970 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1973 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1975 Base = Ptr->getOperand(0);
1976 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1977 int RHSC = (int)RHS->getZExtValue();
1978 if (RHSC < 0 && RHSC > -256) {
1980 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1984 isInc = (Ptr->getOpcode() == ISD::ADD);
1985 Offset = Ptr->getOperand(1);
1987 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1989 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1990 int RHSC = (int)RHS->getZExtValue();
1991 if (RHSC < 0 && RHSC > -0x1000) {
1993 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1994 Base = Ptr->getOperand(0);
1999 if (Ptr->getOpcode() == ISD::ADD) {
2001 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
2002 if (ShOpcVal != ARM_AM::no_shift) {
2003 Base = Ptr->getOperand(1);
2004 Offset = Ptr->getOperand(0);
2006 Base = Ptr->getOperand(0);
2007 Offset = Ptr->getOperand(1);
2012 isInc = (Ptr->getOpcode() == ISD::ADD);
2013 Base = Ptr->getOperand(0);
2014 Offset = Ptr->getOperand(1);
2018 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
2022 /// getPreIndexedAddressParts - returns true by value, base pointer and
2023 /// offset pointer and addressing mode by reference if the node's address
2024 /// can be legally represented as pre-indexed load / store address.
2026 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2028 ISD::MemIndexedMode &AM,
2029 SelectionDAG &DAG) const {
2030 if (Subtarget->isThumb())
2035 bool isSEXTLoad = false;
2036 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2037 Ptr = LD->getBasePtr();
2038 VT = LD->getMemoryVT();
2039 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
2040 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2041 Ptr = ST->getBasePtr();
2042 VT = ST->getMemoryVT();
2047 bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, Offset,
2050 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
2056 /// getPostIndexedAddressParts - returns true by value, base pointer and
2057 /// offset pointer and addressing mode by reference if this node can be
2058 /// combined with a load / store to form a post-indexed load / store.
2059 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
2062 ISD::MemIndexedMode &AM,
2063 SelectionDAG &DAG) const {
2064 if (Subtarget->isThumb())
2069 bool isSEXTLoad = false;
2070 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2071 VT = LD->getMemoryVT();
2072 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
2073 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2074 VT = ST->getMemoryVT();
2079 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
2082 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
2088 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
2092 const SelectionDAG &DAG,
2093 unsigned Depth) const {
2094 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
2095 switch (Op.getOpcode()) {
2097 case ARMISD::CMOV: {
2098 // Bits are known zero/one if known on the LHS and RHS.
2099 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
2100 if (KnownZero == 0 && KnownOne == 0) return;
2102 APInt KnownZeroRHS, KnownOneRHS;
2103 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
2104 KnownZeroRHS, KnownOneRHS, Depth+1);
2105 KnownZero &= KnownZeroRHS;
2106 KnownOne &= KnownOneRHS;
2112 //===----------------------------------------------------------------------===//
2113 // ARM Inline Assembly Support
2114 //===----------------------------------------------------------------------===//
2116 /// getConstraintType - Given a constraint letter, return the type of
2117 /// constraint it is for this target.
2118 ARMTargetLowering::ConstraintType
2119 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
2120 if (Constraint.size() == 1) {
2121 switch (Constraint[0]) {
2123 case 'l': return C_RegisterClass;
2124 case 'w': return C_RegisterClass;
2127 return TargetLowering::getConstraintType(Constraint);
2130 std::pair<unsigned, const TargetRegisterClass*>
2131 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
2133 if (Constraint.size() == 1) {
2134 // GCC RS6000 Constraint Letters
2135 switch (Constraint[0]) {
2137 if (Subtarget->isThumb())
2138 return std::make_pair(0U, ARM::tGPRRegisterClass);
2140 return std::make_pair(0U, ARM::GPRRegisterClass);
2142 return std::make_pair(0U, ARM::GPRRegisterClass);
2145 return std::make_pair(0U, ARM::SPRRegisterClass);
2147 return std::make_pair(0U, ARM::DPRRegisterClass);
2151 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2154 std::vector<unsigned> ARMTargetLowering::
2155 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2157 if (Constraint.size() != 1)
2158 return std::vector<unsigned>();
2160 switch (Constraint[0]) { // GCC ARM Constraint Letters
2163 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
2164 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
2167 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
2168 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
2169 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
2170 ARM::R12, ARM::LR, 0);
2173 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
2174 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
2175 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
2176 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
2177 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
2178 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
2179 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
2180 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
2182 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
2183 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
2184 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
2185 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
2189 return std::vector<unsigned>();
2192 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2193 /// vector. If it is invalid, don't add anything to Ops.
2194 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2197 std::vector<SDValue>&Ops,
2198 SelectionDAG &DAG) const {
2199 SDValue Result(0, 0);
2201 switch (Constraint) {
2203 case 'I': case 'J': case 'K': case 'L':
2204 case 'M': case 'N': case 'O':
2205 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2209 int64_t CVal64 = C->getSExtValue();
2210 int CVal = (int) CVal64;
2211 // None of these constraints allow values larger than 32 bits. Check
2212 // that the value fits in an int.
2216 switch (Constraint) {
2218 if (Subtarget->isThumb()) {
2219 // This must be a constant between 0 and 255, for ADD immediates.
2220 if (CVal >= 0 && CVal <= 255)
2223 // A constant that can be used as an immediate value in a
2224 // data-processing instruction.
2225 if (ARM_AM::getSOImmVal(CVal) != -1)
2231 if (Subtarget->isThumb()) {
2232 // This must be a constant between -255 and -1, for negated ADD
2233 // immediates. This can be used in GCC with an "n" modifier that
2234 // prints the negated value, for use with SUB instructions. It is
2235 // not useful otherwise but is implemented for compatibility.
2236 if (CVal >= -255 && CVal <= -1)
2239 // This must be a constant between -4095 and 4095. It is not clear
2240 // what this constraint is intended for. Implemented for
2241 // compatibility with GCC.
2242 if (CVal >= -4095 && CVal <= 4095)
2248 if (Subtarget->isThumb()) {
2249 // A 32-bit value where only one byte has a nonzero value. Exclude
2250 // zero to match GCC. This constraint is used by GCC internally for
2251 // constants that can be loaded with a move/shift combination.
2252 // It is not useful otherwise but is implemented for compatibility.
2253 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
2256 // A constant whose bitwise inverse can be used as an immediate
2257 // value in a data-processing instruction. This can be used in GCC
2258 // with a "B" modifier that prints the inverted value, for use with
2259 // BIC and MVN instructions. It is not useful otherwise but is
2260 // implemented for compatibility.
2261 if (ARM_AM::getSOImmVal(~CVal) != -1)
2267 if (Subtarget->isThumb()) {
2268 // This must be a constant between -7 and 7,
2269 // for 3-operand ADD/SUB immediate instructions.
2270 if (CVal >= -7 && CVal < 7)
2273 // A constant whose negation can be used as an immediate value in a
2274 // data-processing instruction. This can be used in GCC with an "n"
2275 // modifier that prints the negated value, for use with SUB
2276 // instructions. It is not useful otherwise but is implemented for
2278 if (ARM_AM::getSOImmVal(-CVal) != -1)
2284 if (Subtarget->isThumb()) {
2285 // This must be a multiple of 4 between 0 and 1020, for
2286 // ADD sp + immediate.
2287 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
2290 // A power of two or a constant between 0 and 32. This is used in
2291 // GCC for the shift amount on shifted register operands, but it is
2292 // useful in general for any shift amounts.
2293 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
2299 if (Subtarget->isThumb()) {
2300 // This must be a constant between 0 and 31, for shift amounts.
2301 if (CVal >= 0 && CVal <= 31)
2307 if (Subtarget->isThumb()) {
2308 // This must be a multiple of 4 between -508 and 508, for
2309 // ADD/SUB sp = sp + immediate.
2310 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
2315 Result = DAG.getTargetConstant(CVal, Op.getValueType());
2319 if (Result.getNode()) {
2320 Ops.push_back(Result);
2323 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,