1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMCallingConv.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "MCTargetDesc/ARMAddressingModes.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineModuleInfo.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/PseudoSourceValue.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/ADT/Statistic.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
57 STATISTIC(NumTailCalls, "Number of tail calls");
58 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
60 // This option should go away when tail calls fully work.
62 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
63 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
67 EnableARMLongCalls("arm-long-calls", cl::Hidden,
68 cl::desc("Generate calls via indirect call instructions"),
72 ARMInterworking("arm-interworking", cl::Hidden,
73 cl::desc("Enable / disable ARM interworking (for debugging only)"),
77 class ARMCCState : public CCState {
79 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
80 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,
81 LLVMContext &C, ParmContext PC)
82 : CCState(CC, isVarArg, MF, TM, locs, C) {
83 assert(((PC == Call) || (PC == Prologue)) &&
84 "ARMCCState users must specify whether their context is call"
85 "or prologue generation.");
91 // The APCS parameter registers.
92 static const unsigned GPRArgRegs[] = {
93 ARM::R0, ARM::R1, ARM::R2, ARM::R3
96 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
97 EVT PromotedBitwiseVT) {
98 if (VT != PromotedLdStVT) {
99 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
100 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
101 PromotedLdStVT.getSimpleVT());
103 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
104 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
105 PromotedLdStVT.getSimpleVT());
108 EVT ElemTy = VT.getVectorElementType();
109 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
110 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
111 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
112 if (ElemTy != MVT::i32) {
113 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
114 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
116 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
118 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
119 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
120 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
121 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
122 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
123 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
124 if (VT.isInteger()) {
125 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
126 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
127 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
128 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
129 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
130 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
131 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
132 setTruncStoreAction(VT.getSimpleVT(),
133 (MVT::SimpleValueType)InnerVT, Expand);
135 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
137 // Promote all bit-wise operations.
138 if (VT.isInteger() && VT != PromotedBitwiseVT) {
139 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
140 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
141 PromotedBitwiseVT.getSimpleVT());
142 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
143 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
144 PromotedBitwiseVT.getSimpleVT());
145 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
146 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
147 PromotedBitwiseVT.getSimpleVT());
150 // Neon does not support vector divide/remainder operations.
151 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
152 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
153 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
154 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
155 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
156 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
159 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
160 addRegisterClass(VT, ARM::DPRRegisterClass);
161 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
164 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
165 addRegisterClass(VT, ARM::QPRRegisterClass);
166 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
169 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
170 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
171 return new TargetLoweringObjectFileMachO();
173 return new ARMElfTargetObjectFile();
176 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
177 : TargetLowering(TM, createTLOF(TM)) {
178 Subtarget = &TM.getSubtarget<ARMSubtarget>();
179 RegInfo = TM.getRegisterInfo();
180 Itins = TM.getInstrItineraryData();
182 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
184 if (Subtarget->isTargetDarwin()) {
185 // Uses VFP for Thumb libfuncs if available.
186 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
187 // Single-precision floating-point arithmetic.
188 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
189 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
190 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
191 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
193 // Double-precision floating-point arithmetic.
194 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
195 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
196 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
197 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
199 // Single-precision comparisons.
200 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
201 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
202 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
203 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
204 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
205 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
206 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
207 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
209 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
218 // Double-precision comparisons.
219 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
220 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
221 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
222 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
223 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
224 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
225 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
226 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
228 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
229 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
230 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
231 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
232 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
233 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
234 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
235 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
237 // Floating-point to integer conversions.
238 // i64 conversions are done via library routines even when generating VFP
239 // instructions, so use the same ones.
240 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
241 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
242 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
243 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
245 // Conversions between floating types.
246 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
247 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
249 // Integer to floating-point conversions.
250 // i64 conversions are done via library routines even when generating VFP
251 // instructions, so use the same ones.
252 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
253 // e.g., __floatunsidf vs. __floatunssidfvfp.
254 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
255 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
256 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
257 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
261 // These libcalls are not available in 32-bit.
262 setLibcallName(RTLIB::SHL_I128, 0);
263 setLibcallName(RTLIB::SRL_I128, 0);
264 setLibcallName(RTLIB::SRA_I128, 0);
266 if (Subtarget->isAAPCS_ABI()) {
267 // Double-precision floating-point arithmetic helper functions
268 // RTABI chapter 4.1.2, Table 2
269 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
270 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
271 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
272 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
273 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
278 // Double-precision floating-point comparison helper functions
279 // RTABI chapter 4.1.2, Table 3
280 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
281 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
282 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
283 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
284 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
285 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
286 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
287 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
288 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
289 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
290 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
291 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
292 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
293 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
294 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
295 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
296 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
297 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
298 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
299 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
300 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
301 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
302 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
303 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
305 // Single-precision floating-point arithmetic helper functions
306 // RTABI chapter 4.1.2, Table 4
307 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
308 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
309 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
310 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
311 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
316 // Single-precision floating-point comparison helper functions
317 // RTABI chapter 4.1.2, Table 5
318 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
319 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
320 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
321 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
322 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
323 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
324 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
325 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
326 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
327 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
328 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
329 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
330 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
331 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
332 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
333 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
334 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
338 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
339 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
340 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
341 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
343 // Floating-point to integer conversions.
344 // RTABI chapter 4.1.2, Table 6
345 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
346 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
347 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
348 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
349 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
350 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
351 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
352 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
353 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
362 // Conversions between floating types.
363 // RTABI chapter 4.1.2, Table 7
364 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
365 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
366 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
367 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
369 // Integer to floating-point conversions.
370 // RTABI chapter 4.1.2, Table 8
371 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
372 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
373 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
374 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
375 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
376 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
377 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
378 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
379 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
380 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
381 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
382 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
383 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
384 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
385 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
386 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
388 // Long long helper functions
389 // RTABI chapter 4.2, Table 9
390 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
391 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
392 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
393 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
394 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
395 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
396 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
397 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
398 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
399 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
400 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
401 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
403 // Integer division functions
404 // RTABI chapter 4.3.1
405 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
406 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
407 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
408 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
409 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
410 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
411 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
412 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
413 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
414 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
415 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
416 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
419 // RTABI chapter 4.3.4
420 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
421 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
422 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
425 // Use divmod compiler-rt calls for iOS 5.0 and later.
426 if (Subtarget->getTargetTriple().getOS() == Triple::IOS &&
427 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
428 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
429 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
432 if (Subtarget->isThumb1Only())
433 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
435 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
436 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
437 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
438 if (!Subtarget->isFPOnlySP())
439 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
441 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
444 if (Subtarget->hasNEON()) {
445 addDRTypeForNEON(MVT::v2f32);
446 addDRTypeForNEON(MVT::v8i8);
447 addDRTypeForNEON(MVT::v4i16);
448 addDRTypeForNEON(MVT::v2i32);
449 addDRTypeForNEON(MVT::v1i64);
451 addQRTypeForNEON(MVT::v4f32);
452 addQRTypeForNEON(MVT::v2f64);
453 addQRTypeForNEON(MVT::v16i8);
454 addQRTypeForNEON(MVT::v8i16);
455 addQRTypeForNEON(MVT::v4i32);
456 addQRTypeForNEON(MVT::v2i64);
458 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
459 // neither Neon nor VFP support any arithmetic operations on it.
460 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
461 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
462 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
463 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
464 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
465 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
466 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
467 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
468 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
469 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
470 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
471 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
472 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
473 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
474 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
475 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
476 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
477 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
478 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
479 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
480 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
481 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
482 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
483 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
485 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
487 // Neon does not support some operations on v1i64 and v2i64 types.
488 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
489 // Custom handling for some quad-vector types to detect VMULL.
490 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
491 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
492 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
493 // Custom handling for some vector types to avoid expensive expansions
494 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
495 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
496 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
497 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
498 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
499 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
500 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
501 // a destination type that is wider than the source.
502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
505 setTargetDAGCombine(ISD::INTRINSIC_VOID);
506 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
507 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
508 setTargetDAGCombine(ISD::SHL);
509 setTargetDAGCombine(ISD::SRL);
510 setTargetDAGCombine(ISD::SRA);
511 setTargetDAGCombine(ISD::SIGN_EXTEND);
512 setTargetDAGCombine(ISD::ZERO_EXTEND);
513 setTargetDAGCombine(ISD::ANY_EXTEND);
514 setTargetDAGCombine(ISD::SELECT_CC);
515 setTargetDAGCombine(ISD::BUILD_VECTOR);
516 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
517 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
518 setTargetDAGCombine(ISD::STORE);
519 setTargetDAGCombine(ISD::FP_TO_SINT);
520 setTargetDAGCombine(ISD::FP_TO_UINT);
521 setTargetDAGCombine(ISD::FDIV);
523 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
526 computeRegisterProperties();
528 // ARM does not have f32 extending load.
529 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
531 // ARM does not have i1 sign extending load.
532 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
534 // ARM supports all 4 flavors of integer indexed load / store.
535 if (!Subtarget->isThumb1Only()) {
536 for (unsigned im = (unsigned)ISD::PRE_INC;
537 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
538 setIndexedLoadAction(im, MVT::i1, Legal);
539 setIndexedLoadAction(im, MVT::i8, Legal);
540 setIndexedLoadAction(im, MVT::i16, Legal);
541 setIndexedLoadAction(im, MVT::i32, Legal);
542 setIndexedStoreAction(im, MVT::i1, Legal);
543 setIndexedStoreAction(im, MVT::i8, Legal);
544 setIndexedStoreAction(im, MVT::i16, Legal);
545 setIndexedStoreAction(im, MVT::i32, Legal);
549 // i64 operation support.
550 setOperationAction(ISD::MUL, MVT::i64, Expand);
551 setOperationAction(ISD::MULHU, MVT::i32, Expand);
552 if (Subtarget->isThumb1Only()) {
553 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
554 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
556 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
557 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
558 setOperationAction(ISD::MULHS, MVT::i32, Expand);
560 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
561 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
562 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
563 setOperationAction(ISD::SRL, MVT::i64, Custom);
564 setOperationAction(ISD::SRA, MVT::i64, Custom);
566 if (!Subtarget->isThumb1Only()) {
567 // FIXME: We should do this for Thumb1 as well.
568 setOperationAction(ISD::ADDC, MVT::i32, Custom);
569 setOperationAction(ISD::ADDE, MVT::i32, Custom);
570 setOperationAction(ISD::SUBC, MVT::i32, Custom);
571 setOperationAction(ISD::SUBE, MVT::i32, Custom);
574 // ARM does not have ROTL.
575 setOperationAction(ISD::ROTL, MVT::i32, Expand);
576 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
577 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
578 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
579 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
581 // Only ARMv6 has BSWAP.
582 if (!Subtarget->hasV6Ops())
583 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
585 // These are expanded into libcalls.
586 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
587 // v7M has a hardware divider
588 setOperationAction(ISD::SDIV, MVT::i32, Expand);
589 setOperationAction(ISD::UDIV, MVT::i32, Expand);
591 setOperationAction(ISD::SREM, MVT::i32, Expand);
592 setOperationAction(ISD::UREM, MVT::i32, Expand);
593 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
594 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
596 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
597 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
598 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
599 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
600 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
602 setOperationAction(ISD::TRAP, MVT::Other, Legal);
604 // Use the default implementation.
605 setOperationAction(ISD::VASTART, MVT::Other, Custom);
606 setOperationAction(ISD::VAARG, MVT::Other, Expand);
607 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
608 setOperationAction(ISD::VAEND, MVT::Other, Expand);
609 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
610 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
611 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
612 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
613 setExceptionPointerRegister(ARM::R0);
614 setExceptionSelectorRegister(ARM::R1);
616 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
617 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
618 // the default expansion.
619 // FIXME: This should be checking for v6k, not just v6.
620 if (Subtarget->hasDataBarrier() ||
621 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
622 // membarrier needs custom lowering; the rest are legal and handled
624 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
625 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
626 // Custom lowering for 64-bit ops
627 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
628 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
629 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
630 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
631 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
632 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
633 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
634 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
635 setInsertFencesForAtomic(true);
637 // Set them all for expansion, which will force libcalls.
638 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
639 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
640 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
641 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
642 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
643 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
644 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
645 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
646 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
647 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
648 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
649 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
650 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
651 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
652 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
653 // Unordered/Monotonic case.
654 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
655 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
656 // Since the libcalls include locking, fold in the fences
657 setShouldFoldAtomicFences(true);
660 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
662 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
663 if (!Subtarget->hasV6Ops()) {
664 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
665 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
667 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
669 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
670 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
671 // iff target supports vfp2.
672 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
673 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
676 // We want to custom lower some of our intrinsics.
677 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
678 if (Subtarget->isTargetDarwin()) {
679 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
680 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
681 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
682 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
685 setOperationAction(ISD::SETCC, MVT::i32, Expand);
686 setOperationAction(ISD::SETCC, MVT::f32, Expand);
687 setOperationAction(ISD::SETCC, MVT::f64, Expand);
688 setOperationAction(ISD::SELECT, MVT::i32, Custom);
689 setOperationAction(ISD::SELECT, MVT::f32, Custom);
690 setOperationAction(ISD::SELECT, MVT::f64, Custom);
691 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
692 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
693 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
695 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
696 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
697 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
698 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
699 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
701 // We don't support sin/cos/fmod/copysign/pow
702 setOperationAction(ISD::FSIN, MVT::f64, Expand);
703 setOperationAction(ISD::FSIN, MVT::f32, Expand);
704 setOperationAction(ISD::FCOS, MVT::f32, Expand);
705 setOperationAction(ISD::FCOS, MVT::f64, Expand);
706 setOperationAction(ISD::FREM, MVT::f64, Expand);
707 setOperationAction(ISD::FREM, MVT::f32, Expand);
708 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
709 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
710 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
712 setOperationAction(ISD::FPOW, MVT::f64, Expand);
713 setOperationAction(ISD::FPOW, MVT::f32, Expand);
715 setOperationAction(ISD::FMA, MVT::f64, Expand);
716 setOperationAction(ISD::FMA, MVT::f32, Expand);
718 // Various VFP goodness
719 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
720 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
721 if (Subtarget->hasVFP2()) {
722 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
723 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
724 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
725 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
727 // Special handling for half-precision FP.
728 if (!Subtarget->hasFP16()) {
729 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
730 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
734 // We have target-specific dag combine patterns for the following nodes:
735 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
736 setTargetDAGCombine(ISD::ADD);
737 setTargetDAGCombine(ISD::SUB);
738 setTargetDAGCombine(ISD::MUL);
740 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
741 setTargetDAGCombine(ISD::OR);
742 if (Subtarget->hasNEON())
743 setTargetDAGCombine(ISD::AND);
745 setStackPointerRegisterToSaveRestore(ARM::SP);
747 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
748 setSchedulingPreference(Sched::RegPressure);
750 setSchedulingPreference(Sched::Hybrid);
752 //// temporary - rewrite interface to use type
753 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
755 // On ARM arguments smaller than 4 bytes are extended, so all arguments
756 // are at least 4 bytes aligned.
757 setMinStackArgumentAlignment(4);
759 benefitFromCodePlacementOpt = true;
761 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
764 // FIXME: It might make sense to define the representative register class as the
765 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
766 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
767 // SPR's representative would be DPR_VFP2. This should work well if register
768 // pressure tracking were modified such that a register use would increment the
769 // pressure of the register class's representative and all of it's super
770 // classes' representatives transitively. We have not implemented this because
771 // of the difficulty prior to coalescing of modeling operand register classes
772 // due to the common occurrence of cross class copies and subregister insertions
774 std::pair<const TargetRegisterClass*, uint8_t>
775 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
776 const TargetRegisterClass *RRC = 0;
778 switch (VT.getSimpleVT().SimpleTy) {
780 return TargetLowering::findRepresentativeClass(VT);
781 // Use DPR as representative register class for all floating point
782 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
783 // the cost is 1 for both f32 and f64.
784 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
785 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
786 RRC = ARM::DPRRegisterClass;
787 // When NEON is used for SP, only half of the register file is available
788 // because operations that define both SP and DP results will be constrained
789 // to the VFP2 class (D0-D15). We currently model this constraint prior to
790 // coalescing by double-counting the SP regs. See the FIXME above.
791 if (Subtarget->useNEONForSinglePrecisionFP())
794 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
795 case MVT::v4f32: case MVT::v2f64:
796 RRC = ARM::DPRRegisterClass;
800 RRC = ARM::DPRRegisterClass;
804 RRC = ARM::DPRRegisterClass;
808 return std::make_pair(RRC, Cost);
811 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
814 case ARMISD::Wrapper: return "ARMISD::Wrapper";
815 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
816 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
817 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
818 case ARMISD::CALL: return "ARMISD::CALL";
819 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
820 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
821 case ARMISD::tCALL: return "ARMISD::tCALL";
822 case ARMISD::BRCOND: return "ARMISD::BRCOND";
823 case ARMISD::BR_JT: return "ARMISD::BR_JT";
824 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
825 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
826 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
827 case ARMISD::CMP: return "ARMISD::CMP";
828 case ARMISD::CMPZ: return "ARMISD::CMPZ";
829 case ARMISD::CMPFP: return "ARMISD::CMPFP";
830 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
831 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
832 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
833 case ARMISD::CMOV: return "ARMISD::CMOV";
835 case ARMISD::RBIT: return "ARMISD::RBIT";
837 case ARMISD::FTOSI: return "ARMISD::FTOSI";
838 case ARMISD::FTOUI: return "ARMISD::FTOUI";
839 case ARMISD::SITOF: return "ARMISD::SITOF";
840 case ARMISD::UITOF: return "ARMISD::UITOF";
842 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
843 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
844 case ARMISD::RRX: return "ARMISD::RRX";
846 case ARMISD::ADDC: return "ARMISD::ADDC";
847 case ARMISD::ADDE: return "ARMISD::ADDE";
848 case ARMISD::SUBC: return "ARMISD::SUBC";
849 case ARMISD::SUBE: return "ARMISD::SUBE";
851 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
852 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
854 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
855 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
856 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
858 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
860 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
862 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
864 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
865 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
867 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
869 case ARMISD::VCEQ: return "ARMISD::VCEQ";
870 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
871 case ARMISD::VCGE: return "ARMISD::VCGE";
872 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
873 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
874 case ARMISD::VCGEU: return "ARMISD::VCGEU";
875 case ARMISD::VCGT: return "ARMISD::VCGT";
876 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
877 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
878 case ARMISD::VCGTU: return "ARMISD::VCGTU";
879 case ARMISD::VTST: return "ARMISD::VTST";
881 case ARMISD::VSHL: return "ARMISD::VSHL";
882 case ARMISD::VSHRs: return "ARMISD::VSHRs";
883 case ARMISD::VSHRu: return "ARMISD::VSHRu";
884 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
885 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
886 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
887 case ARMISD::VSHRN: return "ARMISD::VSHRN";
888 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
889 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
890 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
891 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
892 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
893 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
894 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
895 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
896 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
897 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
898 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
899 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
900 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
901 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
902 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
903 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
904 case ARMISD::VDUP: return "ARMISD::VDUP";
905 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
906 case ARMISD::VEXT: return "ARMISD::VEXT";
907 case ARMISD::VREV64: return "ARMISD::VREV64";
908 case ARMISD::VREV32: return "ARMISD::VREV32";
909 case ARMISD::VREV16: return "ARMISD::VREV16";
910 case ARMISD::VZIP: return "ARMISD::VZIP";
911 case ARMISD::VUZP: return "ARMISD::VUZP";
912 case ARMISD::VTRN: return "ARMISD::VTRN";
913 case ARMISD::VTBL1: return "ARMISD::VTBL1";
914 case ARMISD::VTBL2: return "ARMISD::VTBL2";
915 case ARMISD::VMULLs: return "ARMISD::VMULLs";
916 case ARMISD::VMULLu: return "ARMISD::VMULLu";
917 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
918 case ARMISD::FMAX: return "ARMISD::FMAX";
919 case ARMISD::FMIN: return "ARMISD::FMIN";
920 case ARMISD::BFI: return "ARMISD::BFI";
921 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
922 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
923 case ARMISD::VBSL: return "ARMISD::VBSL";
924 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
925 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
926 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
927 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
928 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
929 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
930 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
931 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
932 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
933 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
934 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
935 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
936 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
937 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
938 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
939 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
940 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
941 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
942 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
943 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
947 EVT ARMTargetLowering::getSetCCResultType(EVT VT) const {
948 if (!VT.isVector()) return getPointerTy();
949 return VT.changeVectorElementTypeToInteger();
952 /// getRegClassFor - Return the register class that should be used for the
953 /// specified value type.
954 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
955 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
956 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
957 // load / store 4 to 8 consecutive D registers.
958 if (Subtarget->hasNEON()) {
959 if (VT == MVT::v4i64)
960 return ARM::QQPRRegisterClass;
961 else if (VT == MVT::v8i64)
962 return ARM::QQQQPRRegisterClass;
964 return TargetLowering::getRegClassFor(VT);
967 // Create a fast isel object.
969 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
970 return ARM::createFastISel(funcInfo);
973 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
974 /// be used for loads / stores from the global.
975 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
976 return (Subtarget->isThumb1Only() ? 127 : 4095);
979 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
980 unsigned NumVals = N->getNumValues();
982 return Sched::RegPressure;
984 for (unsigned i = 0; i != NumVals; ++i) {
985 EVT VT = N->getValueType(i);
986 if (VT == MVT::Glue || VT == MVT::Other)
988 if (VT.isFloatingPoint() || VT.isVector())
989 return Sched::Latency;
992 if (!N->isMachineOpcode())
993 return Sched::RegPressure;
995 // Load are scheduled for latency even if there instruction itinerary
997 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
998 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1000 if (MCID.getNumDefs() == 0)
1001 return Sched::RegPressure;
1002 if (!Itins->isEmpty() &&
1003 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1004 return Sched::Latency;
1006 return Sched::RegPressure;
1009 //===----------------------------------------------------------------------===//
1011 //===----------------------------------------------------------------------===//
1013 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1014 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1016 default: llvm_unreachable("Unknown condition code!");
1017 case ISD::SETNE: return ARMCC::NE;
1018 case ISD::SETEQ: return ARMCC::EQ;
1019 case ISD::SETGT: return ARMCC::GT;
1020 case ISD::SETGE: return ARMCC::GE;
1021 case ISD::SETLT: return ARMCC::LT;
1022 case ISD::SETLE: return ARMCC::LE;
1023 case ISD::SETUGT: return ARMCC::HI;
1024 case ISD::SETUGE: return ARMCC::HS;
1025 case ISD::SETULT: return ARMCC::LO;
1026 case ISD::SETULE: return ARMCC::LS;
1030 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1031 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1032 ARMCC::CondCodes &CondCode2) {
1033 CondCode2 = ARMCC::AL;
1035 default: llvm_unreachable("Unknown FP condition!");
1037 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1039 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1041 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1042 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1043 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1044 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1045 case ISD::SETO: CondCode = ARMCC::VC; break;
1046 case ISD::SETUO: CondCode = ARMCC::VS; break;
1047 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1048 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1049 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1051 case ISD::SETULT: CondCode = ARMCC::LT; break;
1053 case ISD::SETULE: CondCode = ARMCC::LE; break;
1055 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1059 //===----------------------------------------------------------------------===//
1060 // Calling Convention Implementation
1061 //===----------------------------------------------------------------------===//
1063 #include "ARMGenCallingConv.inc"
1065 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1066 /// given CallingConvention value.
1067 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1069 bool isVarArg) const {
1072 llvm_unreachable("Unsupported calling convention");
1073 case CallingConv::Fast:
1074 if (Subtarget->hasVFP2() && !isVarArg) {
1075 if (!Subtarget->isAAPCS_ABI())
1076 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1077 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1078 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1081 case CallingConv::C: {
1082 // Use target triple & subtarget features to do actual dispatch.
1083 if (!Subtarget->isAAPCS_ABI())
1084 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1085 else if (Subtarget->hasVFP2() &&
1086 FloatABIType == FloatABI::Hard && !isVarArg)
1087 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1088 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1090 case CallingConv::ARM_AAPCS_VFP:
1091 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1092 case CallingConv::ARM_AAPCS:
1093 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1094 case CallingConv::ARM_APCS:
1095 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1099 /// LowerCallResult - Lower the result values of a call into the
1100 /// appropriate copies out of appropriate physical registers.
1102 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1103 CallingConv::ID CallConv, bool isVarArg,
1104 const SmallVectorImpl<ISD::InputArg> &Ins,
1105 DebugLoc dl, SelectionDAG &DAG,
1106 SmallVectorImpl<SDValue> &InVals) const {
1108 // Assign locations to each value returned by this call.
1109 SmallVector<CCValAssign, 16> RVLocs;
1110 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1111 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1112 CCInfo.AnalyzeCallResult(Ins,
1113 CCAssignFnForNode(CallConv, /* Return*/ true,
1116 // Copy all of the result registers out of their specified physreg.
1117 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1118 CCValAssign VA = RVLocs[i];
1121 if (VA.needsCustom()) {
1122 // Handle f64 or half of a v2f64.
1123 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1125 Chain = Lo.getValue(1);
1126 InFlag = Lo.getValue(2);
1127 VA = RVLocs[++i]; // skip ahead to next loc
1128 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1130 Chain = Hi.getValue(1);
1131 InFlag = Hi.getValue(2);
1132 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1134 if (VA.getLocVT() == MVT::v2f64) {
1135 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1136 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1137 DAG.getConstant(0, MVT::i32));
1139 VA = RVLocs[++i]; // skip ahead to next loc
1140 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1141 Chain = Lo.getValue(1);
1142 InFlag = Lo.getValue(2);
1143 VA = RVLocs[++i]; // skip ahead to next loc
1144 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1145 Chain = Hi.getValue(1);
1146 InFlag = Hi.getValue(2);
1147 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1148 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1149 DAG.getConstant(1, MVT::i32));
1152 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1154 Chain = Val.getValue(1);
1155 InFlag = Val.getValue(2);
1158 switch (VA.getLocInfo()) {
1159 default: llvm_unreachable("Unknown loc info!");
1160 case CCValAssign::Full: break;
1161 case CCValAssign::BCvt:
1162 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1166 InVals.push_back(Val);
1172 /// LowerMemOpCallTo - Store the argument to the stack.
1174 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1175 SDValue StackPtr, SDValue Arg,
1176 DebugLoc dl, SelectionDAG &DAG,
1177 const CCValAssign &VA,
1178 ISD::ArgFlagsTy Flags) const {
1179 unsigned LocMemOffset = VA.getLocMemOffset();
1180 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1181 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1182 return DAG.getStore(Chain, dl, Arg, PtrOff,
1183 MachinePointerInfo::getStack(LocMemOffset),
1187 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1188 SDValue Chain, SDValue &Arg,
1189 RegsToPassVector &RegsToPass,
1190 CCValAssign &VA, CCValAssign &NextVA,
1192 SmallVector<SDValue, 8> &MemOpChains,
1193 ISD::ArgFlagsTy Flags) const {
1195 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1196 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1197 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1199 if (NextVA.isRegLoc())
1200 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1202 assert(NextVA.isMemLoc());
1203 if (StackPtr.getNode() == 0)
1204 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1206 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1212 /// LowerCall - Lowering a call into a callseq_start <-
1213 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1216 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1217 CallingConv::ID CallConv, bool isVarArg,
1219 const SmallVectorImpl<ISD::OutputArg> &Outs,
1220 const SmallVectorImpl<SDValue> &OutVals,
1221 const SmallVectorImpl<ISD::InputArg> &Ins,
1222 DebugLoc dl, SelectionDAG &DAG,
1223 SmallVectorImpl<SDValue> &InVals) const {
1224 MachineFunction &MF = DAG.getMachineFunction();
1225 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1226 bool IsSibCall = false;
1227 // Disable tail calls if they're not supported.
1228 if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
1231 // Check if it's really possible to do a tail call.
1232 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1233 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1234 Outs, OutVals, Ins, DAG);
1235 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1236 // detected sibcalls.
1243 // Analyze operands of the call, assigning locations to each operand.
1244 SmallVector<CCValAssign, 16> ArgLocs;
1245 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1246 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1247 CCInfo.AnalyzeCallOperands(Outs,
1248 CCAssignFnForNode(CallConv, /* Return*/ false,
1251 // Get a count of how many bytes are to be pushed on the stack.
1252 unsigned NumBytes = CCInfo.getNextStackOffset();
1254 // For tail calls, memory operands are available in our caller's stack.
1258 // Adjust the stack pointer for the new arguments...
1259 // These operations are automatically eliminated by the prolog/epilog pass
1261 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1263 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1265 RegsToPassVector RegsToPass;
1266 SmallVector<SDValue, 8> MemOpChains;
1268 // Walk the register/memloc assignments, inserting copies/loads. In the case
1269 // of tail call optimization, arguments are handled later.
1270 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1272 ++i, ++realArgIdx) {
1273 CCValAssign &VA = ArgLocs[i];
1274 SDValue Arg = OutVals[realArgIdx];
1275 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1276 bool isByVal = Flags.isByVal();
1278 // Promote the value if needed.
1279 switch (VA.getLocInfo()) {
1280 default: llvm_unreachable("Unknown loc info!");
1281 case CCValAssign::Full: break;
1282 case CCValAssign::SExt:
1283 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1285 case CCValAssign::ZExt:
1286 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1288 case CCValAssign::AExt:
1289 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1291 case CCValAssign::BCvt:
1292 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1296 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1297 if (VA.needsCustom()) {
1298 if (VA.getLocVT() == MVT::v2f64) {
1299 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1300 DAG.getConstant(0, MVT::i32));
1301 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1302 DAG.getConstant(1, MVT::i32));
1304 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1305 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1307 VA = ArgLocs[++i]; // skip ahead to next loc
1308 if (VA.isRegLoc()) {
1309 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1310 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1312 assert(VA.isMemLoc());
1314 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1315 dl, DAG, VA, Flags));
1318 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1319 StackPtr, MemOpChains, Flags);
1321 } else if (VA.isRegLoc()) {
1322 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1323 } else if (isByVal) {
1324 assert(VA.isMemLoc());
1325 unsigned offset = 0;
1327 // True if this byval aggregate will be split between registers
1329 if (CCInfo.isFirstByValRegValid()) {
1330 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1332 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) {
1333 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1334 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1335 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1336 MachinePointerInfo(),
1338 MemOpChains.push_back(Load.getValue(1));
1339 RegsToPass.push_back(std::make_pair(j, Load));
1341 offset = ARM::R4 - CCInfo.getFirstByValReg();
1342 CCInfo.clearFirstByValReg();
1345 unsigned LocMemOffset = VA.getLocMemOffset();
1346 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1347 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1349 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1350 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1351 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1353 // TODO: Disable AlwaysInline when it becomes possible
1354 // to emit a nested call sequence.
1355 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
1356 Flags.getByValAlign(),
1357 /*isVolatile=*/false,
1358 /*AlwaysInline=*/true,
1359 MachinePointerInfo(0),
1360 MachinePointerInfo(0)));
1362 } else if (!IsSibCall) {
1363 assert(VA.isMemLoc());
1365 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1366 dl, DAG, VA, Flags));
1370 if (!MemOpChains.empty())
1371 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1372 &MemOpChains[0], MemOpChains.size());
1374 // Build a sequence of copy-to-reg nodes chained together with token chain
1375 // and flag operands which copy the outgoing args into the appropriate regs.
1377 // Tail call byval lowering might overwrite argument registers so in case of
1378 // tail call optimization the copies to registers are lowered later.
1380 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1381 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1382 RegsToPass[i].second, InFlag);
1383 InFlag = Chain.getValue(1);
1386 // For tail calls lower the arguments to the 'real' stack slot.
1388 // Force all the incoming stack arguments to be loaded from the stack
1389 // before any new outgoing arguments are stored to the stack, because the
1390 // outgoing stack slots may alias the incoming argument stack slots, and
1391 // the alias isn't otherwise explicit. This is slightly more conservative
1392 // than necessary, because it means that each store effectively depends
1393 // on every argument instead of just those arguments it would clobber.
1395 // Do not flag preceding copytoreg stuff together with the following stuff.
1397 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1398 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1399 RegsToPass[i].second, InFlag);
1400 InFlag = Chain.getValue(1);
1405 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1406 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1407 // node so that legalize doesn't hack it.
1408 bool isDirect = false;
1409 bool isARMFunc = false;
1410 bool isLocalARMFunc = false;
1411 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1413 if (EnableARMLongCalls) {
1414 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1415 && "long-calls with non-static relocation model!");
1416 // Handle a global address or an external symbol. If it's not one of
1417 // those, the target's already in a register, so we don't need to do
1419 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1420 const GlobalValue *GV = G->getGlobal();
1421 // Create a constant pool entry for the callee address
1422 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1423 ARMConstantPoolValue *CPV =
1424 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1426 // Get the address of the callee into a register
1427 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1428 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1429 Callee = DAG.getLoad(getPointerTy(), dl,
1430 DAG.getEntryNode(), CPAddr,
1431 MachinePointerInfo::getConstantPool(),
1433 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1434 const char *Sym = S->getSymbol();
1436 // Create a constant pool entry for the callee address
1437 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1438 ARMConstantPoolValue *CPV =
1439 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1440 ARMPCLabelIndex, 0);
1441 // Get the address of the callee into a register
1442 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1443 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1444 Callee = DAG.getLoad(getPointerTy(), dl,
1445 DAG.getEntryNode(), CPAddr,
1446 MachinePointerInfo::getConstantPool(),
1449 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1450 const GlobalValue *GV = G->getGlobal();
1452 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1453 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1454 getTargetMachine().getRelocationModel() != Reloc::Static;
1455 isARMFunc = !Subtarget->isThumb() || isStub;
1456 // ARM call to a local ARM function is predicable.
1457 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1458 // tBX takes a register source operand.
1459 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1460 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1461 ARMConstantPoolValue *CPV =
1462 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4);
1463 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1464 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1465 Callee = DAG.getLoad(getPointerTy(), dl,
1466 DAG.getEntryNode(), CPAddr,
1467 MachinePointerInfo::getConstantPool(),
1469 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1470 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1471 getPointerTy(), Callee, PICLabel);
1473 // On ELF targets for PIC code, direct calls should go through the PLT
1474 unsigned OpFlags = 0;
1475 if (Subtarget->isTargetELF() &&
1476 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1477 OpFlags = ARMII::MO_PLT;
1478 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1480 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1482 bool isStub = Subtarget->isTargetDarwin() &&
1483 getTargetMachine().getRelocationModel() != Reloc::Static;
1484 isARMFunc = !Subtarget->isThumb() || isStub;
1485 // tBX takes a register source operand.
1486 const char *Sym = S->getSymbol();
1487 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1488 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1489 ARMConstantPoolValue *CPV =
1490 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1491 ARMPCLabelIndex, 4);
1492 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1493 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1494 Callee = DAG.getLoad(getPointerTy(), dl,
1495 DAG.getEntryNode(), CPAddr,
1496 MachinePointerInfo::getConstantPool(),
1498 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1499 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1500 getPointerTy(), Callee, PICLabel);
1502 unsigned OpFlags = 0;
1503 // On ELF targets for PIC code, direct calls should go through the PLT
1504 if (Subtarget->isTargetELF() &&
1505 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1506 OpFlags = ARMII::MO_PLT;
1507 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1511 // FIXME: handle tail calls differently.
1513 if (Subtarget->isThumb()) {
1514 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1515 CallOpc = ARMISD::CALL_NOLINK;
1517 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1519 CallOpc = (isDirect || Subtarget->hasV5TOps())
1520 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1521 : ARMISD::CALL_NOLINK;
1524 std::vector<SDValue> Ops;
1525 Ops.push_back(Chain);
1526 Ops.push_back(Callee);
1528 // Add argument registers to the end of the list so that they are known live
1530 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1531 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1532 RegsToPass[i].second.getValueType()));
1534 if (InFlag.getNode())
1535 Ops.push_back(InFlag);
1537 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1539 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1541 // Returns a chain and a flag for retval copy to use.
1542 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1543 InFlag = Chain.getValue(1);
1545 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1546 DAG.getIntPtrConstant(0, true), InFlag);
1548 InFlag = Chain.getValue(1);
1550 // Handle result values, copying them out of physregs into vregs that we
1552 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1556 /// HandleByVal - Every parameter *after* a byval parameter is passed
1557 /// on the stack. Remember the next parameter register to allocate,
1558 /// and then confiscate the rest of the parameter registers to insure
1561 llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const {
1562 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1563 assert((State->getCallOrPrologue() == Prologue ||
1564 State->getCallOrPrologue() == Call) &&
1565 "unhandled ParmContext");
1566 if ((!State->isFirstByValRegValid()) &&
1567 (ARM::R0 <= reg) && (reg <= ARM::R3)) {
1568 State->setFirstByValReg(reg);
1569 // At a call site, a byval parameter that is split between
1570 // registers and memory needs its size truncated here. In a
1571 // function prologue, such byval parameters are reassembled in
1572 // memory, and are not truncated.
1573 if (State->getCallOrPrologue() == Call) {
1574 unsigned excess = 4 * (ARM::R4 - reg);
1575 assert(size >= excess && "expected larger existing stack allocation");
1579 // Confiscate any remaining parameter registers to preclude their
1580 // assignment to subsequent parameters.
1581 while (State->AllocateReg(GPRArgRegs, 4))
1585 /// MatchingStackOffset - Return true if the given stack call argument is
1586 /// already available in the same position (relatively) of the caller's
1587 /// incoming argument stack.
1589 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1590 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1591 const ARMInstrInfo *TII) {
1592 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1594 if (Arg.getOpcode() == ISD::CopyFromReg) {
1595 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1596 if (!TargetRegisterInfo::isVirtualRegister(VR))
1598 MachineInstr *Def = MRI->getVRegDef(VR);
1601 if (!Flags.isByVal()) {
1602 if (!TII->isLoadFromStackSlot(Def, FI))
1607 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1608 if (Flags.isByVal())
1609 // ByVal argument is passed in as a pointer but it's now being
1610 // dereferenced. e.g.
1611 // define @foo(%struct.X* %A) {
1612 // tail call @bar(%struct.X* byval %A)
1615 SDValue Ptr = Ld->getBasePtr();
1616 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1619 FI = FINode->getIndex();
1623 assert(FI != INT_MAX);
1624 if (!MFI->isFixedObjectIndex(FI))
1626 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1629 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1630 /// for tail call optimization. Targets which want to do tail call
1631 /// optimization should implement this function.
1633 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1634 CallingConv::ID CalleeCC,
1636 bool isCalleeStructRet,
1637 bool isCallerStructRet,
1638 const SmallVectorImpl<ISD::OutputArg> &Outs,
1639 const SmallVectorImpl<SDValue> &OutVals,
1640 const SmallVectorImpl<ISD::InputArg> &Ins,
1641 SelectionDAG& DAG) const {
1642 const Function *CallerF = DAG.getMachineFunction().getFunction();
1643 CallingConv::ID CallerCC = CallerF->getCallingConv();
1644 bool CCMatch = CallerCC == CalleeCC;
1646 // Look for obvious safe cases to perform tail call optimization that do not
1647 // require ABI changes. This is what gcc calls sibcall.
1649 // Do not sibcall optimize vararg calls unless the call site is not passing
1651 if (isVarArg && !Outs.empty())
1654 // Also avoid sibcall optimization if either caller or callee uses struct
1655 // return semantics.
1656 if (isCalleeStructRet || isCallerStructRet)
1659 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1660 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1661 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1662 // support in the assembler and linker to be used. This would need to be
1663 // fixed to fully support tail calls in Thumb1.
1665 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1666 // LR. This means if we need to reload LR, it takes an extra instructions,
1667 // which outweighs the value of the tail call; but here we don't know yet
1668 // whether LR is going to be used. Probably the right approach is to
1669 // generate the tail call here and turn it back into CALL/RET in
1670 // emitEpilogue if LR is used.
1672 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1673 // but we need to make sure there are enough registers; the only valid
1674 // registers are the 4 used for parameters. We don't currently do this
1676 if (Subtarget->isThumb1Only())
1679 // If the calling conventions do not match, then we'd better make sure the
1680 // results are returned in the same way as what the caller expects.
1682 SmallVector<CCValAssign, 16> RVLocs1;
1683 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1684 getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
1685 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1687 SmallVector<CCValAssign, 16> RVLocs2;
1688 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1689 getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
1690 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1692 if (RVLocs1.size() != RVLocs2.size())
1694 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1695 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1697 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1699 if (RVLocs1[i].isRegLoc()) {
1700 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1703 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1709 // If the callee takes no arguments then go on to check the results of the
1711 if (!Outs.empty()) {
1712 // Check if stack adjustment is needed. For now, do not do this if any
1713 // argument is passed on the stack.
1714 SmallVector<CCValAssign, 16> ArgLocs;
1715 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
1716 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1717 CCInfo.AnalyzeCallOperands(Outs,
1718 CCAssignFnForNode(CalleeCC, false, isVarArg));
1719 if (CCInfo.getNextStackOffset()) {
1720 MachineFunction &MF = DAG.getMachineFunction();
1722 // Check if the arguments are already laid out in the right way as
1723 // the caller's fixed stack objects.
1724 MachineFrameInfo *MFI = MF.getFrameInfo();
1725 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1726 const ARMInstrInfo *TII =
1727 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1728 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1730 ++i, ++realArgIdx) {
1731 CCValAssign &VA = ArgLocs[i];
1732 EVT RegVT = VA.getLocVT();
1733 SDValue Arg = OutVals[realArgIdx];
1734 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1735 if (VA.getLocInfo() == CCValAssign::Indirect)
1737 if (VA.needsCustom()) {
1738 // f64 and vector types are split into multiple registers or
1739 // register/stack-slot combinations. The types will not match
1740 // the registers; give up on memory f64 refs until we figure
1741 // out what to do about this.
1744 if (!ArgLocs[++i].isRegLoc())
1746 if (RegVT == MVT::v2f64) {
1747 if (!ArgLocs[++i].isRegLoc())
1749 if (!ArgLocs[++i].isRegLoc())
1752 } else if (!VA.isRegLoc()) {
1753 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1765 ARMTargetLowering::LowerReturn(SDValue Chain,
1766 CallingConv::ID CallConv, bool isVarArg,
1767 const SmallVectorImpl<ISD::OutputArg> &Outs,
1768 const SmallVectorImpl<SDValue> &OutVals,
1769 DebugLoc dl, SelectionDAG &DAG) const {
1771 // CCValAssign - represent the assignment of the return value to a location.
1772 SmallVector<CCValAssign, 16> RVLocs;
1774 // CCState - Info about the registers and stack slots.
1775 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1776 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1778 // Analyze outgoing return values.
1779 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1782 // If this is the first return lowered for this function, add
1783 // the regs to the liveout set for the function.
1784 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1785 for (unsigned i = 0; i != RVLocs.size(); ++i)
1786 if (RVLocs[i].isRegLoc())
1787 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1792 // Copy the result values into the output registers.
1793 for (unsigned i = 0, realRVLocIdx = 0;
1795 ++i, ++realRVLocIdx) {
1796 CCValAssign &VA = RVLocs[i];
1797 assert(VA.isRegLoc() && "Can only return in registers!");
1799 SDValue Arg = OutVals[realRVLocIdx];
1801 switch (VA.getLocInfo()) {
1802 default: llvm_unreachable("Unknown loc info!");
1803 case CCValAssign::Full: break;
1804 case CCValAssign::BCvt:
1805 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1809 if (VA.needsCustom()) {
1810 if (VA.getLocVT() == MVT::v2f64) {
1811 // Extract the first half and return it in two registers.
1812 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1813 DAG.getConstant(0, MVT::i32));
1814 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1815 DAG.getVTList(MVT::i32, MVT::i32), Half);
1817 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1818 Flag = Chain.getValue(1);
1819 VA = RVLocs[++i]; // skip ahead to next loc
1820 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1821 HalfGPRs.getValue(1), Flag);
1822 Flag = Chain.getValue(1);
1823 VA = RVLocs[++i]; // skip ahead to next loc
1825 // Extract the 2nd half and fall through to handle it as an f64 value.
1826 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1827 DAG.getConstant(1, MVT::i32));
1829 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1831 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1832 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1833 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1834 Flag = Chain.getValue(1);
1835 VA = RVLocs[++i]; // skip ahead to next loc
1836 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1839 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1841 // Guarantee that all emitted copies are
1842 // stuck together, avoiding something bad.
1843 Flag = Chain.getValue(1);
1848 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1850 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1855 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1856 if (N->getNumValues() != 1)
1858 if (!N->hasNUsesOfValue(1, 0))
1861 unsigned NumCopies = 0;
1863 SDNode *Use = *N->use_begin();
1864 if (Use->getOpcode() == ISD::CopyToReg) {
1865 Copies[NumCopies++] = Use;
1866 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1867 // f64 returned in a pair of GPRs.
1868 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1870 if (UI->getOpcode() != ISD::CopyToReg)
1872 Copies[UI.getUse().getResNo()] = *UI;
1875 } else if (Use->getOpcode() == ISD::BITCAST) {
1876 // f32 returned in a single GPR.
1877 if (!Use->hasNUsesOfValue(1, 0))
1879 Use = *Use->use_begin();
1880 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1882 Copies[NumCopies++] = Use;
1887 if (NumCopies != 1 && NumCopies != 2)
1890 bool HasRet = false;
1891 for (unsigned i = 0; i < NumCopies; ++i) {
1892 SDNode *Copy = Copies[i];
1893 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1895 if (UI->getOpcode() == ISD::CopyToReg) {
1897 if (Use == Copies[0] || Use == Copies[1])
1901 if (UI->getOpcode() != ARMISD::RET_FLAG)
1910 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1911 if (!EnableARMTailCalls)
1914 if (!CI->isTailCall())
1917 return !Subtarget->isThumb1Only();
1920 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1921 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1922 // one of the above mentioned nodes. It has to be wrapped because otherwise
1923 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1924 // be used to form addressing mode. These wrapped nodes will be selected
1926 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1927 EVT PtrVT = Op.getValueType();
1928 // FIXME there is no actual debug info here
1929 DebugLoc dl = Op.getDebugLoc();
1930 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1932 if (CP->isMachineConstantPoolEntry())
1933 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1934 CP->getAlignment());
1936 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1937 CP->getAlignment());
1938 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1941 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1942 return MachineJumpTableInfo::EK_Inline;
1945 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1946 SelectionDAG &DAG) const {
1947 MachineFunction &MF = DAG.getMachineFunction();
1948 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1949 unsigned ARMPCLabelIndex = 0;
1950 DebugLoc DL = Op.getDebugLoc();
1951 EVT PtrVT = getPointerTy();
1952 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1953 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1955 if (RelocM == Reloc::Static) {
1956 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1958 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1959 ARMPCLabelIndex = AFI->createPICLabelUId();
1960 ARMConstantPoolValue *CPV =
1961 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
1962 ARMCP::CPBlockAddress, PCAdj);
1963 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1965 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1966 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1967 MachinePointerInfo::getConstantPool(),
1969 if (RelocM == Reloc::Static)
1971 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1972 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1975 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1977 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1978 SelectionDAG &DAG) const {
1979 DebugLoc dl = GA->getDebugLoc();
1980 EVT PtrVT = getPointerTy();
1981 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1982 MachineFunction &MF = DAG.getMachineFunction();
1983 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1984 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1985 ARMConstantPoolValue *CPV =
1986 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
1987 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1988 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1989 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1990 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1991 MachinePointerInfo::getConstantPool(),
1993 SDValue Chain = Argument.getValue(1);
1995 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1996 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1998 // call __tls_get_addr.
2001 Entry.Node = Argument;
2002 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2003 Args.push_back(Entry);
2004 // FIXME: is there useful debug info available here?
2005 std::pair<SDValue, SDValue> CallResult =
2006 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()),
2007 false, false, false, false,
2008 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
2009 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
2010 return CallResult.first;
2013 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2014 // "local exec" model.
2016 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2017 SelectionDAG &DAG) const {
2018 const GlobalValue *GV = GA->getGlobal();
2019 DebugLoc dl = GA->getDebugLoc();
2021 SDValue Chain = DAG.getEntryNode();
2022 EVT PtrVT = getPointerTy();
2023 // Get the Thread Pointer
2024 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2026 if (GV->isDeclaration()) {
2027 MachineFunction &MF = DAG.getMachineFunction();
2028 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2029 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2030 // Initial exec model.
2031 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2032 ARMConstantPoolValue *CPV =
2033 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2034 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2036 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2037 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2038 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2039 MachinePointerInfo::getConstantPool(),
2041 Chain = Offset.getValue(1);
2043 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2044 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2046 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2047 MachinePointerInfo::getConstantPool(),
2051 ARMConstantPoolValue *CPV =
2052 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2053 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2054 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2055 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2056 MachinePointerInfo::getConstantPool(),
2060 // The address of the thread local variable is the add of the thread
2061 // pointer with the offset of the variable.
2062 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2066 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2067 // TODO: implement the "local dynamic" model
2068 assert(Subtarget->isTargetELF() &&
2069 "TLS not implemented for non-ELF targets");
2070 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2071 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
2072 // otherwise use the "Local Exec" TLS Model
2073 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
2074 return LowerToTLSGeneralDynamicModel(GA, DAG);
2076 return LowerToTLSExecModels(GA, DAG);
2079 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2080 SelectionDAG &DAG) const {
2081 EVT PtrVT = getPointerTy();
2082 DebugLoc dl = Op.getDebugLoc();
2083 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2084 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2085 if (RelocM == Reloc::PIC_) {
2086 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2087 ARMConstantPoolValue *CPV =
2088 ARMConstantPoolConstant::Create(GV,
2089 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2090 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2091 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2092 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2094 MachinePointerInfo::getConstantPool(),
2096 SDValue Chain = Result.getValue(1);
2097 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2098 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2100 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2101 MachinePointerInfo::getGOT(), false, false, 0);
2105 // If we have T2 ops, we can materialize the address directly via movt/movw
2106 // pair. This is always cheaper.
2107 if (Subtarget->useMovt()) {
2109 // FIXME: Once remat is capable of dealing with instructions with register
2110 // operands, expand this into two nodes.
2111 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2112 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2114 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2115 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2116 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2117 MachinePointerInfo::getConstantPool(),
2122 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2123 SelectionDAG &DAG) const {
2124 EVT PtrVT = getPointerTy();
2125 DebugLoc dl = Op.getDebugLoc();
2126 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2127 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2128 MachineFunction &MF = DAG.getMachineFunction();
2129 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2131 // FIXME: Enable this for static codegen when tool issues are fixed.
2132 if (Subtarget->useMovt() && RelocM != Reloc::Static) {
2134 // FIXME: Once remat is capable of dealing with instructions with register
2135 // operands, expand this into two nodes.
2136 if (RelocM == Reloc::Static)
2137 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2138 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2140 unsigned Wrapper = (RelocM == Reloc::PIC_)
2141 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2142 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2143 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2144 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2145 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2146 MachinePointerInfo::getGOT(), false, false, 0);
2150 unsigned ARMPCLabelIndex = 0;
2152 if (RelocM == Reloc::Static) {
2153 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2155 ARMPCLabelIndex = AFI->createPICLabelUId();
2156 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2157 ARMConstantPoolValue *CPV =
2158 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue,
2160 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2162 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2164 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2165 MachinePointerInfo::getConstantPool(),
2167 SDValue Chain = Result.getValue(1);
2169 if (RelocM == Reloc::PIC_) {
2170 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2171 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2174 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2175 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2181 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2182 SelectionDAG &DAG) const {
2183 assert(Subtarget->isTargetELF() &&
2184 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2185 MachineFunction &MF = DAG.getMachineFunction();
2186 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2187 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2188 EVT PtrVT = getPointerTy();
2189 DebugLoc dl = Op.getDebugLoc();
2190 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2191 ARMConstantPoolValue *CPV =
2192 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2193 ARMPCLabelIndex, PCAdj);
2194 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2195 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2196 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2197 MachinePointerInfo::getConstantPool(),
2199 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2200 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2204 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2206 DebugLoc dl = Op.getDebugLoc();
2207 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2208 Op.getOperand(0), Op.getOperand(1));
2212 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2213 DebugLoc dl = Op.getDebugLoc();
2214 SDValue Val = DAG.getConstant(0, MVT::i32);
2215 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2216 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2217 Op.getOperand(1), Val);
2221 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2222 DebugLoc dl = Op.getDebugLoc();
2223 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2224 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2228 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2229 const ARMSubtarget *Subtarget) const {
2230 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2231 DebugLoc dl = Op.getDebugLoc();
2233 default: return SDValue(); // Don't custom lower most intrinsics.
2234 case Intrinsic::arm_thread_pointer: {
2235 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2236 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2238 case Intrinsic::eh_sjlj_lsda: {
2239 MachineFunction &MF = DAG.getMachineFunction();
2240 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2241 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2242 EVT PtrVT = getPointerTy();
2243 DebugLoc dl = Op.getDebugLoc();
2244 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2246 unsigned PCAdj = (RelocM != Reloc::PIC_)
2247 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2248 ARMConstantPoolValue *CPV =
2249 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2250 ARMCP::CPLSDA, PCAdj);
2251 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2252 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2254 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2255 MachinePointerInfo::getConstantPool(),
2258 if (RelocM == Reloc::PIC_) {
2259 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2260 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2264 case Intrinsic::arm_neon_vmulls:
2265 case Intrinsic::arm_neon_vmullu: {
2266 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2267 ? ARMISD::VMULLs : ARMISD::VMULLu;
2268 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2269 Op.getOperand(1), Op.getOperand(2));
2274 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2275 const ARMSubtarget *Subtarget) {
2276 DebugLoc dl = Op.getDebugLoc();
2277 if (!Subtarget->hasDataBarrier()) {
2278 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2279 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2281 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2282 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2283 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2284 DAG.getConstant(0, MVT::i32));
2287 SDValue Op5 = Op.getOperand(5);
2288 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2289 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2290 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2291 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2293 ARM_MB::MemBOpt DMBOpt;
2294 if (isDeviceBarrier)
2295 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2297 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2298 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2299 DAG.getConstant(DMBOpt, MVT::i32));
2303 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2304 const ARMSubtarget *Subtarget) {
2305 // FIXME: handle "fence singlethread" more efficiently.
2306 DebugLoc dl = Op.getDebugLoc();
2307 if (!Subtarget->hasDataBarrier()) {
2308 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2309 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2311 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2312 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2313 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2314 DAG.getConstant(0, MVT::i32));
2317 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2318 DAG.getConstant(ARM_MB::ISH, MVT::i32));
2321 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2322 const ARMSubtarget *Subtarget) {
2323 // ARM pre v5TE and Thumb1 does not have preload instructions.
2324 if (!(Subtarget->isThumb2() ||
2325 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2326 // Just preserve the chain.
2327 return Op.getOperand(0);
2329 DebugLoc dl = Op.getDebugLoc();
2330 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2332 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2333 // ARMv7 with MP extension has PLDW.
2334 return Op.getOperand(0);
2336 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2337 if (Subtarget->isThumb()) {
2339 isRead = ~isRead & 1;
2340 isData = ~isData & 1;
2343 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2344 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2345 DAG.getConstant(isData, MVT::i32));
2348 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2349 MachineFunction &MF = DAG.getMachineFunction();
2350 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2352 // vastart just stores the address of the VarArgsFrameIndex slot into the
2353 // memory location argument.
2354 DebugLoc dl = Op.getDebugLoc();
2355 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2356 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2357 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2358 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2359 MachinePointerInfo(SV), false, false, 0);
2363 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2364 SDValue &Root, SelectionDAG &DAG,
2365 DebugLoc dl) const {
2366 MachineFunction &MF = DAG.getMachineFunction();
2367 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2369 TargetRegisterClass *RC;
2370 if (AFI->isThumb1OnlyFunction())
2371 RC = ARM::tGPRRegisterClass;
2373 RC = ARM::GPRRegisterClass;
2375 // Transform the arguments stored in physical registers into virtual ones.
2376 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2377 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2380 if (NextVA.isMemLoc()) {
2381 MachineFrameInfo *MFI = MF.getFrameInfo();
2382 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2384 // Create load node to retrieve arguments from the stack.
2385 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2386 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2387 MachinePointerInfo::getFixedStack(FI),
2390 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2391 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2394 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2398 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2399 unsigned &VARegSize, unsigned &VARegSaveSize)
2402 if (CCInfo.isFirstByValRegValid())
2403 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
2405 unsigned int firstUnalloced;
2406 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2407 sizeof(GPRArgRegs) /
2408 sizeof(GPRArgRegs[0]));
2409 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2412 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2413 VARegSize = NumGPRs * 4;
2414 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2417 // The remaining GPRs hold either the beginning of variable-argument
2418 // data, or the beginning of an aggregate passed by value (usuall
2419 // byval). Either way, we allocate stack slots adjacent to the data
2420 // provided by our caller, and store the unallocated registers there.
2421 // If this is a variadic function, the va_list pointer will begin with
2422 // these values; otherwise, this reassembles a (byval) structure that
2423 // was split between registers and memory.
2425 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2426 DebugLoc dl, SDValue &Chain,
2427 unsigned ArgOffset) const {
2428 MachineFunction &MF = DAG.getMachineFunction();
2429 MachineFrameInfo *MFI = MF.getFrameInfo();
2430 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2431 unsigned firstRegToSaveIndex;
2432 if (CCInfo.isFirstByValRegValid())
2433 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
2435 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2436 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2439 unsigned VARegSize, VARegSaveSize;
2440 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2441 if (VARegSaveSize) {
2442 // If this function is vararg, store any remaining integer argument regs
2443 // to their spots on the stack so that they may be loaded by deferencing
2444 // the result of va_next.
2445 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2446 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize,
2447 ArgOffset + VARegSaveSize
2450 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2453 SmallVector<SDValue, 4> MemOps;
2454 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) {
2455 TargetRegisterClass *RC;
2456 if (AFI->isThumb1OnlyFunction())
2457 RC = ARM::tGPRRegisterClass;
2459 RC = ARM::GPRRegisterClass;
2461 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2462 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2464 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2465 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2467 MemOps.push_back(Store);
2468 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2469 DAG.getConstant(4, getPointerTy()));
2471 if (!MemOps.empty())
2472 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2473 &MemOps[0], MemOps.size());
2475 // This will point to the next argument passed via stack.
2476 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2480 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2481 CallingConv::ID CallConv, bool isVarArg,
2482 const SmallVectorImpl<ISD::InputArg>
2484 DebugLoc dl, SelectionDAG &DAG,
2485 SmallVectorImpl<SDValue> &InVals)
2487 MachineFunction &MF = DAG.getMachineFunction();
2488 MachineFrameInfo *MFI = MF.getFrameInfo();
2490 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2492 // Assign locations to all of the incoming arguments.
2493 SmallVector<CCValAssign, 16> ArgLocs;
2494 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2495 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2496 CCInfo.AnalyzeFormalArguments(Ins,
2497 CCAssignFnForNode(CallConv, /* Return*/ false,
2500 SmallVector<SDValue, 16> ArgValues;
2501 int lastInsIndex = -1;
2504 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2505 CCValAssign &VA = ArgLocs[i];
2507 // Arguments stored in registers.
2508 if (VA.isRegLoc()) {
2509 EVT RegVT = VA.getLocVT();
2511 if (VA.needsCustom()) {
2512 // f64 and vector types are split up into multiple registers or
2513 // combinations of registers and stack slots.
2514 if (VA.getLocVT() == MVT::v2f64) {
2515 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2517 VA = ArgLocs[++i]; // skip ahead to next loc
2519 if (VA.isMemLoc()) {
2520 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2521 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2522 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2523 MachinePointerInfo::getFixedStack(FI),
2526 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2529 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2530 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2531 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2532 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2533 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2535 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2538 TargetRegisterClass *RC;
2540 if (RegVT == MVT::f32)
2541 RC = ARM::SPRRegisterClass;
2542 else if (RegVT == MVT::f64)
2543 RC = ARM::DPRRegisterClass;
2544 else if (RegVT == MVT::v2f64)
2545 RC = ARM::QPRRegisterClass;
2546 else if (RegVT == MVT::i32)
2547 RC = (AFI->isThumb1OnlyFunction() ?
2548 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2550 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2552 // Transform the arguments in physical registers into virtual ones.
2553 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2554 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2557 // If this is an 8 or 16-bit value, it is really passed promoted
2558 // to 32 bits. Insert an assert[sz]ext to capture this, then
2559 // truncate to the right size.
2560 switch (VA.getLocInfo()) {
2561 default: llvm_unreachable("Unknown loc info!");
2562 case CCValAssign::Full: break;
2563 case CCValAssign::BCvt:
2564 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2566 case CCValAssign::SExt:
2567 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2568 DAG.getValueType(VA.getValVT()));
2569 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2571 case CCValAssign::ZExt:
2572 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2573 DAG.getValueType(VA.getValVT()));
2574 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2578 InVals.push_back(ArgValue);
2580 } else { // VA.isRegLoc()
2583 assert(VA.isMemLoc());
2584 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2586 int index = ArgLocs[i].getValNo();
2588 // Some Ins[] entries become multiple ArgLoc[] entries.
2589 // Process them only once.
2590 if (index != lastInsIndex)
2592 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2593 // FIXME: For now, all byval parameter objects are marked mutable.
2594 // This can be changed with more analysis.
2595 // In case of tail call optimization mark all arguments mutable.
2596 // Since they could be overwritten by lowering of arguments in case of
2598 if (Flags.isByVal()) {
2599 unsigned VARegSize, VARegSaveSize;
2600 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2601 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0);
2602 unsigned Bytes = Flags.getByValSize() - VARegSize;
2603 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2604 int FI = MFI->CreateFixedObject(Bytes,
2605 VA.getLocMemOffset(), false);
2606 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2608 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2609 VA.getLocMemOffset(), true);
2611 // Create load nodes to retrieve arguments from the stack.
2612 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2613 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2614 MachinePointerInfo::getFixedStack(FI),
2617 lastInsIndex = index;
2624 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset());
2629 /// isFloatingPointZero - Return true if this is +0.0.
2630 static bool isFloatingPointZero(SDValue Op) {
2631 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2632 return CFP->getValueAPF().isPosZero();
2633 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2634 // Maybe this has already been legalized into the constant pool?
2635 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2636 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2637 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2638 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2639 return CFP->getValueAPF().isPosZero();
2645 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2646 /// the given operands.
2648 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2649 SDValue &ARMcc, SelectionDAG &DAG,
2650 DebugLoc dl) const {
2651 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2652 unsigned C = RHSC->getZExtValue();
2653 if (!isLegalICmpImmediate(C)) {
2654 // Constant does not fit, try adjusting it by one?
2659 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2660 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2661 RHS = DAG.getConstant(C-1, MVT::i32);
2666 if (C != 0 && isLegalICmpImmediate(C-1)) {
2667 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2668 RHS = DAG.getConstant(C-1, MVT::i32);
2673 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2674 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2675 RHS = DAG.getConstant(C+1, MVT::i32);
2680 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2681 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2682 RHS = DAG.getConstant(C+1, MVT::i32);
2689 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2690 ARMISD::NodeType CompareType;
2693 CompareType = ARMISD::CMP;
2698 CompareType = ARMISD::CMPZ;
2701 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2702 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2705 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2707 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2708 DebugLoc dl) const {
2710 if (!isFloatingPointZero(RHS))
2711 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2713 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2714 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2717 /// duplicateCmp - Glue values can have only one use, so this function
2718 /// duplicates a comparison node.
2720 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2721 unsigned Opc = Cmp.getOpcode();
2722 DebugLoc DL = Cmp.getDebugLoc();
2723 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2724 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2726 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2727 Cmp = Cmp.getOperand(0);
2728 Opc = Cmp.getOpcode();
2729 if (Opc == ARMISD::CMPFP)
2730 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2732 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2733 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2735 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2738 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2739 SDValue Cond = Op.getOperand(0);
2740 SDValue SelectTrue = Op.getOperand(1);
2741 SDValue SelectFalse = Op.getOperand(2);
2742 DebugLoc dl = Op.getDebugLoc();
2746 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2747 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2749 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2750 const ConstantSDNode *CMOVTrue =
2751 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2752 const ConstantSDNode *CMOVFalse =
2753 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2755 if (CMOVTrue && CMOVFalse) {
2756 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2757 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2761 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2763 False = SelectFalse;
2764 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2769 if (True.getNode() && False.getNode()) {
2770 EVT VT = Op.getValueType();
2771 SDValue ARMcc = Cond.getOperand(2);
2772 SDValue CCR = Cond.getOperand(3);
2773 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2774 assert(True.getValueType() == VT);
2775 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2780 return DAG.getSelectCC(dl, Cond,
2781 DAG.getConstant(0, Cond.getValueType()),
2782 SelectTrue, SelectFalse, ISD::SETNE);
2785 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2786 EVT VT = Op.getValueType();
2787 SDValue LHS = Op.getOperand(0);
2788 SDValue RHS = Op.getOperand(1);
2789 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2790 SDValue TrueVal = Op.getOperand(2);
2791 SDValue FalseVal = Op.getOperand(3);
2792 DebugLoc dl = Op.getDebugLoc();
2794 if (LHS.getValueType() == MVT::i32) {
2796 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2797 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2798 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2801 ARMCC::CondCodes CondCode, CondCode2;
2802 FPCCToARMCC(CC, CondCode, CondCode2);
2804 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2805 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2806 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2807 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2809 if (CondCode2 != ARMCC::AL) {
2810 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2811 // FIXME: Needs another CMP because flag can have but one use.
2812 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2813 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2814 Result, TrueVal, ARMcc2, CCR, Cmp2);
2819 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2820 /// to morph to an integer compare sequence.
2821 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2822 const ARMSubtarget *Subtarget) {
2823 SDNode *N = Op.getNode();
2824 if (!N->hasOneUse())
2825 // Otherwise it requires moving the value from fp to integer registers.
2827 if (!N->getNumValues())
2829 EVT VT = Op.getValueType();
2830 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2831 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2832 // vmrs are very slow, e.g. cortex-a8.
2835 if (isFloatingPointZero(Op)) {
2839 return ISD::isNormalLoad(N);
2842 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2843 if (isFloatingPointZero(Op))
2844 return DAG.getConstant(0, MVT::i32);
2846 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2847 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2848 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2849 Ld->isVolatile(), Ld->isNonTemporal(),
2850 Ld->getAlignment());
2852 llvm_unreachable("Unknown VFP cmp argument!");
2855 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2856 SDValue &RetVal1, SDValue &RetVal2) {
2857 if (isFloatingPointZero(Op)) {
2858 RetVal1 = DAG.getConstant(0, MVT::i32);
2859 RetVal2 = DAG.getConstant(0, MVT::i32);
2863 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2864 SDValue Ptr = Ld->getBasePtr();
2865 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2866 Ld->getChain(), Ptr,
2867 Ld->getPointerInfo(),
2868 Ld->isVolatile(), Ld->isNonTemporal(),
2869 Ld->getAlignment());
2871 EVT PtrType = Ptr.getValueType();
2872 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2873 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2874 PtrType, Ptr, DAG.getConstant(4, PtrType));
2875 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2876 Ld->getChain(), NewPtr,
2877 Ld->getPointerInfo().getWithOffset(4),
2878 Ld->isVolatile(), Ld->isNonTemporal(),
2883 llvm_unreachable("Unknown VFP cmp argument!");
2886 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2887 /// f32 and even f64 comparisons to integer ones.
2889 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2890 SDValue Chain = Op.getOperand(0);
2891 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2892 SDValue LHS = Op.getOperand(2);
2893 SDValue RHS = Op.getOperand(3);
2894 SDValue Dest = Op.getOperand(4);
2895 DebugLoc dl = Op.getDebugLoc();
2897 bool SeenZero = false;
2898 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2899 canChangeToInt(RHS, SeenZero, Subtarget) &&
2900 // If one of the operand is zero, it's safe to ignore the NaN case since
2901 // we only care about equality comparisons.
2902 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2903 // If unsafe fp math optimization is enabled and there are no other uses of
2904 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2905 // to an integer comparison.
2906 if (CC == ISD::SETOEQ)
2908 else if (CC == ISD::SETUNE)
2912 if (LHS.getValueType() == MVT::f32) {
2913 LHS = bitcastf32Toi32(LHS, DAG);
2914 RHS = bitcastf32Toi32(RHS, DAG);
2915 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2916 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2917 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2918 Chain, Dest, ARMcc, CCR, Cmp);
2923 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2924 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2925 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2926 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2927 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2928 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2929 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2935 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2936 SDValue Chain = Op.getOperand(0);
2937 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2938 SDValue LHS = Op.getOperand(2);
2939 SDValue RHS = Op.getOperand(3);
2940 SDValue Dest = Op.getOperand(4);
2941 DebugLoc dl = Op.getDebugLoc();
2943 if (LHS.getValueType() == MVT::i32) {
2945 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2946 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2947 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2948 Chain, Dest, ARMcc, CCR, Cmp);
2951 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2954 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2955 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2956 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2957 if (Result.getNode())
2961 ARMCC::CondCodes CondCode, CondCode2;
2962 FPCCToARMCC(CC, CondCode, CondCode2);
2964 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2965 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2966 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2967 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2968 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2969 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2970 if (CondCode2 != ARMCC::AL) {
2971 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2972 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2973 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2978 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2979 SDValue Chain = Op.getOperand(0);
2980 SDValue Table = Op.getOperand(1);
2981 SDValue Index = Op.getOperand(2);
2982 DebugLoc dl = Op.getDebugLoc();
2984 EVT PTy = getPointerTy();
2985 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2986 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2987 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2988 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2989 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2990 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2991 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2992 if (Subtarget->isThumb2()) {
2993 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2994 // which does another jump to the destination. This also makes it easier
2995 // to translate it to TBB / TBH later.
2996 // FIXME: This might not work if the function is extremely large.
2997 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2998 Addr, Op.getOperand(2), JTI, UId);
3000 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3001 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3002 MachinePointerInfo::getJumpTable(),
3004 Chain = Addr.getValue(1);
3005 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3006 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3008 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3009 MachinePointerInfo::getJumpTable(), false, false, 0);
3010 Chain = Addr.getValue(1);
3011 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3015 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3016 DebugLoc dl = Op.getDebugLoc();
3019 switch (Op.getOpcode()) {
3021 assert(0 && "Invalid opcode!");
3022 case ISD::FP_TO_SINT:
3023 Opc = ARMISD::FTOSI;
3025 case ISD::FP_TO_UINT:
3026 Opc = ARMISD::FTOUI;
3029 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3030 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3033 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3034 EVT VT = Op.getValueType();
3035 DebugLoc dl = Op.getDebugLoc();
3037 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3038 "Invalid type for custom lowering!");
3039 if (VT != MVT::v4f32)
3040 return DAG.UnrollVectorOp(Op.getNode());
3044 switch (Op.getOpcode()) {
3046 assert(0 && "Invalid opcode!");
3047 case ISD::SINT_TO_FP:
3048 CastOpc = ISD::SIGN_EXTEND;
3049 Opc = ISD::SINT_TO_FP;
3051 case ISD::UINT_TO_FP:
3052 CastOpc = ISD::ZERO_EXTEND;
3053 Opc = ISD::UINT_TO_FP;
3057 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3058 return DAG.getNode(Opc, dl, VT, Op);
3061 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3062 EVT VT = Op.getValueType();
3064 return LowerVectorINT_TO_FP(Op, DAG);
3066 DebugLoc dl = Op.getDebugLoc();
3069 switch (Op.getOpcode()) {
3071 assert(0 && "Invalid opcode!");
3072 case ISD::SINT_TO_FP:
3073 Opc = ARMISD::SITOF;
3075 case ISD::UINT_TO_FP:
3076 Opc = ARMISD::UITOF;
3080 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3081 return DAG.getNode(Opc, dl, VT, Op);
3084 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3085 // Implement fcopysign with a fabs and a conditional fneg.
3086 SDValue Tmp0 = Op.getOperand(0);
3087 SDValue Tmp1 = Op.getOperand(1);
3088 DebugLoc dl = Op.getDebugLoc();
3089 EVT VT = Op.getValueType();
3090 EVT SrcVT = Tmp1.getValueType();
3091 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3092 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3093 bool UseNEON = !InGPR && Subtarget->hasNEON();
3096 // Use VBSL to copy the sign bit.
3097 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3098 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3099 DAG.getTargetConstant(EncodedVal, MVT::i32));
3100 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3102 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3103 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3104 DAG.getConstant(32, MVT::i32));
3105 else /*if (VT == MVT::f32)*/
3106 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3107 if (SrcVT == MVT::f32) {
3108 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3110 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3111 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3112 DAG.getConstant(32, MVT::i32));
3113 } else if (VT == MVT::f32)
3114 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3115 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3116 DAG.getConstant(32, MVT::i32));
3117 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3118 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3120 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3122 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3123 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3124 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3126 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3127 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3128 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3129 if (VT == MVT::f32) {
3130 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3131 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3132 DAG.getConstant(0, MVT::i32));
3134 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3140 // Bitcast operand 1 to i32.
3141 if (SrcVT == MVT::f64)
3142 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3143 &Tmp1, 1).getValue(1);
3144 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3146 // Or in the signbit with integer operations.
3147 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3148 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3149 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3150 if (VT == MVT::f32) {
3151 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3152 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3153 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3154 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3157 // f64: Or the high part with signbit and then combine two parts.
3158 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3160 SDValue Lo = Tmp0.getValue(0);
3161 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3162 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3163 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3166 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3167 MachineFunction &MF = DAG.getMachineFunction();
3168 MachineFrameInfo *MFI = MF.getFrameInfo();
3169 MFI->setReturnAddressIsTaken(true);
3171 EVT VT = Op.getValueType();
3172 DebugLoc dl = Op.getDebugLoc();
3173 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3175 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3176 SDValue Offset = DAG.getConstant(4, MVT::i32);
3177 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3178 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3179 MachinePointerInfo(), false, false, 0);
3182 // Return LR, which contains the return address. Mark it an implicit live-in.
3183 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3184 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3187 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3188 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3189 MFI->setFrameAddressIsTaken(true);
3191 EVT VT = Op.getValueType();
3192 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3193 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3194 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3195 ? ARM::R7 : ARM::R11;
3196 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3198 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3199 MachinePointerInfo(),
3204 /// ExpandBITCAST - If the target supports VFP, this function is called to
3205 /// expand a bit convert where either the source or destination type is i64 to
3206 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3207 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3208 /// vectors), since the legalizer won't know what to do with that.
3209 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3210 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3211 DebugLoc dl = N->getDebugLoc();
3212 SDValue Op = N->getOperand(0);
3214 // This function is only supposed to be called for i64 types, either as the
3215 // source or destination of the bit convert.
3216 EVT SrcVT = Op.getValueType();
3217 EVT DstVT = N->getValueType(0);
3218 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3219 "ExpandBITCAST called for non-i64 type");
3221 // Turn i64->f64 into VMOVDRR.
3222 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3223 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3224 DAG.getConstant(0, MVT::i32));
3225 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3226 DAG.getConstant(1, MVT::i32));
3227 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3228 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3231 // Turn f64->i64 into VMOVRRD.
3232 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3233 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3234 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3235 // Merge the pieces into a single i64 value.
3236 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3242 /// getZeroVector - Returns a vector of specified type with all zero elements.
3243 /// Zero vectors are used to represent vector negation and in those cases
3244 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3245 /// not support i64 elements, so sometimes the zero vectors will need to be
3246 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3248 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3249 assert(VT.isVector() && "Expected a vector type");
3250 // The canonical modified immediate encoding of a zero vector is....0!
3251 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3252 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3253 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3254 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3257 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3258 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3259 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3260 SelectionDAG &DAG) const {
3261 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3262 EVT VT = Op.getValueType();
3263 unsigned VTBits = VT.getSizeInBits();
3264 DebugLoc dl = Op.getDebugLoc();
3265 SDValue ShOpLo = Op.getOperand(0);
3266 SDValue ShOpHi = Op.getOperand(1);
3267 SDValue ShAmt = Op.getOperand(2);
3269 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3271 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3273 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3274 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3275 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3276 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3277 DAG.getConstant(VTBits, MVT::i32));
3278 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3279 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3280 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3282 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3283 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3285 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3286 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3289 SDValue Ops[2] = { Lo, Hi };
3290 return DAG.getMergeValues(Ops, 2, dl);
3293 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3294 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3295 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3296 SelectionDAG &DAG) const {
3297 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3298 EVT VT = Op.getValueType();
3299 unsigned VTBits = VT.getSizeInBits();
3300 DebugLoc dl = Op.getDebugLoc();
3301 SDValue ShOpLo = Op.getOperand(0);
3302 SDValue ShOpHi = Op.getOperand(1);
3303 SDValue ShAmt = Op.getOperand(2);
3306 assert(Op.getOpcode() == ISD::SHL_PARTS);
3307 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3308 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3309 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3310 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3311 DAG.getConstant(VTBits, MVT::i32));
3312 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3313 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3315 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3316 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3317 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3319 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3320 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3323 SDValue Ops[2] = { Lo, Hi };
3324 return DAG.getMergeValues(Ops, 2, dl);
3327 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3328 SelectionDAG &DAG) const {
3329 // The rounding mode is in bits 23:22 of the FPSCR.
3330 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3331 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3332 // so that the shift + and get folded into a bitfield extract.
3333 DebugLoc dl = Op.getDebugLoc();
3334 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3335 DAG.getConstant(Intrinsic::arm_get_fpscr,
3337 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3338 DAG.getConstant(1U << 22, MVT::i32));
3339 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3340 DAG.getConstant(22, MVT::i32));
3341 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3342 DAG.getConstant(3, MVT::i32));
3345 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3346 const ARMSubtarget *ST) {
3347 EVT VT = N->getValueType(0);
3348 DebugLoc dl = N->getDebugLoc();
3350 if (!ST->hasV6T2Ops())
3353 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3354 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3357 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3358 const ARMSubtarget *ST) {
3359 EVT VT = N->getValueType(0);
3360 DebugLoc dl = N->getDebugLoc();
3365 // Lower vector shifts on NEON to use VSHL.
3366 assert(ST->hasNEON() && "unexpected vector shift");
3368 // Left shifts translate directly to the vshiftu intrinsic.
3369 if (N->getOpcode() == ISD::SHL)
3370 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3371 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3372 N->getOperand(0), N->getOperand(1));
3374 assert((N->getOpcode() == ISD::SRA ||
3375 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3377 // NEON uses the same intrinsics for both left and right shifts. For
3378 // right shifts, the shift amounts are negative, so negate the vector of
3380 EVT ShiftVT = N->getOperand(1).getValueType();
3381 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3382 getZeroVector(ShiftVT, DAG, dl),
3384 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3385 Intrinsic::arm_neon_vshifts :
3386 Intrinsic::arm_neon_vshiftu);
3387 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3388 DAG.getConstant(vshiftInt, MVT::i32),
3389 N->getOperand(0), NegatedCount);
3392 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3393 const ARMSubtarget *ST) {
3394 EVT VT = N->getValueType(0);
3395 DebugLoc dl = N->getDebugLoc();
3397 // We can get here for a node like i32 = ISD::SHL i32, i64
3401 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3402 "Unknown shift to lower!");
3404 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3405 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3406 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3409 // If we are in thumb mode, we don't have RRX.
3410 if (ST->isThumb1Only()) return SDValue();
3412 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3413 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3414 DAG.getConstant(0, MVT::i32));
3415 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3416 DAG.getConstant(1, MVT::i32));
3418 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3419 // captures the result into a carry flag.
3420 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3421 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3423 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3424 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3426 // Merge the pieces into a single i64 value.
3427 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3430 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3431 SDValue TmpOp0, TmpOp1;
3432 bool Invert = false;
3436 SDValue Op0 = Op.getOperand(0);
3437 SDValue Op1 = Op.getOperand(1);
3438 SDValue CC = Op.getOperand(2);
3439 EVT VT = Op.getValueType();
3440 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3441 DebugLoc dl = Op.getDebugLoc();
3443 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3444 switch (SetCCOpcode) {
3445 default: llvm_unreachable("Illegal FP comparison"); break;
3447 case ISD::SETNE: Invert = true; // Fallthrough
3449 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3451 case ISD::SETLT: Swap = true; // Fallthrough
3453 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3455 case ISD::SETLE: Swap = true; // Fallthrough
3457 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3458 case ISD::SETUGE: Swap = true; // Fallthrough
3459 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3460 case ISD::SETUGT: Swap = true; // Fallthrough
3461 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3462 case ISD::SETUEQ: Invert = true; // Fallthrough
3464 // Expand this to (OLT | OGT).
3468 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3469 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3471 case ISD::SETUO: Invert = true; // Fallthrough
3473 // Expand this to (OLT | OGE).
3477 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3478 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3482 // Integer comparisons.
3483 switch (SetCCOpcode) {
3484 default: llvm_unreachable("Illegal integer comparison"); break;
3485 case ISD::SETNE: Invert = true;
3486 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3487 case ISD::SETLT: Swap = true;
3488 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3489 case ISD::SETLE: Swap = true;
3490 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3491 case ISD::SETULT: Swap = true;
3492 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3493 case ISD::SETULE: Swap = true;
3494 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3497 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3498 if (Opc == ARMISD::VCEQ) {
3501 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3503 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3506 // Ignore bitconvert.
3507 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3508 AndOp = AndOp.getOperand(0);
3510 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3512 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3513 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3520 std::swap(Op0, Op1);
3522 // If one of the operands is a constant vector zero, attempt to fold the
3523 // comparison to a specialized compare-against-zero form.
3525 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3527 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3528 if (Opc == ARMISD::VCGE)
3529 Opc = ARMISD::VCLEZ;
3530 else if (Opc == ARMISD::VCGT)
3531 Opc = ARMISD::VCLTZ;
3536 if (SingleOp.getNode()) {
3539 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3541 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3543 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3545 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3547 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3549 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3552 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3556 Result = DAG.getNOT(dl, Result, VT);
3561 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3562 /// valid vector constant for a NEON instruction with a "modified immediate"
3563 /// operand (e.g., VMOV). If so, return the encoded value.
3564 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3565 unsigned SplatBitSize, SelectionDAG &DAG,
3566 EVT &VT, bool is128Bits, NEONModImmType type) {
3567 unsigned OpCmode, Imm;
3569 // SplatBitSize is set to the smallest size that splats the vector, so a
3570 // zero vector will always have SplatBitSize == 8. However, NEON modified
3571 // immediate instructions others than VMOV do not support the 8-bit encoding
3572 // of a zero vector, and the default encoding of zero is supposed to be the
3577 switch (SplatBitSize) {
3579 if (type != VMOVModImm)
3581 // Any 1-byte value is OK. Op=0, Cmode=1110.
3582 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3585 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3589 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3590 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3591 if ((SplatBits & ~0xff) == 0) {
3592 // Value = 0x00nn: Op=x, Cmode=100x.
3597 if ((SplatBits & ~0xff00) == 0) {
3598 // Value = 0xnn00: Op=x, Cmode=101x.
3600 Imm = SplatBits >> 8;
3606 // NEON's 32-bit VMOV supports splat values where:
3607 // * only one byte is nonzero, or
3608 // * the least significant byte is 0xff and the second byte is nonzero, or
3609 // * the least significant 2 bytes are 0xff and the third is nonzero.
3610 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3611 if ((SplatBits & ~0xff) == 0) {
3612 // Value = 0x000000nn: Op=x, Cmode=000x.
3617 if ((SplatBits & ~0xff00) == 0) {
3618 // Value = 0x0000nn00: Op=x, Cmode=001x.
3620 Imm = SplatBits >> 8;
3623 if ((SplatBits & ~0xff0000) == 0) {
3624 // Value = 0x00nn0000: Op=x, Cmode=010x.
3626 Imm = SplatBits >> 16;
3629 if ((SplatBits & ~0xff000000) == 0) {
3630 // Value = 0xnn000000: Op=x, Cmode=011x.
3632 Imm = SplatBits >> 24;
3636 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3637 if (type == OtherModImm) return SDValue();
3639 if ((SplatBits & ~0xffff) == 0 &&
3640 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3641 // Value = 0x0000nnff: Op=x, Cmode=1100.
3643 Imm = SplatBits >> 8;
3648 if ((SplatBits & ~0xffffff) == 0 &&
3649 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3650 // Value = 0x00nnffff: Op=x, Cmode=1101.
3652 Imm = SplatBits >> 16;
3653 SplatBits |= 0xffff;
3657 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3658 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3659 // VMOV.I32. A (very) minor optimization would be to replicate the value
3660 // and fall through here to test for a valid 64-bit splat. But, then the
3661 // caller would also need to check and handle the change in size.
3665 if (type != VMOVModImm)
3667 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3668 uint64_t BitMask = 0xff;
3670 unsigned ImmMask = 1;
3672 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3673 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3676 } else if ((SplatBits & BitMask) != 0) {
3682 // Op=1, Cmode=1110.
3685 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3690 llvm_unreachable("unexpected size for isNEONModifiedImm");
3694 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3695 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3698 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3699 bool &ReverseVEXT, unsigned &Imm) {
3700 unsigned NumElts = VT.getVectorNumElements();
3701 ReverseVEXT = false;
3703 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3709 // If this is a VEXT shuffle, the immediate value is the index of the first
3710 // element. The other shuffle indices must be the successive elements after
3712 unsigned ExpectedElt = Imm;
3713 for (unsigned i = 1; i < NumElts; ++i) {
3714 // Increment the expected index. If it wraps around, it may still be
3715 // a VEXT but the source vectors must be swapped.
3717 if (ExpectedElt == NumElts * 2) {
3722 if (M[i] < 0) continue; // ignore UNDEF indices
3723 if (ExpectedElt != static_cast<unsigned>(M[i]))
3727 // Adjust the index value if the source operands will be swapped.
3734 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3735 /// instruction with the specified blocksize. (The order of the elements
3736 /// within each block of the vector is reversed.)
3737 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3738 unsigned BlockSize) {
3739 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3740 "Only possible block sizes for VREV are: 16, 32, 64");
3742 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3746 unsigned NumElts = VT.getVectorNumElements();
3747 unsigned BlockElts = M[0] + 1;
3748 // If the first shuffle index is UNDEF, be optimistic.
3750 BlockElts = BlockSize / EltSz;
3752 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3755 for (unsigned i = 0; i < NumElts; ++i) {
3756 if (M[i] < 0) continue; // ignore UNDEF indices
3757 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3764 static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) {
3765 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3766 // range, then 0 is placed into the resulting vector. So pretty much any mask
3767 // of 8 elements can work here.
3768 return VT == MVT::v8i8 && M.size() == 8;
3771 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3772 unsigned &WhichResult) {
3773 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3777 unsigned NumElts = VT.getVectorNumElements();
3778 WhichResult = (M[0] == 0 ? 0 : 1);
3779 for (unsigned i = 0; i < NumElts; i += 2) {
3780 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3781 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3787 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3788 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3789 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3790 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3791 unsigned &WhichResult) {
3792 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3796 unsigned NumElts = VT.getVectorNumElements();
3797 WhichResult = (M[0] == 0 ? 0 : 1);
3798 for (unsigned i = 0; i < NumElts; i += 2) {
3799 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3800 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3806 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3807 unsigned &WhichResult) {
3808 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3812 unsigned NumElts = VT.getVectorNumElements();
3813 WhichResult = (M[0] == 0 ? 0 : 1);
3814 for (unsigned i = 0; i != NumElts; ++i) {
3815 if (M[i] < 0) continue; // ignore UNDEF indices
3816 if ((unsigned) M[i] != 2 * i + WhichResult)
3820 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3821 if (VT.is64BitVector() && EltSz == 32)
3827 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3828 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3829 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3830 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3831 unsigned &WhichResult) {
3832 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3836 unsigned Half = VT.getVectorNumElements() / 2;
3837 WhichResult = (M[0] == 0 ? 0 : 1);
3838 for (unsigned j = 0; j != 2; ++j) {
3839 unsigned Idx = WhichResult;
3840 for (unsigned i = 0; i != Half; ++i) {
3841 int MIdx = M[i + j * Half];
3842 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3848 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3849 if (VT.is64BitVector() && EltSz == 32)
3855 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3856 unsigned &WhichResult) {
3857 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3861 unsigned NumElts = VT.getVectorNumElements();
3862 WhichResult = (M[0] == 0 ? 0 : 1);
3863 unsigned Idx = WhichResult * NumElts / 2;
3864 for (unsigned i = 0; i != NumElts; i += 2) {
3865 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3866 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3871 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3872 if (VT.is64BitVector() && EltSz == 32)
3878 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3879 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3880 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3881 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3882 unsigned &WhichResult) {
3883 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3887 unsigned NumElts = VT.getVectorNumElements();
3888 WhichResult = (M[0] == 0 ? 0 : 1);
3889 unsigned Idx = WhichResult * NumElts / 2;
3890 for (unsigned i = 0; i != NumElts; i += 2) {
3891 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3892 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3897 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3898 if (VT.is64BitVector() && EltSz == 32)
3904 // If N is an integer constant that can be moved into a register in one
3905 // instruction, return an SDValue of such a constant (will become a MOV
3906 // instruction). Otherwise return null.
3907 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3908 const ARMSubtarget *ST, DebugLoc dl) {
3910 if (!isa<ConstantSDNode>(N))
3912 Val = cast<ConstantSDNode>(N)->getZExtValue();
3914 if (ST->isThumb1Only()) {
3915 if (Val <= 255 || ~Val <= 255)
3916 return DAG.getConstant(Val, MVT::i32);
3918 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3919 return DAG.getConstant(Val, MVT::i32);
3924 // If this is a case we can't handle, return null and let the default
3925 // expansion code take care of it.
3926 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3927 const ARMSubtarget *ST) const {
3928 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3929 DebugLoc dl = Op.getDebugLoc();
3930 EVT VT = Op.getValueType();
3932 APInt SplatBits, SplatUndef;
3933 unsigned SplatBitSize;
3935 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3936 if (SplatBitSize <= 64) {
3937 // Check if an immediate VMOV works.
3939 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3940 SplatUndef.getZExtValue(), SplatBitSize,
3941 DAG, VmovVT, VT.is128BitVector(),
3943 if (Val.getNode()) {
3944 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3945 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3948 // Try an immediate VMVN.
3949 uint64_t NegatedImm = (~SplatBits).getZExtValue();
3950 Val = isNEONModifiedImm(NegatedImm,
3951 SplatUndef.getZExtValue(), SplatBitSize,
3952 DAG, VmovVT, VT.is128BitVector(),
3954 if (Val.getNode()) {
3955 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3956 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3961 // Scan through the operands to see if only one value is used.
3962 unsigned NumElts = VT.getVectorNumElements();
3963 bool isOnlyLowElement = true;
3964 bool usesOnlyOneValue = true;
3965 bool isConstant = true;
3967 for (unsigned i = 0; i < NumElts; ++i) {
3968 SDValue V = Op.getOperand(i);
3969 if (V.getOpcode() == ISD::UNDEF)
3972 isOnlyLowElement = false;
3973 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3976 if (!Value.getNode())
3978 else if (V != Value)
3979 usesOnlyOneValue = false;
3982 if (!Value.getNode())
3983 return DAG.getUNDEF(VT);
3985 if (isOnlyLowElement)
3986 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3988 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3990 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3991 // i32 and try again.
3992 if (usesOnlyOneValue && EltSize <= 32) {
3994 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3995 if (VT.getVectorElementType().isFloatingPoint()) {
3996 SmallVector<SDValue, 8> Ops;
3997 for (unsigned i = 0; i < NumElts; ++i)
3998 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4000 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
4001 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
4002 Val = LowerBUILD_VECTOR(Val, DAG, ST);
4004 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4006 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
4008 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
4011 // If all elements are constants and the case above didn't get hit, fall back
4012 // to the default expansion, which will generate a load from the constant
4017 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
4019 SDValue shuffle = ReconstructShuffle(Op, DAG);
4020 if (shuffle != SDValue())
4024 // Vectors with 32- or 64-bit elements can be built by directly assigning
4025 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
4026 // will be legalized.
4027 if (EltSize >= 32) {
4028 // Do the expansion with floating-point types, since that is what the VFP
4029 // registers are defined to use, and since i64 is not legal.
4030 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4031 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4032 SmallVector<SDValue, 8> Ops;
4033 for (unsigned i = 0; i < NumElts; ++i)
4034 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
4035 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4036 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4042 // Gather data to see if the operation can be modelled as a
4043 // shuffle in combination with VEXTs.
4044 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
4045 SelectionDAG &DAG) const {
4046 DebugLoc dl = Op.getDebugLoc();
4047 EVT VT = Op.getValueType();
4048 unsigned NumElts = VT.getVectorNumElements();
4050 SmallVector<SDValue, 2> SourceVecs;
4051 SmallVector<unsigned, 2> MinElts;
4052 SmallVector<unsigned, 2> MaxElts;
4054 for (unsigned i = 0; i < NumElts; ++i) {
4055 SDValue V = Op.getOperand(i);
4056 if (V.getOpcode() == ISD::UNDEF)
4058 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4059 // A shuffle can only come from building a vector from various
4060 // elements of other vectors.
4062 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
4063 VT.getVectorElementType()) {
4064 // This code doesn't know how to handle shuffles where the vector
4065 // element types do not match (this happens because type legalization
4066 // promotes the return type of EXTRACT_VECTOR_ELT).
4067 // FIXME: It might be appropriate to extend this code to handle
4068 // mismatched types.
4072 // Record this extraction against the appropriate vector if possible...
4073 SDValue SourceVec = V.getOperand(0);
4074 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4075 bool FoundSource = false;
4076 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4077 if (SourceVecs[j] == SourceVec) {
4078 if (MinElts[j] > EltNo)
4080 if (MaxElts[j] < EltNo)
4087 // Or record a new source if not...
4089 SourceVecs.push_back(SourceVec);
4090 MinElts.push_back(EltNo);
4091 MaxElts.push_back(EltNo);
4095 // Currently only do something sane when at most two source vectors
4097 if (SourceVecs.size() > 2)
4100 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4101 int VEXTOffsets[2] = {0, 0};
4103 // This loop extracts the usage patterns of the source vectors
4104 // and prepares appropriate SDValues for a shuffle if possible.
4105 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4106 if (SourceVecs[i].getValueType() == VT) {
4107 // No VEXT necessary
4108 ShuffleSrcs[i] = SourceVecs[i];
4111 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4112 // It probably isn't worth padding out a smaller vector just to
4113 // break it down again in a shuffle.
4117 // Since only 64-bit and 128-bit vectors are legal on ARM and
4118 // we've eliminated the other cases...
4119 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
4120 "unexpected vector sizes in ReconstructShuffle");
4122 if (MaxElts[i] - MinElts[i] >= NumElts) {
4123 // Span too large for a VEXT to cope
4127 if (MinElts[i] >= NumElts) {
4128 // The extraction can just take the second half
4129 VEXTOffsets[i] = NumElts;
4130 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4132 DAG.getIntPtrConstant(NumElts));
4133 } else if (MaxElts[i] < NumElts) {
4134 // The extraction can just take the first half
4136 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4138 DAG.getIntPtrConstant(0));
4140 // An actual VEXT is needed
4141 VEXTOffsets[i] = MinElts[i];
4142 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4144 DAG.getIntPtrConstant(0));
4145 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4147 DAG.getIntPtrConstant(NumElts));
4148 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4149 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4153 SmallVector<int, 8> Mask;
4155 for (unsigned i = 0; i < NumElts; ++i) {
4156 SDValue Entry = Op.getOperand(i);
4157 if (Entry.getOpcode() == ISD::UNDEF) {
4162 SDValue ExtractVec = Entry.getOperand(0);
4163 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
4164 .getOperand(1))->getSExtValue();
4165 if (ExtractVec == SourceVecs[0]) {
4166 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4168 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4172 // Final check before we try to produce nonsense...
4173 if (isShuffleMaskLegal(Mask, VT))
4174 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4180 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4181 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4182 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4183 /// are assumed to be legal.
4185 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4187 if (VT.getVectorNumElements() == 4 &&
4188 (VT.is128BitVector() || VT.is64BitVector())) {
4189 unsigned PFIndexes[4];
4190 for (unsigned i = 0; i != 4; ++i) {
4194 PFIndexes[i] = M[i];
4197 // Compute the index in the perfect shuffle table.
4198 unsigned PFTableIndex =
4199 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4200 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4201 unsigned Cost = (PFEntry >> 30);
4208 unsigned Imm, WhichResult;
4210 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4211 return (EltSize >= 32 ||
4212 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4213 isVREVMask(M, VT, 64) ||
4214 isVREVMask(M, VT, 32) ||
4215 isVREVMask(M, VT, 16) ||
4216 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4217 isVTBLMask(M, VT) ||
4218 isVTRNMask(M, VT, WhichResult) ||
4219 isVUZPMask(M, VT, WhichResult) ||
4220 isVZIPMask(M, VT, WhichResult) ||
4221 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4222 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4223 isVZIP_v_undef_Mask(M, VT, WhichResult));
4226 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4227 /// the specified operations to build the shuffle.
4228 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4229 SDValue RHS, SelectionDAG &DAG,
4231 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4232 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4233 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4236 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4245 OP_VUZPL, // VUZP, left result
4246 OP_VUZPR, // VUZP, right result
4247 OP_VZIPL, // VZIP, left result
4248 OP_VZIPR, // VZIP, right result
4249 OP_VTRNL, // VTRN, left result
4250 OP_VTRNR // VTRN, right result
4253 if (OpNum == OP_COPY) {
4254 if (LHSID == (1*9+2)*9+3) return LHS;
4255 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4259 SDValue OpLHS, OpRHS;
4260 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4261 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4262 EVT VT = OpLHS.getValueType();
4265 default: llvm_unreachable("Unknown shuffle opcode!");
4267 // VREV divides the vector in half and swaps within the half.
4268 if (VT.getVectorElementType() == MVT::i32 ||
4269 VT.getVectorElementType() == MVT::f32)
4270 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4271 // vrev <4 x i16> -> VREV32
4272 if (VT.getVectorElementType() == MVT::i16)
4273 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4274 // vrev <4 x i8> -> VREV16
4275 assert(VT.getVectorElementType() == MVT::i8);
4276 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4281 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4282 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4286 return DAG.getNode(ARMISD::VEXT, dl, VT,
4288 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4291 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4292 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4295 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4296 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4299 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4300 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4304 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4305 SmallVectorImpl<int> &ShuffleMask,
4306 SelectionDAG &DAG) {
4307 // Check to see if we can use the VTBL instruction.
4308 SDValue V1 = Op.getOperand(0);
4309 SDValue V2 = Op.getOperand(1);
4310 DebugLoc DL = Op.getDebugLoc();
4312 SmallVector<SDValue, 8> VTBLMask;
4313 for (SmallVectorImpl<int>::iterator
4314 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4315 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4317 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4318 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4319 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4322 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4323 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4327 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4328 SDValue V1 = Op.getOperand(0);
4329 SDValue V2 = Op.getOperand(1);
4330 DebugLoc dl = Op.getDebugLoc();
4331 EVT VT = Op.getValueType();
4332 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4333 SmallVector<int, 8> ShuffleMask;
4335 // Convert shuffles that are directly supported on NEON to target-specific
4336 // DAG nodes, instead of keeping them as shuffles and matching them again
4337 // during code selection. This is more efficient and avoids the possibility
4338 // of inconsistencies between legalization and selection.
4339 // FIXME: floating-point vectors should be canonicalized to integer vectors
4340 // of the same time so that they get CSEd properly.
4341 SVN->getMask(ShuffleMask);
4343 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4344 if (EltSize <= 32) {
4345 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4346 int Lane = SVN->getSplatIndex();
4347 // If this is undef splat, generate it via "just" vdup, if possible.
4348 if (Lane == -1) Lane = 0;
4350 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4351 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4353 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4354 DAG.getConstant(Lane, MVT::i32));
4359 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4362 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4363 DAG.getConstant(Imm, MVT::i32));
4366 if (isVREVMask(ShuffleMask, VT, 64))
4367 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4368 if (isVREVMask(ShuffleMask, VT, 32))
4369 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4370 if (isVREVMask(ShuffleMask, VT, 16))
4371 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4373 // Check for Neon shuffles that modify both input vectors in place.
4374 // If both results are used, i.e., if there are two shuffles with the same
4375 // source operands and with masks corresponding to both results of one of
4376 // these operations, DAG memoization will ensure that a single node is
4377 // used for both shuffles.
4378 unsigned WhichResult;
4379 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4380 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4381 V1, V2).getValue(WhichResult);
4382 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4383 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4384 V1, V2).getValue(WhichResult);
4385 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4386 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4387 V1, V2).getValue(WhichResult);
4389 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4390 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4391 V1, V1).getValue(WhichResult);
4392 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4393 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4394 V1, V1).getValue(WhichResult);
4395 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4396 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4397 V1, V1).getValue(WhichResult);
4400 // If the shuffle is not directly supported and it has 4 elements, use
4401 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4402 unsigned NumElts = VT.getVectorNumElements();
4404 unsigned PFIndexes[4];
4405 for (unsigned i = 0; i != 4; ++i) {
4406 if (ShuffleMask[i] < 0)
4409 PFIndexes[i] = ShuffleMask[i];
4412 // Compute the index in the perfect shuffle table.
4413 unsigned PFTableIndex =
4414 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4415 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4416 unsigned Cost = (PFEntry >> 30);
4419 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4422 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4423 if (EltSize >= 32) {
4424 // Do the expansion with floating-point types, since that is what the VFP
4425 // registers are defined to use, and since i64 is not legal.
4426 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4427 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4428 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4429 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4430 SmallVector<SDValue, 8> Ops;
4431 for (unsigned i = 0; i < NumElts; ++i) {
4432 if (ShuffleMask[i] < 0)
4433 Ops.push_back(DAG.getUNDEF(EltVT));
4435 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4436 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4437 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4440 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4441 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4444 if (VT == MVT::v8i8) {
4445 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4446 if (NewOp.getNode())
4453 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4454 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4455 SDValue Lane = Op.getOperand(1);
4456 if (!isa<ConstantSDNode>(Lane))
4459 SDValue Vec = Op.getOperand(0);
4460 if (Op.getValueType() == MVT::i32 &&
4461 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4462 DebugLoc dl = Op.getDebugLoc();
4463 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4469 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4470 // The only time a CONCAT_VECTORS operation can have legal types is when
4471 // two 64-bit vectors are concatenated to a 128-bit vector.
4472 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4473 "unexpected CONCAT_VECTORS");
4474 DebugLoc dl = Op.getDebugLoc();
4475 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4476 SDValue Op0 = Op.getOperand(0);
4477 SDValue Op1 = Op.getOperand(1);
4478 if (Op0.getOpcode() != ISD::UNDEF)
4479 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4480 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4481 DAG.getIntPtrConstant(0));
4482 if (Op1.getOpcode() != ISD::UNDEF)
4483 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4484 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4485 DAG.getIntPtrConstant(1));
4486 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4489 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4490 /// element has been zero/sign-extended, depending on the isSigned parameter,
4491 /// from an integer type half its size.
4492 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4494 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4495 EVT VT = N->getValueType(0);
4496 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4497 SDNode *BVN = N->getOperand(0).getNode();
4498 if (BVN->getValueType(0) != MVT::v4i32 ||
4499 BVN->getOpcode() != ISD::BUILD_VECTOR)
4501 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4502 unsigned HiElt = 1 - LoElt;
4503 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4504 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4505 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4506 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4507 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4510 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4511 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4514 if (Hi0->isNullValue() && Hi1->isNullValue())
4520 if (N->getOpcode() != ISD::BUILD_VECTOR)
4523 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4524 SDNode *Elt = N->getOperand(i).getNode();
4525 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4526 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4527 unsigned HalfSize = EltSize / 2;
4529 int64_t SExtVal = C->getSExtValue();
4530 if (SExtVal != SExtVal << (64 - HalfSize) >> (64 - HalfSize))
4533 if ((C->getZExtValue() >> HalfSize) != 0)
4544 /// isSignExtended - Check if a node is a vector value that is sign-extended
4545 /// or a constant BUILD_VECTOR with sign-extended elements.
4546 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4547 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4549 if (isExtendedBUILD_VECTOR(N, DAG, true))
4554 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4555 /// or a constant BUILD_VECTOR with zero-extended elements.
4556 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4557 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4559 if (isExtendedBUILD_VECTOR(N, DAG, false))
4564 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4565 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4566 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4567 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4568 return N->getOperand(0);
4569 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4570 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4571 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4572 LD->isNonTemporal(), LD->getAlignment());
4573 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4574 // have been legalized as a BITCAST from v4i32.
4575 if (N->getOpcode() == ISD::BITCAST) {
4576 SDNode *BVN = N->getOperand(0).getNode();
4577 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4578 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4579 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4580 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4581 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4583 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4584 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4585 EVT VT = N->getValueType(0);
4586 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4587 unsigned NumElts = VT.getVectorNumElements();
4588 MVT TruncVT = MVT::getIntegerVT(EltSize);
4589 SmallVector<SDValue, 8> Ops;
4590 for (unsigned i = 0; i != NumElts; ++i) {
4591 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4592 const APInt &CInt = C->getAPIntValue();
4593 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4595 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4596 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4599 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4600 unsigned Opcode = N->getOpcode();
4601 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4602 SDNode *N0 = N->getOperand(0).getNode();
4603 SDNode *N1 = N->getOperand(1).getNode();
4604 return N0->hasOneUse() && N1->hasOneUse() &&
4605 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4610 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4611 unsigned Opcode = N->getOpcode();
4612 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4613 SDNode *N0 = N->getOperand(0).getNode();
4614 SDNode *N1 = N->getOperand(1).getNode();
4615 return N0->hasOneUse() && N1->hasOneUse() &&
4616 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4621 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4622 // Multiplications are only custom-lowered for 128-bit vectors so that
4623 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4624 EVT VT = Op.getValueType();
4625 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4626 SDNode *N0 = Op.getOperand(0).getNode();
4627 SDNode *N1 = Op.getOperand(1).getNode();
4628 unsigned NewOpc = 0;
4630 bool isN0SExt = isSignExtended(N0, DAG);
4631 bool isN1SExt = isSignExtended(N1, DAG);
4632 if (isN0SExt && isN1SExt)
4633 NewOpc = ARMISD::VMULLs;
4635 bool isN0ZExt = isZeroExtended(N0, DAG);
4636 bool isN1ZExt = isZeroExtended(N1, DAG);
4637 if (isN0ZExt && isN1ZExt)
4638 NewOpc = ARMISD::VMULLu;
4639 else if (isN1SExt || isN1ZExt) {
4640 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4641 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4642 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4643 NewOpc = ARMISD::VMULLs;
4645 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4646 NewOpc = ARMISD::VMULLu;
4648 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4650 NewOpc = ARMISD::VMULLu;
4656 if (VT == MVT::v2i64)
4657 // Fall through to expand this. It is not legal.
4660 // Other vector multiplications are legal.
4665 // Legalize to a VMULL instruction.
4666 DebugLoc DL = Op.getDebugLoc();
4668 SDValue Op1 = SkipExtension(N1, DAG);
4670 Op0 = SkipExtension(N0, DAG);
4671 assert(Op0.getValueType().is64BitVector() &&
4672 Op1.getValueType().is64BitVector() &&
4673 "unexpected types for extended operands to VMULL");
4674 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4677 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
4678 // isel lowering to take advantage of no-stall back to back vmul + vmla.
4685 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4686 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4687 EVT Op1VT = Op1.getValueType();
4688 return DAG.getNode(N0->getOpcode(), DL, VT,
4689 DAG.getNode(NewOpc, DL, VT,
4690 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
4691 DAG.getNode(NewOpc, DL, VT,
4692 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
4696 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4698 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4699 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4700 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4701 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4702 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4703 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4704 // Get reciprocal estimate.
4705 // float4 recip = vrecpeq_f32(yf);
4706 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4707 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4708 // Because char has a smaller range than uchar, we can actually get away
4709 // without any newton steps. This requires that we use a weird bias
4710 // of 0xb000, however (again, this has been exhaustively tested).
4711 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4712 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4713 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4714 Y = DAG.getConstant(0xb000, MVT::i32);
4715 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4716 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4717 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4718 // Convert back to short.
4719 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4720 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4725 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4727 // Convert to float.
4728 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4729 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4730 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4731 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4732 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4733 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4735 // Use reciprocal estimate and one refinement step.
4736 // float4 recip = vrecpeq_f32(yf);
4737 // recip *= vrecpsq_f32(yf, recip);
4738 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4739 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4740 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4741 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4743 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4744 // Because short has a smaller range than ushort, we can actually get away
4745 // with only a single newton step. This requires that we use a weird bias
4746 // of 89, however (again, this has been exhaustively tested).
4747 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
4748 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4749 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4750 N1 = DAG.getConstant(0x89, MVT::i32);
4751 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4752 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4753 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4754 // Convert back to integer and return.
4755 // return vmovn_s32(vcvt_s32_f32(result));
4756 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4757 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4761 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4762 EVT VT = Op.getValueType();
4763 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4764 "unexpected type for custom-lowering ISD::SDIV");
4766 DebugLoc dl = Op.getDebugLoc();
4767 SDValue N0 = Op.getOperand(0);
4768 SDValue N1 = Op.getOperand(1);
4771 if (VT == MVT::v8i8) {
4772 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4773 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4775 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4776 DAG.getIntPtrConstant(4));
4777 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4778 DAG.getIntPtrConstant(4));
4779 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4780 DAG.getIntPtrConstant(0));
4781 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4782 DAG.getIntPtrConstant(0));
4784 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4785 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4787 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4788 N0 = LowerCONCAT_VECTORS(N0, DAG);
4790 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4793 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4796 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4797 EVT VT = Op.getValueType();
4798 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4799 "unexpected type for custom-lowering ISD::UDIV");
4801 DebugLoc dl = Op.getDebugLoc();
4802 SDValue N0 = Op.getOperand(0);
4803 SDValue N1 = Op.getOperand(1);
4806 if (VT == MVT::v8i8) {
4807 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4808 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4810 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4811 DAG.getIntPtrConstant(4));
4812 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4813 DAG.getIntPtrConstant(4));
4814 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4815 DAG.getIntPtrConstant(0));
4816 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4817 DAG.getIntPtrConstant(0));
4819 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4820 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4822 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4823 N0 = LowerCONCAT_VECTORS(N0, DAG);
4825 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4826 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4831 // v4i16 sdiv ... Convert to float.
4832 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4833 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4834 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4835 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4836 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4837 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4839 // Use reciprocal estimate and two refinement steps.
4840 // float4 recip = vrecpeq_f32(yf);
4841 // recip *= vrecpsq_f32(yf, recip);
4842 // recip *= vrecpsq_f32(yf, recip);
4843 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4844 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
4845 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4846 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4848 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4849 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4850 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4852 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4853 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4854 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4855 // and that it will never cause us to return an answer too large).
4856 // float4 result = as_float4(as_int4(xf*recip) + 2);
4857 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4858 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4859 N1 = DAG.getConstant(2, MVT::i32);
4860 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4861 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4862 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4863 // Convert back to integer and return.
4864 // return vmovn_u32(vcvt_s32_f32(result));
4865 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4866 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4870 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
4871 EVT VT = Op.getNode()->getValueType(0);
4872 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4875 bool ExtraOp = false;
4876 switch (Op.getOpcode()) {
4877 default: assert(0 && "Invalid code");
4878 case ISD::ADDC: Opc = ARMISD::ADDC; break;
4879 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
4880 case ISD::SUBC: Opc = ARMISD::SUBC; break;
4881 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
4885 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
4887 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
4888 Op.getOperand(1), Op.getOperand(2));
4891 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
4892 // Monotonic load/store is legal for all targets
4893 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
4896 // Aquire/Release load/store is not legal for targets without a
4897 // dmb or equivalent available.
4903 ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results,
4904 SelectionDAG &DAG, unsigned NewOp) {
4905 DebugLoc dl = Node->getDebugLoc();
4906 assert (Node->getValueType(0) == MVT::i64 &&
4907 "Only know how to expand i64 atomics");
4909 SmallVector<SDValue, 6> Ops;
4910 Ops.push_back(Node->getOperand(0)); // Chain
4911 Ops.push_back(Node->getOperand(1)); // Ptr
4913 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4914 Node->getOperand(2), DAG.getIntPtrConstant(0)));
4915 // High part of Val1
4916 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4917 Node->getOperand(2), DAG.getIntPtrConstant(1)));
4918 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) {
4919 // High part of Val1
4920 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4921 Node->getOperand(3), DAG.getIntPtrConstant(0)));
4922 // High part of Val2
4923 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4924 Node->getOperand(3), DAG.getIntPtrConstant(1)));
4926 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
4928 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64,
4929 cast<MemSDNode>(Node)->getMemOperand());
4930 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) };
4931 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
4932 Results.push_back(Result.getValue(2));
4935 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4936 switch (Op.getOpcode()) {
4937 default: llvm_unreachable("Don't know how to custom lower this!");
4938 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4939 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4940 case ISD::GlobalAddress:
4941 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4942 LowerGlobalAddressELF(Op, DAG);
4943 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4944 case ISD::SELECT: return LowerSELECT(Op, DAG);
4945 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4946 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4947 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4948 case ISD::VASTART: return LowerVASTART(Op, DAG);
4949 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4950 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
4951 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4952 case ISD::SINT_TO_FP:
4953 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4954 case ISD::FP_TO_SINT:
4955 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4956 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4957 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4958 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4959 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4960 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4961 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4962 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4963 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4965 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4968 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4969 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4970 case ISD::SRL_PARTS:
4971 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4972 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4973 case ISD::SETCC: return LowerVSETCC(Op, DAG);
4974 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4975 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4976 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4977 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4978 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4979 case ISD::MUL: return LowerMUL(Op, DAG);
4980 case ISD::SDIV: return LowerSDIV(Op, DAG);
4981 case ISD::UDIV: return LowerUDIV(Op, DAG);
4985 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
4986 case ISD::ATOMIC_LOAD:
4987 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
4992 /// ReplaceNodeResults - Replace the results of node with an illegal result
4993 /// type with new values built out of custom code.
4994 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4995 SmallVectorImpl<SDValue>&Results,
4996 SelectionDAG &DAG) const {
4998 switch (N->getOpcode()) {
5000 llvm_unreachable("Don't know how to custom expand this!");
5003 Res = ExpandBITCAST(N, DAG);
5007 Res = Expand64BitShift(N, DAG, Subtarget);
5009 case ISD::ATOMIC_LOAD_ADD:
5010 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG);
5012 case ISD::ATOMIC_LOAD_AND:
5013 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG);
5015 case ISD::ATOMIC_LOAD_NAND:
5016 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG);
5018 case ISD::ATOMIC_LOAD_OR:
5019 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG);
5021 case ISD::ATOMIC_LOAD_SUB:
5022 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG);
5024 case ISD::ATOMIC_LOAD_XOR:
5025 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG);
5027 case ISD::ATOMIC_SWAP:
5028 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG);
5030 case ISD::ATOMIC_CMP_SWAP:
5031 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG);
5035 Results.push_back(Res);
5038 //===----------------------------------------------------------------------===//
5039 // ARM Scheduler Hooks
5040 //===----------------------------------------------------------------------===//
5043 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
5044 MachineBasicBlock *BB,
5045 unsigned Size) const {
5046 unsigned dest = MI->getOperand(0).getReg();
5047 unsigned ptr = MI->getOperand(1).getReg();
5048 unsigned oldval = MI->getOperand(2).getReg();
5049 unsigned newval = MI->getOperand(3).getReg();
5050 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5051 DebugLoc dl = MI->getDebugLoc();
5052 bool isThumb2 = Subtarget->isThumb2();
5054 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5056 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass
5057 : ARM::GPRRegisterClass);
5060 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5061 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass);
5062 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass);
5065 unsigned ldrOpc, strOpc;
5067 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5069 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5070 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5073 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5074 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5077 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5078 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5082 MachineFunction *MF = BB->getParent();
5083 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5084 MachineFunction::iterator It = BB;
5085 ++It; // insert the new blocks after the current block
5087 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5088 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5089 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5090 MF->insert(It, loop1MBB);
5091 MF->insert(It, loop2MBB);
5092 MF->insert(It, exitMBB);
5094 // Transfer the remainder of BB and its successor edges to exitMBB.
5095 exitMBB->splice(exitMBB->begin(), BB,
5096 llvm::next(MachineBasicBlock::iterator(MI)),
5098 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5102 // fallthrough --> loop1MBB
5103 BB->addSuccessor(loop1MBB);
5106 // ldrex dest, [ptr]
5110 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5111 if (ldrOpc == ARM::t2LDREX)
5113 AddDefaultPred(MIB);
5114 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5115 .addReg(dest).addReg(oldval));
5116 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5117 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5118 BB->addSuccessor(loop2MBB);
5119 BB->addSuccessor(exitMBB);
5122 // strex scratch, newval, [ptr]
5126 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr);
5127 if (strOpc == ARM::t2STREX)
5129 AddDefaultPred(MIB);
5130 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5131 .addReg(scratch).addImm(0));
5132 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5133 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5134 BB->addSuccessor(loop1MBB);
5135 BB->addSuccessor(exitMBB);
5141 MI->eraseFromParent(); // The instruction is gone now.
5147 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5148 unsigned Size, unsigned BinOpcode) const {
5149 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5150 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5152 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5153 MachineFunction *MF = BB->getParent();
5154 MachineFunction::iterator It = BB;
5157 unsigned dest = MI->getOperand(0).getReg();
5158 unsigned ptr = MI->getOperand(1).getReg();
5159 unsigned incr = MI->getOperand(2).getReg();
5160 DebugLoc dl = MI->getDebugLoc();
5161 bool isThumb2 = Subtarget->isThumb2();
5163 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5165 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5166 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5169 unsigned ldrOpc, strOpc;
5171 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5173 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5174 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5177 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5178 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5181 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5182 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5186 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5187 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5188 MF->insert(It, loopMBB);
5189 MF->insert(It, exitMBB);
5191 // Transfer the remainder of BB and its successor edges to exitMBB.
5192 exitMBB->splice(exitMBB->begin(), BB,
5193 llvm::next(MachineBasicBlock::iterator(MI)),
5195 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5197 TargetRegisterClass *TRC =
5198 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5199 unsigned scratch = MRI.createVirtualRegister(TRC);
5200 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
5204 // fallthrough --> loopMBB
5205 BB->addSuccessor(loopMBB);
5209 // <binop> scratch2, dest, incr
5210 // strex scratch, scratch2, ptr
5213 // fallthrough --> exitMBB
5215 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5216 if (ldrOpc == ARM::t2LDREX)
5218 AddDefaultPred(MIB);
5220 // operand order needs to go the other way for NAND
5221 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
5222 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5223 addReg(incr).addReg(dest)).addReg(0);
5225 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5226 addReg(dest).addReg(incr)).addReg(0);
5229 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5230 if (strOpc == ARM::t2STREX)
5232 AddDefaultPred(MIB);
5233 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5234 .addReg(scratch).addImm(0));
5235 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5236 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5238 BB->addSuccessor(loopMBB);
5239 BB->addSuccessor(exitMBB);
5245 MI->eraseFromParent(); // The instruction is gone now.
5251 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
5252 MachineBasicBlock *BB,
5255 ARMCC::CondCodes Cond) const {
5256 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5258 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5259 MachineFunction *MF = BB->getParent();
5260 MachineFunction::iterator It = BB;
5263 unsigned dest = MI->getOperand(0).getReg();
5264 unsigned ptr = MI->getOperand(1).getReg();
5265 unsigned incr = MI->getOperand(2).getReg();
5266 unsigned oldval = dest;
5267 DebugLoc dl = MI->getDebugLoc();
5268 bool isThumb2 = Subtarget->isThumb2();
5270 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5272 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5273 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5276 unsigned ldrOpc, strOpc, extendOpc;
5278 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5280 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5281 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5282 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
5285 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5286 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5287 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
5290 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5291 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5296 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5297 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5298 MF->insert(It, loopMBB);
5299 MF->insert(It, exitMBB);
5301 // Transfer the remainder of BB and its successor edges to exitMBB.
5302 exitMBB->splice(exitMBB->begin(), BB,
5303 llvm::next(MachineBasicBlock::iterator(MI)),
5305 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5307 TargetRegisterClass *TRC =
5308 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5309 unsigned scratch = MRI.createVirtualRegister(TRC);
5310 unsigned scratch2 = MRI.createVirtualRegister(TRC);
5314 // fallthrough --> loopMBB
5315 BB->addSuccessor(loopMBB);
5319 // (sign extend dest, if required)
5321 // cmov.cond scratch2, dest, incr
5322 // strex scratch, scratch2, ptr
5325 // fallthrough --> exitMBB
5327 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5328 if (ldrOpc == ARM::t2LDREX)
5330 AddDefaultPred(MIB);
5332 // Sign extend the value, if necessary.
5333 if (signExtend && extendOpc) {
5334 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass);
5335 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
5340 // Build compare and cmov instructions.
5341 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5342 .addReg(oldval).addReg(incr));
5343 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
5344 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR);
5346 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5347 if (strOpc == ARM::t2STREX)
5349 AddDefaultPred(MIB);
5350 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5351 .addReg(scratch).addImm(0));
5352 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5353 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5355 BB->addSuccessor(loopMBB);
5356 BB->addSuccessor(exitMBB);
5362 MI->eraseFromParent(); // The instruction is gone now.
5368 ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
5369 unsigned Op1, unsigned Op2,
5370 bool NeedsCarry, bool IsCmpxchg) const {
5371 // This also handles ATOMIC_SWAP, indicated by Op1==0.
5372 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5374 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5375 MachineFunction *MF = BB->getParent();
5376 MachineFunction::iterator It = BB;
5379 unsigned destlo = MI->getOperand(0).getReg();
5380 unsigned desthi = MI->getOperand(1).getReg();
5381 unsigned ptr = MI->getOperand(2).getReg();
5382 unsigned vallo = MI->getOperand(3).getReg();
5383 unsigned valhi = MI->getOperand(4).getReg();
5384 DebugLoc dl = MI->getDebugLoc();
5385 bool isThumb2 = Subtarget->isThumb2();
5387 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5389 MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass);
5390 MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass);
5391 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5394 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD;
5395 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD;
5397 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5398 MachineBasicBlock *contBB = 0, *cont2BB = 0;
5400 contBB = MF->CreateMachineBasicBlock(LLVM_BB);
5401 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB);
5403 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5404 MF->insert(It, loopMBB);
5406 MF->insert(It, contBB);
5407 MF->insert(It, cont2BB);
5409 MF->insert(It, exitMBB);
5411 // Transfer the remainder of BB and its successor edges to exitMBB.
5412 exitMBB->splice(exitMBB->begin(), BB,
5413 llvm::next(MachineBasicBlock::iterator(MI)),
5415 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5417 TargetRegisterClass *TRC =
5418 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5419 unsigned storesuccess = MRI.createVirtualRegister(TRC);
5423 // fallthrough --> loopMBB
5424 BB->addSuccessor(loopMBB);
5427 // ldrexd r2, r3, ptr
5428 // <binopa> r0, r2, incr
5429 // <binopb> r1, r3, incr
5430 // strexd storesuccess, r0, r1, ptr
5431 // cmp storesuccess, #0
5433 // fallthrough --> exitMBB
5435 // Note that the registers are explicitly specified because there is not any
5436 // way to force the register allocator to allocate a register pair.
5438 // FIXME: The hardcoded registers are not necessary for Thumb2, but we
5439 // need to properly enforce the restriction that the two output registers
5440 // for ldrexd must be different.
5443 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
5444 .addReg(ARM::R2, RegState::Define)
5445 .addReg(ARM::R3, RegState::Define).addReg(ptr));
5446 // Copy r2/r3 into dest. (This copy will normally be coalesced.)
5447 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2);
5448 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3);
5452 for (unsigned i = 0; i < 2; i++) {
5453 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr :
5455 .addReg(i == 0 ? destlo : desthi)
5456 .addReg(i == 0 ? vallo : valhi));
5457 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5458 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5459 BB->addSuccessor(exitMBB);
5460 BB->addSuccessor(i == 0 ? contBB : cont2BB);
5461 BB = (i == 0 ? contBB : cont2BB);
5464 // Copy to physregs for strexd
5465 unsigned setlo = MI->getOperand(5).getReg();
5466 unsigned sethi = MI->getOperand(6).getReg();
5467 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo);
5468 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi);
5470 // Perform binary operation
5471 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0)
5472 .addReg(destlo).addReg(vallo))
5473 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry));
5474 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1)
5475 .addReg(desthi).addReg(valhi)).addReg(0);
5477 // Copy to physregs for strexd
5478 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo);
5479 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi);
5483 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
5484 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr));
5486 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5487 .addReg(storesuccess).addImm(0));
5488 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5489 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5491 BB->addSuccessor(loopMBB);
5492 BB->addSuccessor(exitMBB);
5498 MI->eraseFromParent(); // The instruction is gone now.
5503 /// EmitBasePointerRecalculation - For functions using a base pointer, we
5504 /// rematerialize it (via the frame pointer).
5505 void ARMTargetLowering::
5506 EmitBasePointerRecalculation(MachineInstr *MI, MachineBasicBlock *MBB,
5507 MachineBasicBlock *DispatchBB) const {
5508 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5509 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
5510 MachineFunction &MF = *MI->getParent()->getParent();
5511 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
5512 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
5514 if (!RI.hasBasePointer(MF)) return;
5516 MachineBasicBlock::iterator MBBI = MI;
5518 int32_t NumBytes = AFI->getFramePtrSpillOffset();
5519 unsigned FramePtr = RI.getFrameRegister(MF);
5520 assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
5521 "Base pointer without frame pointer?");
5523 if (AFI->isThumb2Function())
5524 llvm::emitT2RegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6,
5525 FramePtr, -NumBytes, ARMCC::AL, 0, *AII);
5526 else if (AFI->isThumbFunction())
5527 llvm::emitThumbRegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6,
5528 FramePtr, -NumBytes, *AII, RI);
5530 llvm::emitARMRegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6,
5531 FramePtr, -NumBytes, ARMCC::AL, 0, *AII);
5533 if (!RI.needsStackRealignment(MF)) return;
5535 // If there's dynamic realignment, adjust for it.
5536 MachineFrameInfo *MFI = MF.getFrameInfo();
5537 unsigned MaxAlign = MFI->getMaxAlignment();
5538 assert(!AFI->isThumb1OnlyFunction());
5540 // Emit bic r6, r6, MaxAlign
5541 unsigned bicOpc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri;
5544 BuildMI(*MBB, MBBI, MI->getDebugLoc(), TII->get(bicOpc), ARM::R6)
5545 .addReg(ARM::R6, RegState::Kill)
5546 .addImm(MaxAlign - 1)));
5549 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
5550 /// registers the function context.
5551 void ARMTargetLowering::
5552 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
5553 MachineBasicBlock *DispatchBB, int FI) const {
5554 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5555 DebugLoc dl = MI->getDebugLoc();
5556 MachineFunction *MF = MBB->getParent();
5557 MachineRegisterInfo *MRI = &MF->getRegInfo();
5558 MachineConstantPool *MCP = MF->getConstantPool();
5559 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
5560 const Function *F = MF->getFunction();
5562 bool isThumb = Subtarget->isThumb();
5563 bool isThumb2 = Subtarget->isThumb2();
5565 unsigned PCLabelId = AFI->createPICLabelUId();
5566 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
5567 ARMConstantPoolValue *CPV =
5568 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
5569 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
5571 const TargetRegisterClass *TRC =
5572 isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5574 // Grab constant pool and fixed stack memory operands.
5575 MachineMemOperand *CPMMO =
5576 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
5577 MachineMemOperand::MOLoad, 4, 4);
5579 MachineMemOperand *FIMMOSt =
5580 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
5581 MachineMemOperand::MOStore, 4, 4);
5583 EmitBasePointerRecalculation(MI, MBB, DispatchBB);
5585 // Load the address of the dispatch MBB into the jump buffer.
5587 // Incoming value: jbuf
5588 // ldr.n r5, LCPI1_1
5591 // str r5, [$jbuf, #+4] ; &jbuf[1]
5592 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5593 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
5594 .addConstantPoolIndex(CPI)
5595 .addMemOperand(CPMMO));
5596 // Set the low bit because of thumb mode.
5597 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5599 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
5600 .addReg(NewVReg1, RegState::Kill)
5602 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5603 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
5604 .addReg(NewVReg2, RegState::Kill)
5606 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
5607 .addReg(NewVReg3, RegState::Kill)
5609 .addImm(36) // &jbuf[1] :: pc
5610 .addMemOperand(FIMMOSt));
5611 } else if (isThumb) {
5612 // Incoming value: jbuf
5613 // ldr.n r1, LCPI1_4
5617 // add r2, $jbuf, #+4 ; &jbuf[1]
5619 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5620 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
5621 .addConstantPoolIndex(CPI)
5622 .addMemOperand(CPMMO));
5623 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5624 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
5625 .addReg(NewVReg1, RegState::Kill)
5627 // Set the low bit because of thumb mode.
5628 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5629 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
5630 .addReg(ARM::CPSR, RegState::Define)
5632 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5633 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
5634 .addReg(ARM::CPSR, RegState::Define)
5635 .addReg(NewVReg2, RegState::Kill)
5636 .addReg(NewVReg3, RegState::Kill));
5637 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
5638 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
5640 .addImm(36)); // &jbuf[1] :: pc
5641 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
5642 .addReg(NewVReg4, RegState::Kill)
5643 .addReg(NewVReg5, RegState::Kill)
5645 .addMemOperand(FIMMOSt));
5647 // Incoming value: jbuf
5650 // str r1, [$jbuf, #+4] ; &jbuf[1]
5651 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5652 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
5653 .addConstantPoolIndex(CPI)
5655 .addMemOperand(CPMMO));
5656 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5657 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
5658 .addReg(NewVReg1, RegState::Kill)
5659 .addImm(PCLabelId));
5660 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
5661 .addReg(NewVReg2, RegState::Kill)
5663 .addImm(36) // &jbuf[1] :: pc
5664 .addMemOperand(FIMMOSt));
5668 MachineBasicBlock *ARMTargetLowering::
5669 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
5670 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5671 DebugLoc dl = MI->getDebugLoc();
5672 MachineFunction *MF = MBB->getParent();
5673 MachineRegisterInfo *MRI = &MF->getRegInfo();
5674 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
5675 MachineFrameInfo *MFI = MF->getFrameInfo();
5676 int FI = MFI->getFunctionContextIndex();
5678 const TargetRegisterClass *TRC =
5679 Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5681 // Get a mapping of the call site numbers to all of the landing pads they're
5683 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
5684 unsigned MaxCSNum = 0;
5685 MachineModuleInfo &MMI = MF->getMMI();
5686 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E; ++BB) {
5687 if (!BB->isLandingPad()) continue;
5689 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
5691 for (MachineBasicBlock::iterator
5692 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
5693 if (!II->isEHLabel()) continue;
5695 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
5696 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
5698 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
5699 for (SmallVectorImpl<unsigned>::iterator
5700 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
5701 CSI != CSE; ++CSI) {
5702 CallSiteNumToLPad[*CSI].push_back(BB);
5703 MaxCSNum = std::max(MaxCSNum, *CSI);
5709 // Get an ordered list of the machine basic blocks for the jump table.
5710 std::vector<MachineBasicBlock*> LPadList;
5711 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
5712 LPadList.reserve(CallSiteNumToLPad.size());
5713 for (unsigned I = 1; I <= MaxCSNum; ++I) {
5714 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
5715 for (SmallVectorImpl<MachineBasicBlock*>::iterator
5716 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
5717 LPadList.push_back(*II);
5718 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
5722 assert(!LPadList.empty() &&
5723 "No landing pad destinations for the dispatch jump table!");
5725 // Create the jump table and associated information.
5726 MachineJumpTableInfo *JTI =
5727 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
5728 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
5729 unsigned UId = AFI->createJumpTableUId();
5731 // Create the MBBs for the dispatch code.
5733 // Shove the dispatch's address into the return slot in the function context.
5734 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
5735 DispatchBB->setIsLandingPad();
5737 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
5738 BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP));
5739 DispatchBB->addSuccessor(TrapBB);
5741 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
5742 DispatchBB->addSuccessor(DispContBB);
5745 MF->insert(MF->end(), DispatchBB);
5746 MF->insert(MF->end(), DispContBB);
5747 MF->insert(MF->end(), TrapBB);
5749 // Insert code into the entry block that creates and registers the function
5751 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
5753 MachineMemOperand *FIMMOLd =
5754 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
5755 MachineMemOperand::MOLoad |
5756 MachineMemOperand::MOVolatile, 4, 4);
5758 if (Subtarget->isThumb2()) {
5759 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5760 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
5763 .addMemOperand(FIMMOLd));
5764 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
5766 .addImm(LPadList.size()));
5767 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
5772 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5773 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg2)
5774 .addJumpTableIndex(MJTI)
5777 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5780 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg3)
5781 .addReg(NewVReg2, RegState::Kill)
5783 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
5785 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
5786 .addReg(NewVReg3, RegState::Kill)
5788 .addJumpTableIndex(MJTI)
5790 } else if (Subtarget->isThumb()) {
5791 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5792 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
5795 .addMemOperand(FIMMOLd));
5797 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
5799 .addImm(LPadList.size()));
5800 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
5805 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5806 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
5807 .addReg(ARM::CPSR, RegState::Define)
5811 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5812 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
5813 .addJumpTableIndex(MJTI)
5816 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5817 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
5818 .addReg(ARM::CPSR, RegState::Define)
5819 .addReg(NewVReg2, RegState::Kill)
5822 MachineMemOperand *JTMMOLd =
5823 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
5824 MachineMemOperand::MOLoad, 4, 4);
5826 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
5827 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
5828 .addReg(NewVReg4, RegState::Kill)
5830 .addMemOperand(JTMMOLd));
5832 unsigned NewVReg6 = MRI->createVirtualRegister(TRC);
5833 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
5834 .addReg(ARM::CPSR, RegState::Define)
5835 .addReg(NewVReg5, RegState::Kill)
5838 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
5839 .addReg(NewVReg6, RegState::Kill)
5840 .addJumpTableIndex(MJTI)
5843 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5844 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
5847 .addMemOperand(FIMMOLd));
5848 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
5850 .addImm(LPadList.size()));
5851 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
5856 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5858 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg2)
5860 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
5861 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5862 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg3)
5863 .addJumpTableIndex(MJTI)
5866 MachineMemOperand *JTMMOLd =
5867 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
5868 MachineMemOperand::MOLoad, 4, 4);
5869 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5871 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg4)
5872 .addReg(NewVReg2, RegState::Kill)
5875 .addMemOperand(JTMMOLd));
5877 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
5878 .addReg(NewVReg4, RegState::Kill)
5880 .addJumpTableIndex(MJTI)
5884 // Add the jump table entries as successors to the MBB.
5885 MachineBasicBlock *PrevMBB = 0;
5886 for (std::vector<MachineBasicBlock*>::iterator
5887 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
5888 MachineBasicBlock *CurMBB = *I;
5889 if (PrevMBB != CurMBB)
5890 DispContBB->addSuccessor(CurMBB);
5894 // N.B. the order the invoke BBs are processed in doesn't matter here.
5895 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
5896 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
5897 const unsigned *SavedRegs = RI.getCalleeSavedRegs(MF);
5898 SmallVector<MachineBasicBlock*, 64> MBBLPads;
5899 for (SmallPtrSet<MachineBasicBlock*, 64>::iterator
5900 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) {
5901 MachineBasicBlock *BB = *I;
5903 // Remove the landing pad successor from the invoke block and replace it
5904 // with the new dispatch block.
5905 for (MachineBasicBlock::succ_iterator
5906 SI = BB->succ_begin(), SE = BB->succ_end(); SI != SE; ++SI) {
5907 MachineBasicBlock *SMBB = *SI;
5908 if (SMBB->isLandingPad()) {
5909 BB->removeSuccessor(SMBB);
5910 MBBLPads.push_back(SMBB);
5914 BB->addSuccessor(DispatchBB);
5916 // Find the invoke call and mark all of the callee-saved registers as
5917 // 'implicit defined' so that they're spilled. This prevents code from
5918 // moving instructions to before the EH block, where they will never be
5920 for (MachineBasicBlock::reverse_iterator
5921 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
5922 if (!II->getDesc().isCall()) continue;
5924 DenseMap<unsigned, bool> DefRegs;
5925 for (MachineInstr::mop_iterator
5926 OI = II->operands_begin(), OE = II->operands_end();
5928 if (!OI->isReg()) continue;
5929 DefRegs[OI->getReg()] = true;
5932 MachineInstrBuilder MIB(&*II);
5934 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
5935 if (!TRC->contains(SavedRegs[i])) continue;
5936 if (!DefRegs[SavedRegs[i]])
5937 MIB.addReg(SavedRegs[i], RegState::ImplicitDefine | RegState::Dead);
5944 // Mark all former landing pads as non-landing pads. The dispatch is the only
5946 for (SmallVectorImpl<MachineBasicBlock*>::iterator
5947 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
5948 (*I)->setIsLandingPad(false);
5950 // The instruction is gone now.
5951 MI->eraseFromParent();
5957 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
5958 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
5959 E = MBB->succ_end(); I != E; ++I)
5962 llvm_unreachable("Expecting a BB with two successors!");
5966 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
5967 MachineBasicBlock *BB) const {
5968 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5969 DebugLoc dl = MI->getDebugLoc();
5970 bool isThumb2 = Subtarget->isThumb2();
5971 switch (MI->getOpcode()) {
5974 llvm_unreachable("Unexpected instr type to insert");
5976 // The Thumb2 pre-indexed stores have the same MI operands, they just
5977 // define them differently in the .td files from the isel patterns, so
5978 // they need pseudos.
5979 case ARM::t2STR_preidx:
5980 MI->setDesc(TII->get(ARM::t2STR_PRE));
5982 case ARM::t2STRB_preidx:
5983 MI->setDesc(TII->get(ARM::t2STRB_PRE));
5985 case ARM::t2STRH_preidx:
5986 MI->setDesc(TII->get(ARM::t2STRH_PRE));
5989 case ARM::STRi_preidx:
5990 case ARM::STRBi_preidx: {
5991 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
5992 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
5993 // Decode the offset.
5994 unsigned Offset = MI->getOperand(4).getImm();
5995 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
5996 Offset = ARM_AM::getAM2Offset(Offset);
6000 MachineMemOperand *MMO = *MI->memoperands_begin();
6001 BuildMI(*BB, MI, dl, TII->get(NewOpc))
6002 .addOperand(MI->getOperand(0)) // Rn_wb
6003 .addOperand(MI->getOperand(1)) // Rt
6004 .addOperand(MI->getOperand(2)) // Rn
6005 .addImm(Offset) // offset (skip GPR==zero_reg)
6006 .addOperand(MI->getOperand(5)) // pred
6007 .addOperand(MI->getOperand(6))
6008 .addMemOperand(MMO);
6009 MI->eraseFromParent();
6012 case ARM::STRr_preidx:
6013 case ARM::STRBr_preidx:
6014 case ARM::STRH_preidx: {
6016 switch (MI->getOpcode()) {
6017 default: llvm_unreachable("unexpected opcode!");
6018 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
6019 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
6020 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
6022 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
6023 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
6024 MIB.addOperand(MI->getOperand(i));
6025 MI->eraseFromParent();
6028 case ARM::ATOMIC_LOAD_ADD_I8:
6029 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6030 case ARM::ATOMIC_LOAD_ADD_I16:
6031 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6032 case ARM::ATOMIC_LOAD_ADD_I32:
6033 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6035 case ARM::ATOMIC_LOAD_AND_I8:
6036 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6037 case ARM::ATOMIC_LOAD_AND_I16:
6038 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6039 case ARM::ATOMIC_LOAD_AND_I32:
6040 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6042 case ARM::ATOMIC_LOAD_OR_I8:
6043 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6044 case ARM::ATOMIC_LOAD_OR_I16:
6045 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6046 case ARM::ATOMIC_LOAD_OR_I32:
6047 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6049 case ARM::ATOMIC_LOAD_XOR_I8:
6050 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6051 case ARM::ATOMIC_LOAD_XOR_I16:
6052 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6053 case ARM::ATOMIC_LOAD_XOR_I32:
6054 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6056 case ARM::ATOMIC_LOAD_NAND_I8:
6057 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6058 case ARM::ATOMIC_LOAD_NAND_I16:
6059 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6060 case ARM::ATOMIC_LOAD_NAND_I32:
6061 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6063 case ARM::ATOMIC_LOAD_SUB_I8:
6064 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6065 case ARM::ATOMIC_LOAD_SUB_I16:
6066 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6067 case ARM::ATOMIC_LOAD_SUB_I32:
6068 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6070 case ARM::ATOMIC_LOAD_MIN_I8:
6071 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
6072 case ARM::ATOMIC_LOAD_MIN_I16:
6073 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
6074 case ARM::ATOMIC_LOAD_MIN_I32:
6075 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
6077 case ARM::ATOMIC_LOAD_MAX_I8:
6078 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
6079 case ARM::ATOMIC_LOAD_MAX_I16:
6080 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
6081 case ARM::ATOMIC_LOAD_MAX_I32:
6082 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
6084 case ARM::ATOMIC_LOAD_UMIN_I8:
6085 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
6086 case ARM::ATOMIC_LOAD_UMIN_I16:
6087 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
6088 case ARM::ATOMIC_LOAD_UMIN_I32:
6089 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
6091 case ARM::ATOMIC_LOAD_UMAX_I8:
6092 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
6093 case ARM::ATOMIC_LOAD_UMAX_I16:
6094 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
6095 case ARM::ATOMIC_LOAD_UMAX_I32:
6096 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
6098 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
6099 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
6100 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
6102 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
6103 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
6104 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
6107 case ARM::ATOMADD6432:
6108 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr,
6109 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr,
6110 /*NeedsCarry*/ true);
6111 case ARM::ATOMSUB6432:
6112 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
6113 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
6114 /*NeedsCarry*/ true);
6115 case ARM::ATOMOR6432:
6116 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr,
6117 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6118 case ARM::ATOMXOR6432:
6119 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr,
6120 isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6121 case ARM::ATOMAND6432:
6122 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr,
6123 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6124 case ARM::ATOMSWAP6432:
6125 return EmitAtomicBinary64(MI, BB, 0, 0, false);
6126 case ARM::ATOMCMPXCHG6432:
6127 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
6128 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
6129 /*NeedsCarry*/ false, /*IsCmpxchg*/true);
6131 case ARM::tMOVCCr_pseudo: {
6132 // To "insert" a SELECT_CC instruction, we actually have to insert the
6133 // diamond control-flow pattern. The incoming instruction knows the
6134 // destination vreg to set, the condition code register to branch on, the
6135 // true/false values to select between, and a branch opcode to use.
6136 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6137 MachineFunction::iterator It = BB;
6143 // cmpTY ccX, r1, r2
6145 // fallthrough --> copy0MBB
6146 MachineBasicBlock *thisMBB = BB;
6147 MachineFunction *F = BB->getParent();
6148 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6149 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6150 F->insert(It, copy0MBB);
6151 F->insert(It, sinkMBB);
6153 // Transfer the remainder of BB and its successor edges to sinkMBB.
6154 sinkMBB->splice(sinkMBB->begin(), BB,
6155 llvm::next(MachineBasicBlock::iterator(MI)),
6157 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6159 BB->addSuccessor(copy0MBB);
6160 BB->addSuccessor(sinkMBB);
6162 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
6163 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
6166 // %FalseValue = ...
6167 // # fallthrough to sinkMBB
6170 // Update machine-CFG edges
6171 BB->addSuccessor(sinkMBB);
6174 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6177 BuildMI(*BB, BB->begin(), dl,
6178 TII->get(ARM::PHI), MI->getOperand(0).getReg())
6179 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6180 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6182 MI->eraseFromParent(); // The pseudo instruction is gone now.
6187 case ARM::BCCZi64: {
6188 // If there is an unconditional branch to the other successor, remove it.
6189 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
6191 // Compare both parts that make up the double comparison separately for
6193 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
6195 unsigned LHS1 = MI->getOperand(1).getReg();
6196 unsigned LHS2 = MI->getOperand(2).getReg();
6198 AddDefaultPred(BuildMI(BB, dl,
6199 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6200 .addReg(LHS1).addImm(0));
6201 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6202 .addReg(LHS2).addImm(0)
6203 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
6205 unsigned RHS1 = MI->getOperand(3).getReg();
6206 unsigned RHS2 = MI->getOperand(4).getReg();
6207 AddDefaultPred(BuildMI(BB, dl,
6208 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6209 .addReg(LHS1).addReg(RHS1));
6210 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6211 .addReg(LHS2).addReg(RHS2)
6212 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
6215 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
6216 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
6217 if (MI->getOperand(0).getImm() == ARMCC::NE)
6218 std::swap(destMBB, exitMBB);
6220 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6221 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
6223 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
6225 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
6227 MI->eraseFromParent(); // The pseudo instruction is gone now.
6231 case ARM::Int_eh_sjlj_setjmp:
6232 case ARM::Int_eh_sjlj_setjmp_nofp:
6233 case ARM::tInt_eh_sjlj_setjmp:
6234 case ARM::t2Int_eh_sjlj_setjmp:
6235 case ARM::t2Int_eh_sjlj_setjmp_nofp:
6236 EmitSjLjDispatchBlock(MI, BB);
6241 // To insert an ABS instruction, we have to insert the
6242 // diamond control-flow pattern. The incoming instruction knows the
6243 // source vreg to test against 0, the destination vreg to set,
6244 // the condition code register to branch on, the
6245 // true/false values to select between, and a branch opcode to use.
6250 // BCC (branch to SinkBB if V0 >= 0)
6251 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
6252 // SinkBB: V1 = PHI(V2, V3)
6253 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6254 MachineFunction::iterator BBI = BB;
6256 MachineFunction *Fn = BB->getParent();
6257 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
6258 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
6259 Fn->insert(BBI, RSBBB);
6260 Fn->insert(BBI, SinkBB);
6262 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
6263 unsigned int ABSDstReg = MI->getOperand(0).getReg();
6264 bool isThumb2 = Subtarget->isThumb2();
6265 MachineRegisterInfo &MRI = Fn->getRegInfo();
6266 // In Thumb mode S must not be specified if source register is the SP or
6267 // PC and if destination register is the SP, so restrict register class
6268 unsigned NewMovDstReg = MRI.createVirtualRegister(
6269 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
6270 unsigned NewRsbDstReg = MRI.createVirtualRegister(
6271 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
6273 // Transfer the remainder of BB and its successor edges to sinkMBB.
6274 SinkBB->splice(SinkBB->begin(), BB,
6275 llvm::next(MachineBasicBlock::iterator(MI)),
6277 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
6279 BB->addSuccessor(RSBBB);
6280 BB->addSuccessor(SinkBB);
6282 // fall through to SinkMBB
6283 RSBBB->addSuccessor(SinkBB);
6285 // insert a movs at the end of BB
6286 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVr : ARM::MOVr),
6288 .addReg(ABSSrcReg, RegState::Kill)
6289 .addImm((unsigned)ARMCC::AL).addReg(0)
6290 .addReg(ARM::CPSR, RegState::Define);
6292 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
6294 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
6295 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
6297 // insert rsbri in RSBBB
6298 // Note: BCC and rsbri will be converted into predicated rsbmi
6299 // by if-conversion pass
6300 BuildMI(*RSBBB, RSBBB->begin(), dl,
6301 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
6302 .addReg(NewMovDstReg, RegState::Kill)
6303 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
6305 // insert PHI in SinkBB,
6306 // reuse ABSDstReg to not change uses of ABS instruction
6307 BuildMI(*SinkBB, SinkBB->begin(), dl,
6308 TII->get(ARM::PHI), ABSDstReg)
6309 .addReg(NewRsbDstReg).addMBB(RSBBB)
6310 .addReg(NewMovDstReg).addMBB(BB);
6312 // remove ABS instruction
6313 MI->eraseFromParent();
6315 // return last added BB
6321 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
6322 SDNode *Node) const {
6323 const MCInstrDesc &MCID = MI->getDesc();
6324 if (!MCID.hasPostISelHook()) {
6325 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
6326 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
6330 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
6331 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
6332 // operand is still set to noreg. If needed, set the optional operand's
6333 // register to CPSR, and remove the redundant implicit def.
6335 // e.g. ADCS (...opt:%noreg, CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
6337 // Rename pseudo opcodes.
6338 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
6340 const ARMBaseInstrInfo *TII =
6341 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
6342 MI->setDesc(TII->get(NewOpc));
6344 unsigned ccOutIdx = MCID.getNumOperands() - 1;
6346 // Any ARM instruction that sets the 's' bit should specify an optional
6347 // "cc_out" operand in the last operand position.
6348 if (!MCID.hasOptionalDef() || !MCID.OpInfo[ccOutIdx].isOptionalDef()) {
6349 assert(!NewOpc && "Optional cc_out operand required");
6352 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
6353 // since we already have an optional CPSR def.
6354 bool definesCPSR = false;
6355 bool deadCPSR = false;
6356 for (unsigned i = MCID.getNumOperands(), e = MI->getNumOperands();
6358 const MachineOperand &MO = MI->getOperand(i);
6359 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
6363 MI->RemoveOperand(i);
6368 assert(!NewOpc && "Optional cc_out operand required");
6371 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
6373 assert(!MI->getOperand(ccOutIdx).getReg() &&
6374 "expect uninitialized optional cc_out operand");
6378 // If this instruction was defined with an optional CPSR def and its dag node
6379 // had a live implicit CPSR def, then activate the optional CPSR def.
6380 MachineOperand &MO = MI->getOperand(ccOutIdx);
6381 MO.setReg(ARM::CPSR);
6385 //===----------------------------------------------------------------------===//
6386 // ARM Optimization Hooks
6387 //===----------------------------------------------------------------------===//
6390 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
6391 TargetLowering::DAGCombinerInfo &DCI) {
6392 SelectionDAG &DAG = DCI.DAG;
6393 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6394 EVT VT = N->getValueType(0);
6395 unsigned Opc = N->getOpcode();
6396 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
6397 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
6398 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
6399 ISD::CondCode CC = ISD::SETCC_INVALID;
6402 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
6404 SDValue CCOp = Slct.getOperand(0);
6405 if (CCOp.getOpcode() == ISD::SETCC)
6406 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
6409 bool DoXform = false;
6411 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
6414 if (LHS.getOpcode() == ISD::Constant &&
6415 cast<ConstantSDNode>(LHS)->isNullValue()) {
6417 } else if (CC != ISD::SETCC_INVALID &&
6418 RHS.getOpcode() == ISD::Constant &&
6419 cast<ConstantSDNode>(RHS)->isNullValue()) {
6420 std::swap(LHS, RHS);
6421 SDValue Op0 = Slct.getOperand(0);
6422 EVT OpVT = isSlctCC ? Op0.getValueType() :
6423 Op0.getOperand(0).getValueType();
6424 bool isInt = OpVT.isInteger();
6425 CC = ISD::getSetCCInverse(CC, isInt);
6427 if (!TLI.isCondCodeLegal(CC, OpVT))
6428 return SDValue(); // Inverse operator isn't legal.
6435 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
6437 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
6438 Slct.getOperand(0), Slct.getOperand(1), CC);
6439 SDValue CCOp = Slct.getOperand(0);
6441 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
6442 CCOp.getOperand(0), CCOp.getOperand(1), CC);
6443 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
6444 CCOp, OtherOp, Result);
6449 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
6450 // (only after legalization).
6451 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
6452 TargetLowering::DAGCombinerInfo &DCI,
6453 const ARMSubtarget *Subtarget) {
6455 // Only perform optimization if after legalize, and if NEON is available. We
6456 // also expected both operands to be BUILD_VECTORs.
6457 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
6458 || N0.getOpcode() != ISD::BUILD_VECTOR
6459 || N1.getOpcode() != ISD::BUILD_VECTOR)
6462 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
6463 EVT VT = N->getValueType(0);
6464 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
6467 // Check that the vector operands are of the right form.
6468 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
6469 // operands, where N is the size of the formed vector.
6470 // Each EXTRACT_VECTOR should have the same input vector and odd or even
6471 // index such that we have a pair wise add pattern.
6473 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
6474 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6476 SDValue Vec = N0->getOperand(0)->getOperand(0);
6477 SDNode *V = Vec.getNode();
6478 unsigned nextIndex = 0;
6480 // For each operands to the ADD which are BUILD_VECTORs,
6481 // check to see if each of their operands are an EXTRACT_VECTOR with
6482 // the same vector and appropriate index.
6483 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
6484 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
6485 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6487 SDValue ExtVec0 = N0->getOperand(i);
6488 SDValue ExtVec1 = N1->getOperand(i);
6490 // First operand is the vector, verify its the same.
6491 if (V != ExtVec0->getOperand(0).getNode() ||
6492 V != ExtVec1->getOperand(0).getNode())
6495 // Second is the constant, verify its correct.
6496 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
6497 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
6499 // For the constant, we want to see all the even or all the odd.
6500 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
6501 || C1->getZExtValue() != nextIndex+1)
6510 // Create VPADDL node.
6511 SelectionDAG &DAG = DCI.DAG;
6512 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6514 // Build operand list.
6515 SmallVector<SDValue, 8> Ops;
6516 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
6517 TLI.getPointerTy()));
6519 // Input is the vector.
6522 // Get widened type and narrowed type.
6524 unsigned numElem = VT.getVectorNumElements();
6525 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
6526 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
6527 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
6528 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
6530 assert(0 && "Invalid vector element type for padd optimization.");
6533 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
6534 widenType, &Ops[0], Ops.size());
6535 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp);
6538 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
6539 /// operands N0 and N1. This is a helper for PerformADDCombine that is
6540 /// called with the default operands, and if that fails, with commuted
6542 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
6543 TargetLowering::DAGCombinerInfo &DCI,
6544 const ARMSubtarget *Subtarget){
6546 // Attempt to create vpaddl for this add.
6547 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
6548 if (Result.getNode())
6551 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
6552 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
6553 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
6554 if (Result.getNode()) return Result;
6559 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
6561 static SDValue PerformADDCombine(SDNode *N,
6562 TargetLowering::DAGCombinerInfo &DCI,
6563 const ARMSubtarget *Subtarget) {
6564 SDValue N0 = N->getOperand(0);
6565 SDValue N1 = N->getOperand(1);
6567 // First try with the default operand order.
6568 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
6569 if (Result.getNode())
6572 // If that didn't work, try again with the operands commuted.
6573 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
6576 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
6578 static SDValue PerformSUBCombine(SDNode *N,
6579 TargetLowering::DAGCombinerInfo &DCI) {
6580 SDValue N0 = N->getOperand(0);
6581 SDValue N1 = N->getOperand(1);
6583 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
6584 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
6585 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
6586 if (Result.getNode()) return Result;
6592 /// PerformVMULCombine
6593 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
6594 /// special multiplier accumulator forwarding.
6600 static SDValue PerformVMULCombine(SDNode *N,
6601 TargetLowering::DAGCombinerInfo &DCI,
6602 const ARMSubtarget *Subtarget) {
6603 if (!Subtarget->hasVMLxForwarding())
6606 SelectionDAG &DAG = DCI.DAG;
6607 SDValue N0 = N->getOperand(0);
6608 SDValue N1 = N->getOperand(1);
6609 unsigned Opcode = N0.getOpcode();
6610 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
6611 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
6612 Opcode = N1.getOpcode();
6613 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
6614 Opcode != ISD::FADD && Opcode != ISD::FSUB)
6619 EVT VT = N->getValueType(0);
6620 DebugLoc DL = N->getDebugLoc();
6621 SDValue N00 = N0->getOperand(0);
6622 SDValue N01 = N0->getOperand(1);
6623 return DAG.getNode(Opcode, DL, VT,
6624 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
6625 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
6628 static SDValue PerformMULCombine(SDNode *N,
6629 TargetLowering::DAGCombinerInfo &DCI,
6630 const ARMSubtarget *Subtarget) {
6631 SelectionDAG &DAG = DCI.DAG;
6633 if (Subtarget->isThumb1Only())
6636 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
6639 EVT VT = N->getValueType(0);
6640 if (VT.is64BitVector() || VT.is128BitVector())
6641 return PerformVMULCombine(N, DCI, Subtarget);
6645 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
6649 uint64_t MulAmt = C->getZExtValue();
6650 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
6651 ShiftAmt = ShiftAmt & (32 - 1);
6652 SDValue V = N->getOperand(0);
6653 DebugLoc DL = N->getDebugLoc();
6656 MulAmt >>= ShiftAmt;
6657 if (isPowerOf2_32(MulAmt - 1)) {
6658 // (mul x, 2^N + 1) => (add (shl x, N), x)
6659 Res = DAG.getNode(ISD::ADD, DL, VT,
6660 V, DAG.getNode(ISD::SHL, DL, VT,
6661 V, DAG.getConstant(Log2_32(MulAmt-1),
6663 } else if (isPowerOf2_32(MulAmt + 1)) {
6664 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6665 Res = DAG.getNode(ISD::SUB, DL, VT,
6666 DAG.getNode(ISD::SHL, DL, VT,
6667 V, DAG.getConstant(Log2_32(MulAmt+1),
6674 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
6675 DAG.getConstant(ShiftAmt, MVT::i32));
6677 // Do not add new nodes to DAG combiner worklist.
6678 DCI.CombineTo(N, Res, false);
6682 static SDValue PerformANDCombine(SDNode *N,
6683 TargetLowering::DAGCombinerInfo &DCI) {
6685 // Attempt to use immediate-form VBIC
6686 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
6687 DebugLoc dl = N->getDebugLoc();
6688 EVT VT = N->getValueType(0);
6689 SelectionDAG &DAG = DCI.DAG;
6691 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6694 APInt SplatBits, SplatUndef;
6695 unsigned SplatBitSize;
6698 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
6699 if (SplatBitSize <= 64) {
6701 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
6702 SplatUndef.getZExtValue(), SplatBitSize,
6703 DAG, VbicVT, VT.is128BitVector(),
6705 if (Val.getNode()) {
6707 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
6708 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
6709 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
6717 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
6718 static SDValue PerformORCombine(SDNode *N,
6719 TargetLowering::DAGCombinerInfo &DCI,
6720 const ARMSubtarget *Subtarget) {
6721 // Attempt to use immediate-form VORR
6722 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
6723 DebugLoc dl = N->getDebugLoc();
6724 EVT VT = N->getValueType(0);
6725 SelectionDAG &DAG = DCI.DAG;
6727 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6730 APInt SplatBits, SplatUndef;
6731 unsigned SplatBitSize;
6733 if (BVN && Subtarget->hasNEON() &&
6734 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
6735 if (SplatBitSize <= 64) {
6737 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
6738 SplatUndef.getZExtValue(), SplatBitSize,
6739 DAG, VorrVT, VT.is128BitVector(),
6741 if (Val.getNode()) {
6743 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
6744 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
6745 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
6750 SDValue N0 = N->getOperand(0);
6751 if (N0.getOpcode() != ISD::AND)
6753 SDValue N1 = N->getOperand(1);
6755 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
6756 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
6757 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
6759 unsigned SplatBitSize;
6762 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
6764 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
6765 HasAnyUndefs) && !HasAnyUndefs) {
6766 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
6768 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
6769 HasAnyUndefs) && !HasAnyUndefs &&
6770 SplatBits0 == ~SplatBits1) {
6771 // Canonicalize the vector type to make instruction selection simpler.
6772 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
6773 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
6774 N0->getOperand(1), N0->getOperand(0),
6776 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
6781 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
6784 // BFI is only available on V6T2+
6785 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
6788 DebugLoc DL = N->getDebugLoc();
6789 // 1) or (and A, mask), val => ARMbfi A, val, mask
6790 // iff (val & mask) == val
6792 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
6793 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
6794 // && mask == ~mask2
6795 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
6796 // && ~mask == mask2
6797 // (i.e., copy a bitfield value into another bitfield of the same width)
6802 SDValue N00 = N0.getOperand(0);
6804 // The value and the mask need to be constants so we can verify this is
6805 // actually a bitfield set. If the mask is 0xffff, we can do better
6806 // via a movt instruction, so don't use BFI in that case.
6807 SDValue MaskOp = N0.getOperand(1);
6808 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
6811 unsigned Mask = MaskC->getZExtValue();
6815 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
6816 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
6818 unsigned Val = N1C->getZExtValue();
6819 if ((Val & ~Mask) != Val)
6822 if (ARM::isBitFieldInvertedMask(Mask)) {
6823 Val >>= CountTrailingZeros_32(~Mask);
6825 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
6826 DAG.getConstant(Val, MVT::i32),
6827 DAG.getConstant(Mask, MVT::i32));
6829 // Do not add new nodes to DAG combiner worklist.
6830 DCI.CombineTo(N, Res, false);
6833 } else if (N1.getOpcode() == ISD::AND) {
6834 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
6835 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
6838 unsigned Mask2 = N11C->getZExtValue();
6840 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
6842 if (ARM::isBitFieldInvertedMask(Mask) &&
6844 // The pack halfword instruction works better for masks that fit it,
6845 // so use that when it's available.
6846 if (Subtarget->hasT2ExtractPack() &&
6847 (Mask == 0xffff || Mask == 0xffff0000))
6850 unsigned amt = CountTrailingZeros_32(Mask2);
6851 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
6852 DAG.getConstant(amt, MVT::i32));
6853 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
6854 DAG.getConstant(Mask, MVT::i32));
6855 // Do not add new nodes to DAG combiner worklist.
6856 DCI.CombineTo(N, Res, false);
6858 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
6860 // The pack halfword instruction works better for masks that fit it,
6861 // so use that when it's available.
6862 if (Subtarget->hasT2ExtractPack() &&
6863 (Mask2 == 0xffff || Mask2 == 0xffff0000))
6866 unsigned lsb = CountTrailingZeros_32(Mask);
6867 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
6868 DAG.getConstant(lsb, MVT::i32));
6869 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
6870 DAG.getConstant(Mask2, MVT::i32));
6871 // Do not add new nodes to DAG combiner worklist.
6872 DCI.CombineTo(N, Res, false);
6877 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
6878 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
6879 ARM::isBitFieldInvertedMask(~Mask)) {
6880 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
6881 // where lsb(mask) == #shamt and masked bits of B are known zero.
6882 SDValue ShAmt = N00.getOperand(1);
6883 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
6884 unsigned LSB = CountTrailingZeros_32(Mask);
6888 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
6889 DAG.getConstant(~Mask, MVT::i32));
6891 // Do not add new nodes to DAG combiner worklist.
6892 DCI.CombineTo(N, Res, false);
6898 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
6899 /// the bits being cleared by the AND are not demanded by the BFI.
6900 static SDValue PerformBFICombine(SDNode *N,
6901 TargetLowering::DAGCombinerInfo &DCI) {
6902 SDValue N1 = N->getOperand(1);
6903 if (N1.getOpcode() == ISD::AND) {
6904 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
6907 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
6908 unsigned LSB = CountTrailingZeros_32(~InvMask);
6909 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB;
6910 unsigned Mask = (1 << Width)-1;
6911 unsigned Mask2 = N11C->getZExtValue();
6912 if ((Mask & (~Mask2)) == 0)
6913 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
6914 N->getOperand(0), N1.getOperand(0),
6920 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
6921 /// ARMISD::VMOVRRD.
6922 static SDValue PerformVMOVRRDCombine(SDNode *N,
6923 TargetLowering::DAGCombinerInfo &DCI) {
6924 // vmovrrd(vmovdrr x, y) -> x,y
6925 SDValue InDouble = N->getOperand(0);
6926 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
6927 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
6929 // vmovrrd(load f64) -> (load i32), (load i32)
6930 SDNode *InNode = InDouble.getNode();
6931 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
6932 InNode->getValueType(0) == MVT::f64 &&
6933 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
6934 !cast<LoadSDNode>(InNode)->isVolatile()) {
6935 // TODO: Should this be done for non-FrameIndex operands?
6936 LoadSDNode *LD = cast<LoadSDNode>(InNode);
6938 SelectionDAG &DAG = DCI.DAG;
6939 DebugLoc DL = LD->getDebugLoc();
6940 SDValue BasePtr = LD->getBasePtr();
6941 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
6942 LD->getPointerInfo(), LD->isVolatile(),
6943 LD->isNonTemporal(), LD->getAlignment());
6945 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
6946 DAG.getConstant(4, MVT::i32));
6947 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
6948 LD->getPointerInfo(), LD->isVolatile(),
6949 LD->isNonTemporal(),
6950 std::min(4U, LD->getAlignment() / 2));
6952 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
6953 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
6954 DCI.RemoveFromWorklist(LD);
6962 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
6963 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
6964 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
6965 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
6966 SDValue Op0 = N->getOperand(0);
6967 SDValue Op1 = N->getOperand(1);
6968 if (Op0.getOpcode() == ISD::BITCAST)
6969 Op0 = Op0.getOperand(0);
6970 if (Op1.getOpcode() == ISD::BITCAST)
6971 Op1 = Op1.getOperand(0);
6972 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
6973 Op0.getNode() == Op1.getNode() &&
6974 Op0.getResNo() == 0 && Op1.getResNo() == 1)
6975 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6976 N->getValueType(0), Op0.getOperand(0));
6980 /// PerformSTORECombine - Target-specific dag combine xforms for
6982 static SDValue PerformSTORECombine(SDNode *N,
6983 TargetLowering::DAGCombinerInfo &DCI) {
6984 // Bitcast an i64 store extracted from a vector to f64.
6985 // Otherwise, the i64 value will be legalized to a pair of i32 values.
6986 StoreSDNode *St = cast<StoreSDNode>(N);
6987 SDValue StVal = St->getValue();
6988 if (!ISD::isNormalStore(St) || St->isVolatile())
6991 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
6992 StVal.getNode()->hasOneUse() && !St->isVolatile()) {
6993 SelectionDAG &DAG = DCI.DAG;
6994 DebugLoc DL = St->getDebugLoc();
6995 SDValue BasePtr = St->getBasePtr();
6996 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
6997 StVal.getNode()->getOperand(0), BasePtr,
6998 St->getPointerInfo(), St->isVolatile(),
6999 St->isNonTemporal(), St->getAlignment());
7001 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
7002 DAG.getConstant(4, MVT::i32));
7003 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
7004 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
7005 St->isNonTemporal(),
7006 std::min(4U, St->getAlignment() / 2));
7009 if (StVal.getValueType() != MVT::i64 ||
7010 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7013 SelectionDAG &DAG = DCI.DAG;
7014 DebugLoc dl = StVal.getDebugLoc();
7015 SDValue IntVec = StVal.getOperand(0);
7016 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
7017 IntVec.getValueType().getVectorNumElements());
7018 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
7019 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7020 Vec, StVal.getOperand(1));
7021 dl = N->getDebugLoc();
7022 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
7023 // Make the DAGCombiner fold the bitcasts.
7024 DCI.AddToWorklist(Vec.getNode());
7025 DCI.AddToWorklist(ExtElt.getNode());
7026 DCI.AddToWorklist(V.getNode());
7027 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
7028 St->getPointerInfo(), St->isVolatile(),
7029 St->isNonTemporal(), St->getAlignment(),
7033 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
7034 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
7035 /// i64 vector to have f64 elements, since the value can then be loaded
7036 /// directly into a VFP register.
7037 static bool hasNormalLoadOperand(SDNode *N) {
7038 unsigned NumElts = N->getValueType(0).getVectorNumElements();
7039 for (unsigned i = 0; i < NumElts; ++i) {
7040 SDNode *Elt = N->getOperand(i).getNode();
7041 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
7047 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
7048 /// ISD::BUILD_VECTOR.
7049 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
7050 TargetLowering::DAGCombinerInfo &DCI){
7051 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
7052 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
7053 // into a pair of GPRs, which is fine when the value is used as a scalar,
7054 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
7055 SelectionDAG &DAG = DCI.DAG;
7056 if (N->getNumOperands() == 2) {
7057 SDValue RV = PerformVMOVDRRCombine(N, DAG);
7062 // Load i64 elements as f64 values so that type legalization does not split
7063 // them up into i32 values.
7064 EVT VT = N->getValueType(0);
7065 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
7067 DebugLoc dl = N->getDebugLoc();
7068 SmallVector<SDValue, 8> Ops;
7069 unsigned NumElts = VT.getVectorNumElements();
7070 for (unsigned i = 0; i < NumElts; ++i) {
7071 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
7073 // Make the DAGCombiner fold the bitcast.
7074 DCI.AddToWorklist(V.getNode());
7076 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
7077 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
7078 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
7081 /// PerformInsertEltCombine - Target-specific dag combine xforms for
7082 /// ISD::INSERT_VECTOR_ELT.
7083 static SDValue PerformInsertEltCombine(SDNode *N,
7084 TargetLowering::DAGCombinerInfo &DCI) {
7085 // Bitcast an i64 load inserted into a vector to f64.
7086 // Otherwise, the i64 value will be legalized to a pair of i32 values.
7087 EVT VT = N->getValueType(0);
7088 SDNode *Elt = N->getOperand(1).getNode();
7089 if (VT.getVectorElementType() != MVT::i64 ||
7090 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
7093 SelectionDAG &DAG = DCI.DAG;
7094 DebugLoc dl = N->getDebugLoc();
7095 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
7096 VT.getVectorNumElements());
7097 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
7098 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
7099 // Make the DAGCombiner fold the bitcasts.
7100 DCI.AddToWorklist(Vec.getNode());
7101 DCI.AddToWorklist(V.getNode());
7102 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
7103 Vec, V, N->getOperand(2));
7104 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
7107 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
7108 /// ISD::VECTOR_SHUFFLE.
7109 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
7110 // The LLVM shufflevector instruction does not require the shuffle mask
7111 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
7112 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
7113 // operands do not match the mask length, they are extended by concatenating
7114 // them with undef vectors. That is probably the right thing for other
7115 // targets, but for NEON it is better to concatenate two double-register
7116 // size vector operands into a single quad-register size vector. Do that
7117 // transformation here:
7118 // shuffle(concat(v1, undef), concat(v2, undef)) ->
7119 // shuffle(concat(v1, v2), undef)
7120 SDValue Op0 = N->getOperand(0);
7121 SDValue Op1 = N->getOperand(1);
7122 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
7123 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
7124 Op0.getNumOperands() != 2 ||
7125 Op1.getNumOperands() != 2)
7127 SDValue Concat0Op1 = Op0.getOperand(1);
7128 SDValue Concat1Op1 = Op1.getOperand(1);
7129 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
7130 Concat1Op1.getOpcode() != ISD::UNDEF)
7132 // Skip the transformation if any of the types are illegal.
7133 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7134 EVT VT = N->getValueType(0);
7135 if (!TLI.isTypeLegal(VT) ||
7136 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
7137 !TLI.isTypeLegal(Concat1Op1.getValueType()))
7140 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
7141 Op0.getOperand(0), Op1.getOperand(0));
7142 // Translate the shuffle mask.
7143 SmallVector<int, 16> NewMask;
7144 unsigned NumElts = VT.getVectorNumElements();
7145 unsigned HalfElts = NumElts/2;
7146 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7147 for (unsigned n = 0; n < NumElts; ++n) {
7148 int MaskElt = SVN->getMaskElt(n);
7150 if (MaskElt < (int)HalfElts)
7152 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
7153 NewElt = HalfElts + MaskElt - NumElts;
7154 NewMask.push_back(NewElt);
7156 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
7157 DAG.getUNDEF(VT), NewMask.data());
7160 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
7161 /// NEON load/store intrinsics to merge base address updates.
7162 static SDValue CombineBaseUpdate(SDNode *N,
7163 TargetLowering::DAGCombinerInfo &DCI) {
7164 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7167 SelectionDAG &DAG = DCI.DAG;
7168 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
7169 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
7170 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
7171 SDValue Addr = N->getOperand(AddrOpIdx);
7173 // Search for a use of the address operand that is an increment.
7174 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7175 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7177 if (User->getOpcode() != ISD::ADD ||
7178 UI.getUse().getResNo() != Addr.getResNo())
7181 // Check that the add is independent of the load/store. Otherwise, folding
7182 // it would create a cycle.
7183 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7186 // Find the new opcode for the updating load/store.
7188 bool isLaneOp = false;
7189 unsigned NewOpc = 0;
7190 unsigned NumVecs = 0;
7192 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7194 default: assert(0 && "unexpected intrinsic for Neon base update");
7195 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
7197 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
7199 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
7201 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
7203 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
7204 NumVecs = 2; isLaneOp = true; break;
7205 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
7206 NumVecs = 3; isLaneOp = true; break;
7207 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
7208 NumVecs = 4; isLaneOp = true; break;
7209 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
7210 NumVecs = 1; isLoad = false; break;
7211 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
7212 NumVecs = 2; isLoad = false; break;
7213 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
7214 NumVecs = 3; isLoad = false; break;
7215 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
7216 NumVecs = 4; isLoad = false; break;
7217 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
7218 NumVecs = 2; isLoad = false; isLaneOp = true; break;
7219 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
7220 NumVecs = 3; isLoad = false; isLaneOp = true; break;
7221 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
7222 NumVecs = 4; isLoad = false; isLaneOp = true; break;
7226 switch (N->getOpcode()) {
7227 default: assert(0 && "unexpected opcode for Neon base update");
7228 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
7229 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
7230 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
7234 // Find the size of memory referenced by the load/store.
7237 VecTy = N->getValueType(0);
7239 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
7240 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7242 NumBytes /= VecTy.getVectorNumElements();
7244 // If the increment is a constant, it must match the memory ref size.
7245 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7246 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7247 uint64_t IncVal = CInc->getZExtValue();
7248 if (IncVal != NumBytes)
7250 } else if (NumBytes >= 3 * 16) {
7251 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
7252 // separate instructions that make it harder to use a non-constant update.
7256 // Create the new updating load/store node.
7258 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
7260 for (n = 0; n < NumResultVecs; ++n)
7262 Tys[n++] = MVT::i32;
7263 Tys[n] = MVT::Other;
7264 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
7265 SmallVector<SDValue, 8> Ops;
7266 Ops.push_back(N->getOperand(0)); // incoming chain
7267 Ops.push_back(N->getOperand(AddrOpIdx));
7269 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
7270 Ops.push_back(N->getOperand(i));
7272 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7273 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
7274 Ops.data(), Ops.size(),
7275 MemInt->getMemoryVT(),
7276 MemInt->getMemOperand());
7279 std::vector<SDValue> NewResults;
7280 for (unsigned i = 0; i < NumResultVecs; ++i) {
7281 NewResults.push_back(SDValue(UpdN.getNode(), i));
7283 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
7284 DCI.CombineTo(N, NewResults);
7285 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7292 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
7293 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
7294 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
7296 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
7297 SelectionDAG &DAG = DCI.DAG;
7298 EVT VT = N->getValueType(0);
7299 // vldN-dup instructions only support 64-bit vectors for N > 1.
7300 if (!VT.is64BitVector())
7303 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
7304 SDNode *VLD = N->getOperand(0).getNode();
7305 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
7307 unsigned NumVecs = 0;
7308 unsigned NewOpc = 0;
7309 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
7310 if (IntNo == Intrinsic::arm_neon_vld2lane) {
7312 NewOpc = ARMISD::VLD2DUP;
7313 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
7315 NewOpc = ARMISD::VLD3DUP;
7316 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
7318 NewOpc = ARMISD::VLD4DUP;
7323 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
7324 // numbers match the load.
7325 unsigned VLDLaneNo =
7326 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
7327 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
7329 // Ignore uses of the chain result.
7330 if (UI.getUse().getResNo() == NumVecs)
7333 if (User->getOpcode() != ARMISD::VDUPLANE ||
7334 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
7338 // Create the vldN-dup node.
7341 for (n = 0; n < NumVecs; ++n)
7343 Tys[n] = MVT::Other;
7344 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
7345 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
7346 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
7347 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
7348 Ops, 2, VLDMemInt->getMemoryVT(),
7349 VLDMemInt->getMemOperand());
7352 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
7354 unsigned ResNo = UI.getUse().getResNo();
7355 // Ignore uses of the chain result.
7356 if (ResNo == NumVecs)
7359 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
7362 // Now the vldN-lane intrinsic is dead except for its chain result.
7363 // Update uses of the chain.
7364 std::vector<SDValue> VLDDupResults;
7365 for (unsigned n = 0; n < NumVecs; ++n)
7366 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
7367 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
7368 DCI.CombineTo(VLD, VLDDupResults);
7373 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
7374 /// ARMISD::VDUPLANE.
7375 static SDValue PerformVDUPLANECombine(SDNode *N,
7376 TargetLowering::DAGCombinerInfo &DCI) {
7377 SDValue Op = N->getOperand(0);
7379 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
7380 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
7381 if (CombineVLDDUP(N, DCI))
7382 return SDValue(N, 0);
7384 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
7385 // redundant. Ignore bit_converts for now; element sizes are checked below.
7386 while (Op.getOpcode() == ISD::BITCAST)
7387 Op = Op.getOperand(0);
7388 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
7391 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
7392 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
7393 // The canonical VMOV for a zero vector uses a 32-bit element size.
7394 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7396 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
7398 EVT VT = N->getValueType(0);
7399 if (EltSize > VT.getVectorElementType().getSizeInBits())
7402 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
7405 // isConstVecPow2 - Return true if each vector element is a power of 2, all
7406 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
7407 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
7411 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
7413 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
7418 APFloat APF = C->getValueAPF();
7419 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
7420 != APFloat::opOK || !isExact)
7423 c0 = (I == 0) ? cN : c0;
7424 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
7431 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
7432 /// can replace combinations of VMUL and VCVT (floating-point to integer)
7433 /// when the VMUL has a constant operand that is a power of 2.
7435 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
7436 /// vmul.f32 d16, d17, d16
7437 /// vcvt.s32.f32 d16, d16
7439 /// vcvt.s32.f32 d16, d16, #3
7440 static SDValue PerformVCVTCombine(SDNode *N,
7441 TargetLowering::DAGCombinerInfo &DCI,
7442 const ARMSubtarget *Subtarget) {
7443 SelectionDAG &DAG = DCI.DAG;
7444 SDValue Op = N->getOperand(0);
7446 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
7447 Op.getOpcode() != ISD::FMUL)
7451 SDValue N0 = Op->getOperand(0);
7452 SDValue ConstVec = Op->getOperand(1);
7453 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
7455 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7456 !isConstVecPow2(ConstVec, isSigned, C))
7459 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
7460 Intrinsic::arm_neon_vcvtfp2fxu;
7461 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
7463 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
7464 DAG.getConstant(Log2_64(C), MVT::i32));
7467 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
7468 /// can replace combinations of VCVT (integer to floating-point) and VDIV
7469 /// when the VDIV has a constant operand that is a power of 2.
7471 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
7472 /// vcvt.f32.s32 d16, d16
7473 /// vdiv.f32 d16, d17, d16
7475 /// vcvt.f32.s32 d16, d16, #3
7476 static SDValue PerformVDIVCombine(SDNode *N,
7477 TargetLowering::DAGCombinerInfo &DCI,
7478 const ARMSubtarget *Subtarget) {
7479 SelectionDAG &DAG = DCI.DAG;
7480 SDValue Op = N->getOperand(0);
7481 unsigned OpOpcode = Op.getNode()->getOpcode();
7483 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
7484 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
7488 SDValue ConstVec = N->getOperand(1);
7489 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
7491 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7492 !isConstVecPow2(ConstVec, isSigned, C))
7495 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
7496 Intrinsic::arm_neon_vcvtfxu2fp;
7497 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
7499 DAG.getConstant(IntrinsicOpcode, MVT::i32),
7500 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32));
7503 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
7504 /// operand of a vector shift operation, where all the elements of the
7505 /// build_vector must have the same constant integer value.
7506 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
7507 // Ignore bit_converts.
7508 while (Op.getOpcode() == ISD::BITCAST)
7509 Op = Op.getOperand(0);
7510 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
7511 APInt SplatBits, SplatUndef;
7512 unsigned SplatBitSize;
7514 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
7515 HasAnyUndefs, ElementBits) ||
7516 SplatBitSize > ElementBits)
7518 Cnt = SplatBits.getSExtValue();
7522 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
7523 /// operand of a vector shift left operation. That value must be in the range:
7524 /// 0 <= Value < ElementBits for a left shift; or
7525 /// 0 <= Value <= ElementBits for a long left shift.
7526 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
7527 assert(VT.isVector() && "vector shift count is not a vector type");
7528 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
7529 if (! getVShiftImm(Op, ElementBits, Cnt))
7531 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
7534 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
7535 /// operand of a vector shift right operation. For a shift opcode, the value
7536 /// is positive, but for an intrinsic the value count must be negative. The
7537 /// absolute value must be in the range:
7538 /// 1 <= |Value| <= ElementBits for a right shift; or
7539 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
7540 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
7542 assert(VT.isVector() && "vector shift count is not a vector type");
7543 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
7544 if (! getVShiftImm(Op, ElementBits, Cnt))
7548 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
7551 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
7552 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
7553 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
7556 // Don't do anything for most intrinsics.
7559 // Vector shifts: check for immediate versions and lower them.
7560 // Note: This is done during DAG combining instead of DAG legalizing because
7561 // the build_vectors for 64-bit vector element shift counts are generally
7562 // not legal, and it is hard to see their values after they get legalized to
7563 // loads from a constant pool.
7564 case Intrinsic::arm_neon_vshifts:
7565 case Intrinsic::arm_neon_vshiftu:
7566 case Intrinsic::arm_neon_vshiftls:
7567 case Intrinsic::arm_neon_vshiftlu:
7568 case Intrinsic::arm_neon_vshiftn:
7569 case Intrinsic::arm_neon_vrshifts:
7570 case Intrinsic::arm_neon_vrshiftu:
7571 case Intrinsic::arm_neon_vrshiftn:
7572 case Intrinsic::arm_neon_vqshifts:
7573 case Intrinsic::arm_neon_vqshiftu:
7574 case Intrinsic::arm_neon_vqshiftsu:
7575 case Intrinsic::arm_neon_vqshiftns:
7576 case Intrinsic::arm_neon_vqshiftnu:
7577 case Intrinsic::arm_neon_vqshiftnsu:
7578 case Intrinsic::arm_neon_vqrshiftns:
7579 case Intrinsic::arm_neon_vqrshiftnu:
7580 case Intrinsic::arm_neon_vqrshiftnsu: {
7581 EVT VT = N->getOperand(1).getValueType();
7583 unsigned VShiftOpc = 0;
7586 case Intrinsic::arm_neon_vshifts:
7587 case Intrinsic::arm_neon_vshiftu:
7588 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
7589 VShiftOpc = ARMISD::VSHL;
7592 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
7593 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
7594 ARMISD::VSHRs : ARMISD::VSHRu);
7599 case Intrinsic::arm_neon_vshiftls:
7600 case Intrinsic::arm_neon_vshiftlu:
7601 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
7603 llvm_unreachable("invalid shift count for vshll intrinsic");
7605 case Intrinsic::arm_neon_vrshifts:
7606 case Intrinsic::arm_neon_vrshiftu:
7607 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
7611 case Intrinsic::arm_neon_vqshifts:
7612 case Intrinsic::arm_neon_vqshiftu:
7613 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
7617 case Intrinsic::arm_neon_vqshiftsu:
7618 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
7620 llvm_unreachable("invalid shift count for vqshlu intrinsic");
7622 case Intrinsic::arm_neon_vshiftn:
7623 case Intrinsic::arm_neon_vrshiftn:
7624 case Intrinsic::arm_neon_vqshiftns:
7625 case Intrinsic::arm_neon_vqshiftnu:
7626 case Intrinsic::arm_neon_vqshiftnsu:
7627 case Intrinsic::arm_neon_vqrshiftns:
7628 case Intrinsic::arm_neon_vqrshiftnu:
7629 case Intrinsic::arm_neon_vqrshiftnsu:
7630 // Narrowing shifts require an immediate right shift.
7631 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
7633 llvm_unreachable("invalid shift count for narrowing vector shift "
7637 llvm_unreachable("unhandled vector shift");
7641 case Intrinsic::arm_neon_vshifts:
7642 case Intrinsic::arm_neon_vshiftu:
7643 // Opcode already set above.
7645 case Intrinsic::arm_neon_vshiftls:
7646 case Intrinsic::arm_neon_vshiftlu:
7647 if (Cnt == VT.getVectorElementType().getSizeInBits())
7648 VShiftOpc = ARMISD::VSHLLi;
7650 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
7651 ARMISD::VSHLLs : ARMISD::VSHLLu);
7653 case Intrinsic::arm_neon_vshiftn:
7654 VShiftOpc = ARMISD::VSHRN; break;
7655 case Intrinsic::arm_neon_vrshifts:
7656 VShiftOpc = ARMISD::VRSHRs; break;
7657 case Intrinsic::arm_neon_vrshiftu:
7658 VShiftOpc = ARMISD::VRSHRu; break;
7659 case Intrinsic::arm_neon_vrshiftn:
7660 VShiftOpc = ARMISD::VRSHRN; break;
7661 case Intrinsic::arm_neon_vqshifts:
7662 VShiftOpc = ARMISD::VQSHLs; break;
7663 case Intrinsic::arm_neon_vqshiftu:
7664 VShiftOpc = ARMISD::VQSHLu; break;
7665 case Intrinsic::arm_neon_vqshiftsu:
7666 VShiftOpc = ARMISD::VQSHLsu; break;
7667 case Intrinsic::arm_neon_vqshiftns:
7668 VShiftOpc = ARMISD::VQSHRNs; break;
7669 case Intrinsic::arm_neon_vqshiftnu:
7670 VShiftOpc = ARMISD::VQSHRNu; break;
7671 case Intrinsic::arm_neon_vqshiftnsu:
7672 VShiftOpc = ARMISD::VQSHRNsu; break;
7673 case Intrinsic::arm_neon_vqrshiftns:
7674 VShiftOpc = ARMISD::VQRSHRNs; break;
7675 case Intrinsic::arm_neon_vqrshiftnu:
7676 VShiftOpc = ARMISD::VQRSHRNu; break;
7677 case Intrinsic::arm_neon_vqrshiftnsu:
7678 VShiftOpc = ARMISD::VQRSHRNsu; break;
7681 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
7682 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
7685 case Intrinsic::arm_neon_vshiftins: {
7686 EVT VT = N->getOperand(1).getValueType();
7688 unsigned VShiftOpc = 0;
7690 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
7691 VShiftOpc = ARMISD::VSLI;
7692 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
7693 VShiftOpc = ARMISD::VSRI;
7695 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
7698 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
7699 N->getOperand(1), N->getOperand(2),
7700 DAG.getConstant(Cnt, MVT::i32));
7703 case Intrinsic::arm_neon_vqrshifts:
7704 case Intrinsic::arm_neon_vqrshiftu:
7705 // No immediate versions of these to check for.
7712 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
7713 /// lowers them. As with the vector shift intrinsics, this is done during DAG
7714 /// combining instead of DAG legalizing because the build_vectors for 64-bit
7715 /// vector element shift counts are generally not legal, and it is hard to see
7716 /// their values after they get legalized to loads from a constant pool.
7717 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
7718 const ARMSubtarget *ST) {
7719 EVT VT = N->getValueType(0);
7721 // Nothing to be done for scalar shifts.
7722 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7723 if (!VT.isVector() || !TLI.isTypeLegal(VT))
7726 assert(ST->hasNEON() && "unexpected vector shift");
7729 switch (N->getOpcode()) {
7730 default: llvm_unreachable("unexpected shift opcode");
7733 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
7734 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
7735 DAG.getConstant(Cnt, MVT::i32));
7740 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
7741 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
7742 ARMISD::VSHRs : ARMISD::VSHRu);
7743 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
7744 DAG.getConstant(Cnt, MVT::i32));
7750 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
7751 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
7752 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
7753 const ARMSubtarget *ST) {
7754 SDValue N0 = N->getOperand(0);
7756 // Check for sign- and zero-extensions of vector extract operations of 8-
7757 // and 16-bit vector elements. NEON supports these directly. They are
7758 // handled during DAG combining because type legalization will promote them
7759 // to 32-bit types and it is messy to recognize the operations after that.
7760 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7761 SDValue Vec = N0.getOperand(0);
7762 SDValue Lane = N0.getOperand(1);
7763 EVT VT = N->getValueType(0);
7764 EVT EltVT = N0.getValueType();
7765 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7767 if (VT == MVT::i32 &&
7768 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
7769 TLI.isTypeLegal(Vec.getValueType()) &&
7770 isa<ConstantSDNode>(Lane)) {
7773 switch (N->getOpcode()) {
7774 default: llvm_unreachable("unexpected opcode");
7775 case ISD::SIGN_EXTEND:
7776 Opc = ARMISD::VGETLANEs;
7778 case ISD::ZERO_EXTEND:
7779 case ISD::ANY_EXTEND:
7780 Opc = ARMISD::VGETLANEu;
7783 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
7790 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
7791 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
7792 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
7793 const ARMSubtarget *ST) {
7794 // If the target supports NEON, try to use vmax/vmin instructions for f32
7795 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
7796 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
7797 // a NaN; only do the transformation when it matches that behavior.
7799 // For now only do this when using NEON for FP operations; if using VFP, it
7800 // is not obvious that the benefit outweighs the cost of switching to the
7802 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
7803 N->getValueType(0) != MVT::f32)
7806 SDValue CondLHS = N->getOperand(0);
7807 SDValue CondRHS = N->getOperand(1);
7808 SDValue LHS = N->getOperand(2);
7809 SDValue RHS = N->getOperand(3);
7810 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
7812 unsigned Opcode = 0;
7814 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
7815 IsReversed = false; // x CC y ? x : y
7816 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
7817 IsReversed = true ; // x CC y ? y : x
7831 // If LHS is NaN, an ordered comparison will be false and the result will
7832 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
7833 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
7834 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
7835 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
7837 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
7838 // will return -0, so vmin can only be used for unsafe math or if one of
7839 // the operands is known to be nonzero.
7840 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
7842 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
7844 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
7853 // If LHS is NaN, an ordered comparison will be false and the result will
7854 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
7855 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
7856 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
7857 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
7859 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
7860 // will return +0, so vmax can only be used for unsafe math or if one of
7861 // the operands is known to be nonzero.
7862 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
7864 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
7866 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
7872 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
7875 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
7877 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
7878 SDValue Cmp = N->getOperand(4);
7879 if (Cmp.getOpcode() != ARMISD::CMPZ)
7880 // Only looking at EQ and NE cases.
7883 EVT VT = N->getValueType(0);
7884 DebugLoc dl = N->getDebugLoc();
7885 SDValue LHS = Cmp.getOperand(0);
7886 SDValue RHS = Cmp.getOperand(1);
7887 SDValue FalseVal = N->getOperand(0);
7888 SDValue TrueVal = N->getOperand(1);
7889 SDValue ARMcc = N->getOperand(2);
7890 ARMCC::CondCodes CC =
7891 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
7909 /// FIXME: Turn this into a target neutral optimization?
7911 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
7912 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
7913 N->getOperand(3), Cmp);
7914 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
7916 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
7917 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
7918 N->getOperand(3), NewCmp);
7921 if (Res.getNode()) {
7922 APInt KnownZero, KnownOne;
7923 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
7924 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne);
7925 // Capture demanded bits information that would be otherwise lost.
7926 if (KnownZero == 0xfffffffe)
7927 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7928 DAG.getValueType(MVT::i1));
7929 else if (KnownZero == 0xffffff00)
7930 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7931 DAG.getValueType(MVT::i8));
7932 else if (KnownZero == 0xffff0000)
7933 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7934 DAG.getValueType(MVT::i16));
7940 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
7941 DAGCombinerInfo &DCI) const {
7942 switch (N->getOpcode()) {
7944 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
7945 case ISD::SUB: return PerformSUBCombine(N, DCI);
7946 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
7947 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
7948 case ISD::AND: return PerformANDCombine(N, DCI);
7949 case ARMISD::BFI: return PerformBFICombine(N, DCI);
7950 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
7951 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
7952 case ISD::STORE: return PerformSTORECombine(N, DCI);
7953 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
7954 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
7955 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
7956 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
7957 case ISD::FP_TO_SINT:
7958 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
7959 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
7960 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
7963 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
7964 case ISD::SIGN_EXTEND:
7965 case ISD::ZERO_EXTEND:
7966 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
7967 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
7968 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
7969 case ARMISD::VLD2DUP:
7970 case ARMISD::VLD3DUP:
7971 case ARMISD::VLD4DUP:
7972 return CombineBaseUpdate(N, DCI);
7973 case ISD::INTRINSIC_VOID:
7974 case ISD::INTRINSIC_W_CHAIN:
7975 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7976 case Intrinsic::arm_neon_vld1:
7977 case Intrinsic::arm_neon_vld2:
7978 case Intrinsic::arm_neon_vld3:
7979 case Intrinsic::arm_neon_vld4:
7980 case Intrinsic::arm_neon_vld2lane:
7981 case Intrinsic::arm_neon_vld3lane:
7982 case Intrinsic::arm_neon_vld4lane:
7983 case Intrinsic::arm_neon_vst1:
7984 case Intrinsic::arm_neon_vst2:
7985 case Intrinsic::arm_neon_vst3:
7986 case Intrinsic::arm_neon_vst4:
7987 case Intrinsic::arm_neon_vst2lane:
7988 case Intrinsic::arm_neon_vst3lane:
7989 case Intrinsic::arm_neon_vst4lane:
7990 return CombineBaseUpdate(N, DCI);
7998 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
8000 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
8003 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
8004 if (!Subtarget->allowsUnalignedMem())
8007 switch (VT.getSimpleVT().SimpleTy) {
8014 // FIXME: VLD1 etc with standard alignment is legal.
8018 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
8023 switch (VT.getSimpleVT().SimpleTy) {
8024 default: return false;
8039 if ((V & (Scale - 1)) != 0)
8042 return V == (V & ((1LL << 5) - 1));
8045 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
8046 const ARMSubtarget *Subtarget) {
8053 switch (VT.getSimpleVT().SimpleTy) {
8054 default: return false;
8059 // + imm12 or - imm8
8061 return V == (V & ((1LL << 8) - 1));
8062 return V == (V & ((1LL << 12) - 1));
8065 // Same as ARM mode. FIXME: NEON?
8066 if (!Subtarget->hasVFP2())
8071 return V == (V & ((1LL << 8) - 1));
8075 /// isLegalAddressImmediate - Return true if the integer value can be used
8076 /// as the offset of the target addressing mode for load / store of the
8078 static bool isLegalAddressImmediate(int64_t V, EVT VT,
8079 const ARMSubtarget *Subtarget) {
8086 if (Subtarget->isThumb1Only())
8087 return isLegalT1AddressImmediate(V, VT);
8088 else if (Subtarget->isThumb2())
8089 return isLegalT2AddressImmediate(V, VT, Subtarget);
8094 switch (VT.getSimpleVT().SimpleTy) {
8095 default: return false;
8100 return V == (V & ((1LL << 12) - 1));
8103 return V == (V & ((1LL << 8) - 1));
8106 if (!Subtarget->hasVFP2()) // FIXME: NEON?
8111 return V == (V & ((1LL << 8) - 1));
8115 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
8117 int Scale = AM.Scale;
8121 switch (VT.getSimpleVT().SimpleTy) {
8122 default: return false;
8131 return Scale == 2 || Scale == 4 || Scale == 8;
8134 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
8138 // Note, we allow "void" uses (basically, uses that aren't loads or
8139 // stores), because arm allows folding a scale into many arithmetic
8140 // operations. This should be made more precise and revisited later.
8142 // Allow r << imm, but the imm has to be a multiple of two.
8143 if (Scale & 1) return false;
8144 return isPowerOf2_32(Scale);
8148 /// isLegalAddressingMode - Return true if the addressing mode represented
8149 /// by AM is legal for this target, for a load/store of the specified type.
8150 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8152 EVT VT = getValueType(Ty, true);
8153 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
8156 // Can never fold addr of global into load/store.
8161 case 0: // no scale reg, must be "r+i" or "r", or "i".
8164 if (Subtarget->isThumb1Only())
8168 // ARM doesn't support any R+R*scale+imm addr modes.
8175 if (Subtarget->isThumb2())
8176 return isLegalT2ScaledAddressingMode(AM, VT);
8178 int Scale = AM.Scale;
8179 switch (VT.getSimpleVT().SimpleTy) {
8180 default: return false;
8184 if (Scale < 0) Scale = -Scale;
8188 return isPowerOf2_32(Scale & ~1);
8192 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
8197 // Note, we allow "void" uses (basically, uses that aren't loads or
8198 // stores), because arm allows folding a scale into many arithmetic
8199 // operations. This should be made more precise and revisited later.
8201 // Allow r << imm, but the imm has to be a multiple of two.
8202 if (Scale & 1) return false;
8203 return isPowerOf2_32(Scale);
8210 /// isLegalICmpImmediate - Return true if the specified immediate is legal
8211 /// icmp immediate, that is the target has icmp instructions which can compare
8212 /// a register against the immediate without having to materialize the
8213 /// immediate into a register.
8214 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8215 if (!Subtarget->isThumb())
8216 return ARM_AM::getSOImmVal(Imm) != -1;
8217 if (Subtarget->isThumb2())
8218 return ARM_AM::getT2SOImmVal(Imm) != -1;
8219 return Imm >= 0 && Imm <= 255;
8222 /// isLegalAddImmediate - Return true if the specified immediate is legal
8223 /// add immediate, that is the target has add instructions which can add
8224 /// a register with the immediate without having to materialize the
8225 /// immediate into a register.
8226 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8227 return ARM_AM::getSOImmVal(Imm) != -1;
8230 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
8231 bool isSEXTLoad, SDValue &Base,
8232 SDValue &Offset, bool &isInc,
8233 SelectionDAG &DAG) {
8234 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
8237 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
8239 Base = Ptr->getOperand(0);
8240 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
8241 int RHSC = (int)RHS->getZExtValue();
8242 if (RHSC < 0 && RHSC > -256) {
8243 assert(Ptr->getOpcode() == ISD::ADD);
8245 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
8249 isInc = (Ptr->getOpcode() == ISD::ADD);
8250 Offset = Ptr->getOperand(1);
8252 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
8254 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
8255 int RHSC = (int)RHS->getZExtValue();
8256 if (RHSC < 0 && RHSC > -0x1000) {
8257 assert(Ptr->getOpcode() == ISD::ADD);
8259 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
8260 Base = Ptr->getOperand(0);
8265 if (Ptr->getOpcode() == ISD::ADD) {
8267 ARM_AM::ShiftOpc ShOpcVal=
8268 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
8269 if (ShOpcVal != ARM_AM::no_shift) {
8270 Base = Ptr->getOperand(1);
8271 Offset = Ptr->getOperand(0);
8273 Base = Ptr->getOperand(0);
8274 Offset = Ptr->getOperand(1);
8279 isInc = (Ptr->getOpcode() == ISD::ADD);
8280 Base = Ptr->getOperand(0);
8281 Offset = Ptr->getOperand(1);
8285 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
8289 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
8290 bool isSEXTLoad, SDValue &Base,
8291 SDValue &Offset, bool &isInc,
8292 SelectionDAG &DAG) {
8293 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
8296 Base = Ptr->getOperand(0);
8297 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
8298 int RHSC = (int)RHS->getZExtValue();
8299 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
8300 assert(Ptr->getOpcode() == ISD::ADD);
8302 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
8304 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
8305 isInc = Ptr->getOpcode() == ISD::ADD;
8306 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
8314 /// getPreIndexedAddressParts - returns true by value, base pointer and
8315 /// offset pointer and addressing mode by reference if the node's address
8316 /// can be legally represented as pre-indexed load / store address.
8318 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8320 ISD::MemIndexedMode &AM,
8321 SelectionDAG &DAG) const {
8322 if (Subtarget->isThumb1Only())
8327 bool isSEXTLoad = false;
8328 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8329 Ptr = LD->getBasePtr();
8330 VT = LD->getMemoryVT();
8331 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
8332 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8333 Ptr = ST->getBasePtr();
8334 VT = ST->getMemoryVT();
8339 bool isLegal = false;
8340 if (Subtarget->isThumb2())
8341 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
8342 Offset, isInc, DAG);
8344 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
8345 Offset, isInc, DAG);
8349 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
8353 /// getPostIndexedAddressParts - returns true by value, base pointer and
8354 /// offset pointer and addressing mode by reference if this node can be
8355 /// combined with a load / store to form a post-indexed load / store.
8356 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
8359 ISD::MemIndexedMode &AM,
8360 SelectionDAG &DAG) const {
8361 if (Subtarget->isThumb1Only())
8366 bool isSEXTLoad = false;
8367 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8368 VT = LD->getMemoryVT();
8369 Ptr = LD->getBasePtr();
8370 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
8371 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8372 VT = ST->getMemoryVT();
8373 Ptr = ST->getBasePtr();
8378 bool isLegal = false;
8379 if (Subtarget->isThumb2())
8380 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
8383 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
8389 // Swap base ptr and offset to catch more post-index load / store when
8390 // it's legal. In Thumb2 mode, offset must be an immediate.
8391 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
8392 !Subtarget->isThumb2())
8393 std::swap(Base, Offset);
8395 // Post-indexed load / store update the base pointer.
8400 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
8404 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8408 const SelectionDAG &DAG,
8409 unsigned Depth) const {
8410 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
8411 switch (Op.getOpcode()) {
8413 case ARMISD::CMOV: {
8414 // Bits are known zero/one if known on the LHS and RHS.
8415 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
8416 if (KnownZero == 0 && KnownOne == 0) return;
8418 APInt KnownZeroRHS, KnownOneRHS;
8419 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
8420 KnownZeroRHS, KnownOneRHS, Depth+1);
8421 KnownZero &= KnownZeroRHS;
8422 KnownOne &= KnownOneRHS;
8428 //===----------------------------------------------------------------------===//
8429 // ARM Inline Assembly Support
8430 //===----------------------------------------------------------------------===//
8432 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
8433 // Looking for "rev" which is V6+.
8434 if (!Subtarget->hasV6Ops())
8437 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
8438 std::string AsmStr = IA->getAsmString();
8439 SmallVector<StringRef, 4> AsmPieces;
8440 SplitString(AsmStr, AsmPieces, ";\n");
8442 switch (AsmPieces.size()) {
8443 default: return false;
8445 AsmStr = AsmPieces[0];
8447 SplitString(AsmStr, AsmPieces, " \t,");
8450 if (AsmPieces.size() == 3 &&
8451 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
8452 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
8453 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
8454 if (Ty && Ty->getBitWidth() == 32)
8455 return IntrinsicLowering::LowerToByteSwap(CI);
8463 /// getConstraintType - Given a constraint letter, return the type of
8464 /// constraint it is for this target.
8465 ARMTargetLowering::ConstraintType
8466 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
8467 if (Constraint.size() == 1) {
8468 switch (Constraint[0]) {
8470 case 'l': return C_RegisterClass;
8471 case 'w': return C_RegisterClass;
8472 case 'h': return C_RegisterClass;
8473 case 'x': return C_RegisterClass;
8474 case 't': return C_RegisterClass;
8475 case 'j': return C_Other; // Constant for movw.
8476 // An address with a single base register. Due to the way we
8477 // currently handle addresses it is the same as an 'r' memory constraint.
8478 case 'Q': return C_Memory;
8480 } else if (Constraint.size() == 2) {
8481 switch (Constraint[0]) {
8483 // All 'U+' constraints are addresses.
8484 case 'U': return C_Memory;
8487 return TargetLowering::getConstraintType(Constraint);
8490 /// Examine constraint type and operand type and determine a weight value.
8491 /// This object must already have been set up with the operand type
8492 /// and the current alternative constraint selected.
8493 TargetLowering::ConstraintWeight
8494 ARMTargetLowering::getSingleConstraintMatchWeight(
8495 AsmOperandInfo &info, const char *constraint) const {
8496 ConstraintWeight weight = CW_Invalid;
8497 Value *CallOperandVal = info.CallOperandVal;
8498 // If we don't have a value, we can't do a match,
8499 // but allow it at the lowest weight.
8500 if (CallOperandVal == NULL)
8502 Type *type = CallOperandVal->getType();
8503 // Look at the constraint type.
8504 switch (*constraint) {
8506 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8509 if (type->isIntegerTy()) {
8510 if (Subtarget->isThumb())
8511 weight = CW_SpecificReg;
8513 weight = CW_Register;
8517 if (type->isFloatingPointTy())
8518 weight = CW_Register;
8524 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
8526 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8528 if (Constraint.size() == 1) {
8529 // GCC ARM Constraint Letters
8530 switch (Constraint[0]) {
8531 case 'l': // Low regs or general regs.
8532 if (Subtarget->isThumb())
8533 return RCPair(0U, ARM::tGPRRegisterClass);
8535 return RCPair(0U, ARM::GPRRegisterClass);
8536 case 'h': // High regs or no regs.
8537 if (Subtarget->isThumb())
8538 return RCPair(0U, ARM::hGPRRegisterClass);
8541 return RCPair(0U, ARM::GPRRegisterClass);
8544 return RCPair(0U, ARM::SPRRegisterClass);
8545 if (VT.getSizeInBits() == 64)
8546 return RCPair(0U, ARM::DPRRegisterClass);
8547 if (VT.getSizeInBits() == 128)
8548 return RCPair(0U, ARM::QPRRegisterClass);
8552 return RCPair(0U, ARM::SPR_8RegisterClass);
8553 if (VT.getSizeInBits() == 64)
8554 return RCPair(0U, ARM::DPR_8RegisterClass);
8555 if (VT.getSizeInBits() == 128)
8556 return RCPair(0U, ARM::QPR_8RegisterClass);
8560 return RCPair(0U, ARM::SPRRegisterClass);
8564 if (StringRef("{cc}").equals_lower(Constraint))
8565 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
8567 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8570 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8571 /// vector. If it is invalid, don't add anything to Ops.
8572 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8573 std::string &Constraint,
8574 std::vector<SDValue>&Ops,
8575 SelectionDAG &DAG) const {
8576 SDValue Result(0, 0);
8578 // Currently only support length 1 constraints.
8579 if (Constraint.length() != 1) return;
8581 char ConstraintLetter = Constraint[0];
8582 switch (ConstraintLetter) {
8585 case 'I': case 'J': case 'K': case 'L':
8586 case 'M': case 'N': case 'O':
8587 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
8591 int64_t CVal64 = C->getSExtValue();
8592 int CVal = (int) CVal64;
8593 // None of these constraints allow values larger than 32 bits. Check
8594 // that the value fits in an int.
8598 switch (ConstraintLetter) {
8600 // Constant suitable for movw, must be between 0 and
8602 if (Subtarget->hasV6T2Ops())
8603 if (CVal >= 0 && CVal <= 65535)
8607 if (Subtarget->isThumb1Only()) {
8608 // This must be a constant between 0 and 255, for ADD
8610 if (CVal >= 0 && CVal <= 255)
8612 } else if (Subtarget->isThumb2()) {
8613 // A constant that can be used as an immediate value in a
8614 // data-processing instruction.
8615 if (ARM_AM::getT2SOImmVal(CVal) != -1)
8618 // A constant that can be used as an immediate value in a
8619 // data-processing instruction.
8620 if (ARM_AM::getSOImmVal(CVal) != -1)
8626 if (Subtarget->isThumb()) { // FIXME thumb2
8627 // This must be a constant between -255 and -1, for negated ADD
8628 // immediates. This can be used in GCC with an "n" modifier that
8629 // prints the negated value, for use with SUB instructions. It is
8630 // not useful otherwise but is implemented for compatibility.
8631 if (CVal >= -255 && CVal <= -1)
8634 // This must be a constant between -4095 and 4095. It is not clear
8635 // what this constraint is intended for. Implemented for
8636 // compatibility with GCC.
8637 if (CVal >= -4095 && CVal <= 4095)
8643 if (Subtarget->isThumb1Only()) {
8644 // A 32-bit value where only one byte has a nonzero value. Exclude
8645 // zero to match GCC. This constraint is used by GCC internally for
8646 // constants that can be loaded with a move/shift combination.
8647 // It is not useful otherwise but is implemented for compatibility.
8648 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
8650 } else if (Subtarget->isThumb2()) {
8651 // A constant whose bitwise inverse can be used as an immediate
8652 // value in a data-processing instruction. This can be used in GCC
8653 // with a "B" modifier that prints the inverted value, for use with
8654 // BIC and MVN instructions. It is not useful otherwise but is
8655 // implemented for compatibility.
8656 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
8659 // A constant whose bitwise inverse can be used as an immediate
8660 // value in a data-processing instruction. This can be used in GCC
8661 // with a "B" modifier that prints the inverted value, for use with
8662 // BIC and MVN instructions. It is not useful otherwise but is
8663 // implemented for compatibility.
8664 if (ARM_AM::getSOImmVal(~CVal) != -1)
8670 if (Subtarget->isThumb1Only()) {
8671 // This must be a constant between -7 and 7,
8672 // for 3-operand ADD/SUB immediate instructions.
8673 if (CVal >= -7 && CVal < 7)
8675 } else if (Subtarget->isThumb2()) {
8676 // A constant whose negation can be used as an immediate value in a
8677 // data-processing instruction. This can be used in GCC with an "n"
8678 // modifier that prints the negated value, for use with SUB
8679 // instructions. It is not useful otherwise but is implemented for
8681 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
8684 // A constant whose negation can be used as an immediate value in a
8685 // data-processing instruction. This can be used in GCC with an "n"
8686 // modifier that prints the negated value, for use with SUB
8687 // instructions. It is not useful otherwise but is implemented for
8689 if (ARM_AM::getSOImmVal(-CVal) != -1)
8695 if (Subtarget->isThumb()) { // FIXME thumb2
8696 // This must be a multiple of 4 between 0 and 1020, for
8697 // ADD sp + immediate.
8698 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
8701 // A power of two or a constant between 0 and 32. This is used in
8702 // GCC for the shift amount on shifted register operands, but it is
8703 // useful in general for any shift amounts.
8704 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
8710 if (Subtarget->isThumb()) { // FIXME thumb2
8711 // This must be a constant between 0 and 31, for shift amounts.
8712 if (CVal >= 0 && CVal <= 31)
8718 if (Subtarget->isThumb()) { // FIXME thumb2
8719 // This must be a multiple of 4 between -508 and 508, for
8720 // ADD/SUB sp = sp + immediate.
8721 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
8726 Result = DAG.getTargetConstant(CVal, Op.getValueType());
8730 if (Result.getNode()) {
8731 Ops.push_back(Result);
8734 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8738 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8739 // The ARM target isn't yet aware of offsets.
8743 bool ARM::isBitFieldInvertedMask(unsigned v) {
8744 if (v == 0xffffffff)
8746 // there can be 1's on either or both "outsides", all the "inside"
8748 unsigned int lsb = 0, msb = 31;
8749 while (v & (1 << msb)) --msb;
8750 while (v & (1 << lsb)) ++lsb;
8751 for (unsigned int i = lsb; i <= msb; ++i) {
8758 /// isFPImmLegal - Returns true if the target can instruction select the
8759 /// specified FP immediate natively. If false, the legalizer will
8760 /// materialize the FP immediate as a load from a constant pool.
8761 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
8762 if (!Subtarget->hasVFP3())
8765 return ARM_AM::getFP32Imm(Imm) != -1;
8767 return ARM_AM::getFP64Imm(Imm) != -1;
8771 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
8772 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
8773 /// specified in the intrinsic calls.
8774 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
8776 unsigned Intrinsic) const {
8777 switch (Intrinsic) {
8778 case Intrinsic::arm_neon_vld1:
8779 case Intrinsic::arm_neon_vld2:
8780 case Intrinsic::arm_neon_vld3:
8781 case Intrinsic::arm_neon_vld4:
8782 case Intrinsic::arm_neon_vld2lane:
8783 case Intrinsic::arm_neon_vld3lane:
8784 case Intrinsic::arm_neon_vld4lane: {
8785 Info.opc = ISD::INTRINSIC_W_CHAIN;
8786 // Conservatively set memVT to the entire set of vectors loaded.
8787 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
8788 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
8789 Info.ptrVal = I.getArgOperand(0);
8791 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
8792 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
8793 Info.vol = false; // volatile loads with NEON intrinsics not supported
8794 Info.readMem = true;
8795 Info.writeMem = false;
8798 case Intrinsic::arm_neon_vst1:
8799 case Intrinsic::arm_neon_vst2:
8800 case Intrinsic::arm_neon_vst3:
8801 case Intrinsic::arm_neon_vst4:
8802 case Intrinsic::arm_neon_vst2lane:
8803 case Intrinsic::arm_neon_vst3lane:
8804 case Intrinsic::arm_neon_vst4lane: {
8805 Info.opc = ISD::INTRINSIC_VOID;
8806 // Conservatively set memVT to the entire set of vectors stored.
8807 unsigned NumElts = 0;
8808 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
8809 Type *ArgTy = I.getArgOperand(ArgI)->getType();
8810 if (!ArgTy->isVectorTy())
8812 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
8814 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
8815 Info.ptrVal = I.getArgOperand(0);
8817 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
8818 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
8819 Info.vol = false; // volatile stores with NEON intrinsics not supported
8820 Info.readMem = false;
8821 Info.writeMem = true;
8824 case Intrinsic::arm_strexd: {
8825 Info.opc = ISD::INTRINSIC_W_CHAIN;
8826 Info.memVT = MVT::i64;
8827 Info.ptrVal = I.getArgOperand(2);
8831 Info.readMem = false;
8832 Info.writeMem = true;
8835 case Intrinsic::arm_ldrexd: {
8836 Info.opc = ISD::INTRINSIC_W_CHAIN;
8837 Info.memVT = MVT::i64;
8838 Info.ptrVal = I.getArgOperand(0);
8842 Info.readMem = true;
8843 Info.writeMem = false;