1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
25 class ARMConstantPoolValue;
29 // ARM Specific DAG Nodes
31 // Start the numbering where the builtin ops and target ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
40 // Add pseudo op to model memcpy for struct byval.
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
51 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
53 PIC_ADD, // Add with a PC operand and a PIC label.
55 CMP, // ARM compare instructions.
56 CMN, // ARM CMN instructions.
57 CMPZ, // ARM compare that sets only Z flag.
58 CMPFP, // ARM VFP compare instruction, sets FPSCR.
59 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
60 FMSTAT, // ARM fmstat instruction.
62 CMOV, // ARM conditional move instructions.
66 RBIT, // ARM bitreverse instruction
68 FTOSI, // FP to sint within a FP register.
69 FTOUI, // FP to uint within a FP register.
70 SITOF, // sint to FP within a FP register.
71 UITOF, // uint to FP within a FP register.
73 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
74 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
75 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
77 ADDC, // Add with carry
78 ADDE, // Add using carry
79 SUBC, // Sub with carry
80 SUBE, // Sub using carry
82 VMOVRRD, // double to two gprs.
83 VMOVDRR, // Two gprs to double.
85 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
86 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
88 TC_RETURN, // Tail call return pseudo.
92 DYN_ALLOC, // Dynamic allocation on the stack.
94 MEMBARRIER_MCR, // Memory barrier (MCR)
98 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
100 VCEQ, // Vector compare equal.
101 VCEQZ, // Vector compare equal to zero.
102 VCGE, // Vector compare greater than or equal.
103 VCGEZ, // Vector compare greater than or equal to zero.
104 VCLEZ, // Vector compare less than or equal to zero.
105 VCGEU, // Vector compare unsigned greater than or equal.
106 VCGT, // Vector compare greater than.
107 VCGTZ, // Vector compare greater than zero.
108 VCLTZ, // Vector compare less than zero.
109 VCGTU, // Vector compare unsigned greater than.
110 VTST, // Vector test bits.
112 // Vector shift by immediate:
114 VSHRs, // ...right (signed)
115 VSHRu, // ...right (unsigned)
117 // Vector rounding shift by immediate:
118 VRSHRs, // ...right (signed)
119 VRSHRu, // ...right (unsigned)
120 VRSHRN, // ...right narrow
122 // Vector saturating shift by immediate:
123 VQSHLs, // ...left (signed)
124 VQSHLu, // ...left (unsigned)
125 VQSHLsu, // ...left (signed to unsigned)
126 VQSHRNs, // ...right narrow (signed)
127 VQSHRNu, // ...right narrow (unsigned)
128 VQSHRNsu, // ...right narrow (signed to unsigned)
130 // Vector saturating rounding shift by immediate:
131 VQRSHRNs, // ...right narrow (signed)
132 VQRSHRNu, // ...right narrow (unsigned)
133 VQRSHRNsu, // ...right narrow (signed to unsigned)
135 // Vector shift and insert:
139 // Vector get lane (VMOV scalar to ARM core register)
140 // (These are used for 8- and 16-bit element types only.)
141 VGETLANEu, // zero-extend vector extract element
142 VGETLANEs, // sign-extend vector extract element
144 // Vector move immediate and move negated immediate:
148 // Vector move f32 immediate:
157 VREV64, // reverse elements within 64-bit doublewords
158 VREV32, // reverse elements within 32-bit words
159 VREV16, // reverse elements within 16-bit halfwords
160 VZIP, // zip (interleave)
161 VUZP, // unzip (deinterleave)
163 VTBL1, // 1-register shuffle with mask
164 VTBL2, // 2-register shuffle with mask
166 // Vector multiply long:
168 VMULLu, // ...unsigned
170 UMLAL, // 64bit Unsigned Accumulate Multiply
171 SMLAL, // 64bit Signed Accumulate Multiply
173 // Operands of the standard BUILD_VECTOR node are not legalized, which
174 // is fine if BUILD_VECTORs are always lowered to shuffles or other
175 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
176 // operands need to be legalized. Define an ARM-specific version of
177 // BUILD_VECTOR for this purpose.
180 // Floating-point max and min:
189 // Vector OR with immediate
191 // Vector AND with NOT of immediate
194 // Vector bitwise select
197 // Vector load N-element structure to all lanes:
198 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
202 // NEON loads with post-increment base updates:
214 // NEON stores with post-increment base updates:
225 /// Define some predicates that are used for node matching.
227 bool isBitFieldInvertedMask(unsigned v);
230 //===--------------------------------------------------------------------===//
231 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
233 class ARMTargetLowering : public TargetLowering {
235 explicit ARMTargetLowering(const TargetMachine &TM,
236 const ARMSubtarget &STI);
238 unsigned getJumpTableEncoding() const override;
240 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
242 /// ReplaceNodeResults - Replace the results of node with an illegal result
243 /// type with new values built out of custom code.
245 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
246 SelectionDAG &DAG) const override;
248 const char *getTargetNodeName(unsigned Opcode) const override;
250 bool isSelectSupported(SelectSupportKind Kind) const override {
251 // ARM does not support scalar condition selects on vectors.
252 return (Kind != ScalarCondVectorVal);
255 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
256 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
259 EmitInstrWithCustomInserter(MachineInstr *MI,
260 MachineBasicBlock *MBB) const override;
262 void AdjustInstrPostInstrSelection(MachineInstr *MI,
263 SDNode *Node) const override;
265 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
266 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
268 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
270 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
271 /// unaligned memory accesses of the specified type. Returns whether it
272 /// is "fast" by reference in the second argument.
273 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
275 bool *Fast) const override;
277 EVT getOptimalMemOpType(uint64_t Size,
278 unsigned DstAlign, unsigned SrcAlign,
279 bool IsMemset, bool ZeroMemset,
281 MachineFunction &MF) const override;
283 using TargetLowering::isZExtFree;
284 bool isZExtFree(SDValue Val, EVT VT2) const override;
286 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
289 /// isLegalAddressingMode - Return true if the addressing mode represented
290 /// by AM is legal for this target, for a load/store of the specified type.
291 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
292 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
294 /// isLegalICmpImmediate - Return true if the specified immediate is legal
295 /// icmp immediate, that is the target has icmp instructions which can
296 /// compare a register against the immediate without having to materialize
297 /// the immediate into a register.
298 bool isLegalICmpImmediate(int64_t Imm) const override;
300 /// isLegalAddImmediate - Return true if the specified immediate is legal
301 /// add immediate, that is the target has add instructions which can
302 /// add a register and the immediate without having to materialize
303 /// the immediate into a register.
304 bool isLegalAddImmediate(int64_t Imm) const override;
306 /// getPreIndexedAddressParts - returns true by value, base pointer and
307 /// offset pointer and addressing mode by reference if the node's address
308 /// can be legally represented as pre-indexed load / store address.
309 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
310 ISD::MemIndexedMode &AM,
311 SelectionDAG &DAG) const override;
313 /// getPostIndexedAddressParts - returns true by value, base pointer and
314 /// offset pointer and addressing mode by reference if this node can be
315 /// combined with a load / store to form a post-indexed load / store.
316 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
317 SDValue &Offset, ISD::MemIndexedMode &AM,
318 SelectionDAG &DAG) const override;
320 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
322 const SelectionDAG &DAG,
323 unsigned Depth) const override;
326 bool ExpandInlineAsm(CallInst *CI) const override;
329 getConstraintType(const std::string &Constraint) const override;
331 /// Examine constraint string and operand type and determine a weight value.
332 /// The operand object must already have been set up with the operand type.
333 ConstraintWeight getSingleConstraintMatchWeight(
334 AsmOperandInfo &info, const char *constraint) const override;
336 std::pair<unsigned, const TargetRegisterClass*>
337 getRegForInlineAsmConstraint(const std::string &Constraint,
338 MVT VT) const override;
340 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
341 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
342 /// true it means one of the asm constraint of the inline asm instruction
343 /// being processed is 'm'.
344 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
345 std::vector<SDValue> &Ops,
346 SelectionDAG &DAG) const override;
348 const ARMSubtarget* getSubtarget() const {
352 /// getRegClassFor - Return the register class that should be used for the
353 /// specified value type.
354 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
356 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
357 /// be used for loads / stores from the global.
358 unsigned getMaximalGlobalOffset() const override;
360 /// Returns true if a cast between SrcAS and DestAS is a noop.
361 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
362 // Addrspacecasts are always noops.
366 /// createFastISel - This method returns a target specific FastISel object,
367 /// or null if the target does not support "fast" ISel.
368 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
369 const TargetLibraryInfo *libInfo) const override;
371 Sched::Preference getSchedulingPreference(SDNode *N) const override;
374 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
375 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
377 /// isFPImmLegal - Returns true if the target can instruction select the
378 /// specified FP immediate natively. If false, the legalizer will
379 /// materialize the FP immediate as a load from a constant pool.
380 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
382 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
384 unsigned Intrinsic) const override;
386 /// \brief Returns true if it is beneficial to convert a load of a constant
387 /// to just the constant itself.
388 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
389 Type *Ty) const override;
391 /// \brief Returns true if an argument of type Ty needs to be passed in a
392 /// contiguous block of registers in calling convention CallConv.
393 bool functionArgumentNeedsConsecutiveRegisters(
394 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
396 bool hasLoadLinkedStoreConditional() const override;
397 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
398 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
399 AtomicOrdering Ord) const override;
400 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
401 Value *Addr, AtomicOrdering Ord) const override;
403 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
404 bool IsStore, bool IsLoad) const override;
405 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
406 bool IsStore, bool IsLoad) const override;
408 bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
409 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
410 bool shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
412 bool useLoadStackGuardNode() const override;
414 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
415 unsigned &Cost) const override;
418 std::pair<const TargetRegisterClass*, uint8_t>
419 findRepresentativeClass(MVT VT) const override;
422 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
423 /// make the right decision when generating code for different targets.
424 const ARMSubtarget *Subtarget;
426 const TargetRegisterInfo *RegInfo;
428 const InstrItineraryData *Itins;
430 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
432 unsigned ARMPCLabelIndex;
434 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
435 void addDRTypeForNEON(MVT VT);
436 void addQRTypeForNEON(MVT VT);
437 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
439 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
440 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
441 SDValue Chain, SDValue &Arg,
442 RegsToPassVector &RegsToPass,
443 CCValAssign &VA, CCValAssign &NextVA,
445 SmallVectorImpl<SDValue> &MemOpChains,
446 ISD::ArgFlagsTy Flags) const;
447 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
448 SDValue &Root, SelectionDAG &DAG,
451 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
452 bool isVarArg) const;
453 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
454 bool isVarArg) const;
455 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
456 SDLoc dl, SelectionDAG &DAG,
457 const CCValAssign &VA,
458 ISD::ArgFlagsTy Flags) const;
459 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
460 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
461 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
462 const ARMSubtarget *Subtarget) const;
463 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
464 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
465 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
466 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
467 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
468 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
469 SelectionDAG &DAG) const;
470 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
472 TLSModel::Model model) const;
473 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
474 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
475 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
476 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
477 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
478 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
479 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
480 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
483 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
484 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
485 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
486 const ARMSubtarget *ST) const;
487 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
488 const ARMSubtarget *ST) const;
489 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
490 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
491 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
492 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
493 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
494 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
495 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
497 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
499 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
500 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
501 /// expanded to FMAs when this method returns true, otherwise fmuladd is
502 /// expanded to fmul + fadd.
504 /// ARM supports both fused and unfused multiply-add operations; we already
505 /// lower a pair of fmul and fadd to the latter so it's not clear that there
506 /// would be a gain or that the gain would be worthwhile enough to risk
507 /// correctness bugs.
508 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
510 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
512 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
513 CallingConv::ID CallConv, bool isVarArg,
514 const SmallVectorImpl<ISD::InputArg> &Ins,
515 SDLoc dl, SelectionDAG &DAG,
516 SmallVectorImpl<SDValue> &InVals,
517 bool isThisReturn, SDValue ThisVal) const;
520 LowerFormalArguments(SDValue Chain,
521 CallingConv::ID CallConv, bool isVarArg,
522 const SmallVectorImpl<ISD::InputArg> &Ins,
523 SDLoc dl, SelectionDAG &DAG,
524 SmallVectorImpl<SDValue> &InVals) const override;
526 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
527 SDLoc dl, SDValue &Chain,
528 const Value *OrigArg,
529 unsigned InRegsParamRecordIdx,
530 unsigned OffsetFromOrigArg,
534 unsigned ByValStoreOffset,
535 unsigned TotalArgRegsSaveSize) const;
537 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
538 SDLoc dl, SDValue &Chain,
540 unsigned TotalArgRegsSaveSize,
541 bool ForceMutable = false) const;
543 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
544 unsigned InRegsParamRecordIdx,
546 unsigned &ArgRegsSize,
547 unsigned &ArgRegsSaveSize) const;
550 LowerCall(TargetLowering::CallLoweringInfo &CLI,
551 SmallVectorImpl<SDValue> &InVals) const override;
553 /// HandleByVal - Target-specific cleanup for ByVal support.
554 void HandleByVal(CCState *, unsigned &, unsigned) const override;
556 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
557 /// for tail call optimization. Targets which want to do tail call
558 /// optimization should implement this function.
559 bool IsEligibleForTailCallOptimization(SDValue Callee,
560 CallingConv::ID CalleeCC,
562 bool isCalleeStructRet,
563 bool isCallerStructRet,
564 const SmallVectorImpl<ISD::OutputArg> &Outs,
565 const SmallVectorImpl<SDValue> &OutVals,
566 const SmallVectorImpl<ISD::InputArg> &Ins,
567 SelectionDAG& DAG) const;
569 bool CanLowerReturn(CallingConv::ID CallConv,
570 MachineFunction &MF, bool isVarArg,
571 const SmallVectorImpl<ISD::OutputArg> &Outs,
572 LLVMContext &Context) const override;
575 LowerReturn(SDValue Chain,
576 CallingConv::ID CallConv, bool isVarArg,
577 const SmallVectorImpl<ISD::OutputArg> &Outs,
578 const SmallVectorImpl<SDValue> &OutVals,
579 SDLoc dl, SelectionDAG &DAG) const override;
581 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
583 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
585 SDValue getCMOV(SDLoc dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
586 SDValue ARMcc, SDValue CCR, SDValue Cmp,
587 SelectionDAG &DAG) const;
588 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
589 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
590 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
591 SelectionDAG &DAG, SDLoc dl) const;
592 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
594 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
596 void SetupEntryBlockForSjLj(MachineInstr *MI,
597 MachineBasicBlock *MBB,
598 MachineBasicBlock *DispatchBB, int FI) const;
600 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
601 MachineBasicBlock *MBB) const;
603 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
605 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
606 MachineBasicBlock *MBB) const;
608 MachineBasicBlock *EmitLowered__chkstk(MachineInstr *MI,
609 MachineBasicBlock *MBB) const;
612 enum NEONModImmType {
619 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
620 const TargetLibraryInfo *libInfo);
624 #endif // ARMISELLOWERING_H