1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
19 #include "ARMSubtarget.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
28 class ARMConstantPoolValue;
31 // ARM Specific DAG Nodes
33 // Start the numbering where the builtin ops and target ops leave off.
34 FIRST_NUMBER = ISD::BUILTIN_OP_END,
36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
37 // TargetExternalSymbol, and TargetGlobalAddress.
38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
44 CALL, // Function call.
45 CALL_PRED, // Function call that's predicable.
46 CALL_NOLINK, // Function call with branch not branch-and-link.
47 tCALL, // Thumb function call.
48 BRCOND, // Conditional branch.
49 BR_JT, // Jumptable branch.
50 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
51 RET_FLAG, // Return with a flag operand.
53 PIC_ADD, // Add with a PC operand and a PIC label.
55 CMP, // ARM compare instructions.
56 CMPZ, // ARM compare that sets only Z flag.
57 CMPFP, // ARM VFP compare instruction, sets FPSCR.
58 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
59 FMSTAT, // ARM fmstat instruction.
61 CMOV, // ARM conditional move instructions.
62 CAND, // ARM conditional and instructions.
63 COR, // ARM conditional or instructions.
64 CXOR, // ARM conditional xor instructions.
68 RBIT, // ARM bitreverse instruction
70 FTOSI, // FP to sint within a FP register.
71 FTOUI, // FP to uint within a FP register.
72 SITOF, // sint to FP within a FP register.
73 UITOF, // uint to FP within a FP register.
75 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
76 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
77 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
79 ADDC, // Add with carry
80 ADDE, // Add using carry
81 SUBC, // Sub with carry
82 SUBE, // Sub using carry
84 VMOVRRD, // double to two gprs.
85 VMOVDRR, // Two gprs to double.
87 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
88 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
90 TC_RETURN, // Tail call return pseudo.
94 DYN_ALLOC, // Dynamic allocation on the stack.
96 MEMBARRIER, // Memory barrier (DMB)
97 MEMBARRIER_MCR, // Memory barrier (MCR)
101 VCEQ, // Vector compare equal.
102 VCEQZ, // Vector compare equal to zero.
103 VCGE, // Vector compare greater than or equal.
104 VCGEZ, // Vector compare greater than or equal to zero.
105 VCLEZ, // Vector compare less than or equal to zero.
106 VCGEU, // Vector compare unsigned greater than or equal.
107 VCGT, // Vector compare greater than.
108 VCGTZ, // Vector compare greater than zero.
109 VCLTZ, // Vector compare less than zero.
110 VCGTU, // Vector compare unsigned greater than.
111 VTST, // Vector test bits.
113 // Vector shift by immediate:
115 VSHRs, // ...right (signed)
116 VSHRu, // ...right (unsigned)
117 VSHLLs, // ...left long (signed)
118 VSHLLu, // ...left long (unsigned)
119 VSHLLi, // ...left long (with maximum shift count)
120 VSHRN, // ...right narrow
122 // Vector rounding shift by immediate:
123 VRSHRs, // ...right (signed)
124 VRSHRu, // ...right (unsigned)
125 VRSHRN, // ...right narrow
127 // Vector saturating shift by immediate:
128 VQSHLs, // ...left (signed)
129 VQSHLu, // ...left (unsigned)
130 VQSHLsu, // ...left (signed to unsigned)
131 VQSHRNs, // ...right narrow (signed)
132 VQSHRNu, // ...right narrow (unsigned)
133 VQSHRNsu, // ...right narrow (signed to unsigned)
135 // Vector saturating rounding shift by immediate:
136 VQRSHRNs, // ...right narrow (signed)
137 VQRSHRNu, // ...right narrow (unsigned)
138 VQRSHRNsu, // ...right narrow (signed to unsigned)
140 // Vector shift and insert:
144 // Vector get lane (VMOV scalar to ARM core register)
145 // (These are used for 8- and 16-bit element types only.)
146 VGETLANEu, // zero-extend vector extract element
147 VGETLANEs, // sign-extend vector extract element
149 // Vector move immediate and move negated immediate:
153 // Vector move f32 immediate:
162 VREV64, // reverse elements within 64-bit doublewords
163 VREV32, // reverse elements within 32-bit words
164 VREV16, // reverse elements within 16-bit halfwords
165 VZIP, // zip (interleave)
166 VUZP, // unzip (deinterleave)
168 VTBL1, // 1-register shuffle with mask
169 VTBL2, // 2-register shuffle with mask
171 // Vector multiply long:
173 VMULLu, // ...unsigned
175 // Operands of the standard BUILD_VECTOR node are not legalized, which
176 // is fine if BUILD_VECTORs are always lowered to shuffles or other
177 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
178 // operands need to be legalized. Define an ARM-specific version of
179 // BUILD_VECTOR for this purpose.
182 // Floating-point max and min:
189 // Vector OR with immediate
191 // Vector AND with NOT of immediate
194 // Vector bitwise select
197 // Vector load N-element structure to all lanes:
198 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
202 // NEON loads with post-increment base updates:
214 // NEON stores with post-increment base updates:
223 // 64-bit atomic ops (value split into two registers)
235 /// Define some predicates that are used for node matching.
237 bool isBitFieldInvertedMask(unsigned v);
240 //===--------------------------------------------------------------------===//
241 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
243 class ARMTargetLowering : public TargetLowering {
245 explicit ARMTargetLowering(TargetMachine &TM);
247 virtual unsigned getJumpTableEncoding(void) const;
249 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
251 /// ReplaceNodeResults - Replace the results of node with an illegal result
252 /// type with new values built out of custom code.
254 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
255 SelectionDAG &DAG) const;
257 virtual const char *getTargetNodeName(unsigned Opcode) const;
259 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
260 virtual EVT getSetCCResultType(EVT VT) const;
262 virtual MachineBasicBlock *
263 EmitInstrWithCustomInserter(MachineInstr *MI,
264 MachineBasicBlock *MBB) const;
267 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
269 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
270 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
272 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
274 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
275 /// unaligned memory accesses. of the specified type.
276 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
278 virtual EVT getOptimalMemOpType(uint64_t Size,
279 unsigned DstAlign, unsigned SrcAlign,
282 MachineFunction &MF) const;
284 /// isLegalAddressingMode - Return true if the addressing mode represented
285 /// by AM is legal for this target, for a load/store of the specified type.
286 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
287 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
289 /// isLegalICmpImmediate - Return true if the specified immediate is legal
290 /// icmp immediate, that is the target has icmp instructions which can
291 /// compare a register against the immediate without having to materialize
292 /// the immediate into a register.
293 virtual bool isLegalICmpImmediate(int64_t Imm) const;
295 /// isLegalAddImmediate - Return true if the specified immediate is legal
296 /// add immediate, that is the target has add instructions which can
297 /// add a register and the immediate without having to materialize
298 /// the immediate into a register.
299 virtual bool isLegalAddImmediate(int64_t Imm) const;
301 /// getPreIndexedAddressParts - returns true by value, base pointer and
302 /// offset pointer and addressing mode by reference if the node's address
303 /// can be legally represented as pre-indexed load / store address.
304 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
306 ISD::MemIndexedMode &AM,
307 SelectionDAG &DAG) const;
309 /// getPostIndexedAddressParts - returns true by value, base pointer and
310 /// offset pointer and addressing mode by reference if this node can be
311 /// combined with a load / store to form a post-indexed load / store.
312 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
313 SDValue &Base, SDValue &Offset,
314 ISD::MemIndexedMode &AM,
315 SelectionDAG &DAG) const;
317 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
320 const SelectionDAG &DAG,
321 unsigned Depth) const;
324 virtual bool ExpandInlineAsm(CallInst *CI) const;
326 ConstraintType getConstraintType(const std::string &Constraint) const;
328 /// Examine constraint string and operand type and determine a weight value.
329 /// The operand object must already have been set up with the operand type.
330 ConstraintWeight getSingleConstraintMatchWeight(
331 AsmOperandInfo &info, const char *constraint) const;
333 std::pair<unsigned, const TargetRegisterClass*>
334 getRegForInlineAsmConstraint(const std::string &Constraint,
337 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
338 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
339 /// true it means one of the asm constraint of the inline asm instruction
340 /// being processed is 'm'.
341 virtual void LowerAsmOperandForConstraint(SDValue Op,
342 std::string &Constraint,
343 std::vector<SDValue> &Ops,
344 SelectionDAG &DAG) const;
346 const ARMSubtarget* getSubtarget() const {
350 /// getRegClassFor - Return the register class that should be used for the
351 /// specified value type.
352 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
354 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
355 /// be used for loads / stores from the global.
356 virtual unsigned getMaximalGlobalOffset() const;
358 /// createFastISel - This method returns a target specific FastISel object,
359 /// or null if the target does not support "fast" ISel.
360 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
362 Sched::Preference getSchedulingPreference(SDNode *N) const;
364 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
365 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
367 /// isFPImmLegal - Returns true if the target can instruction select the
368 /// specified FP immediate natively. If false, the legalizer will
369 /// materialize the FP immediate as a load from a constant pool.
370 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
372 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
374 unsigned Intrinsic) const;
376 std::pair<const TargetRegisterClass*, uint8_t>
377 findRepresentativeClass(EVT VT) const;
380 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
381 /// make the right decision when generating code for different targets.
382 const ARMSubtarget *Subtarget;
384 const TargetRegisterInfo *RegInfo;
386 const InstrItineraryData *Itins;
388 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
390 unsigned ARMPCLabelIndex;
392 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
393 void addDRTypeForNEON(EVT VT);
394 void addQRTypeForNEON(EVT VT);
396 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
397 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
398 SDValue Chain, SDValue &Arg,
399 RegsToPassVector &RegsToPass,
400 CCValAssign &VA, CCValAssign &NextVA,
402 SmallVector<SDValue, 8> &MemOpChains,
403 ISD::ArgFlagsTy Flags) const;
404 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
405 SDValue &Root, SelectionDAG &DAG,
408 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
409 bool isVarArg) const;
410 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
411 DebugLoc dl, SelectionDAG &DAG,
412 const CCValAssign &VA,
413 ISD::ArgFlagsTy Flags) const;
414 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
415 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
416 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
417 const ARMSubtarget *Subtarget) const;
418 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
419 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
420 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
421 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
422 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
423 SelectionDAG &DAG) const;
424 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
426 TLSModel::Model model) const;
427 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
428 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
429 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
430 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
431 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
432 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
433 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
434 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
435 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
436 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
437 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
439 const ARMSubtarget *ST) const;
440 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
441 const ARMSubtarget *ST) const;
443 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
445 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
446 CallingConv::ID CallConv, bool isVarArg,
447 const SmallVectorImpl<ISD::InputArg> &Ins,
448 DebugLoc dl, SelectionDAG &DAG,
449 SmallVectorImpl<SDValue> &InVals) const;
452 LowerFormalArguments(SDValue Chain,
453 CallingConv::ID CallConv, bool isVarArg,
454 const SmallVectorImpl<ISD::InputArg> &Ins,
455 DebugLoc dl, SelectionDAG &DAG,
456 SmallVectorImpl<SDValue> &InVals) const;
458 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
459 DebugLoc dl, SDValue &Chain, unsigned ArgOffset)
462 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
463 unsigned &VARegSize, unsigned &VARegSaveSize) const;
466 LowerCall(SDValue Chain, SDValue Callee,
467 CallingConv::ID CallConv, bool isVarArg,
468 bool doesNotRet, bool &isTailCall,
469 const SmallVectorImpl<ISD::OutputArg> &Outs,
470 const SmallVectorImpl<SDValue> &OutVals,
471 const SmallVectorImpl<ISD::InputArg> &Ins,
472 DebugLoc dl, SelectionDAG &DAG,
473 SmallVectorImpl<SDValue> &InVals) const;
475 /// HandleByVal - Target-specific cleanup for ByVal support.
476 virtual void HandleByVal(CCState *, unsigned &) const;
478 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
479 /// for tail call optimization. Targets which want to do tail call
480 /// optimization should implement this function.
481 bool IsEligibleForTailCallOptimization(SDValue Callee,
482 CallingConv::ID CalleeCC,
484 bool isCalleeStructRet,
485 bool isCallerStructRet,
486 const SmallVectorImpl<ISD::OutputArg> &Outs,
487 const SmallVectorImpl<SDValue> &OutVals,
488 const SmallVectorImpl<ISD::InputArg> &Ins,
489 SelectionDAG& DAG) const;
491 LowerReturn(SDValue Chain,
492 CallingConv::ID CallConv, bool isVarArg,
493 const SmallVectorImpl<ISD::OutputArg> &Outs,
494 const SmallVectorImpl<SDValue> &OutVals,
495 DebugLoc dl, SelectionDAG &DAG) const;
497 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
499 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
501 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
502 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
503 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
504 SelectionDAG &DAG, DebugLoc dl) const;
505 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
507 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
509 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
510 MachineBasicBlock *BB,
511 unsigned Size) const;
512 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
513 MachineBasicBlock *BB,
515 unsigned BinOpcode) const;
516 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
517 MachineBasicBlock *BB,
520 bool NeedsCarry = false,
521 bool IsCmpxchg = false) const;
522 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
523 MachineBasicBlock *BB,
526 ARMCC::CondCodes Cond) const;
528 void SetupEntryBlockForSjLj(MachineInstr *MI,
529 MachineBasicBlock *MBB,
530 MachineBasicBlock *DispatchBB, int FI) const;
532 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
533 MachineBasicBlock *MBB) const;
535 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
538 enum NEONModImmType {
546 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
550 #endif // ARMISELLOWERING_H