1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
25 class ARMConstantPoolValue;
29 // ARM Specific DAG Nodes
30 enum NodeType : unsigned {
31 // Start the numbering where the builtin ops and target ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
40 // Add pseudo op to model memcpy for struct byval.
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
51 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
53 PIC_ADD, // Add with a PC operand and a PIC label.
55 CMP, // ARM compare instructions.
56 CMN, // ARM CMN instructions.
57 CMPZ, // ARM compare that sets only Z flag.
58 CMPFP, // ARM VFP compare instruction, sets FPSCR.
59 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
60 FMSTAT, // ARM fmstat instruction.
62 CMOV, // ARM conditional move instructions.
66 RBIT, // ARM bitreverse instruction
68 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
69 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
70 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
72 ADDC, // Add with carry
73 ADDE, // Add using carry
74 SUBC, // Sub with carry
75 SUBE, // Sub using carry
77 VMOVRRD, // double to two gprs.
78 VMOVDRR, // Two gprs to double.
80 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
81 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
82 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
84 TC_RETURN, // Tail call return pseudo.
88 DYN_ALLOC, // Dynamic allocation on the stack.
90 MEMBARRIER_MCR, // Memory barrier (MCR)
94 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
95 WIN__DBZCHK, // Windows' divide by zero check
97 VCEQ, // Vector compare equal.
98 VCEQZ, // Vector compare equal to zero.
99 VCGE, // Vector compare greater than or equal.
100 VCGEZ, // Vector compare greater than or equal to zero.
101 VCLEZ, // Vector compare less than or equal to zero.
102 VCGEU, // Vector compare unsigned greater than or equal.
103 VCGT, // Vector compare greater than.
104 VCGTZ, // Vector compare greater than zero.
105 VCLTZ, // Vector compare less than zero.
106 VCGTU, // Vector compare unsigned greater than.
107 VTST, // Vector test bits.
109 // Vector shift by immediate:
111 VSHRs, // ...right (signed)
112 VSHRu, // ...right (unsigned)
114 // Vector rounding shift by immediate:
115 VRSHRs, // ...right (signed)
116 VRSHRu, // ...right (unsigned)
117 VRSHRN, // ...right narrow
119 // Vector saturating shift by immediate:
120 VQSHLs, // ...left (signed)
121 VQSHLu, // ...left (unsigned)
122 VQSHLsu, // ...left (signed to unsigned)
123 VQSHRNs, // ...right narrow (signed)
124 VQSHRNu, // ...right narrow (unsigned)
125 VQSHRNsu, // ...right narrow (signed to unsigned)
127 // Vector saturating rounding shift by immediate:
128 VQRSHRNs, // ...right narrow (signed)
129 VQRSHRNu, // ...right narrow (unsigned)
130 VQRSHRNsu, // ...right narrow (signed to unsigned)
132 // Vector shift and insert:
136 // Vector get lane (VMOV scalar to ARM core register)
137 // (These are used for 8- and 16-bit element types only.)
138 VGETLANEu, // zero-extend vector extract element
139 VGETLANEs, // sign-extend vector extract element
141 // Vector move immediate and move negated immediate:
145 // Vector move f32 immediate:
154 VREV64, // reverse elements within 64-bit doublewords
155 VREV32, // reverse elements within 32-bit words
156 VREV16, // reverse elements within 16-bit halfwords
157 VZIP, // zip (interleave)
158 VUZP, // unzip (deinterleave)
160 VTBL1, // 1-register shuffle with mask
161 VTBL2, // 2-register shuffle with mask
163 // Vector multiply long:
165 VMULLu, // ...unsigned
167 UMLAL, // 64bit Unsigned Accumulate Multiply
168 SMLAL, // 64bit Signed Accumulate Multiply
170 // Operands of the standard BUILD_VECTOR node are not legalized, which
171 // is fine if BUILD_VECTORs are always lowered to shuffles or other
172 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
173 // operands need to be legalized. Define an ARM-specific version of
174 // BUILD_VECTOR for this purpose.
180 // Vector OR with immediate
182 // Vector AND with NOT of immediate
185 // Vector bitwise select
188 // Vector load N-element structure to all lanes:
189 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
193 // NEON loads with post-increment base updates:
205 // NEON stores with post-increment base updates:
216 /// Define some predicates that are used for node matching.
218 bool isBitFieldInvertedMask(unsigned v);
221 //===--------------------------------------------------------------------===//
222 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
224 class ARMTargetLowering : public TargetLowering {
226 explicit ARMTargetLowering(const TargetMachine &TM,
227 const ARMSubtarget &STI);
229 unsigned getJumpTableEncoding() const override;
230 bool useSoftFloat() const override;
232 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
234 /// ReplaceNodeResults - Replace the results of node with an illegal result
235 /// type with new values built out of custom code.
237 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
238 SelectionDAG &DAG) const override;
240 const char *getTargetNodeName(unsigned Opcode) const override;
242 bool isSelectSupported(SelectSupportKind Kind) const override {
243 // ARM does not support scalar condition selects on vectors.
244 return (Kind != ScalarCondVectorVal);
247 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
248 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
249 EVT VT) const override;
252 EmitInstrWithCustomInserter(MachineInstr *MI,
253 MachineBasicBlock *MBB) const override;
255 void AdjustInstrPostInstrSelection(MachineInstr *MI,
256 SDNode *Node) const override;
258 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
259 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
261 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
263 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
264 /// unaligned memory accesses of the specified type. Returns whether it
265 /// is "fast" by reference in the second argument.
266 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
268 bool *Fast) const override;
270 EVT getOptimalMemOpType(uint64_t Size,
271 unsigned DstAlign, unsigned SrcAlign,
272 bool IsMemset, bool ZeroMemset,
274 MachineFunction &MF) const override;
276 using TargetLowering::isZExtFree;
277 bool isZExtFree(SDValue Val, EVT VT2) const override;
279 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
281 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
284 /// isLegalAddressingMode - Return true if the addressing mode represented
285 /// by AM is legal for this target, for a load/store of the specified type.
286 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
287 Type *Ty, unsigned AS) const override;
288 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
290 /// isLegalICmpImmediate - Return true if the specified immediate is legal
291 /// icmp immediate, that is the target has icmp instructions which can
292 /// compare a register against the immediate without having to materialize
293 /// the immediate into a register.
294 bool isLegalICmpImmediate(int64_t Imm) const override;
296 /// isLegalAddImmediate - Return true if the specified immediate is legal
297 /// add immediate, that is the target has add instructions which can
298 /// add a register and the immediate without having to materialize
299 /// the immediate into a register.
300 bool isLegalAddImmediate(int64_t Imm) const override;
302 /// getPreIndexedAddressParts - returns true by value, base pointer and
303 /// offset pointer and addressing mode by reference if the node's address
304 /// can be legally represented as pre-indexed load / store address.
305 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
306 ISD::MemIndexedMode &AM,
307 SelectionDAG &DAG) const override;
309 /// getPostIndexedAddressParts - returns true by value, base pointer and
310 /// offset pointer and addressing mode by reference if this node can be
311 /// combined with a load / store to form a post-indexed load / store.
312 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
313 SDValue &Offset, ISD::MemIndexedMode &AM,
314 SelectionDAG &DAG) const override;
316 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
318 const SelectionDAG &DAG,
319 unsigned Depth) const override;
322 bool ExpandInlineAsm(CallInst *CI) const override;
324 ConstraintType getConstraintType(StringRef Constraint) const override;
326 /// Examine constraint string and operand type and determine a weight value.
327 /// The operand object must already have been set up with the operand type.
328 ConstraintWeight getSingleConstraintMatchWeight(
329 AsmOperandInfo &info, const char *constraint) const override;
331 std::pair<unsigned, const TargetRegisterClass *>
332 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
333 StringRef Constraint, MVT VT) const override;
335 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
336 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
337 /// true it means one of the asm constraint of the inline asm instruction
338 /// being processed is 'm'.
339 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
340 std::vector<SDValue> &Ops,
341 SelectionDAG &DAG) const override;
344 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
345 if (ConstraintCode == "Q")
346 return InlineAsm::Constraint_Q;
347 else if (ConstraintCode.size() == 2) {
348 if (ConstraintCode[0] == 'U') {
349 switch(ConstraintCode[1]) {
353 return InlineAsm::Constraint_Um;
355 return InlineAsm::Constraint_Un;
357 return InlineAsm::Constraint_Uq;
359 return InlineAsm::Constraint_Us;
361 return InlineAsm::Constraint_Ut;
363 return InlineAsm::Constraint_Uv;
365 return InlineAsm::Constraint_Uy;
369 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
372 const ARMSubtarget* getSubtarget() const {
376 /// getRegClassFor - Return the register class that should be used for the
377 /// specified value type.
378 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
380 /// Returns true if a cast between SrcAS and DestAS is a noop.
381 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
382 // Addrspacecasts are always noops.
386 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
387 unsigned &PrefAlign) const override;
389 /// createFastISel - This method returns a target specific FastISel object,
390 /// or null if the target does not support "fast" ISel.
391 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
392 const TargetLibraryInfo *libInfo) const override;
394 Sched::Preference getSchedulingPreference(SDNode *N) const override;
397 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
398 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
400 /// isFPImmLegal - Returns true if the target can instruction select the
401 /// specified FP immediate natively. If false, the legalizer will
402 /// materialize the FP immediate as a load from a constant pool.
403 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
405 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
407 unsigned Intrinsic) const override;
409 /// \brief Returns true if it is beneficial to convert a load of a constant
410 /// to just the constant itself.
411 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
412 Type *Ty) const override;
414 /// \brief Returns true if an argument of type Ty needs to be passed in a
415 /// contiguous block of registers in calling convention CallConv.
416 bool functionArgumentNeedsConsecutiveRegisters(
417 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
419 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
420 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
421 AtomicOrdering Ord) const override;
422 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
423 Value *Addr, AtomicOrdering Ord) const override;
425 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
427 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
428 bool IsStore, bool IsLoad) const override;
429 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
430 bool IsStore, bool IsLoad) const override;
432 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
434 bool lowerInterleavedLoad(LoadInst *LI,
435 ArrayRef<ShuffleVectorInst *> Shuffles,
436 ArrayRef<unsigned> Indices,
437 unsigned Factor) const override;
438 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
439 unsigned Factor) const override;
441 TargetLoweringBase::AtomicExpansionKind
442 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
443 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
444 TargetLoweringBase::AtomicExpansionKind
445 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
446 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
448 bool useLoadStackGuardNode() const override;
450 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
451 unsigned &Cost) const override;
454 std::pair<const TargetRegisterClass *, uint8_t>
455 findRepresentativeClass(const TargetRegisterInfo *TRI,
456 MVT VT) const override;
459 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
460 /// make the right decision when generating code for different targets.
461 const ARMSubtarget *Subtarget;
463 const TargetRegisterInfo *RegInfo;
465 const InstrItineraryData *Itins;
467 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
469 unsigned ARMPCLabelIndex;
471 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
472 void addDRTypeForNEON(MVT VT);
473 void addQRTypeForNEON(MVT VT);
474 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
476 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
477 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
478 SDValue Chain, SDValue &Arg,
479 RegsToPassVector &RegsToPass,
480 CCValAssign &VA, CCValAssign &NextVA,
482 SmallVectorImpl<SDValue> &MemOpChains,
483 ISD::ArgFlagsTy Flags) const;
484 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
485 SDValue &Root, SelectionDAG &DAG,
488 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
489 bool isVarArg) const;
490 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
491 bool isVarArg) const;
492 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
493 SDLoc dl, SelectionDAG &DAG,
494 const CCValAssign &VA,
495 ISD::ArgFlagsTy Flags) const;
496 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
497 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
498 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
499 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
500 const ARMSubtarget *Subtarget) const;
501 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
502 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
503 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
504 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
505 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
506 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
507 SelectionDAG &DAG) const;
508 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
510 TLSModel::Model model) const;
511 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
512 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
513 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
514 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
515 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
516 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
517 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
518 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
519 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
520 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
521 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
522 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
523 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
524 const ARMSubtarget *ST) const;
525 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
526 const ARMSubtarget *ST) const;
527 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
528 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
529 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
530 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
531 SmallVectorImpl<SDValue> &Results) const;
532 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
533 SDValue &Chain) const;
534 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
535 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
536 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
537 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
538 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
539 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
541 unsigned getRegisterByName(const char* RegName, EVT VT,
542 SelectionDAG &DAG) const override;
544 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
545 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
546 /// expanded to FMAs when this method returns true, otherwise fmuladd is
547 /// expanded to fmul + fadd.
549 /// ARM supports both fused and unfused multiply-add operations; we already
550 /// lower a pair of fmul and fadd to the latter so it's not clear that there
551 /// would be a gain or that the gain would be worthwhile enough to risk
552 /// correctness bugs.
553 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
555 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
557 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
558 CallingConv::ID CallConv, bool isVarArg,
559 const SmallVectorImpl<ISD::InputArg> &Ins,
560 SDLoc dl, SelectionDAG &DAG,
561 SmallVectorImpl<SDValue> &InVals,
562 bool isThisReturn, SDValue ThisVal) const;
565 LowerFormalArguments(SDValue Chain,
566 CallingConv::ID CallConv, bool isVarArg,
567 const SmallVectorImpl<ISD::InputArg> &Ins,
568 SDLoc dl, SelectionDAG &DAG,
569 SmallVectorImpl<SDValue> &InVals) const override;
571 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
572 SDLoc dl, SDValue &Chain,
573 const Value *OrigArg,
574 unsigned InRegsParamRecordIdx,
576 unsigned ArgSize) const;
578 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
579 SDLoc dl, SDValue &Chain,
581 unsigned TotalArgRegsSaveSize,
582 bool ForceMutable = false) const;
585 LowerCall(TargetLowering::CallLoweringInfo &CLI,
586 SmallVectorImpl<SDValue> &InVals) const override;
588 /// HandleByVal - Target-specific cleanup for ByVal support.
589 void HandleByVal(CCState *, unsigned &, unsigned) const override;
591 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
592 /// for tail call optimization. Targets which want to do tail call
593 /// optimization should implement this function.
594 bool IsEligibleForTailCallOptimization(SDValue Callee,
595 CallingConv::ID CalleeCC,
597 bool isCalleeStructRet,
598 bool isCallerStructRet,
599 const SmallVectorImpl<ISD::OutputArg> &Outs,
600 const SmallVectorImpl<SDValue> &OutVals,
601 const SmallVectorImpl<ISD::InputArg> &Ins,
602 SelectionDAG& DAG) const;
604 bool CanLowerReturn(CallingConv::ID CallConv,
605 MachineFunction &MF, bool isVarArg,
606 const SmallVectorImpl<ISD::OutputArg> &Outs,
607 LLVMContext &Context) const override;
610 LowerReturn(SDValue Chain,
611 CallingConv::ID CallConv, bool isVarArg,
612 const SmallVectorImpl<ISD::OutputArg> &Outs,
613 const SmallVectorImpl<SDValue> &OutVals,
614 SDLoc dl, SelectionDAG &DAG) const override;
616 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
618 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
620 SDValue getCMOV(SDLoc dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
621 SDValue ARMcc, SDValue CCR, SDValue Cmp,
622 SelectionDAG &DAG) const;
623 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
624 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
625 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
626 SelectionDAG &DAG, SDLoc dl) const;
627 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
629 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
631 void SetupEntryBlockForSjLj(MachineInstr *MI,
632 MachineBasicBlock *MBB,
633 MachineBasicBlock *DispatchBB, int FI) const;
635 void EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const;
637 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
639 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
640 MachineBasicBlock *MBB) const;
642 MachineBasicBlock *EmitLowered__chkstk(MachineInstr *MI,
643 MachineBasicBlock *MBB) const;
644 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr *MI,
645 MachineBasicBlock *MBB) const;
648 enum NEONModImmType {
655 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
656 const TargetLibraryInfo *libInfo);
660 #endif // ARMISELLOWERING_H