1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
19 #include "ARMSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
28 class ARMConstantPoolValue;
31 // ARM Specific DAG Nodes
33 // Start the numbering where the builtin ops and target ops leave off.
34 FIRST_NUMBER = ISD::BUILTIN_OP_END,
36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
37 // TargetExternalSymbol, and TargetGlobalAddress.
38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
44 // Add pseudo op to model memcpy for struct byval.
47 CALL, // Function call.
48 CALL_PRED, // Function call that's predicable.
49 CALL_NOLINK, // Function call with branch not branch-and-link.
50 tCALL, // Thumb function call.
51 BRCOND, // Conditional branch.
52 BR_JT, // Jumptable branch.
53 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
54 RET_FLAG, // Return with a flag operand.
55 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
57 PIC_ADD, // Add with a PC operand and a PIC label.
59 CMP, // ARM compare instructions.
60 CMN, // ARM CMN instructions.
61 CMPZ, // ARM compare that sets only Z flag.
62 CMPFP, // ARM VFP compare instruction, sets FPSCR.
63 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
64 FMSTAT, // ARM fmstat instruction.
66 CMOV, // ARM conditional move instructions.
70 RBIT, // ARM bitreverse instruction
72 FTOSI, // FP to sint within a FP register.
73 FTOUI, // FP to uint within a FP register.
74 SITOF, // sint to FP within a FP register.
75 UITOF, // uint to FP within a FP register.
77 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
78 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
79 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
81 ADDC, // Add with carry
82 ADDE, // Add using carry
83 SUBC, // Sub with carry
84 SUBE, // Sub using carry
86 VMOVRRD, // double to two gprs.
87 VMOVDRR, // Two gprs to double.
89 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
90 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
92 TC_RETURN, // Tail call return pseudo.
96 DYN_ALLOC, // Dynamic allocation on the stack.
98 MEMBARRIER_MCR, // Memory barrier (MCR)
102 VCEQ, // Vector compare equal.
103 VCEQZ, // Vector compare equal to zero.
104 VCGE, // Vector compare greater than or equal.
105 VCGEZ, // Vector compare greater than or equal to zero.
106 VCLEZ, // Vector compare less than or equal to zero.
107 VCGEU, // Vector compare unsigned greater than or equal.
108 VCGT, // Vector compare greater than.
109 VCGTZ, // Vector compare greater than zero.
110 VCLTZ, // Vector compare less than zero.
111 VCGTU, // Vector compare unsigned greater than.
112 VTST, // Vector test bits.
114 // Vector shift by immediate:
116 VSHRs, // ...right (signed)
117 VSHRu, // ...right (unsigned)
118 VSHLLs, // ...left long (signed)
119 VSHLLu, // ...left long (unsigned)
120 VSHLLi, // ...left long (with maximum shift count)
121 VSHRN, // ...right narrow
123 // Vector rounding shift by immediate:
124 VRSHRs, // ...right (signed)
125 VRSHRu, // ...right (unsigned)
126 VRSHRN, // ...right narrow
128 // Vector saturating shift by immediate:
129 VQSHLs, // ...left (signed)
130 VQSHLu, // ...left (unsigned)
131 VQSHLsu, // ...left (signed to unsigned)
132 VQSHRNs, // ...right narrow (signed)
133 VQSHRNu, // ...right narrow (unsigned)
134 VQSHRNsu, // ...right narrow (signed to unsigned)
136 // Vector saturating rounding shift by immediate:
137 VQRSHRNs, // ...right narrow (signed)
138 VQRSHRNu, // ...right narrow (unsigned)
139 VQRSHRNsu, // ...right narrow (signed to unsigned)
141 // Vector shift and insert:
145 // Vector get lane (VMOV scalar to ARM core register)
146 // (These are used for 8- and 16-bit element types only.)
147 VGETLANEu, // zero-extend vector extract element
148 VGETLANEs, // sign-extend vector extract element
150 // Vector move immediate and move negated immediate:
154 // Vector move f32 immediate:
163 VREV64, // reverse elements within 64-bit doublewords
164 VREV32, // reverse elements within 32-bit words
165 VREV16, // reverse elements within 16-bit halfwords
166 VZIP, // zip (interleave)
167 VUZP, // unzip (deinterleave)
169 VTBL1, // 1-register shuffle with mask
170 VTBL2, // 2-register shuffle with mask
172 // Vector multiply long:
174 VMULLu, // ...unsigned
176 UMLAL, // 64bit Unsigned Accumulate Multiply
177 SMLAL, // 64bit Signed Accumulate Multiply
179 // Operands of the standard BUILD_VECTOR node are not legalized, which
180 // is fine if BUILD_VECTORs are always lowered to shuffles or other
181 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
182 // operands need to be legalized. Define an ARM-specific version of
183 // BUILD_VECTOR for this purpose.
186 // Floating-point max and min:
195 // Vector OR with immediate
197 // Vector AND with NOT of immediate
200 // Vector bitwise select
203 // Vector load N-element structure to all lanes:
204 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
208 // NEON loads with post-increment base updates:
220 // NEON stores with post-increment base updates:
231 /// Define some predicates that are used for node matching.
233 bool isBitFieldInvertedMask(unsigned v);
236 //===--------------------------------------------------------------------===//
237 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
239 class ARMTargetLowering : public TargetLowering {
241 explicit ARMTargetLowering(TargetMachine &TM);
243 virtual unsigned getJumpTableEncoding() const;
245 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
247 /// ReplaceNodeResults - Replace the results of node with an illegal result
248 /// type with new values built out of custom code.
250 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
251 SelectionDAG &DAG) const;
253 virtual const char *getTargetNodeName(unsigned Opcode) const;
255 virtual bool isSelectSupported(SelectSupportKind Kind) const {
256 // ARM does not support scalar condition selects on vectors.
257 return (Kind != ScalarCondVectorVal);
260 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
261 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
263 virtual MachineBasicBlock *
264 EmitInstrWithCustomInserter(MachineInstr *MI,
265 MachineBasicBlock *MBB) const;
268 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
270 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
271 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
273 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
275 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
276 /// unaligned memory accesses of the specified type. Returns whether it
277 /// is "fast" by reference in the second argument.
278 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
280 virtual EVT getOptimalMemOpType(uint64_t Size,
281 unsigned DstAlign, unsigned SrcAlign,
282 bool IsMemset, bool ZeroMemset,
284 MachineFunction &MF) const;
286 using TargetLowering::isZExtFree;
287 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
289 virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const;
292 /// isLegalAddressingMode - Return true if the addressing mode represented
293 /// by AM is legal for this target, for a load/store of the specified type.
294 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
295 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
297 /// isLegalICmpImmediate - Return true if the specified immediate is legal
298 /// icmp immediate, that is the target has icmp instructions which can
299 /// compare a register against the immediate without having to materialize
300 /// the immediate into a register.
301 virtual bool isLegalICmpImmediate(int64_t Imm) const;
303 /// isLegalAddImmediate - Return true if the specified immediate is legal
304 /// add immediate, that is the target has add instructions which can
305 /// add a register and the immediate without having to materialize
306 /// the immediate into a register.
307 virtual bool isLegalAddImmediate(int64_t Imm) const;
309 /// getPreIndexedAddressParts - returns true by value, base pointer and
310 /// offset pointer and addressing mode by reference if the node's address
311 /// can be legally represented as pre-indexed load / store address.
312 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
314 ISD::MemIndexedMode &AM,
315 SelectionDAG &DAG) const;
317 /// getPostIndexedAddressParts - returns true by value, base pointer and
318 /// offset pointer and addressing mode by reference if this node can be
319 /// combined with a load / store to form a post-indexed load / store.
320 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
321 SDValue &Base, SDValue &Offset,
322 ISD::MemIndexedMode &AM,
323 SelectionDAG &DAG) const;
325 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
328 const SelectionDAG &DAG,
329 unsigned Depth) const;
332 virtual bool ExpandInlineAsm(CallInst *CI) const;
334 ConstraintType getConstraintType(const std::string &Constraint) const;
336 /// Examine constraint string and operand type and determine a weight value.
337 /// The operand object must already have been set up with the operand type.
338 ConstraintWeight getSingleConstraintMatchWeight(
339 AsmOperandInfo &info, const char *constraint) const;
341 std::pair<unsigned, const TargetRegisterClass*>
342 getRegForInlineAsmConstraint(const std::string &Constraint,
345 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
346 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
347 /// true it means one of the asm constraint of the inline asm instruction
348 /// being processed is 'm'.
349 virtual void LowerAsmOperandForConstraint(SDValue Op,
350 std::string &Constraint,
351 std::vector<SDValue> &Ops,
352 SelectionDAG &DAG) const;
354 const ARMSubtarget* getSubtarget() const {
358 /// getRegClassFor - Return the register class that should be used for the
359 /// specified value type.
360 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const;
362 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
363 /// be used for loads / stores from the global.
364 virtual unsigned getMaximalGlobalOffset() const;
366 /// createFastISel - This method returns a target specific FastISel object,
367 /// or null if the target does not support "fast" ISel.
368 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
369 const TargetLibraryInfo *libInfo) const;
371 Sched::Preference getSchedulingPreference(SDNode *N) const;
373 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
374 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
376 /// isFPImmLegal - Returns true if the target can instruction select the
377 /// specified FP immediate natively. If false, the legalizer will
378 /// materialize the FP immediate as a load from a constant pool.
379 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
381 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
383 unsigned Intrinsic) const;
385 std::pair<const TargetRegisterClass*, uint8_t>
386 findRepresentativeClass(MVT VT) const;
389 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
390 /// make the right decision when generating code for different targets.
391 const ARMSubtarget *Subtarget;
393 const TargetRegisterInfo *RegInfo;
395 const InstrItineraryData *Itins;
397 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
399 unsigned ARMPCLabelIndex;
401 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
402 void addDRTypeForNEON(MVT VT);
403 void addQRTypeForNEON(MVT VT);
405 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
406 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
407 SDValue Chain, SDValue &Arg,
408 RegsToPassVector &RegsToPass,
409 CCValAssign &VA, CCValAssign &NextVA,
411 SmallVectorImpl<SDValue> &MemOpChains,
412 ISD::ArgFlagsTy Flags) const;
413 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
414 SDValue &Root, SelectionDAG &DAG,
417 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
418 bool isVarArg) const;
419 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
420 SDLoc dl, SelectionDAG &DAG,
421 const CCValAssign &VA,
422 ISD::ArgFlagsTy Flags) const;
423 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
424 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
425 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
426 const ARMSubtarget *Subtarget) const;
427 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
428 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
429 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
430 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
431 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
432 SelectionDAG &DAG) const;
433 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
435 TLSModel::Model model) const;
436 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
437 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
439 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
440 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
441 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
442 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
443 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
444 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
445 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
446 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
447 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
448 const ARMSubtarget *ST) const;
449 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
450 const ARMSubtarget *ST) const;
451 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
453 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
454 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
455 /// expanded to FMAs when this method returns true, otherwise fmuladd is
456 /// expanded to fmul + fadd.
458 /// ARM supports both fused and unfused multiply-add operations; we already
459 /// lower a pair of fmul and fadd to the latter so it's not clear that there
460 /// would be a gain or that the gain would be worthwhile enough to risk
461 /// correctness bugs.
462 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const { return false; }
464 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
466 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
467 CallingConv::ID CallConv, bool isVarArg,
468 const SmallVectorImpl<ISD::InputArg> &Ins,
469 SDLoc dl, SelectionDAG &DAG,
470 SmallVectorImpl<SDValue> &InVals,
471 bool isThisReturn, SDValue ThisVal) const;
474 LowerFormalArguments(SDValue Chain,
475 CallingConv::ID CallConv, bool isVarArg,
476 const SmallVectorImpl<ISD::InputArg> &Ins,
477 SDLoc dl, SelectionDAG &DAG,
478 SmallVectorImpl<SDValue> &InVals) const;
480 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
481 SDLoc dl, SDValue &Chain,
482 const Value *OrigArg,
483 unsigned InRegsParamRecordIdx,
484 unsigned OffsetFromOrigArg,
487 bool ForceMutable) const;
489 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
490 SDLoc dl, SDValue &Chain,
492 bool ForceMutable = false) const;
494 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
495 unsigned InRegsParamRecordIdx,
497 unsigned &ArgRegsSize,
498 unsigned &ArgRegsSaveSize) const;
501 LowerCall(TargetLowering::CallLoweringInfo &CLI,
502 SmallVectorImpl<SDValue> &InVals) const;
504 /// HandleByVal - Target-specific cleanup for ByVal support.
505 virtual void HandleByVal(CCState *, unsigned &, unsigned) const;
507 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
508 /// for tail call optimization. Targets which want to do tail call
509 /// optimization should implement this function.
510 bool IsEligibleForTailCallOptimization(SDValue Callee,
511 CallingConv::ID CalleeCC,
513 bool isCalleeStructRet,
514 bool isCallerStructRet,
515 const SmallVectorImpl<ISD::OutputArg> &Outs,
516 const SmallVectorImpl<SDValue> &OutVals,
517 const SmallVectorImpl<ISD::InputArg> &Ins,
518 SelectionDAG& DAG) const;
520 virtual bool CanLowerReturn(CallingConv::ID CallConv,
521 MachineFunction &MF, bool isVarArg,
522 const SmallVectorImpl<ISD::OutputArg> &Outs,
523 LLVMContext &Context) const;
526 LowerReturn(SDValue Chain,
527 CallingConv::ID CallConv, bool isVarArg,
528 const SmallVectorImpl<ISD::OutputArg> &Outs,
529 const SmallVectorImpl<SDValue> &OutVals,
530 SDLoc dl, SelectionDAG &DAG) const;
532 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
534 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
536 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
537 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
538 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
539 SelectionDAG &DAG, SDLoc dl) const;
540 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
542 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
544 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
545 MachineBasicBlock *BB,
546 unsigned Size) const;
547 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
548 MachineBasicBlock *BB,
550 unsigned BinOpcode) const;
551 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
552 MachineBasicBlock *BB,
555 bool NeedsCarry = false,
556 bool IsCmpxchg = false,
557 bool IsMinMax = false,
558 ARMCC::CondCodes CC = ARMCC::AL) const;
559 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
560 MachineBasicBlock *BB,
563 ARMCC::CondCodes Cond) const;
564 MachineBasicBlock *EmitAtomicLoad64(MachineInstr *MI,
565 MachineBasicBlock *BB) const;
567 void SetupEntryBlockForSjLj(MachineInstr *MI,
568 MachineBasicBlock *MBB,
569 MachineBasicBlock *DispatchBB, int FI) const;
571 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
572 MachineBasicBlock *MBB) const;
574 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
576 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
577 MachineBasicBlock *MBB) const;
580 enum NEONModImmType {
588 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
589 const TargetLibraryInfo *libInfo);
593 #endif // ARMISELLOWERING_H