1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
27 class ARMConstantPoolValue;
30 // ARM Specific DAG Nodes
32 // Start the numbering where the builtin ops and target ops leave off.
33 FIRST_NUMBER = ISD::BUILTIN_OP_END,
35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
36 // TargetExternalSymbol, and TargetGlobalAddress.
37 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
39 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
41 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
52 PIC_ADD, // Add with a PC operand and a PIC label.
54 CMP, // ARM compare instructions.
55 CMPZ, // ARM compare that sets only Z flag.
56 CMPFP, // ARM VFP compare instruction, sets FPSCR.
57 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
58 FMSTAT, // ARM fmstat instruction.
59 CMOV, // ARM conditional move instructions.
63 RBIT, // ARM bitreverse instruction
65 FTOSI, // FP to sint within a FP register.
66 FTOUI, // FP to uint within a FP register.
67 SITOF, // sint to FP within a FP register.
68 UITOF, // uint to FP within a FP register.
70 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
71 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
72 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
74 ADDC, // Add with carry
75 ADDE, // Add using carry
76 SUBC, // Sub with carry
77 SUBE, // Sub using carry
79 VMOVRRD, // double to two gprs.
80 VMOVDRR, // Two gprs to double.
82 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
83 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
84 EH_SJLJ_DISPATCHSETUP, // SjLj exception handling dispatch setup.
86 TC_RETURN, // Tail call return pseudo.
90 DYN_ALLOC, // Dynamic allocation on the stack.
92 MEMBARRIER, // Memory barrier (DMB)
93 MEMBARRIER_MCR, // Memory barrier (MCR)
97 VCEQ, // Vector compare equal.
98 VCEQZ, // Vector compare equal to zero.
99 VCGE, // Vector compare greater than or equal.
100 VCGEZ, // Vector compare greater than or equal to zero.
101 VCLEZ, // Vector compare less than or equal to zero.
102 VCGEU, // Vector compare unsigned greater than or equal.
103 VCGT, // Vector compare greater than.
104 VCGTZ, // Vector compare greater than zero.
105 VCLTZ, // Vector compare less than zero.
106 VCGTU, // Vector compare unsigned greater than.
107 VTST, // Vector test bits.
109 // Vector shift by immediate:
111 VSHRs, // ...right (signed)
112 VSHRu, // ...right (unsigned)
113 VSHLLs, // ...left long (signed)
114 VSHLLu, // ...left long (unsigned)
115 VSHLLi, // ...left long (with maximum shift count)
116 VSHRN, // ...right narrow
118 // Vector rounding shift by immediate:
119 VRSHRs, // ...right (signed)
120 VRSHRu, // ...right (unsigned)
121 VRSHRN, // ...right narrow
123 // Vector saturating shift by immediate:
124 VQSHLs, // ...left (signed)
125 VQSHLu, // ...left (unsigned)
126 VQSHLsu, // ...left (signed to unsigned)
127 VQSHRNs, // ...right narrow (signed)
128 VQSHRNu, // ...right narrow (unsigned)
129 VQSHRNsu, // ...right narrow (signed to unsigned)
131 // Vector saturating rounding shift by immediate:
132 VQRSHRNs, // ...right narrow (signed)
133 VQRSHRNu, // ...right narrow (unsigned)
134 VQRSHRNsu, // ...right narrow (signed to unsigned)
136 // Vector shift and insert:
140 // Vector get lane (VMOV scalar to ARM core register)
141 // (These are used for 8- and 16-bit element types only.)
142 VGETLANEu, // zero-extend vector extract element
143 VGETLANEs, // sign-extend vector extract element
145 // Vector move immediate and move negated immediate:
155 VREV64, // reverse elements within 64-bit doublewords
156 VREV32, // reverse elements within 32-bit words
157 VREV16, // reverse elements within 16-bit halfwords
158 VZIP, // zip (interleave)
159 VUZP, // unzip (deinterleave)
161 VTBL1, // 1-register shuffle with mask
162 VTBL2, // 2-register shuffle with mask
164 // Vector multiply long:
166 VMULLu, // ...unsigned
168 // Operands of the standard BUILD_VECTOR node are not legalized, which
169 // is fine if BUILD_VECTORs are always lowered to shuffles or other
170 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
171 // operands need to be legalized. Define an ARM-specific version of
172 // BUILD_VECTOR for this purpose.
175 // Floating-point max and min:
182 // Vector OR with immediate
184 // Vector AND with NOT of immediate
187 // Vector bitwise select
190 // Vector load N-element structure to all lanes:
191 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
195 // NEON loads with post-increment base updates:
207 // NEON stores with post-increment base updates:
216 // 64-bit atomic ops (value split into two registers)
228 /// Define some predicates that are used for node matching.
230 bool isBitFieldInvertedMask(unsigned v);
233 //===--------------------------------------------------------------------===//
234 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
236 class ARMTargetLowering : public TargetLowering {
238 explicit ARMTargetLowering(TargetMachine &TM);
240 virtual unsigned getJumpTableEncoding(void) const;
242 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
244 /// ReplaceNodeResults - Replace the results of node with an illegal result
245 /// type with new values built out of custom code.
247 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
248 SelectionDAG &DAG) const;
250 virtual const char *getTargetNodeName(unsigned Opcode) const;
252 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
253 virtual EVT getSetCCResultType(EVT VT) const;
255 virtual MachineBasicBlock *
256 EmitInstrWithCustomInserter(MachineInstr *MI,
257 MachineBasicBlock *MBB) const;
260 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
262 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
263 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
265 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
267 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
268 /// unaligned memory accesses. of the specified type.
269 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
271 virtual EVT getOptimalMemOpType(uint64_t Size,
272 unsigned DstAlign, unsigned SrcAlign,
273 bool NonScalarIntSafe,
275 MachineFunction &MF) const;
277 /// isLegalAddressingMode - Return true if the addressing mode represented
278 /// by AM is legal for this target, for a load/store of the specified type.
279 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
280 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
282 /// isLegalICmpImmediate - Return true if the specified immediate is legal
283 /// icmp immediate, that is the target has icmp instructions which can
284 /// compare a register against the immediate without having to materialize
285 /// the immediate into a register.
286 virtual bool isLegalICmpImmediate(int64_t Imm) const;
288 /// isLegalAddImmediate - Return true if the specified immediate is legal
289 /// add immediate, that is the target has add instructions which can
290 /// add a register and the immediate without having to materialize
291 /// the immediate into a register.
292 virtual bool isLegalAddImmediate(int64_t Imm) const;
294 /// getPreIndexedAddressParts - returns true by value, base pointer and
295 /// offset pointer and addressing mode by reference if the node's address
296 /// can be legally represented as pre-indexed load / store address.
297 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
299 ISD::MemIndexedMode &AM,
300 SelectionDAG &DAG) const;
302 /// getPostIndexedAddressParts - returns true by value, base pointer and
303 /// offset pointer and addressing mode by reference if this node can be
304 /// combined with a load / store to form a post-indexed load / store.
305 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
306 SDValue &Base, SDValue &Offset,
307 ISD::MemIndexedMode &AM,
308 SelectionDAG &DAG) const;
310 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
314 const SelectionDAG &DAG,
315 unsigned Depth) const;
318 virtual bool ExpandInlineAsm(CallInst *CI) const;
320 ConstraintType getConstraintType(const std::string &Constraint) const;
322 /// Examine constraint string and operand type and determine a weight value.
323 /// The operand object must already have been set up with the operand type.
324 ConstraintWeight getSingleConstraintMatchWeight(
325 AsmOperandInfo &info, const char *constraint) const;
327 std::pair<unsigned, const TargetRegisterClass*>
328 getRegForInlineAsmConstraint(const std::string &Constraint,
331 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
332 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
333 /// true it means one of the asm constraint of the inline asm instruction
334 /// being processed is 'm'.
335 virtual void LowerAsmOperandForConstraint(SDValue Op,
336 std::string &Constraint,
337 std::vector<SDValue> &Ops,
338 SelectionDAG &DAG) const;
340 const ARMSubtarget* getSubtarget() const {
344 /// getRegClassFor - Return the register class that should be used for the
345 /// specified value type.
346 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
348 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
349 /// be used for loads / stores from the global.
350 virtual unsigned getMaximalGlobalOffset() const;
352 /// createFastISel - This method returns a target specific FastISel object,
353 /// or null if the target does not support "fast" ISel.
354 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
356 Sched::Preference getSchedulingPreference(SDNode *N) const;
358 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
359 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
361 /// isFPImmLegal - Returns true if the target can instruction select the
362 /// specified FP immediate natively. If false, the legalizer will
363 /// materialize the FP immediate as a load from a constant pool.
364 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
366 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
368 unsigned Intrinsic) const;
370 std::pair<const TargetRegisterClass*, uint8_t>
371 findRepresentativeClass(EVT VT) const;
374 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
375 /// make the right decision when generating code for different targets.
376 const ARMSubtarget *Subtarget;
378 const TargetRegisterInfo *RegInfo;
380 const InstrItineraryData *Itins;
382 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
384 unsigned ARMPCLabelIndex;
386 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
387 void addDRTypeForNEON(EVT VT);
388 void addQRTypeForNEON(EVT VT);
390 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
391 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
392 SDValue Chain, SDValue &Arg,
393 RegsToPassVector &RegsToPass,
394 CCValAssign &VA, CCValAssign &NextVA,
396 SmallVector<SDValue, 8> &MemOpChains,
397 ISD::ArgFlagsTy Flags) const;
398 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
399 SDValue &Root, SelectionDAG &DAG,
402 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
403 bool isVarArg) const;
404 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
405 DebugLoc dl, SelectionDAG &DAG,
406 const CCValAssign &VA,
407 ISD::ArgFlagsTy Flags) const;
408 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
409 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
410 SDValue LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) const;
411 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
412 const ARMSubtarget *Subtarget) const;
413 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
414 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
415 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
416 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
417 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
418 SelectionDAG &DAG) const;
419 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
420 SelectionDAG &DAG) const;
421 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
422 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
423 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
424 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
425 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
426 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
427 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
428 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
429 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
430 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
431 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
432 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
433 const ARMSubtarget *ST) const;
435 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
437 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
438 CallingConv::ID CallConv, bool isVarArg,
439 const SmallVectorImpl<ISD::InputArg> &Ins,
440 DebugLoc dl, SelectionDAG &DAG,
441 SmallVectorImpl<SDValue> &InVals) const;
444 LowerFormalArguments(SDValue Chain,
445 CallingConv::ID CallConv, bool isVarArg,
446 const SmallVectorImpl<ISD::InputArg> &Ins,
447 DebugLoc dl, SelectionDAG &DAG,
448 SmallVectorImpl<SDValue> &InVals) const;
450 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
451 DebugLoc dl, SDValue &Chain, unsigned ArgOffset)
454 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
455 unsigned &VARegSize, unsigned &VARegSaveSize) const;
458 LowerCall(SDValue Chain, SDValue Callee,
459 CallingConv::ID CallConv, bool isVarArg,
461 const SmallVectorImpl<ISD::OutputArg> &Outs,
462 const SmallVectorImpl<SDValue> &OutVals,
463 const SmallVectorImpl<ISD::InputArg> &Ins,
464 DebugLoc dl, SelectionDAG &DAG,
465 SmallVectorImpl<SDValue> &InVals) const;
467 /// HandleByVal - Target-specific cleanup for ByVal support.
468 virtual void HandleByVal(CCState *, unsigned &) const;
470 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
471 /// for tail call optimization. Targets which want to do tail call
472 /// optimization should implement this function.
473 bool IsEligibleForTailCallOptimization(SDValue Callee,
474 CallingConv::ID CalleeCC,
476 bool isCalleeStructRet,
477 bool isCallerStructRet,
478 const SmallVectorImpl<ISD::OutputArg> &Outs,
479 const SmallVectorImpl<SDValue> &OutVals,
480 const SmallVectorImpl<ISD::InputArg> &Ins,
481 SelectionDAG& DAG) const;
483 LowerReturn(SDValue Chain,
484 CallingConv::ID CallConv, bool isVarArg,
485 const SmallVectorImpl<ISD::OutputArg> &Outs,
486 const SmallVectorImpl<SDValue> &OutVals,
487 DebugLoc dl, SelectionDAG &DAG) const;
489 virtual bool isUsedByReturnOnly(SDNode *N) const;
491 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
493 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
494 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
495 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
496 SelectionDAG &DAG, DebugLoc dl) const;
497 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
499 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
501 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
502 MachineBasicBlock *BB,
503 unsigned Size) const;
504 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
505 MachineBasicBlock *BB,
507 unsigned BinOpcode) const;
508 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
509 MachineBasicBlock *BB,
512 bool NeedsCarry = false,
513 bool IsCmpxchg = false) const;
514 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
515 MachineBasicBlock *BB,
518 ARMCC::CondCodes Cond) const;
520 void EmitBasePointerRecalculation(MachineInstr *MI, MachineBasicBlock *MBB,
521 MachineBasicBlock *DispatchBB) const;
523 void SetupEntryBlockForSjLj(MachineInstr *MI,
524 MachineBasicBlock *MBB,
525 MachineBasicBlock *DispatchBB, int FI) const;
527 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
528 MachineBasicBlock *MBB) const;
530 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
533 enum NEONModImmType {
541 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
545 #endif // ARMISELLOWERING_H