1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
25 class ARMConstantPoolValue;
28 // ARM Specific DAG Nodes
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
34 // TargetExternalSymbol, and TargetGlobalAddress.
35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
37 CALL, // Function call.
38 CALL_PRED, // Function call that's predicable.
39 CALL_NOLINK, // Function call with branch not branch-and-link.
40 tCALL, // Thumb function call.
41 BRCOND, // Conditional branch.
42 BR_JT, // Jumptable branch.
43 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
44 RET_FLAG, // Return with a flag operand.
46 PIC_ADD, // Add with a PC operand and a PIC label.
48 CMP, // ARM compare instructions.
49 CMPZ, // ARM compare that sets only Z flag.
50 CMPFP, // ARM VFP compare instruction, sets FPSCR.
51 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
52 FMSTAT, // ARM fmstat instruction.
53 CMOV, // ARM conditional move instructions.
54 CNEG, // ARM conditional negate instructions.
56 FTOSI, // FP to sint within a FP register.
57 FTOUI, // FP to uint within a FP register.
58 SITOF, // sint to FP within a FP register.
59 UITOF, // uint to FP within a FP register.
61 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
62 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
63 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
65 FMRRD, // double to two gprs.
66 FMDRR, // Two gprs to double.
68 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
69 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
73 DYN_ALLOC, // Dynamic allocation on the stack.
75 VCEQ, // Vector compare equal.
76 VCGE, // Vector compare greater than or equal.
77 VCGEU, // Vector compare unsigned greater than or equal.
78 VCGT, // Vector compare greater than.
79 VCGTU, // Vector compare unsigned greater than.
80 VTST, // Vector test bits.
82 // Vector shift by immediate:
84 VSHRs, // ...right (signed)
85 VSHRu, // ...right (unsigned)
86 VSHLLs, // ...left long (signed)
87 VSHLLu, // ...left long (unsigned)
88 VSHLLi, // ...left long (with maximum shift count)
89 VSHRN, // ...right narrow
91 // Vector rounding shift by immediate:
92 VRSHRs, // ...right (signed)
93 VRSHRu, // ...right (unsigned)
94 VRSHRN, // ...right narrow
96 // Vector saturating shift by immediate:
97 VQSHLs, // ...left (signed)
98 VQSHLu, // ...left (unsigned)
99 VQSHLsu, // ...left (signed to unsigned)
100 VQSHRNs, // ...right narrow (signed)
101 VQSHRNu, // ...right narrow (unsigned)
102 VQSHRNsu, // ...right narrow (signed to unsigned)
104 // Vector saturating rounding shift by immediate:
105 VQRSHRNs, // ...right narrow (signed)
106 VQRSHRNu, // ...right narrow (unsigned)
107 VQRSHRNsu, // ...right narrow (signed to unsigned)
109 // Vector shift and insert:
113 // Vector get lane (VMOV scalar to ARM core register)
114 // (These are used for 8- and 16-bit element types only.)
115 VGETLANEu, // zero-extend vector extract element
116 VGETLANEs, // sign-extend vector extract element
118 // Vector duplicate lane (128-bit result only; 64-bit is a shuffle)
119 VDUPLANEQ, // splat a lane from a 64-bit vector to a 128-bit vector
121 // Vector load/store with (de)interleaving
131 /// Define some predicates that are used for node matching.
133 /// getVMOVImm - If this is a build_vector of constants which can be
134 /// formed by using a VMOV instruction of the specified element size,
135 /// return the constant being splatted. The ByteSize field indicates the
136 /// number of bytes of each element [1248].
137 SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
139 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
140 /// instruction with the specified blocksize. (The order of the elements
141 /// within each block of the vector is reversed.)
142 bool isVREVMask(ShuffleVectorSDNode *N, unsigned blocksize);
145 //===--------------------------------------------------------------------===//
146 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
148 class ARMTargetLowering : public TargetLowering {
149 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
151 explicit ARMTargetLowering(TargetMachine &TM);
153 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
155 /// ReplaceNodeResults - Replace the results of node with an illegal result
156 /// type with new values built out of custom code.
158 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
161 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
163 virtual const char *getTargetNodeName(unsigned Opcode) const;
165 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
166 MachineBasicBlock *MBB) const;
168 /// isLegalAddressingMode - Return true if the addressing mode represented
169 /// by AM is legal for this target, for a load/store of the specified type.
170 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
172 /// getPreIndexedAddressParts - returns true by value, base pointer and
173 /// offset pointer and addressing mode by reference if the node's address
174 /// can be legally represented as pre-indexed load / store address.
175 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
177 ISD::MemIndexedMode &AM,
178 SelectionDAG &DAG) const;
180 /// getPostIndexedAddressParts - returns true by value, base pointer and
181 /// offset pointer and addressing mode by reference if this node can be
182 /// combined with a load / store to form a post-indexed load / store.
183 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
184 SDValue &Base, SDValue &Offset,
185 ISD::MemIndexedMode &AM,
186 SelectionDAG &DAG) const;
188 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
192 const SelectionDAG &DAG,
193 unsigned Depth) const;
194 ConstraintType getConstraintType(const std::string &Constraint) const;
195 std::pair<unsigned, const TargetRegisterClass*>
196 getRegForInlineAsmConstraint(const std::string &Constraint,
198 std::vector<unsigned>
199 getRegClassForInlineAsmConstraint(const std::string &Constraint,
202 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
203 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
204 /// true it means one of the asm constraint of the inline asm instruction
205 /// being processed is 'm'.
206 virtual void LowerAsmOperandForConstraint(SDValue Op,
207 char ConstraintLetter,
209 std::vector<SDValue> &Ops,
210 SelectionDAG &DAG) const;
212 virtual const ARMSubtarget* getSubtarget() {
216 /// getFunctionAlignment - Return the Log2 alignment of this function.
217 virtual unsigned getFunctionAlignment(const Function *F) const;
220 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
221 /// make the right decision when generating code for different targets.
222 const ARMSubtarget *Subtarget;
224 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
226 unsigned ARMPCLabelIndex;
228 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
229 void addDRTypeForNEON(MVT VT);
230 void addQRTypeForNEON(MVT VT);
232 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
233 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
234 SDValue Chain, SDValue &Arg,
235 RegsToPassVector &RegsToPass,
236 CCValAssign &VA, CCValAssign &NextVA,
238 SmallVector<SDValue, 8> &MemOpChains,
239 ISD::ArgFlagsTy Flags);
240 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
241 SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
243 CCAssignFn *CCAssignFnForNode(unsigned CC, bool Return, bool isVarArg) const;
244 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
245 DebugLoc dl, SelectionDAG &DAG,
246 const CCValAssign &VA,
247 ISD::ArgFlagsTy Flags);
248 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG);
249 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
250 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
251 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
252 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
253 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
255 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
257 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
258 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
259 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
260 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
262 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
264 SDValue Dst, SDValue Src,
265 SDValue Size, unsigned Align,
267 const Value *DstSV, uint64_t DstSVOff,
268 const Value *SrcSV, uint64_t SrcSVOff);
269 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
270 unsigned CallConv, bool isVarArg,
271 const SmallVectorImpl<ISD::InputArg> &Ins,
272 DebugLoc dl, SelectionDAG &DAG,
273 SmallVectorImpl<SDValue> &InVals);
276 LowerFormalArguments(SDValue Chain,
277 unsigned CallConv, bool isVarArg,
278 const SmallVectorImpl<ISD::InputArg> &Ins,
279 DebugLoc dl, SelectionDAG &DAG,
280 SmallVectorImpl<SDValue> &InVals);
283 LowerCall(SDValue Chain, SDValue Callee,
284 unsigned CallConv, bool isVarArg,
286 const SmallVectorImpl<ISD::OutputArg> &Outs,
287 const SmallVectorImpl<ISD::InputArg> &Ins,
288 DebugLoc dl, SelectionDAG &DAG,
289 SmallVectorImpl<SDValue> &InVals);
292 LowerReturn(SDValue Chain,
293 unsigned CallConv, bool isVarArg,
294 const SmallVectorImpl<ISD::OutputArg> &Outs,
295 DebugLoc dl, SelectionDAG &DAG);
299 #endif // ARMISELLOWERING_H