1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
25 class ARMConstantPoolValue;
28 // ARM Specific DAG Nodes
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
34 // TargetExternalSymbol, and TargetGlobalAddress.
35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
37 CALL, // Function call.
38 CALL_PRED, // Function call that's predicable.
39 CALL_NOLINK, // Function call with branch not branch-and-link.
40 tCALL, // Thumb function call.
41 BRCOND, // Conditional branch.
42 BR_JT, // Jumptable branch.
43 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
44 RET_FLAG, // Return with a flag operand.
46 PIC_ADD, // Add with a PC operand and a PIC label.
48 CMP, // ARM compare instructions.
49 CMPZ, // ARM compare that sets only Z flag.
50 CMPFP, // ARM VFP compare instruction, sets FPSCR.
51 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
52 FMSTAT, // ARM fmstat instruction.
53 CMOV, // ARM conditional move instructions.
54 CNEG, // ARM conditional negate instructions.
56 FTOSI, // FP to sint within a FP register.
57 FTOUI, // FP to uint within a FP register.
58 SITOF, // sint to FP within a FP register.
59 UITOF, // uint to FP within a FP register.
61 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
62 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
63 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
65 VMOVRRD, // double to two gprs.
66 VMOVDRR, // Two gprs to double.
68 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
69 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
73 DYN_ALLOC, // Dynamic allocation on the stack.
75 VCEQ, // Vector compare equal.
76 VCGE, // Vector compare greater than or equal.
77 VCGEU, // Vector compare unsigned greater than or equal.
78 VCGT, // Vector compare greater than.
79 VCGTU, // Vector compare unsigned greater than.
80 VTST, // Vector test bits.
82 // Vector shift by immediate:
84 VSHRs, // ...right (signed)
85 VSHRu, // ...right (unsigned)
86 VSHLLs, // ...left long (signed)
87 VSHLLu, // ...left long (unsigned)
88 VSHLLi, // ...left long (with maximum shift count)
89 VSHRN, // ...right narrow
91 // Vector rounding shift by immediate:
92 VRSHRs, // ...right (signed)
93 VRSHRu, // ...right (unsigned)
94 VRSHRN, // ...right narrow
96 // Vector saturating shift by immediate:
97 VQSHLs, // ...left (signed)
98 VQSHLu, // ...left (unsigned)
99 VQSHLsu, // ...left (signed to unsigned)
100 VQSHRNs, // ...right narrow (signed)
101 VQSHRNu, // ...right narrow (unsigned)
102 VQSHRNsu, // ...right narrow (signed to unsigned)
104 // Vector saturating rounding shift by immediate:
105 VQRSHRNs, // ...right narrow (signed)
106 VQRSHRNu, // ...right narrow (unsigned)
107 VQRSHRNsu, // ...right narrow (signed to unsigned)
109 // Vector shift and insert:
113 // Vector get lane (VMOV scalar to ARM core register)
114 // (These are used for 8- and 16-bit element types only.)
115 VGETLANEu, // zero-extend vector extract element
116 VGETLANEs, // sign-extend vector extract element
124 VREV64, // reverse elements within 64-bit doublewords
125 VREV32, // reverse elements within 32-bit words
126 VREV16, // reverse elements within 16-bit halfwords
127 VZIP, // zip (interleave)
128 VUZP, // unzip (deinterleave)
133 /// Define some predicates that are used for node matching.
135 /// getVMOVImm - If this is a build_vector of constants which can be
136 /// formed by using a VMOV instruction of the specified element size,
137 /// return the constant being splatted. The ByteSize field indicates the
138 /// number of bytes of each element [1248].
139 SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
141 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
142 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
143 /// instruction, returns its 8-bit integer representation. Otherwise,
145 int getVFPf32Imm(const APFloat &FPImm);
146 int getVFPf64Imm(const APFloat &FPImm);
149 //===--------------------------------------------------------------------===//
150 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
152 class ARMTargetLowering : public TargetLowering {
153 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
155 explicit ARMTargetLowering(TargetMachine &TM);
157 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
159 /// ReplaceNodeResults - Replace the results of node with an illegal result
160 /// type with new values built out of custom code.
162 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
165 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
167 virtual const char *getTargetNodeName(unsigned Opcode) const;
169 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
170 MachineBasicBlock *MBB,
171 DenseMap<MachineBasicBlock*, MachineBasicBlock*>*) const;
173 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
174 /// unaligned memory accesses. of the specified type.
175 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
176 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
178 /// isLegalAddressingMode - Return true if the addressing mode represented
179 /// by AM is legal for this target, for a load/store of the specified type.
180 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
181 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
183 /// isLegalICmpImmediate - Return true if the specified immediate is legal
184 /// icmp immediate, that is the target has icmp instructions which can compare
185 /// a register against the immediate without having to materialize the
186 /// immediate into a register.
187 virtual bool isLegalICmpImmediate(int64_t Imm) const;
189 /// getPreIndexedAddressParts - returns true by value, base pointer and
190 /// offset pointer and addressing mode by reference if the node's address
191 /// can be legally represented as pre-indexed load / store address.
192 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
194 ISD::MemIndexedMode &AM,
195 SelectionDAG &DAG) const;
197 /// getPostIndexedAddressParts - returns true by value, base pointer and
198 /// offset pointer and addressing mode by reference if this node can be
199 /// combined with a load / store to form a post-indexed load / store.
200 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
201 SDValue &Base, SDValue &Offset,
202 ISD::MemIndexedMode &AM,
203 SelectionDAG &DAG) const;
205 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
209 const SelectionDAG &DAG,
210 unsigned Depth) const;
213 ConstraintType getConstraintType(const std::string &Constraint) const;
214 std::pair<unsigned, const TargetRegisterClass*>
215 getRegForInlineAsmConstraint(const std::string &Constraint,
217 std::vector<unsigned>
218 getRegClassForInlineAsmConstraint(const std::string &Constraint,
221 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
222 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
223 /// true it means one of the asm constraint of the inline asm instruction
224 /// being processed is 'm'.
225 virtual void LowerAsmOperandForConstraint(SDValue Op,
226 char ConstraintLetter,
228 std::vector<SDValue> &Ops,
229 SelectionDAG &DAG) const;
231 virtual const ARMSubtarget* getSubtarget() {
235 /// getFunctionAlignment - Return the Log2 alignment of this function.
236 virtual unsigned getFunctionAlignment(const Function *F) const;
238 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
239 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
241 /// isFPImmLegal - Returns true if the target can instruction select the
242 /// specified FP immediate natively. If false, the legalizer will
243 /// materialize the FP immediate as a load from a constant pool.
244 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
247 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
248 /// make the right decision when generating code for different targets.
249 const ARMSubtarget *Subtarget;
251 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
253 unsigned ARMPCLabelIndex;
255 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
256 void addDRTypeForNEON(EVT VT);
257 void addQRTypeForNEON(EVT VT);
259 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
260 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
261 SDValue Chain, SDValue &Arg,
262 RegsToPassVector &RegsToPass,
263 CCValAssign &VA, CCValAssign &NextVA,
265 SmallVector<SDValue, 8> &MemOpChains,
266 ISD::ArgFlagsTy Flags);
267 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
268 SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
270 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const;
271 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
272 DebugLoc dl, SelectionDAG &DAG,
273 const CCValAssign &VA,
274 ISD::ArgFlagsTy Flags);
275 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG);
276 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
277 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
278 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
279 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
280 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
281 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
283 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
285 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
286 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
287 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
288 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
289 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
290 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
291 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG);
292 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG);
294 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
296 SDValue Dst, SDValue Src,
297 SDValue Size, unsigned Align,
299 const Value *DstSV, uint64_t DstSVOff,
300 const Value *SrcSV, uint64_t SrcSVOff);
301 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
302 CallingConv::ID CallConv, bool isVarArg,
303 const SmallVectorImpl<ISD::InputArg> &Ins,
304 DebugLoc dl, SelectionDAG &DAG,
305 SmallVectorImpl<SDValue> &InVals);
308 LowerFormalArguments(SDValue Chain,
309 CallingConv::ID CallConv, bool isVarArg,
310 const SmallVectorImpl<ISD::InputArg> &Ins,
311 DebugLoc dl, SelectionDAG &DAG,
312 SmallVectorImpl<SDValue> &InVals);
315 LowerCall(SDValue Chain, SDValue Callee,
316 CallingConv::ID CallConv, bool isVarArg,
318 const SmallVectorImpl<ISD::OutputArg> &Outs,
319 const SmallVectorImpl<ISD::InputArg> &Ins,
320 DebugLoc dl, SelectionDAG &DAG,
321 SmallVectorImpl<SDValue> &InVals);
324 LowerReturn(SDValue Chain,
325 CallingConv::ID CallConv, bool isVarArg,
326 const SmallVectorImpl<ISD::OutputArg> &Outs,
327 DebugLoc dl, SelectionDAG &DAG);
329 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
330 SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl);
334 #endif // ARMISELLOWERING_H