1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
19 #include "ARMSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Target/TargetTransformImpl.h"
29 class ARMConstantPoolValue;
32 // ARM Specific DAG Nodes
34 // Start the numbering where the builtin ops and target ops leave off.
35 FIRST_NUMBER = ISD::BUILTIN_OP_END,
37 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
38 // TargetExternalSymbol, and TargetGlobalAddress.
39 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
41 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
43 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
45 // Add pseudo op to model memcpy for struct byval.
48 CALL, // Function call.
49 CALL_PRED, // Function call that's predicable.
50 CALL_NOLINK, // Function call with branch not branch-and-link.
51 tCALL, // Thumb function call.
52 BRCOND, // Conditional branch.
53 BR_JT, // Jumptable branch.
54 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
55 RET_FLAG, // Return with a flag operand.
57 PIC_ADD, // Add with a PC operand and a PIC label.
59 CMP, // ARM compare instructions.
60 CMN, // ARM CMN instructions.
61 CMPZ, // ARM compare that sets only Z flag.
62 CMPFP, // ARM VFP compare instruction, sets FPSCR.
63 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
64 FMSTAT, // ARM fmstat instruction.
66 CMOV, // ARM conditional move instructions.
70 RBIT, // ARM bitreverse instruction
72 FTOSI, // FP to sint within a FP register.
73 FTOUI, // FP to uint within a FP register.
74 SITOF, // sint to FP within a FP register.
75 UITOF, // uint to FP within a FP register.
77 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
78 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
79 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
81 ADDC, // Add with carry
82 ADDE, // Add using carry
83 SUBC, // Sub with carry
84 SUBE, // Sub using carry
86 VMOVRRD, // double to two gprs.
87 VMOVDRR, // Two gprs to double.
89 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
90 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
92 TC_RETURN, // Tail call return pseudo.
96 DYN_ALLOC, // Dynamic allocation on the stack.
98 MEMBARRIER, // Memory barrier (DMB)
99 MEMBARRIER_MCR, // Memory barrier (MCR)
103 VCEQ, // Vector compare equal.
104 VCEQZ, // Vector compare equal to zero.
105 VCGE, // Vector compare greater than or equal.
106 VCGEZ, // Vector compare greater than or equal to zero.
107 VCLEZ, // Vector compare less than or equal to zero.
108 VCGEU, // Vector compare unsigned greater than or equal.
109 VCGT, // Vector compare greater than.
110 VCGTZ, // Vector compare greater than zero.
111 VCLTZ, // Vector compare less than zero.
112 VCGTU, // Vector compare unsigned greater than.
113 VTST, // Vector test bits.
115 // Vector shift by immediate:
117 VSHRs, // ...right (signed)
118 VSHRu, // ...right (unsigned)
119 VSHLLs, // ...left long (signed)
120 VSHLLu, // ...left long (unsigned)
121 VSHLLi, // ...left long (with maximum shift count)
122 VSHRN, // ...right narrow
124 // Vector rounding shift by immediate:
125 VRSHRs, // ...right (signed)
126 VRSHRu, // ...right (unsigned)
127 VRSHRN, // ...right narrow
129 // Vector saturating shift by immediate:
130 VQSHLs, // ...left (signed)
131 VQSHLu, // ...left (unsigned)
132 VQSHLsu, // ...left (signed to unsigned)
133 VQSHRNs, // ...right narrow (signed)
134 VQSHRNu, // ...right narrow (unsigned)
135 VQSHRNsu, // ...right narrow (signed to unsigned)
137 // Vector saturating rounding shift by immediate:
138 VQRSHRNs, // ...right narrow (signed)
139 VQRSHRNu, // ...right narrow (unsigned)
140 VQRSHRNsu, // ...right narrow (signed to unsigned)
142 // Vector shift and insert:
146 // Vector get lane (VMOV scalar to ARM core register)
147 // (These are used for 8- and 16-bit element types only.)
148 VGETLANEu, // zero-extend vector extract element
149 VGETLANEs, // sign-extend vector extract element
151 // Vector move immediate and move negated immediate:
155 // Vector move f32 immediate:
164 VREV64, // reverse elements within 64-bit doublewords
165 VREV32, // reverse elements within 32-bit words
166 VREV16, // reverse elements within 16-bit halfwords
167 VZIP, // zip (interleave)
168 VUZP, // unzip (deinterleave)
170 VTBL1, // 1-register shuffle with mask
171 VTBL2, // 2-register shuffle with mask
173 // Vector multiply long:
175 VMULLu, // ...unsigned
177 UMLAL, // 64bit Unsigned Accumulate Multiply
178 SMLAL, // 64bit Signed Accumulate Multiply
180 // Operands of the standard BUILD_VECTOR node are not legalized, which
181 // is fine if BUILD_VECTORs are always lowered to shuffles or other
182 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
183 // operands need to be legalized. Define an ARM-specific version of
184 // BUILD_VECTOR for this purpose.
187 // Floating-point max and min:
194 // Vector OR with immediate
196 // Vector AND with NOT of immediate
199 // Vector bitwise select
202 // Vector load N-element structure to all lanes:
203 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
207 // NEON loads with post-increment base updates:
219 // NEON stores with post-increment base updates:
228 // 64-bit atomic ops (value split into two registers)
244 /// Define some predicates that are used for node matching.
246 bool isBitFieldInvertedMask(unsigned v);
249 //===--------------------------------------------------------------------===//
250 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
252 class ARMTargetLowering : public TargetLowering {
254 explicit ARMTargetLowering(TargetMachine &TM);
256 virtual unsigned getJumpTableEncoding() const;
258 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
260 /// ReplaceNodeResults - Replace the results of node with an illegal result
261 /// type with new values built out of custom code.
263 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
264 SelectionDAG &DAG) const;
266 virtual const char *getTargetNodeName(unsigned Opcode) const;
268 virtual bool isSelectSupported(SelectSupportKind Kind) const {
269 // ARM does not support scalar condition selects on vectors.
270 return (Kind != ScalarCondVectorVal);
273 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
274 virtual EVT getSetCCResultType(EVT VT) const;
276 virtual MachineBasicBlock *
277 EmitInstrWithCustomInserter(MachineInstr *MI,
278 MachineBasicBlock *MBB) const;
281 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
283 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
284 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
286 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
288 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
289 /// unaligned memory accesses of the specified type. Returns whether it
290 /// is "fast" by reference in the second argument.
291 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
293 virtual EVT getOptimalMemOpType(uint64_t Size,
294 unsigned DstAlign, unsigned SrcAlign,
295 bool IsMemset, bool ZeroMemset,
297 MachineFunction &MF) const;
299 using TargetLowering::isZExtFree;
300 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
302 /// isLegalAddressingMode - Return true if the addressing mode represented
303 /// by AM is legal for this target, for a load/store of the specified type.
304 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
305 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
307 /// isLegalICmpImmediate - Return true if the specified immediate is legal
308 /// icmp immediate, that is the target has icmp instructions which can
309 /// compare a register against the immediate without having to materialize
310 /// the immediate into a register.
311 virtual bool isLegalICmpImmediate(int64_t Imm) const;
313 /// isLegalAddImmediate - Return true if the specified immediate is legal
314 /// add immediate, that is the target has add instructions which can
315 /// add a register and the immediate without having to materialize
316 /// the immediate into a register.
317 virtual bool isLegalAddImmediate(int64_t Imm) const;
319 /// getPreIndexedAddressParts - returns true by value, base pointer and
320 /// offset pointer and addressing mode by reference if the node's address
321 /// can be legally represented as pre-indexed load / store address.
322 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
324 ISD::MemIndexedMode &AM,
325 SelectionDAG &DAG) const;
327 /// getPostIndexedAddressParts - returns true by value, base pointer and
328 /// offset pointer and addressing mode by reference if this node can be
329 /// combined with a load / store to form a post-indexed load / store.
330 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
331 SDValue &Base, SDValue &Offset,
332 ISD::MemIndexedMode &AM,
333 SelectionDAG &DAG) const;
335 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
338 const SelectionDAG &DAG,
339 unsigned Depth) const;
342 virtual bool ExpandInlineAsm(CallInst *CI) const;
344 ConstraintType getConstraintType(const std::string &Constraint) const;
346 /// Examine constraint string and operand type and determine a weight value.
347 /// The operand object must already have been set up with the operand type.
348 ConstraintWeight getSingleConstraintMatchWeight(
349 AsmOperandInfo &info, const char *constraint) const;
351 std::pair<unsigned, const TargetRegisterClass*>
352 getRegForInlineAsmConstraint(const std::string &Constraint,
355 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
356 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
357 /// true it means one of the asm constraint of the inline asm instruction
358 /// being processed is 'm'.
359 virtual void LowerAsmOperandForConstraint(SDValue Op,
360 std::string &Constraint,
361 std::vector<SDValue> &Ops,
362 SelectionDAG &DAG) const;
364 const ARMSubtarget* getSubtarget() const {
368 /// getRegClassFor - Return the register class that should be used for the
369 /// specified value type.
370 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const;
372 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
373 /// be used for loads / stores from the global.
374 virtual unsigned getMaximalGlobalOffset() const;
376 /// createFastISel - This method returns a target specific FastISel object,
377 /// or null if the target does not support "fast" ISel.
378 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
379 const TargetLibraryInfo *libInfo) const;
381 Sched::Preference getSchedulingPreference(SDNode *N) const;
383 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
384 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
386 /// isFPImmLegal - Returns true if the target can instruction select the
387 /// specified FP immediate natively. If false, the legalizer will
388 /// materialize the FP immediate as a load from a constant pool.
389 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
391 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
393 unsigned Intrinsic) const;
395 std::pair<const TargetRegisterClass*, uint8_t>
396 findRepresentativeClass(MVT VT) const;
399 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
400 /// make the right decision when generating code for different targets.
401 const ARMSubtarget *Subtarget;
403 const TargetRegisterInfo *RegInfo;
405 const InstrItineraryData *Itins;
407 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
409 unsigned ARMPCLabelIndex;
411 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
412 void addDRTypeForNEON(MVT VT);
413 void addQRTypeForNEON(MVT VT);
415 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
416 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
417 SDValue Chain, SDValue &Arg,
418 RegsToPassVector &RegsToPass,
419 CCValAssign &VA, CCValAssign &NextVA,
421 SmallVector<SDValue, 8> &MemOpChains,
422 ISD::ArgFlagsTy Flags) const;
423 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
424 SDValue &Root, SelectionDAG &DAG,
427 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
428 bool isVarArg) const;
429 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
430 DebugLoc dl, SelectionDAG &DAG,
431 const CCValAssign &VA,
432 ISD::ArgFlagsTy Flags) const;
433 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
434 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
435 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
436 const ARMSubtarget *Subtarget) const;
437 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
439 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
440 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
441 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
442 SelectionDAG &DAG) const;
443 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
445 TLSModel::Model model) const;
446 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
447 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
448 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
449 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
450 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
451 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
452 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
453 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
454 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
455 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
456 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
457 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
458 const ARMSubtarget *ST) const;
459 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
460 const ARMSubtarget *ST) const;
462 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
464 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
465 CallingConv::ID CallConv, bool isVarArg,
466 const SmallVectorImpl<ISD::InputArg> &Ins,
467 DebugLoc dl, SelectionDAG &DAG,
468 SmallVectorImpl<SDValue> &InVals) const;
471 LowerFormalArguments(SDValue Chain,
472 CallingConv::ID CallConv, bool isVarArg,
473 const SmallVectorImpl<ISD::InputArg> &Ins,
474 DebugLoc dl, SelectionDAG &DAG,
475 SmallVectorImpl<SDValue> &InVals) const;
477 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
478 DebugLoc dl, SDValue &Chain,
479 const Value *OrigArg,
480 unsigned OffsetFromOrigArg,
482 bool ForceMutable = false)
485 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
486 unsigned &VARegSize, unsigned &VARegSaveSize) const;
489 LowerCall(TargetLowering::CallLoweringInfo &CLI,
490 SmallVectorImpl<SDValue> &InVals) const;
492 /// HandleByVal - Target-specific cleanup for ByVal support.
493 virtual void HandleByVal(CCState *, unsigned &, unsigned) const;
495 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
496 /// for tail call optimization. Targets which want to do tail call
497 /// optimization should implement this function.
498 bool IsEligibleForTailCallOptimization(SDValue Callee,
499 CallingConv::ID CalleeCC,
501 bool isCalleeStructRet,
502 bool isCallerStructRet,
503 const SmallVectorImpl<ISD::OutputArg> &Outs,
504 const SmallVectorImpl<SDValue> &OutVals,
505 const SmallVectorImpl<ISD::InputArg> &Ins,
506 SelectionDAG& DAG) const;
508 virtual bool CanLowerReturn(CallingConv::ID CallConv,
509 MachineFunction &MF, bool isVarArg,
510 const SmallVectorImpl<ISD::OutputArg> &Outs,
511 LLVMContext &Context) const;
514 LowerReturn(SDValue Chain,
515 CallingConv::ID CallConv, bool isVarArg,
516 const SmallVectorImpl<ISD::OutputArg> &Outs,
517 const SmallVectorImpl<SDValue> &OutVals,
518 DebugLoc dl, SelectionDAG &DAG) const;
520 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
522 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
524 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
525 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
526 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
527 SelectionDAG &DAG, DebugLoc dl) const;
528 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
530 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
532 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
533 MachineBasicBlock *BB,
534 unsigned Size) const;
535 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
536 MachineBasicBlock *BB,
538 unsigned BinOpcode) const;
539 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
540 MachineBasicBlock *BB,
543 bool NeedsCarry = false,
544 bool IsCmpxchg = false,
545 bool IsMinMax = false,
546 ARMCC::CondCodes CC = ARMCC::AL) const;
547 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
548 MachineBasicBlock *BB,
551 ARMCC::CondCodes Cond) const;
553 void SetupEntryBlockForSjLj(MachineInstr *MI,
554 MachineBasicBlock *MBB,
555 MachineBasicBlock *DispatchBB, int FI) const;
557 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
558 MachineBasicBlock *MBB) const;
560 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
562 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
563 MachineBasicBlock *MBB) const;
566 enum NEONModImmType {
574 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
575 const TargetLibraryInfo *libInfo);
578 class ARMScalarTargetTransformImpl : public ScalarTargetTransformImpl {
579 const ARMSubtarget *Subtarget;
581 explicit ARMScalarTargetTransformImpl(const TargetLowering *TL) :
582 ScalarTargetTransformImpl(TL),
583 Subtarget(&TL->getTargetMachine().getSubtarget<ARMSubtarget>()) {};
585 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
589 #endif // ARMISELLOWERING_H