1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
25 class ARMConstantPoolValue;
29 // ARM Specific DAG Nodes
30 enum NodeType : unsigned {
31 // Start the numbering where the builtin ops and target ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
40 // Add pseudo op to model memcpy for struct byval.
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
51 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
53 PIC_ADD, // Add with a PC operand and a PIC label.
55 CMP, // ARM compare instructions.
56 CMN, // ARM CMN instructions.
57 CMPZ, // ARM compare that sets only Z flag.
58 CMPFP, // ARM VFP compare instruction, sets FPSCR.
59 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
60 FMSTAT, // ARM fmstat instruction.
62 CMOV, // ARM conditional move instructions.
66 RBIT, // ARM bitreverse instruction
68 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
69 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
70 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
72 ADDC, // Add with carry
73 ADDE, // Add using carry
74 SUBC, // Sub with carry
75 SUBE, // Sub using carry
77 VMOVRRD, // double to two gprs.
78 VMOVDRR, // Two gprs to double.
80 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
81 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
83 TC_RETURN, // Tail call return pseudo.
87 DYN_ALLOC, // Dynamic allocation on the stack.
89 MEMBARRIER_MCR, // Memory barrier (MCR)
93 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
95 VCEQ, // Vector compare equal.
96 VCEQZ, // Vector compare equal to zero.
97 VCGE, // Vector compare greater than or equal.
98 VCGEZ, // Vector compare greater than or equal to zero.
99 VCLEZ, // Vector compare less than or equal to zero.
100 VCGEU, // Vector compare unsigned greater than or equal.
101 VCGT, // Vector compare greater than.
102 VCGTZ, // Vector compare greater than zero.
103 VCLTZ, // Vector compare less than zero.
104 VCGTU, // Vector compare unsigned greater than.
105 VTST, // Vector test bits.
107 // Vector shift by immediate:
109 VSHRs, // ...right (signed)
110 VSHRu, // ...right (unsigned)
112 // Vector rounding shift by immediate:
113 VRSHRs, // ...right (signed)
114 VRSHRu, // ...right (unsigned)
115 VRSHRN, // ...right narrow
117 // Vector saturating shift by immediate:
118 VQSHLs, // ...left (signed)
119 VQSHLu, // ...left (unsigned)
120 VQSHLsu, // ...left (signed to unsigned)
121 VQSHRNs, // ...right narrow (signed)
122 VQSHRNu, // ...right narrow (unsigned)
123 VQSHRNsu, // ...right narrow (signed to unsigned)
125 // Vector saturating rounding shift by immediate:
126 VQRSHRNs, // ...right narrow (signed)
127 VQRSHRNu, // ...right narrow (unsigned)
128 VQRSHRNsu, // ...right narrow (signed to unsigned)
130 // Vector shift and insert:
134 // Vector get lane (VMOV scalar to ARM core register)
135 // (These are used for 8- and 16-bit element types only.)
136 VGETLANEu, // zero-extend vector extract element
137 VGETLANEs, // sign-extend vector extract element
139 // Vector move immediate and move negated immediate:
143 // Vector move f32 immediate:
152 VREV64, // reverse elements within 64-bit doublewords
153 VREV32, // reverse elements within 32-bit words
154 VREV16, // reverse elements within 16-bit halfwords
155 VZIP, // zip (interleave)
156 VUZP, // unzip (deinterleave)
158 VTBL1, // 1-register shuffle with mask
159 VTBL2, // 2-register shuffle with mask
161 // Vector multiply long:
163 VMULLu, // ...unsigned
165 UMLAL, // 64bit Unsigned Accumulate Multiply
166 SMLAL, // 64bit Signed Accumulate Multiply
168 // Operands of the standard BUILD_VECTOR node are not legalized, which
169 // is fine if BUILD_VECTORs are always lowered to shuffles or other
170 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
171 // operands need to be legalized. Define an ARM-specific version of
172 // BUILD_VECTOR for this purpose.
175 // Floating-point max and min:
184 // Vector OR with immediate
186 // Vector AND with NOT of immediate
189 // Vector bitwise select
192 // Vector load N-element structure to all lanes:
193 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
197 // NEON loads with post-increment base updates:
209 // NEON stores with post-increment base updates:
220 /// Define some predicates that are used for node matching.
222 bool isBitFieldInvertedMask(unsigned v);
225 //===--------------------------------------------------------------------===//
226 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
228 class ARMTargetLowering : public TargetLowering {
230 explicit ARMTargetLowering(const TargetMachine &TM,
231 const ARMSubtarget &STI);
233 unsigned getJumpTableEncoding() const override;
234 bool useSoftFloat() const override;
236 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
238 /// ReplaceNodeResults - Replace the results of node with an illegal result
239 /// type with new values built out of custom code.
241 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
242 SelectionDAG &DAG) const override;
244 const char *getTargetNodeName(unsigned Opcode) const override;
246 bool isSelectSupported(SelectSupportKind Kind) const override {
247 // ARM does not support scalar condition selects on vectors.
248 return (Kind != ScalarCondVectorVal);
251 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
252 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
255 EmitInstrWithCustomInserter(MachineInstr *MI,
256 MachineBasicBlock *MBB) const override;
258 void AdjustInstrPostInstrSelection(MachineInstr *MI,
259 SDNode *Node) const override;
261 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
262 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
264 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
266 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
267 /// unaligned memory accesses of the specified type. Returns whether it
268 /// is "fast" by reference in the second argument.
269 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
271 bool *Fast) const override;
273 EVT getOptimalMemOpType(uint64_t Size,
274 unsigned DstAlign, unsigned SrcAlign,
275 bool IsMemset, bool ZeroMemset,
277 MachineFunction &MF) const override;
279 using TargetLowering::isZExtFree;
280 bool isZExtFree(SDValue Val, EVT VT2) const override;
282 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
284 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
287 /// isLegalAddressingMode - Return true if the addressing mode represented
288 /// by AM is legal for this target, for a load/store of the specified type.
289 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
290 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
292 /// isLegalICmpImmediate - Return true if the specified immediate is legal
293 /// icmp immediate, that is the target has icmp instructions which can
294 /// compare a register against the immediate without having to materialize
295 /// the immediate into a register.
296 bool isLegalICmpImmediate(int64_t Imm) const override;
298 /// isLegalAddImmediate - Return true if the specified immediate is legal
299 /// add immediate, that is the target has add instructions which can
300 /// add a register and the immediate without having to materialize
301 /// the immediate into a register.
302 bool isLegalAddImmediate(int64_t Imm) const override;
304 /// getPreIndexedAddressParts - returns true by value, base pointer and
305 /// offset pointer and addressing mode by reference if the node's address
306 /// can be legally represented as pre-indexed load / store address.
307 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
308 ISD::MemIndexedMode &AM,
309 SelectionDAG &DAG) const override;
311 /// getPostIndexedAddressParts - returns true by value, base pointer and
312 /// offset pointer and addressing mode by reference if this node can be
313 /// combined with a load / store to form a post-indexed load / store.
314 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
315 SDValue &Offset, ISD::MemIndexedMode &AM,
316 SelectionDAG &DAG) const override;
318 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
320 const SelectionDAG &DAG,
321 unsigned Depth) const override;
324 bool ExpandInlineAsm(CallInst *CI) const override;
327 getConstraintType(const std::string &Constraint) const override;
329 /// Examine constraint string and operand type and determine a weight value.
330 /// The operand object must already have been set up with the operand type.
331 ConstraintWeight getSingleConstraintMatchWeight(
332 AsmOperandInfo &info, const char *constraint) const override;
334 std::pair<unsigned, const TargetRegisterClass *>
335 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
336 const std::string &Constraint,
337 MVT VT) const override;
339 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
340 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
341 /// true it means one of the asm constraint of the inline asm instruction
342 /// being processed is 'm'.
343 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
344 std::vector<SDValue> &Ops,
345 SelectionDAG &DAG) const override;
347 unsigned getInlineAsmMemConstraint(
348 const std::string &ConstraintCode) const override {
349 // FIXME: Map different constraints differently.
350 return InlineAsm::Constraint_m;
353 const ARMSubtarget* getSubtarget() const {
357 /// getRegClassFor - Return the register class that should be used for the
358 /// specified value type.
359 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
361 /// Returns true if a cast between SrcAS and DestAS is a noop.
362 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
363 // Addrspacecasts are always noops.
367 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
368 unsigned &PrefAlign) const override;
370 /// createFastISel - This method returns a target specific FastISel object,
371 /// or null if the target does not support "fast" ISel.
372 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
373 const TargetLibraryInfo *libInfo) const override;
375 Sched::Preference getSchedulingPreference(SDNode *N) const override;
378 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
379 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
381 /// isFPImmLegal - Returns true if the target can instruction select the
382 /// specified FP immediate natively. If false, the legalizer will
383 /// materialize the FP immediate as a load from a constant pool.
384 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
386 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
388 unsigned Intrinsic) const override;
390 /// \brief Returns true if it is beneficial to convert a load of a constant
391 /// to just the constant itself.
392 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
393 Type *Ty) const override;
395 /// \brief Returns true if an argument of type Ty needs to be passed in a
396 /// contiguous block of registers in calling convention CallConv.
397 bool functionArgumentNeedsConsecutiveRegisters(
398 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
400 bool hasLoadLinkedStoreConditional() const override;
401 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
402 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
403 AtomicOrdering Ord) const override;
404 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
405 Value *Addr, AtomicOrdering Ord) const override;
407 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
408 bool IsStore, bool IsLoad) const override;
409 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
410 bool IsStore, bool IsLoad) const override;
412 bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
413 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
414 TargetLoweringBase::AtomicRMWExpansionKind
415 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
417 bool useLoadStackGuardNode() const override;
419 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
420 unsigned &Cost) const override;
423 std::pair<const TargetRegisterClass *, uint8_t>
424 findRepresentativeClass(const TargetRegisterInfo *TRI,
425 MVT VT) const override;
428 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
429 /// make the right decision when generating code for different targets.
430 const ARMSubtarget *Subtarget;
432 const TargetRegisterInfo *RegInfo;
434 const InstrItineraryData *Itins;
436 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
438 unsigned ARMPCLabelIndex;
440 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
441 void addDRTypeForNEON(MVT VT);
442 void addQRTypeForNEON(MVT VT);
443 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
445 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
446 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
447 SDValue Chain, SDValue &Arg,
448 RegsToPassVector &RegsToPass,
449 CCValAssign &VA, CCValAssign &NextVA,
451 SmallVectorImpl<SDValue> &MemOpChains,
452 ISD::ArgFlagsTy Flags) const;
453 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
454 SDValue &Root, SelectionDAG &DAG,
457 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
458 bool isVarArg) const;
459 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
460 bool isVarArg) const;
461 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
462 SDLoc dl, SelectionDAG &DAG,
463 const CCValAssign &VA,
464 ISD::ArgFlagsTy Flags) const;
465 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
466 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
467 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
468 const ARMSubtarget *Subtarget) const;
469 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
470 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
471 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
472 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
473 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
474 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
475 SelectionDAG &DAG) const;
476 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
478 TLSModel::Model model) const;
479 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
480 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
483 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
484 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
485 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
486 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
487 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
488 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
489 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
490 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
491 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
492 const ARMSubtarget *ST) const;
493 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
494 const ARMSubtarget *ST) const;
495 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
496 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
497 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
498 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
499 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
500 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
501 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
503 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
505 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
506 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
507 /// expanded to FMAs when this method returns true, otherwise fmuladd is
508 /// expanded to fmul + fadd.
510 /// ARM supports both fused and unfused multiply-add operations; we already
511 /// lower a pair of fmul and fadd to the latter so it's not clear that there
512 /// would be a gain or that the gain would be worthwhile enough to risk
513 /// correctness bugs.
514 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
516 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
518 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
519 CallingConv::ID CallConv, bool isVarArg,
520 const SmallVectorImpl<ISD::InputArg> &Ins,
521 SDLoc dl, SelectionDAG &DAG,
522 SmallVectorImpl<SDValue> &InVals,
523 bool isThisReturn, SDValue ThisVal) const;
526 LowerFormalArguments(SDValue Chain,
527 CallingConv::ID CallConv, bool isVarArg,
528 const SmallVectorImpl<ISD::InputArg> &Ins,
529 SDLoc dl, SelectionDAG &DAG,
530 SmallVectorImpl<SDValue> &InVals) const override;
532 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
533 SDLoc dl, SDValue &Chain,
534 const Value *OrigArg,
535 unsigned InRegsParamRecordIdx,
537 unsigned ArgSize) const;
539 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
540 SDLoc dl, SDValue &Chain,
542 unsigned TotalArgRegsSaveSize,
543 bool ForceMutable = false) const;
546 LowerCall(TargetLowering::CallLoweringInfo &CLI,
547 SmallVectorImpl<SDValue> &InVals) const override;
549 /// HandleByVal - Target-specific cleanup for ByVal support.
550 void HandleByVal(CCState *, unsigned &, unsigned) const override;
552 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
553 /// for tail call optimization. Targets which want to do tail call
554 /// optimization should implement this function.
555 bool IsEligibleForTailCallOptimization(SDValue Callee,
556 CallingConv::ID CalleeCC,
558 bool isCalleeStructRet,
559 bool isCallerStructRet,
560 const SmallVectorImpl<ISD::OutputArg> &Outs,
561 const SmallVectorImpl<SDValue> &OutVals,
562 const SmallVectorImpl<ISD::InputArg> &Ins,
563 SelectionDAG& DAG) const;
565 bool CanLowerReturn(CallingConv::ID CallConv,
566 MachineFunction &MF, bool isVarArg,
567 const SmallVectorImpl<ISD::OutputArg> &Outs,
568 LLVMContext &Context) const override;
571 LowerReturn(SDValue Chain,
572 CallingConv::ID CallConv, bool isVarArg,
573 const SmallVectorImpl<ISD::OutputArg> &Outs,
574 const SmallVectorImpl<SDValue> &OutVals,
575 SDLoc dl, SelectionDAG &DAG) const override;
577 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
579 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
581 SDValue getCMOV(SDLoc dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
582 SDValue ARMcc, SDValue CCR, SDValue Cmp,
583 SelectionDAG &DAG) const;
584 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
585 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
586 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
587 SelectionDAG &DAG, SDLoc dl) const;
588 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
590 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
592 void SetupEntryBlockForSjLj(MachineInstr *MI,
593 MachineBasicBlock *MBB,
594 MachineBasicBlock *DispatchBB, int FI) const;
596 void EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const;
598 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
600 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
601 MachineBasicBlock *MBB) const;
603 MachineBasicBlock *EmitLowered__chkstk(MachineInstr *MI,
604 MachineBasicBlock *MBB) const;
607 enum NEONModImmType {
614 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
615 const TargetLibraryInfo *libInfo);
619 #endif // ARMISELLOWERING_H