1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
23 class ARMConstantPoolValue;
27 // ARM Specific DAG Nodes
29 // Start the numbering where the builting ops and target ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
32 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
33 // TargetExternalSymbol, and TargetGlobalAddress.
34 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
36 CALL, // Function call.
37 CALL_NOLINK, // Function call with branch not branch-and-link.
38 tCALL, // Thumb function call.
39 BRCOND, // Conditional branch.
40 BR_JT, // Jumptable branch.
41 RET_FLAG, // Return with a flag operand.
43 PIC_ADD, // Add with a PC operand and a PIC label.
45 CMP, // ARM compare instructions.
46 CMPNZ, // ARM compare that uses only N or Z flags.
47 CMPFP, // ARM VFP compare instruction, sets FPSCR.
48 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
49 FMSTAT, // ARM fmstat instruction.
50 CMOV, // ARM conditional move instructions.
51 CNEG, // ARM conditional negate instructions.
53 FTOSI, // FP to sint within a FP register.
54 FTOUI, // FP to uint within a FP register.
55 SITOF, // sint to FP within a FP register.
56 UITOF, // uint to FP within a FP register.
58 MULHILOU, // Lo,Hi = umul LHS, RHS.
59 MULHILOS, // Lo,Hi = smul LHS, RHS.
61 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
62 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
63 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
65 FMRRD, // double to two gprs.
66 FMDRR // Two gprs to double.
70 //===----------------------------------------------------------------------===//
71 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
73 class ARMTargetLowering : public TargetLowering {
74 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
76 ARMTargetLowering(TargetMachine &TM);
78 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
79 virtual const char *getTargetNodeName(unsigned Opcode) const;
81 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
82 MachineBasicBlock *MBB);
84 /// isLegalAddressingMode - Return true if the addressing mode represented
85 /// by AM is legal for this target, for a load/store of the specified type.
86 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
88 /// isLegalAddressImmediate - Return true if the integer value can be used
89 /// as the offset of the target addressing mode for load / store of the
91 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
93 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
94 /// the offset of the target addressing mode.
95 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
97 /// isLegalAddressScale - Return true if the integer value can be used as
98 /// the scale of the target addressing mode for load / store of the given
100 virtual bool isLegalAddressScale(int64_t S, const Type *Ty) const;
102 /// getPreIndexedAddressParts - returns true by value, base pointer and
103 /// offset pointer and addressing mode by reference if the node's address
104 /// can be legally represented as pre-indexed load / store address.
105 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
107 ISD::MemIndexedMode &AM,
110 /// getPostIndexedAddressParts - returns true by value, base pointer and
111 /// offset pointer and addressing mode by reference if this node can be
112 /// combined with a load / store to form a post-indexed load / store.
113 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
114 SDOperand &Base, SDOperand &Offset,
115 ISD::MemIndexedMode &AM,
118 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
122 unsigned Depth) const;
123 ConstraintType getConstraintType(const std::string &Constraint) const;
124 std::pair<unsigned, const TargetRegisterClass*>
125 getRegForInlineAsmConstraint(const std::string &Constraint,
126 MVT::ValueType VT) const;
127 std::vector<unsigned>
128 getRegClassForInlineAsmConstraint(const std::string &Constraint,
129 MVT::ValueType VT) const;
131 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
132 /// make the right decision when generating code for different targets.
133 const ARMSubtarget *Subtarget;
135 /// ARMPCLabelIndex - Keep track the number of ARM PC labels created.
137 unsigned ARMPCLabelIndex;
139 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
140 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
141 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
142 SDOperand LowerBR_JT(SDOperand Op, SelectionDAG &DAG);
146 #endif // ARMISELLOWERING_H