1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
19 #include "ARMSubtarget.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
28 class ARMConstantPoolValue;
31 // ARM Specific DAG Nodes
33 // Start the numbering where the builtin ops and target ops leave off.
34 FIRST_NUMBER = ISD::BUILTIN_OP_END,
36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
37 // TargetExternalSymbol, and TargetGlobalAddress.
38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
44 // Add pseudo op to model memcpy for struct byval.
47 CALL, // Function call.
48 CALL_PRED, // Function call that's predicable.
49 CALL_NOLINK, // Function call with branch not branch-and-link.
50 tCALL, // Thumb function call.
51 BRCOND, // Conditional branch.
52 BR_JT, // Jumptable branch.
53 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
54 RET_FLAG, // Return with a flag operand.
56 PIC_ADD, // Add with a PC operand and a PIC label.
58 CMP, // ARM compare instructions.
59 CMN, // ARM CMN instructions.
60 CMPZ, // ARM compare that sets only Z flag.
61 CMPFP, // ARM VFP compare instruction, sets FPSCR.
62 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
63 FMSTAT, // ARM fmstat instruction.
65 CMOV, // ARM conditional move instructions.
66 CAND, // ARM conditional and instructions.
67 COR, // ARM conditional or instructions.
68 CXOR, // ARM conditional xor instructions.
72 RBIT, // ARM bitreverse instruction
74 FTOSI, // FP to sint within a FP register.
75 FTOUI, // FP to uint within a FP register.
76 SITOF, // sint to FP within a FP register.
77 UITOF, // uint to FP within a FP register.
79 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
80 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
81 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
83 ADDC, // Add with carry
84 ADDE, // Add using carry
85 SUBC, // Sub with carry
86 SUBE, // Sub using carry
88 VMOVRRD, // double to two gprs.
89 VMOVDRR, // Two gprs to double.
91 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
92 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
94 TC_RETURN, // Tail call return pseudo.
98 DYN_ALLOC, // Dynamic allocation on the stack.
100 MEMBARRIER, // Memory barrier (DMB)
101 MEMBARRIER_MCR, // Memory barrier (MCR)
105 VCEQ, // Vector compare equal.
106 VCEQZ, // Vector compare equal to zero.
107 VCGE, // Vector compare greater than or equal.
108 VCGEZ, // Vector compare greater than or equal to zero.
109 VCLEZ, // Vector compare less than or equal to zero.
110 VCGEU, // Vector compare unsigned greater than or equal.
111 VCGT, // Vector compare greater than.
112 VCGTZ, // Vector compare greater than zero.
113 VCLTZ, // Vector compare less than zero.
114 VCGTU, // Vector compare unsigned greater than.
115 VTST, // Vector test bits.
117 // Vector shift by immediate:
119 VSHRs, // ...right (signed)
120 VSHRu, // ...right (unsigned)
121 VSHLLs, // ...left long (signed)
122 VSHLLu, // ...left long (unsigned)
123 VSHLLi, // ...left long (with maximum shift count)
124 VSHRN, // ...right narrow
126 // Vector rounding shift by immediate:
127 VRSHRs, // ...right (signed)
128 VRSHRu, // ...right (unsigned)
129 VRSHRN, // ...right narrow
131 // Vector saturating shift by immediate:
132 VQSHLs, // ...left (signed)
133 VQSHLu, // ...left (unsigned)
134 VQSHLsu, // ...left (signed to unsigned)
135 VQSHRNs, // ...right narrow (signed)
136 VQSHRNu, // ...right narrow (unsigned)
137 VQSHRNsu, // ...right narrow (signed to unsigned)
139 // Vector saturating rounding shift by immediate:
140 VQRSHRNs, // ...right narrow (signed)
141 VQRSHRNu, // ...right narrow (unsigned)
142 VQRSHRNsu, // ...right narrow (signed to unsigned)
144 // Vector shift and insert:
148 // Vector get lane (VMOV scalar to ARM core register)
149 // (These are used for 8- and 16-bit element types only.)
150 VGETLANEu, // zero-extend vector extract element
151 VGETLANEs, // sign-extend vector extract element
153 // Vector move immediate and move negated immediate:
157 // Vector move f32 immediate:
166 VREV64, // reverse elements within 64-bit doublewords
167 VREV32, // reverse elements within 32-bit words
168 VREV16, // reverse elements within 16-bit halfwords
169 VZIP, // zip (interleave)
170 VUZP, // unzip (deinterleave)
172 VTBL1, // 1-register shuffle with mask
173 VTBL2, // 2-register shuffle with mask
175 // Vector multiply long:
177 VMULLu, // ...unsigned
179 // Operands of the standard BUILD_VECTOR node are not legalized, which
180 // is fine if BUILD_VECTORs are always lowered to shuffles or other
181 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
182 // operands need to be legalized. Define an ARM-specific version of
183 // BUILD_VECTOR for this purpose.
186 // Floating-point max and min:
193 // Vector OR with immediate
195 // Vector AND with NOT of immediate
198 // Vector bitwise select
201 // Vector load N-element structure to all lanes:
202 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
206 // NEON loads with post-increment base updates:
218 // NEON stores with post-increment base updates:
227 // 64-bit atomic ops (value split into two registers)
239 /// Define some predicates that are used for node matching.
241 bool isBitFieldInvertedMask(unsigned v);
244 //===--------------------------------------------------------------------===//
245 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
247 class ARMTargetLowering : public TargetLowering {
249 explicit ARMTargetLowering(TargetMachine &TM);
251 virtual unsigned getJumpTableEncoding(void) const;
253 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
255 /// ReplaceNodeResults - Replace the results of node with an illegal result
256 /// type with new values built out of custom code.
258 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
259 SelectionDAG &DAG) const;
261 virtual const char *getTargetNodeName(unsigned Opcode) const;
263 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
264 virtual EVT getSetCCResultType(EVT VT) const;
266 virtual MachineBasicBlock *
267 EmitInstrWithCustomInserter(MachineInstr *MI,
268 MachineBasicBlock *MBB) const;
271 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
273 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
274 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
276 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
278 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
279 /// unaligned memory accesses. of the specified type.
280 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
282 virtual EVT getOptimalMemOpType(uint64_t Size,
283 unsigned DstAlign, unsigned SrcAlign,
286 MachineFunction &MF) const;
288 /// isLegalAddressingMode - Return true if the addressing mode represented
289 /// by AM is legal for this target, for a load/store of the specified type.
290 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
291 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
293 /// isLegalICmpImmediate - Return true if the specified immediate is legal
294 /// icmp immediate, that is the target has icmp instructions which can
295 /// compare a register against the immediate without having to materialize
296 /// the immediate into a register.
297 virtual bool isLegalICmpImmediate(int64_t Imm) const;
299 /// isLegalAddImmediate - Return true if the specified immediate is legal
300 /// add immediate, that is the target has add instructions which can
301 /// add a register and the immediate without having to materialize
302 /// the immediate into a register.
303 virtual bool isLegalAddImmediate(int64_t Imm) const;
305 /// getPreIndexedAddressParts - returns true by value, base pointer and
306 /// offset pointer and addressing mode by reference if the node's address
307 /// can be legally represented as pre-indexed load / store address.
308 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
310 ISD::MemIndexedMode &AM,
311 SelectionDAG &DAG) const;
313 /// getPostIndexedAddressParts - returns true by value, base pointer and
314 /// offset pointer and addressing mode by reference if this node can be
315 /// combined with a load / store to form a post-indexed load / store.
316 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
317 SDValue &Base, SDValue &Offset,
318 ISD::MemIndexedMode &AM,
319 SelectionDAG &DAG) const;
321 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
324 const SelectionDAG &DAG,
325 unsigned Depth) const;
328 virtual bool ExpandInlineAsm(CallInst *CI) const;
330 ConstraintType getConstraintType(const std::string &Constraint) const;
332 /// Examine constraint string and operand type and determine a weight value.
333 /// The operand object must already have been set up with the operand type.
334 ConstraintWeight getSingleConstraintMatchWeight(
335 AsmOperandInfo &info, const char *constraint) const;
337 std::pair<unsigned, const TargetRegisterClass*>
338 getRegForInlineAsmConstraint(const std::string &Constraint,
341 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
342 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
343 /// true it means one of the asm constraint of the inline asm instruction
344 /// being processed is 'm'.
345 virtual void LowerAsmOperandForConstraint(SDValue Op,
346 std::string &Constraint,
347 std::vector<SDValue> &Ops,
348 SelectionDAG &DAG) const;
350 const ARMSubtarget* getSubtarget() const {
354 /// getRegClassFor - Return the register class that should be used for the
355 /// specified value type.
356 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
358 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
359 /// be used for loads / stores from the global.
360 virtual unsigned getMaximalGlobalOffset() const;
362 /// createFastISel - This method returns a target specific FastISel object,
363 /// or null if the target does not support "fast" ISel.
364 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
366 Sched::Preference getSchedulingPreference(SDNode *N) const;
368 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
369 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
371 /// isFPImmLegal - Returns true if the target can instruction select the
372 /// specified FP immediate natively. If false, the legalizer will
373 /// materialize the FP immediate as a load from a constant pool.
374 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
376 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
378 unsigned Intrinsic) const;
380 std::pair<const TargetRegisterClass*, uint8_t>
381 findRepresentativeClass(EVT VT) const;
384 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
385 /// make the right decision when generating code for different targets.
386 const ARMSubtarget *Subtarget;
388 const TargetRegisterInfo *RegInfo;
390 const InstrItineraryData *Itins;
392 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
394 unsigned ARMPCLabelIndex;
396 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
397 void addDRTypeForNEON(EVT VT);
398 void addQRTypeForNEON(EVT VT);
400 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
401 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
402 SDValue Chain, SDValue &Arg,
403 RegsToPassVector &RegsToPass,
404 CCValAssign &VA, CCValAssign &NextVA,
406 SmallVector<SDValue, 8> &MemOpChains,
407 ISD::ArgFlagsTy Flags) const;
408 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
409 SDValue &Root, SelectionDAG &DAG,
412 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
413 bool isVarArg) const;
414 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
415 DebugLoc dl, SelectionDAG &DAG,
416 const CCValAssign &VA,
417 ISD::ArgFlagsTy Flags) const;
418 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
419 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
420 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
421 const ARMSubtarget *Subtarget) const;
422 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
423 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
424 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
425 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
426 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
427 SelectionDAG &DAG) const;
428 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
430 TLSModel::Model model) const;
431 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
432 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
433 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
434 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
435 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
436 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
437 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
439 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
440 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
441 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
442 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
443 const ARMSubtarget *ST) const;
444 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
445 const ARMSubtarget *ST) const;
447 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
449 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
450 CallingConv::ID CallConv, bool isVarArg,
451 const SmallVectorImpl<ISD::InputArg> &Ins,
452 DebugLoc dl, SelectionDAG &DAG,
453 SmallVectorImpl<SDValue> &InVals) const;
456 LowerFormalArguments(SDValue Chain,
457 CallingConv::ID CallConv, bool isVarArg,
458 const SmallVectorImpl<ISD::InputArg> &Ins,
459 DebugLoc dl, SelectionDAG &DAG,
460 SmallVectorImpl<SDValue> &InVals) const;
462 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
463 DebugLoc dl, SDValue &Chain, unsigned ArgOffset)
466 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
467 unsigned &VARegSize, unsigned &VARegSaveSize) const;
470 LowerCall(TargetLowering::CallLoweringInfo &CLI,
471 SmallVectorImpl<SDValue> &InVals) const;
473 /// HandleByVal - Target-specific cleanup for ByVal support.
474 virtual void HandleByVal(CCState *, unsigned &) const;
476 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
477 /// for tail call optimization. Targets which want to do tail call
478 /// optimization should implement this function.
479 bool IsEligibleForTailCallOptimization(SDValue Callee,
480 CallingConv::ID CalleeCC,
482 bool isCalleeStructRet,
483 bool isCallerStructRet,
484 const SmallVectorImpl<ISD::OutputArg> &Outs,
485 const SmallVectorImpl<SDValue> &OutVals,
486 const SmallVectorImpl<ISD::InputArg> &Ins,
487 SelectionDAG& DAG) const;
489 LowerReturn(SDValue Chain,
490 CallingConv::ID CallConv, bool isVarArg,
491 const SmallVectorImpl<ISD::OutputArg> &Outs,
492 const SmallVectorImpl<SDValue> &OutVals,
493 DebugLoc dl, SelectionDAG &DAG) const;
495 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
497 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
499 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
500 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
501 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
502 SelectionDAG &DAG, DebugLoc dl) const;
503 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
505 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
507 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
508 MachineBasicBlock *BB,
509 unsigned Size) const;
510 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
511 MachineBasicBlock *BB,
513 unsigned BinOpcode) const;
514 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
515 MachineBasicBlock *BB,
518 bool NeedsCarry = false,
519 bool IsCmpxchg = false) const;
520 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
521 MachineBasicBlock *BB,
524 ARMCC::CondCodes Cond) const;
526 void SetupEntryBlockForSjLj(MachineInstr *MI,
527 MachineBasicBlock *MBB,
528 MachineBasicBlock *DispatchBB, int FI) const;
530 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
531 MachineBasicBlock *MBB) const;
533 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
535 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
536 MachineBasicBlock *MBB) const;
539 enum NEONModImmType {
547 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
551 #endif // ARMISELLOWERING_H