1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
23 class ARMConstantPoolValue;
27 // ARM Specific DAG Nodes
29 // Start the numbering where the builting ops and target ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
32 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
33 // TargetExternalSymbol, and TargetGlobalAddress.
34 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
36 CALL, // Function call.
37 CALL_NOLINK, // Function call with branch not branch-and-link.
38 tCALL, // Thumb function call.
39 BRCOND, // Conditional branch.
40 BR_JT, // Jumptable branch.
41 RET_FLAG, // Return with a flag operand.
43 PIC_ADD, // Add with a PC operand and a PIC label.
45 CMP, // ARM compare instructions.
46 CMPNZ, // ARM compare that uses only N or Z flags.
47 CMPFP, // ARM VFP compare instruction, sets FPSCR.
48 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
49 FMSTAT, // ARM fmstat instruction.
50 CMOV, // ARM conditional move instructions.
51 CNEG, // ARM conditional negate instructions.
53 FTOSI, // FP to sint within a FP register.
54 FTOUI, // FP to uint within a FP register.
55 SITOF, // sint to FP within a FP register.
56 UITOF, // uint to FP within a FP register.
58 MULHILOU, // Lo,Hi = umul LHS, RHS.
59 MULHILOS, // Lo,Hi = smul LHS, RHS.
61 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
62 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
63 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
65 FMRRD, // double to two gprs.
66 FMDRR, // Two gprs to double.
72 //===----------------------------------------------------------------------===//
73 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
75 class ARMTargetLowering : public TargetLowering {
76 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
78 ARMTargetLowering(TargetMachine &TM);
80 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
81 virtual const char *getTargetNodeName(unsigned Opcode) const;
83 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
84 MachineBasicBlock *MBB);
86 /// isLegalAddressingMode - Return true if the addressing mode represented
87 /// by AM is legal for this target, for a load/store of the specified type.
88 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
90 /// getPreIndexedAddressParts - returns true by value, base pointer and
91 /// offset pointer and addressing mode by reference if the node's address
92 /// can be legally represented as pre-indexed load / store address.
93 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
95 ISD::MemIndexedMode &AM,
98 /// getPostIndexedAddressParts - returns true by value, base pointer and
99 /// offset pointer and addressing mode by reference if this node can be
100 /// combined with a load / store to form a post-indexed load / store.
101 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
102 SDOperand &Base, SDOperand &Offset,
103 ISD::MemIndexedMode &AM,
106 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
110 unsigned Depth) const;
111 ConstraintType getConstraintType(const std::string &Constraint) const;
112 std::pair<unsigned, const TargetRegisterClass*>
113 getRegForInlineAsmConstraint(const std::string &Constraint,
114 MVT::ValueType VT) const;
115 std::vector<unsigned>
116 getRegClassForInlineAsmConstraint(const std::string &Constraint,
117 MVT::ValueType VT) const;
119 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
120 /// make the right decision when generating code for different targets.
121 const ARMSubtarget *Subtarget;
123 /// ARMPCLabelIndex - Keep track the number of ARM PC labels created.
125 unsigned ARMPCLabelIndex;
127 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
128 SDOperand LowerGlobalAddressDarwin(SDOperand Op, SelectionDAG &DAG);
129 SDOperand LowerGlobalAddressELF(SDOperand Op, SelectionDAG &DAG);
130 SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
131 SDOperand LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
133 SDOperand LowerToTLSExecModels(GlobalAddressSDNode *GA,
135 SDOperand LowerGLOBAL_OFFSET_TABLE(SDOperand Op, SelectionDAG &DAG);
136 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
137 SDOperand LowerBR_JT(SDOperand Op, SelectionDAG &DAG);
141 #endif // ARMISELLOWERING_H