1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
19 #include "ARMSubtarget.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
28 class ARMConstantPoolValue;
31 // ARM Specific DAG Nodes
33 // Start the numbering where the builtin ops and target ops leave off.
34 FIRST_NUMBER = ISD::BUILTIN_OP_END,
36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
37 // TargetExternalSymbol, and TargetGlobalAddress.
38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
44 // Add pseudo op to model memcpy for struct byval.
47 CALL, // Function call.
48 CALL_PRED, // Function call that's predicable.
49 CALL_NOLINK, // Function call with branch not branch-and-link.
50 tCALL, // Thumb function call.
51 BRCOND, // Conditional branch.
52 BR_JT, // Jumptable branch.
53 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
54 RET_FLAG, // Return with a flag operand.
56 PIC_ADD, // Add with a PC operand and a PIC label.
58 CMP, // ARM compare instructions.
59 CMPZ, // ARM compare that sets only Z flag.
60 CMPFP, // ARM VFP compare instruction, sets FPSCR.
61 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
62 FMSTAT, // ARM fmstat instruction.
64 CMOV, // ARM conditional move instructions.
65 CAND, // ARM conditional and instructions.
66 COR, // ARM conditional or instructions.
67 CXOR, // ARM conditional xor instructions.
71 RBIT, // ARM bitreverse instruction
73 FTOSI, // FP to sint within a FP register.
74 FTOUI, // FP to uint within a FP register.
75 SITOF, // sint to FP within a FP register.
76 UITOF, // uint to FP within a FP register.
78 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
79 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
80 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
82 ADDC, // Add with carry
83 ADDE, // Add using carry
84 SUBC, // Sub with carry
85 SUBE, // Sub using carry
87 VMOVRRD, // double to two gprs.
88 VMOVDRR, // Two gprs to double.
90 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
91 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
93 TC_RETURN, // Tail call return pseudo.
97 DYN_ALLOC, // Dynamic allocation on the stack.
99 MEMBARRIER, // Memory barrier (DMB)
100 MEMBARRIER_MCR, // Memory barrier (MCR)
104 VCEQ, // Vector compare equal.
105 VCEQZ, // Vector compare equal to zero.
106 VCGE, // Vector compare greater than or equal.
107 VCGEZ, // Vector compare greater than or equal to zero.
108 VCLEZ, // Vector compare less than or equal to zero.
109 VCGEU, // Vector compare unsigned greater than or equal.
110 VCGT, // Vector compare greater than.
111 VCGTZ, // Vector compare greater than zero.
112 VCLTZ, // Vector compare less than zero.
113 VCGTU, // Vector compare unsigned greater than.
114 VTST, // Vector test bits.
116 // Vector shift by immediate:
118 VSHRs, // ...right (signed)
119 VSHRu, // ...right (unsigned)
120 VSHLLs, // ...left long (signed)
121 VSHLLu, // ...left long (unsigned)
122 VSHLLi, // ...left long (with maximum shift count)
123 VSHRN, // ...right narrow
125 // Vector rounding shift by immediate:
126 VRSHRs, // ...right (signed)
127 VRSHRu, // ...right (unsigned)
128 VRSHRN, // ...right narrow
130 // Vector saturating shift by immediate:
131 VQSHLs, // ...left (signed)
132 VQSHLu, // ...left (unsigned)
133 VQSHLsu, // ...left (signed to unsigned)
134 VQSHRNs, // ...right narrow (signed)
135 VQSHRNu, // ...right narrow (unsigned)
136 VQSHRNsu, // ...right narrow (signed to unsigned)
138 // Vector saturating rounding shift by immediate:
139 VQRSHRNs, // ...right narrow (signed)
140 VQRSHRNu, // ...right narrow (unsigned)
141 VQRSHRNsu, // ...right narrow (signed to unsigned)
143 // Vector shift and insert:
147 // Vector get lane (VMOV scalar to ARM core register)
148 // (These are used for 8- and 16-bit element types only.)
149 VGETLANEu, // zero-extend vector extract element
150 VGETLANEs, // sign-extend vector extract element
152 // Vector move immediate and move negated immediate:
156 // Vector move f32 immediate:
165 VREV64, // reverse elements within 64-bit doublewords
166 VREV32, // reverse elements within 32-bit words
167 VREV16, // reverse elements within 16-bit halfwords
168 VZIP, // zip (interleave)
169 VUZP, // unzip (deinterleave)
171 VTBL1, // 1-register shuffle with mask
172 VTBL2, // 2-register shuffle with mask
174 // Vector multiply long:
176 VMULLu, // ...unsigned
178 // Operands of the standard BUILD_VECTOR node are not legalized, which
179 // is fine if BUILD_VECTORs are always lowered to shuffles or other
180 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
181 // operands need to be legalized. Define an ARM-specific version of
182 // BUILD_VECTOR for this purpose.
185 // Floating-point max and min:
192 // Vector OR with immediate
194 // Vector AND with NOT of immediate
197 // Vector bitwise select
200 // Vector load N-element structure to all lanes:
201 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
205 // NEON loads with post-increment base updates:
217 // NEON stores with post-increment base updates:
226 // 64-bit atomic ops (value split into two registers)
238 /// Define some predicates that are used for node matching.
240 bool isBitFieldInvertedMask(unsigned v);
243 //===--------------------------------------------------------------------===//
244 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
246 class ARMTargetLowering : public TargetLowering {
248 explicit ARMTargetLowering(TargetMachine &TM);
250 virtual unsigned getJumpTableEncoding(void) const;
252 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
254 /// ReplaceNodeResults - Replace the results of node with an illegal result
255 /// type with new values built out of custom code.
257 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
258 SelectionDAG &DAG) const;
260 virtual const char *getTargetNodeName(unsigned Opcode) const;
262 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
263 virtual EVT getSetCCResultType(EVT VT) const;
265 virtual MachineBasicBlock *
266 EmitInstrWithCustomInserter(MachineInstr *MI,
267 MachineBasicBlock *MBB) const;
270 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
272 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
273 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
275 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
277 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
278 /// unaligned memory accesses. of the specified type.
279 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
281 virtual EVT getOptimalMemOpType(uint64_t Size,
282 unsigned DstAlign, unsigned SrcAlign,
285 MachineFunction &MF) const;
287 /// isLegalAddressingMode - Return true if the addressing mode represented
288 /// by AM is legal for this target, for a load/store of the specified type.
289 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
290 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
292 /// isLegalICmpImmediate - Return true if the specified immediate is legal
293 /// icmp immediate, that is the target has icmp instructions which can
294 /// compare a register against the immediate without having to materialize
295 /// the immediate into a register.
296 virtual bool isLegalICmpImmediate(int64_t Imm) const;
298 /// isLegalAddImmediate - Return true if the specified immediate is legal
299 /// add immediate, that is the target has add instructions which can
300 /// add a register and the immediate without having to materialize
301 /// the immediate into a register.
302 virtual bool isLegalAddImmediate(int64_t Imm) const;
304 /// getPreIndexedAddressParts - returns true by value, base pointer and
305 /// offset pointer and addressing mode by reference if the node's address
306 /// can be legally represented as pre-indexed load / store address.
307 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
309 ISD::MemIndexedMode &AM,
310 SelectionDAG &DAG) const;
312 /// getPostIndexedAddressParts - returns true by value, base pointer and
313 /// offset pointer and addressing mode by reference if this node can be
314 /// combined with a load / store to form a post-indexed load / store.
315 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
316 SDValue &Base, SDValue &Offset,
317 ISD::MemIndexedMode &AM,
318 SelectionDAG &DAG) const;
320 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
323 const SelectionDAG &DAG,
324 unsigned Depth) const;
327 virtual bool ExpandInlineAsm(CallInst *CI) const;
329 ConstraintType getConstraintType(const std::string &Constraint) const;
331 /// Examine constraint string and operand type and determine a weight value.
332 /// The operand object must already have been set up with the operand type.
333 ConstraintWeight getSingleConstraintMatchWeight(
334 AsmOperandInfo &info, const char *constraint) const;
336 std::pair<unsigned, const TargetRegisterClass*>
337 getRegForInlineAsmConstraint(const std::string &Constraint,
340 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
341 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
342 /// true it means one of the asm constraint of the inline asm instruction
343 /// being processed is 'm'.
344 virtual void LowerAsmOperandForConstraint(SDValue Op,
345 std::string &Constraint,
346 std::vector<SDValue> &Ops,
347 SelectionDAG &DAG) const;
349 const ARMSubtarget* getSubtarget() const {
353 /// getRegClassFor - Return the register class that should be used for the
354 /// specified value type.
355 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
357 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
358 /// be used for loads / stores from the global.
359 virtual unsigned getMaximalGlobalOffset() const;
361 /// createFastISel - This method returns a target specific FastISel object,
362 /// or null if the target does not support "fast" ISel.
363 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
365 Sched::Preference getSchedulingPreference(SDNode *N) const;
367 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
368 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
370 /// isFPImmLegal - Returns true if the target can instruction select the
371 /// specified FP immediate natively. If false, the legalizer will
372 /// materialize the FP immediate as a load from a constant pool.
373 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
375 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
377 unsigned Intrinsic) const;
379 std::pair<const TargetRegisterClass*, uint8_t>
380 findRepresentativeClass(EVT VT) const;
383 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
384 /// make the right decision when generating code for different targets.
385 const ARMSubtarget *Subtarget;
387 const TargetRegisterInfo *RegInfo;
389 const InstrItineraryData *Itins;
391 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
393 unsigned ARMPCLabelIndex;
395 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
396 void addDRTypeForNEON(EVT VT);
397 void addQRTypeForNEON(EVT VT);
399 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
400 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
401 SDValue Chain, SDValue &Arg,
402 RegsToPassVector &RegsToPass,
403 CCValAssign &VA, CCValAssign &NextVA,
405 SmallVector<SDValue, 8> &MemOpChains,
406 ISD::ArgFlagsTy Flags) const;
407 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
408 SDValue &Root, SelectionDAG &DAG,
411 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
412 bool isVarArg) const;
413 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
414 DebugLoc dl, SelectionDAG &DAG,
415 const CCValAssign &VA,
416 ISD::ArgFlagsTy Flags) const;
417 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
418 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
419 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
420 const ARMSubtarget *Subtarget) const;
421 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
422 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
423 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
424 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
425 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
426 SelectionDAG &DAG) const;
427 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
429 TLSModel::Model model) const;
430 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
431 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
432 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
433 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
434 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
435 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
436 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
437 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
439 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
440 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
441 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
442 const ARMSubtarget *ST) const;
443 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
444 const ARMSubtarget *ST) const;
446 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
448 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
449 CallingConv::ID CallConv, bool isVarArg,
450 const SmallVectorImpl<ISD::InputArg> &Ins,
451 DebugLoc dl, SelectionDAG &DAG,
452 SmallVectorImpl<SDValue> &InVals) const;
455 LowerFormalArguments(SDValue Chain,
456 CallingConv::ID CallConv, bool isVarArg,
457 const SmallVectorImpl<ISD::InputArg> &Ins,
458 DebugLoc dl, SelectionDAG &DAG,
459 SmallVectorImpl<SDValue> &InVals) const;
461 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
462 DebugLoc dl, SDValue &Chain, unsigned ArgOffset)
465 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
466 unsigned &VARegSize, unsigned &VARegSaveSize) const;
469 LowerCall(TargetLowering::CallLoweringInfo &CLI,
470 SmallVectorImpl<SDValue> &InVals) const;
472 /// HandleByVal - Target-specific cleanup for ByVal support.
473 virtual void HandleByVal(CCState *, unsigned &) const;
475 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
476 /// for tail call optimization. Targets which want to do tail call
477 /// optimization should implement this function.
478 bool IsEligibleForTailCallOptimization(SDValue Callee,
479 CallingConv::ID CalleeCC,
481 bool isCalleeStructRet,
482 bool isCallerStructRet,
483 const SmallVectorImpl<ISD::OutputArg> &Outs,
484 const SmallVectorImpl<SDValue> &OutVals,
485 const SmallVectorImpl<ISD::InputArg> &Ins,
486 SelectionDAG& DAG) const;
488 LowerReturn(SDValue Chain,
489 CallingConv::ID CallConv, bool isVarArg,
490 const SmallVectorImpl<ISD::OutputArg> &Outs,
491 const SmallVectorImpl<SDValue> &OutVals,
492 DebugLoc dl, SelectionDAG &DAG) const;
494 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
496 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
498 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
499 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
500 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
501 SelectionDAG &DAG, DebugLoc dl) const;
502 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
504 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
506 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
507 MachineBasicBlock *BB,
508 unsigned Size) const;
509 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
510 MachineBasicBlock *BB,
512 unsigned BinOpcode) const;
513 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
514 MachineBasicBlock *BB,
517 bool NeedsCarry = false,
518 bool IsCmpxchg = false) const;
519 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
520 MachineBasicBlock *BB,
523 ARMCC::CondCodes Cond) const;
525 void SetupEntryBlockForSjLj(MachineInstr *MI,
526 MachineBasicBlock *MBB,
527 MachineBasicBlock *DispatchBB, int FI) const;
529 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
530 MachineBasicBlock *MBB) const;
532 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
534 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
535 MachineBasicBlock *MBB) const;
538 enum NEONModImmType {
546 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
550 #endif // ARMISELLOWERING_H