1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
25 class ARMConstantPoolValue;
29 // ARM Specific DAG Nodes
30 enum NodeType : unsigned {
31 // Start the numbering where the builtin ops and target ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
40 // Add pseudo op to model memcpy for struct byval.
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
51 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
53 PIC_ADD, // Add with a PC operand and a PIC label.
55 CMP, // ARM compare instructions.
56 CMN, // ARM CMN instructions.
57 CMPZ, // ARM compare that sets only Z flag.
58 CMPFP, // ARM VFP compare instruction, sets FPSCR.
59 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
60 FMSTAT, // ARM fmstat instruction.
62 CMOV, // ARM conditional move instructions.
66 RBIT, // ARM bitreverse instruction
68 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
69 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
70 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
72 ADDC, // Add with carry
73 ADDE, // Add using carry
74 SUBC, // Sub with carry
75 SUBE, // Sub using carry
77 VMOVRRD, // double to two gprs.
78 VMOVDRR, // Two gprs to double.
80 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
81 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
82 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
84 TC_RETURN, // Tail call return pseudo.
88 DYN_ALLOC, // Dynamic allocation on the stack.
90 MEMBARRIER_MCR, // Memory barrier (MCR)
94 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
96 VCEQ, // Vector compare equal.
97 VCEQZ, // Vector compare equal to zero.
98 VCGE, // Vector compare greater than or equal.
99 VCGEZ, // Vector compare greater than or equal to zero.
100 VCLEZ, // Vector compare less than or equal to zero.
101 VCGEU, // Vector compare unsigned greater than or equal.
102 VCGT, // Vector compare greater than.
103 VCGTZ, // Vector compare greater than zero.
104 VCLTZ, // Vector compare less than zero.
105 VCGTU, // Vector compare unsigned greater than.
106 VTST, // Vector test bits.
108 // Vector shift by immediate:
110 VSHRs, // ...right (signed)
111 VSHRu, // ...right (unsigned)
113 // Vector rounding shift by immediate:
114 VRSHRs, // ...right (signed)
115 VRSHRu, // ...right (unsigned)
116 VRSHRN, // ...right narrow
118 // Vector saturating shift by immediate:
119 VQSHLs, // ...left (signed)
120 VQSHLu, // ...left (unsigned)
121 VQSHLsu, // ...left (signed to unsigned)
122 VQSHRNs, // ...right narrow (signed)
123 VQSHRNu, // ...right narrow (unsigned)
124 VQSHRNsu, // ...right narrow (signed to unsigned)
126 // Vector saturating rounding shift by immediate:
127 VQRSHRNs, // ...right narrow (signed)
128 VQRSHRNu, // ...right narrow (unsigned)
129 VQRSHRNsu, // ...right narrow (signed to unsigned)
131 // Vector shift and insert:
135 // Vector get lane (VMOV scalar to ARM core register)
136 // (These are used for 8- and 16-bit element types only.)
137 VGETLANEu, // zero-extend vector extract element
138 VGETLANEs, // sign-extend vector extract element
140 // Vector move immediate and move negated immediate:
144 // Vector move f32 immediate:
153 VREV64, // reverse elements within 64-bit doublewords
154 VREV32, // reverse elements within 32-bit words
155 VREV16, // reverse elements within 16-bit halfwords
156 VZIP, // zip (interleave)
157 VUZP, // unzip (deinterleave)
159 VTBL1, // 1-register shuffle with mask
160 VTBL2, // 2-register shuffle with mask
162 // Vector multiply long:
164 VMULLu, // ...unsigned
166 UMLAL, // 64bit Unsigned Accumulate Multiply
167 SMLAL, // 64bit Signed Accumulate Multiply
169 // Operands of the standard BUILD_VECTOR node are not legalized, which
170 // is fine if BUILD_VECTORs are always lowered to shuffles or other
171 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
172 // operands need to be legalized. Define an ARM-specific version of
173 // BUILD_VECTOR for this purpose.
179 // Vector OR with immediate
181 // Vector AND with NOT of immediate
184 // Vector bitwise select
187 // Vector load N-element structure to all lanes:
188 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
192 // NEON loads with post-increment base updates:
204 // NEON stores with post-increment base updates:
215 /// Define some predicates that are used for node matching.
217 bool isBitFieldInvertedMask(unsigned v);
220 //===--------------------------------------------------------------------===//
221 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
223 class ARMTargetLowering : public TargetLowering {
225 explicit ARMTargetLowering(const TargetMachine &TM,
226 const ARMSubtarget &STI);
228 unsigned getJumpTableEncoding() const override;
229 bool useSoftFloat() const override;
231 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
233 /// ReplaceNodeResults - Replace the results of node with an illegal result
234 /// type with new values built out of custom code.
236 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
237 SelectionDAG &DAG) const override;
239 const char *getTargetNodeName(unsigned Opcode) const override;
241 bool isSelectSupported(SelectSupportKind Kind) const override {
242 // ARM does not support scalar condition selects on vectors.
243 return (Kind != ScalarCondVectorVal);
246 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
247 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
248 EVT VT) const override;
251 EmitInstrWithCustomInserter(MachineInstr *MI,
252 MachineBasicBlock *MBB) const override;
254 void AdjustInstrPostInstrSelection(MachineInstr *MI,
255 SDNode *Node) const override;
257 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
258 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
260 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
262 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
263 /// unaligned memory accesses of the specified type. Returns whether it
264 /// is "fast" by reference in the second argument.
265 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
267 bool *Fast) const override;
269 EVT getOptimalMemOpType(uint64_t Size,
270 unsigned DstAlign, unsigned SrcAlign,
271 bool IsMemset, bool ZeroMemset,
273 MachineFunction &MF) const override;
275 using TargetLowering::isZExtFree;
276 bool isZExtFree(SDValue Val, EVT VT2) const override;
278 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
280 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
283 /// isLegalAddressingMode - Return true if the addressing mode represented
284 /// by AM is legal for this target, for a load/store of the specified type.
285 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
286 Type *Ty, unsigned AS) const override;
287 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
289 /// isLegalICmpImmediate - Return true if the specified immediate is legal
290 /// icmp immediate, that is the target has icmp instructions which can
291 /// compare a register against the immediate without having to materialize
292 /// the immediate into a register.
293 bool isLegalICmpImmediate(int64_t Imm) const override;
295 /// isLegalAddImmediate - Return true if the specified immediate is legal
296 /// add immediate, that is the target has add instructions which can
297 /// add a register and the immediate without having to materialize
298 /// the immediate into a register.
299 bool isLegalAddImmediate(int64_t Imm) const override;
301 /// getPreIndexedAddressParts - returns true by value, base pointer and
302 /// offset pointer and addressing mode by reference if the node's address
303 /// can be legally represented as pre-indexed load / store address.
304 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
305 ISD::MemIndexedMode &AM,
306 SelectionDAG &DAG) const override;
308 /// getPostIndexedAddressParts - returns true by value, base pointer and
309 /// offset pointer and addressing mode by reference if this node can be
310 /// combined with a load / store to form a post-indexed load / store.
311 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
312 SDValue &Offset, ISD::MemIndexedMode &AM,
313 SelectionDAG &DAG) const override;
315 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
317 const SelectionDAG &DAG,
318 unsigned Depth) const override;
321 bool ExpandInlineAsm(CallInst *CI) const override;
323 ConstraintType getConstraintType(StringRef Constraint) const override;
325 /// Examine constraint string and operand type and determine a weight value.
326 /// The operand object must already have been set up with the operand type.
327 ConstraintWeight getSingleConstraintMatchWeight(
328 AsmOperandInfo &info, const char *constraint) const override;
330 std::pair<unsigned, const TargetRegisterClass *>
331 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
332 StringRef Constraint, MVT VT) const override;
334 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
335 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
336 /// true it means one of the asm constraint of the inline asm instruction
337 /// being processed is 'm'.
338 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
339 std::vector<SDValue> &Ops,
340 SelectionDAG &DAG) const override;
343 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
344 if (ConstraintCode == "Q")
345 return InlineAsm::Constraint_Q;
346 else if (ConstraintCode.size() == 2) {
347 if (ConstraintCode[0] == 'U') {
348 switch(ConstraintCode[1]) {
352 return InlineAsm::Constraint_Um;
354 return InlineAsm::Constraint_Un;
356 return InlineAsm::Constraint_Uq;
358 return InlineAsm::Constraint_Us;
360 return InlineAsm::Constraint_Ut;
362 return InlineAsm::Constraint_Uv;
364 return InlineAsm::Constraint_Uy;
368 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
371 const ARMSubtarget* getSubtarget() const {
375 /// getRegClassFor - Return the register class that should be used for the
376 /// specified value type.
377 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
379 /// Returns true if a cast between SrcAS and DestAS is a noop.
380 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
381 // Addrspacecasts are always noops.
385 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
386 unsigned &PrefAlign) const override;
388 /// createFastISel - This method returns a target specific FastISel object,
389 /// or null if the target does not support "fast" ISel.
390 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
391 const TargetLibraryInfo *libInfo) const override;
393 Sched::Preference getSchedulingPreference(SDNode *N) const override;
396 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
397 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
399 /// isFPImmLegal - Returns true if the target can instruction select the
400 /// specified FP immediate natively. If false, the legalizer will
401 /// materialize the FP immediate as a load from a constant pool.
402 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
404 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
406 unsigned Intrinsic) const override;
408 /// \brief Returns true if it is beneficial to convert a load of a constant
409 /// to just the constant itself.
410 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
411 Type *Ty) const override;
413 /// \brief Returns true if an argument of type Ty needs to be passed in a
414 /// contiguous block of registers in calling convention CallConv.
415 bool functionArgumentNeedsConsecutiveRegisters(
416 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
418 bool hasLoadLinkedStoreConditional() const override;
419 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
420 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
421 AtomicOrdering Ord) const override;
422 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
423 Value *Addr, AtomicOrdering Ord) const override;
425 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
426 bool IsStore, bool IsLoad) const override;
427 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
428 bool IsStore, bool IsLoad) const override;
430 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
432 bool lowerInterleavedLoad(LoadInst *LI,
433 ArrayRef<ShuffleVectorInst *> Shuffles,
434 ArrayRef<unsigned> Indices,
435 unsigned Factor) const override;
436 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
437 unsigned Factor) const override;
439 bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
440 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
441 TargetLoweringBase::AtomicRMWExpansionKind
442 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
444 bool useLoadStackGuardNode() const override;
446 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
447 unsigned &Cost) const override;
450 std::pair<const TargetRegisterClass *, uint8_t>
451 findRepresentativeClass(const TargetRegisterInfo *TRI,
452 MVT VT) const override;
455 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
456 /// make the right decision when generating code for different targets.
457 const ARMSubtarget *Subtarget;
459 const TargetRegisterInfo *RegInfo;
461 const InstrItineraryData *Itins;
463 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
465 unsigned ARMPCLabelIndex;
467 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
468 void addDRTypeForNEON(MVT VT);
469 void addQRTypeForNEON(MVT VT);
470 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
472 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
473 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
474 SDValue Chain, SDValue &Arg,
475 RegsToPassVector &RegsToPass,
476 CCValAssign &VA, CCValAssign &NextVA,
478 SmallVectorImpl<SDValue> &MemOpChains,
479 ISD::ArgFlagsTy Flags) const;
480 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
481 SDValue &Root, SelectionDAG &DAG,
484 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
485 bool isVarArg) const;
486 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
487 bool isVarArg) const;
488 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
489 SDLoc dl, SelectionDAG &DAG,
490 const CCValAssign &VA,
491 ISD::ArgFlagsTy Flags) const;
492 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
493 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
494 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
495 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
496 const ARMSubtarget *Subtarget) const;
497 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
498 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
499 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
500 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
501 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
502 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
503 SelectionDAG &DAG) const;
504 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
506 TLSModel::Model model) const;
507 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
508 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
509 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
510 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
511 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
512 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
513 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
514 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
515 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
516 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
517 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
518 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
519 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
520 const ARMSubtarget *ST) const;
521 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
522 const ARMSubtarget *ST) const;
523 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
524 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
525 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
526 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
527 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
528 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
529 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
530 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
532 unsigned getRegisterByName(const char* RegName, EVT VT,
533 SelectionDAG &DAG) const override;
535 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
536 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
537 /// expanded to FMAs when this method returns true, otherwise fmuladd is
538 /// expanded to fmul + fadd.
540 /// ARM supports both fused and unfused multiply-add operations; we already
541 /// lower a pair of fmul and fadd to the latter so it's not clear that there
542 /// would be a gain or that the gain would be worthwhile enough to risk
543 /// correctness bugs.
544 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
546 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
548 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
549 CallingConv::ID CallConv, bool isVarArg,
550 const SmallVectorImpl<ISD::InputArg> &Ins,
551 SDLoc dl, SelectionDAG &DAG,
552 SmallVectorImpl<SDValue> &InVals,
553 bool isThisReturn, SDValue ThisVal) const;
556 LowerFormalArguments(SDValue Chain,
557 CallingConv::ID CallConv, bool isVarArg,
558 const SmallVectorImpl<ISD::InputArg> &Ins,
559 SDLoc dl, SelectionDAG &DAG,
560 SmallVectorImpl<SDValue> &InVals) const override;
562 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
563 SDLoc dl, SDValue &Chain,
564 const Value *OrigArg,
565 unsigned InRegsParamRecordIdx,
567 unsigned ArgSize) const;
569 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
570 SDLoc dl, SDValue &Chain,
572 unsigned TotalArgRegsSaveSize,
573 bool ForceMutable = false) const;
576 LowerCall(TargetLowering::CallLoweringInfo &CLI,
577 SmallVectorImpl<SDValue> &InVals) const override;
579 /// HandleByVal - Target-specific cleanup for ByVal support.
580 void HandleByVal(CCState *, unsigned &, unsigned) const override;
582 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
583 /// for tail call optimization. Targets which want to do tail call
584 /// optimization should implement this function.
585 bool IsEligibleForTailCallOptimization(SDValue Callee,
586 CallingConv::ID CalleeCC,
588 bool isCalleeStructRet,
589 bool isCallerStructRet,
590 const SmallVectorImpl<ISD::OutputArg> &Outs,
591 const SmallVectorImpl<SDValue> &OutVals,
592 const SmallVectorImpl<ISD::InputArg> &Ins,
593 SelectionDAG& DAG) const;
595 bool CanLowerReturn(CallingConv::ID CallConv,
596 MachineFunction &MF, bool isVarArg,
597 const SmallVectorImpl<ISD::OutputArg> &Outs,
598 LLVMContext &Context) const override;
601 LowerReturn(SDValue Chain,
602 CallingConv::ID CallConv, bool isVarArg,
603 const SmallVectorImpl<ISD::OutputArg> &Outs,
604 const SmallVectorImpl<SDValue> &OutVals,
605 SDLoc dl, SelectionDAG &DAG) const override;
607 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
609 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
611 SDValue getCMOV(SDLoc dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
612 SDValue ARMcc, SDValue CCR, SDValue Cmp,
613 SelectionDAG &DAG) const;
614 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
615 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
616 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
617 SelectionDAG &DAG, SDLoc dl) const;
618 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
620 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
622 void SetupEntryBlockForSjLj(MachineInstr *MI,
623 MachineBasicBlock *MBB,
624 MachineBasicBlock *DispatchBB, int FI) const;
626 void EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const;
628 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
630 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
631 MachineBasicBlock *MBB) const;
633 MachineBasicBlock *EmitLowered__chkstk(MachineInstr *MI,
634 MachineBasicBlock *MBB) const;
637 enum NEONModImmType {
644 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
645 const TargetLibraryInfo *libInfo);
649 #endif // ARMISELLOWERING_H