1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
27 class ARMConstantPoolValue;
30 // ARM Specific DAG Nodes
32 // Start the numbering where the builtin ops and target ops leave off.
33 FIRST_NUMBER = ISD::BUILTIN_OP_END,
35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
36 // TargetExternalSymbol, and TargetGlobalAddress.
37 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
39 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
41 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
52 PIC_ADD, // Add with a PC operand and a PIC label.
54 CMP, // ARM compare instructions.
55 CMPZ, // ARM compare that sets only Z flag.
56 CMPFP, // ARM VFP compare instruction, sets FPSCR.
57 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
58 FMSTAT, // ARM fmstat instruction.
59 CMOV, // ARM conditional move instructions.
63 RBIT, // ARM bitreverse instruction
65 FTOSI, // FP to sint within a FP register.
66 FTOUI, // FP to uint within a FP register.
67 SITOF, // sint to FP within a FP register.
68 UITOF, // uint to FP within a FP register.
70 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
71 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
72 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
74 ADDC, // Add with carry
75 ADDE, // Add using carry
76 SUBC, // Sub with carry
77 SUBE, // Sub using carry
79 VMOVRRD, // double to two gprs.
80 VMOVDRR, // Two gprs to double.
82 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
83 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
84 EH_SJLJ_DISPATCHSETUP, // SjLj exception handling dispatch setup.
86 TC_RETURN, // Tail call return pseudo.
90 DYN_ALLOC, // Dynamic allocation on the stack.
92 MEMBARRIER, // Memory barrier (DMB)
93 MEMBARRIER_MCR, // Memory barrier (MCR)
97 VCEQ, // Vector compare equal.
98 VCEQZ, // Vector compare equal to zero.
99 VCGE, // Vector compare greater than or equal.
100 VCGEZ, // Vector compare greater than or equal to zero.
101 VCLEZ, // Vector compare less than or equal to zero.
102 VCGEU, // Vector compare unsigned greater than or equal.
103 VCGT, // Vector compare greater than.
104 VCGTZ, // Vector compare greater than zero.
105 VCLTZ, // Vector compare less than zero.
106 VCGTU, // Vector compare unsigned greater than.
107 VTST, // Vector test bits.
109 // Vector shift by immediate:
111 VSHRs, // ...right (signed)
112 VSHRu, // ...right (unsigned)
113 VSHLLs, // ...left long (signed)
114 VSHLLu, // ...left long (unsigned)
115 VSHLLi, // ...left long (with maximum shift count)
116 VSHRN, // ...right narrow
118 // Vector rounding shift by immediate:
119 VRSHRs, // ...right (signed)
120 VRSHRu, // ...right (unsigned)
121 VRSHRN, // ...right narrow
123 // Vector saturating shift by immediate:
124 VQSHLs, // ...left (signed)
125 VQSHLu, // ...left (unsigned)
126 VQSHLsu, // ...left (signed to unsigned)
127 VQSHRNs, // ...right narrow (signed)
128 VQSHRNu, // ...right narrow (unsigned)
129 VQSHRNsu, // ...right narrow (signed to unsigned)
131 // Vector saturating rounding shift by immediate:
132 VQRSHRNs, // ...right narrow (signed)
133 VQRSHRNu, // ...right narrow (unsigned)
134 VQRSHRNsu, // ...right narrow (signed to unsigned)
136 // Vector shift and insert:
140 // Vector get lane (VMOV scalar to ARM core register)
141 // (These are used for 8- and 16-bit element types only.)
142 VGETLANEu, // zero-extend vector extract element
143 VGETLANEs, // sign-extend vector extract element
145 // Vector move immediate and move negated immediate:
155 VREV64, // reverse elements within 64-bit doublewords
156 VREV32, // reverse elements within 32-bit words
157 VREV16, // reverse elements within 16-bit halfwords
158 VZIP, // zip (interleave)
159 VUZP, // unzip (deinterleave)
161 VTBL1, // 1-register shuffle with mask
162 VTBL2, // 2-register shuffle with mask
164 // Vector multiply long:
166 VMULLu, // ...unsigned
168 // Operands of the standard BUILD_VECTOR node are not legalized, which
169 // is fine if BUILD_VECTORs are always lowered to shuffles or other
170 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
171 // operands need to be legalized. Define an ARM-specific version of
172 // BUILD_VECTOR for this purpose.
175 // Floating-point max and min:
182 // Vector OR with immediate
184 // Vector AND with NOT of immediate
187 // Vector bitwise select
190 // Vector load N-element structure to all lanes:
191 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
195 // NEON loads with post-increment base updates:
207 // NEON stores with post-increment base updates:
216 // 64-bit atomic ops (value split into two registers)
228 /// Define some predicates that are used for node matching.
230 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
231 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
232 /// instruction, returns its 8-bit integer representation. Otherwise,
234 int getVFPf32Imm(const APFloat &FPImm);
235 int getVFPf64Imm(const APFloat &FPImm);
236 bool isBitFieldInvertedMask(unsigned v);
239 //===--------------------------------------------------------------------===//
240 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
242 class ARMTargetLowering : public TargetLowering {
244 explicit ARMTargetLowering(TargetMachine &TM);
246 virtual unsigned getJumpTableEncoding(void) const;
248 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
250 /// ReplaceNodeResults - Replace the results of node with an illegal result
251 /// type with new values built out of custom code.
253 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
254 SelectionDAG &DAG) const;
256 virtual const char *getTargetNodeName(unsigned Opcode) const;
258 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
259 virtual EVT getSetCCResultType(EVT VT) const;
261 virtual MachineBasicBlock *
262 EmitInstrWithCustomInserter(MachineInstr *MI,
263 MachineBasicBlock *MBB) const;
266 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
268 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
269 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
271 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
273 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
274 /// unaligned memory accesses. of the specified type.
275 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
276 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
278 /// isLegalAddressingMode - Return true if the addressing mode represented
279 /// by AM is legal for this target, for a load/store of the specified type.
280 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
281 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
283 /// isLegalICmpImmediate - Return true if the specified immediate is legal
284 /// icmp immediate, that is the target has icmp instructions which can
285 /// compare a register against the immediate without having to materialize
286 /// the immediate into a register.
287 virtual bool isLegalICmpImmediate(int64_t Imm) const;
289 /// isLegalAddImmediate - Return true if the specified immediate is legal
290 /// add immediate, that is the target has add instructions which can
291 /// add a register and the immediate without having to materialize
292 /// the immediate into a register.
293 virtual bool isLegalAddImmediate(int64_t Imm) const;
295 /// getPreIndexedAddressParts - returns true by value, base pointer and
296 /// offset pointer and addressing mode by reference if the node's address
297 /// can be legally represented as pre-indexed load / store address.
298 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
300 ISD::MemIndexedMode &AM,
301 SelectionDAG &DAG) const;
303 /// getPostIndexedAddressParts - returns true by value, base pointer and
304 /// offset pointer and addressing mode by reference if this node can be
305 /// combined with a load / store to form a post-indexed load / store.
306 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
307 SDValue &Base, SDValue &Offset,
308 ISD::MemIndexedMode &AM,
309 SelectionDAG &DAG) const;
311 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
315 const SelectionDAG &DAG,
316 unsigned Depth) const;
319 virtual bool ExpandInlineAsm(CallInst *CI) const;
321 ConstraintType getConstraintType(const std::string &Constraint) const;
323 /// Examine constraint string and operand type and determine a weight value.
324 /// The operand object must already have been set up with the operand type.
325 ConstraintWeight getSingleConstraintMatchWeight(
326 AsmOperandInfo &info, const char *constraint) const;
328 std::pair<unsigned, const TargetRegisterClass*>
329 getRegForInlineAsmConstraint(const std::string &Constraint,
332 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
333 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
334 /// true it means one of the asm constraint of the inline asm instruction
335 /// being processed is 'm'.
336 virtual void LowerAsmOperandForConstraint(SDValue Op,
337 std::string &Constraint,
338 std::vector<SDValue> &Ops,
339 SelectionDAG &DAG) const;
341 const ARMSubtarget* getSubtarget() const {
345 /// getRegClassFor - Return the register class that should be used for the
346 /// specified value type.
347 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
349 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
350 /// be used for loads / stores from the global.
351 virtual unsigned getMaximalGlobalOffset() const;
353 /// createFastISel - This method returns a target specific FastISel object,
354 /// or null if the target does not support "fast" ISel.
355 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
357 Sched::Preference getSchedulingPreference(SDNode *N) const;
359 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
360 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
362 /// isFPImmLegal - Returns true if the target can instruction select the
363 /// specified FP immediate natively. If false, the legalizer will
364 /// materialize the FP immediate as a load from a constant pool.
365 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
367 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
369 unsigned Intrinsic) const;
371 std::pair<const TargetRegisterClass*, uint8_t>
372 findRepresentativeClass(EVT VT) const;
375 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
376 /// make the right decision when generating code for different targets.
377 const ARMSubtarget *Subtarget;
379 const TargetRegisterInfo *RegInfo;
381 const InstrItineraryData *Itins;
383 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
385 unsigned ARMPCLabelIndex;
387 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
388 void addDRTypeForNEON(EVT VT);
389 void addQRTypeForNEON(EVT VT);
391 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
392 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
393 SDValue Chain, SDValue &Arg,
394 RegsToPassVector &RegsToPass,
395 CCValAssign &VA, CCValAssign &NextVA,
397 SmallVector<SDValue, 8> &MemOpChains,
398 ISD::ArgFlagsTy Flags) const;
399 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
400 SDValue &Root, SelectionDAG &DAG,
403 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
404 bool isVarArg) const;
405 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
406 DebugLoc dl, SelectionDAG &DAG,
407 const CCValAssign &VA,
408 ISD::ArgFlagsTy Flags) const;
409 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
410 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
411 SDValue LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) const;
412 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
413 const ARMSubtarget *Subtarget) const;
414 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
415 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
416 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
417 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
418 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
419 SelectionDAG &DAG) const;
420 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
421 SelectionDAG &DAG) const;
422 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
423 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
424 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
425 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
426 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
427 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
428 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
429 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
430 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
431 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
432 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
433 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
434 const ARMSubtarget *ST) const;
436 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
439 CallingConv::ID CallConv, bool isVarArg,
440 const SmallVectorImpl<ISD::InputArg> &Ins,
441 DebugLoc dl, SelectionDAG &DAG,
442 SmallVectorImpl<SDValue> &InVals) const;
445 LowerFormalArguments(SDValue Chain,
446 CallingConv::ID CallConv, bool isVarArg,
447 const SmallVectorImpl<ISD::InputArg> &Ins,
448 DebugLoc dl, SelectionDAG &DAG,
449 SmallVectorImpl<SDValue> &InVals) const;
451 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
452 DebugLoc dl, SDValue &Chain, unsigned ArgOffset)
455 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
456 unsigned &VARegSize, unsigned &VARegSaveSize) const;
459 LowerCall(SDValue Chain, SDValue Callee,
460 CallingConv::ID CallConv, bool isVarArg,
462 const SmallVectorImpl<ISD::OutputArg> &Outs,
463 const SmallVectorImpl<SDValue> &OutVals,
464 const SmallVectorImpl<ISD::InputArg> &Ins,
465 DebugLoc dl, SelectionDAG &DAG,
466 SmallVectorImpl<SDValue> &InVals) const;
468 /// HandleByVal - Target-specific cleanup for ByVal support.
469 virtual void HandleByVal(CCState *, unsigned &) const;
471 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
472 /// for tail call optimization. Targets which want to do tail call
473 /// optimization should implement this function.
474 bool IsEligibleForTailCallOptimization(SDValue Callee,
475 CallingConv::ID CalleeCC,
477 bool isCalleeStructRet,
478 bool isCallerStructRet,
479 const SmallVectorImpl<ISD::OutputArg> &Outs,
480 const SmallVectorImpl<SDValue> &OutVals,
481 const SmallVectorImpl<ISD::InputArg> &Ins,
482 SelectionDAG& DAG) const;
484 LowerReturn(SDValue Chain,
485 CallingConv::ID CallConv, bool isVarArg,
486 const SmallVectorImpl<ISD::OutputArg> &Outs,
487 const SmallVectorImpl<SDValue> &OutVals,
488 DebugLoc dl, SelectionDAG &DAG) const;
490 virtual bool isUsedByReturnOnly(SDNode *N) const;
492 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
494 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
495 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
496 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
497 SelectionDAG &DAG, DebugLoc dl) const;
498 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
500 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
502 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
503 MachineBasicBlock *BB,
504 unsigned Size) const;
505 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
506 MachineBasicBlock *BB,
508 unsigned BinOpcode) const;
509 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
510 MachineBasicBlock *BB,
513 bool NeedsCarry = false,
514 bool IsCmpxchg = false) const;
515 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
516 MachineBasicBlock *BB,
519 ARMCC::CondCodes Cond) const;
521 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
524 enum NEONModImmType {
532 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
536 #endif // ARMISELLOWERING_H