1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
25 class ARMConstantPoolValue;
29 // ARM Specific DAG Nodes
30 enum NodeType : unsigned {
31 // Start the numbering where the builtin ops and target ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
40 // Add pseudo op to model memcpy for struct byval.
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
51 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
53 PIC_ADD, // Add with a PC operand and a PIC label.
55 CMP, // ARM compare instructions.
56 CMN, // ARM CMN instructions.
57 CMPZ, // ARM compare that sets only Z flag.
58 CMPFP, // ARM VFP compare instruction, sets FPSCR.
59 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
60 FMSTAT, // ARM fmstat instruction.
62 CMOV, // ARM conditional move instructions.
66 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
67 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
68 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
70 ADDC, // Add with carry
71 ADDE, // Add using carry
72 SUBC, // Sub with carry
73 SUBE, // Sub using carry
75 VMOVRRD, // double to two gprs.
76 VMOVDRR, // Two gprs to double.
78 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
79 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
80 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
82 TC_RETURN, // Tail call return pseudo.
86 DYN_ALLOC, // Dynamic allocation on the stack.
88 MEMBARRIER_MCR, // Memory barrier (MCR)
92 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
93 WIN__DBZCHK, // Windows' divide by zero check
95 VCEQ, // Vector compare equal.
96 VCEQZ, // Vector compare equal to zero.
97 VCGE, // Vector compare greater than or equal.
98 VCGEZ, // Vector compare greater than or equal to zero.
99 VCLEZ, // Vector compare less than or equal to zero.
100 VCGEU, // Vector compare unsigned greater than or equal.
101 VCGT, // Vector compare greater than.
102 VCGTZ, // Vector compare greater than zero.
103 VCLTZ, // Vector compare less than zero.
104 VCGTU, // Vector compare unsigned greater than.
105 VTST, // Vector test bits.
107 // Vector shift by immediate:
109 VSHRs, // ...right (signed)
110 VSHRu, // ...right (unsigned)
112 // Vector rounding shift by immediate:
113 VRSHRs, // ...right (signed)
114 VRSHRu, // ...right (unsigned)
115 VRSHRN, // ...right narrow
117 // Vector saturating shift by immediate:
118 VQSHLs, // ...left (signed)
119 VQSHLu, // ...left (unsigned)
120 VQSHLsu, // ...left (signed to unsigned)
121 VQSHRNs, // ...right narrow (signed)
122 VQSHRNu, // ...right narrow (unsigned)
123 VQSHRNsu, // ...right narrow (signed to unsigned)
125 // Vector saturating rounding shift by immediate:
126 VQRSHRNs, // ...right narrow (signed)
127 VQRSHRNu, // ...right narrow (unsigned)
128 VQRSHRNsu, // ...right narrow (signed to unsigned)
130 // Vector shift and insert:
134 // Vector get lane (VMOV scalar to ARM core register)
135 // (These are used for 8- and 16-bit element types only.)
136 VGETLANEu, // zero-extend vector extract element
137 VGETLANEs, // sign-extend vector extract element
139 // Vector move immediate and move negated immediate:
143 // Vector move f32 immediate:
152 VREV64, // reverse elements within 64-bit doublewords
153 VREV32, // reverse elements within 32-bit words
154 VREV16, // reverse elements within 16-bit halfwords
155 VZIP, // zip (interleave)
156 VUZP, // unzip (deinterleave)
158 VTBL1, // 1-register shuffle with mask
159 VTBL2, // 2-register shuffle with mask
161 // Vector multiply long:
163 VMULLu, // ...unsigned
165 UMLAL, // 64bit Unsigned Accumulate Multiply
166 SMLAL, // 64bit Signed Accumulate Multiply
168 // Operands of the standard BUILD_VECTOR node are not legalized, which
169 // is fine if BUILD_VECTORs are always lowered to shuffles or other
170 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
171 // operands need to be legalized. Define an ARM-specific version of
172 // BUILD_VECTOR for this purpose.
178 // Vector OR with immediate
180 // Vector AND with NOT of immediate
183 // Vector bitwise select
186 // Pseudo-instruction representing a memory copy using ldm/stm
190 // Vector load N-element structure to all lanes:
191 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
195 // NEON loads with post-increment base updates:
207 // NEON stores with post-increment base updates:
218 /// Define some predicates that are used for node matching.
220 bool isBitFieldInvertedMask(unsigned v);
223 //===--------------------------------------------------------------------===//
224 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
226 class ARMTargetLowering : public TargetLowering {
228 explicit ARMTargetLowering(const TargetMachine &TM,
229 const ARMSubtarget &STI);
231 unsigned getJumpTableEncoding() const override;
232 bool useSoftFloat() const override;
234 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
236 /// ReplaceNodeResults - Replace the results of node with an illegal result
237 /// type with new values built out of custom code.
239 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
240 SelectionDAG &DAG) const override;
242 const char *getTargetNodeName(unsigned Opcode) const override;
244 bool isSelectSupported(SelectSupportKind Kind) const override {
245 // ARM does not support scalar condition selects on vectors.
246 return (Kind != ScalarCondVectorVal);
249 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
250 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
251 EVT VT) const override;
254 EmitInstrWithCustomInserter(MachineInstr *MI,
255 MachineBasicBlock *MBB) const override;
257 void AdjustInstrPostInstrSelection(MachineInstr *MI,
258 SDNode *Node) const override;
260 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
261 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
262 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
264 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
266 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
267 /// unaligned memory accesses of the specified type. Returns whether it
268 /// is "fast" by reference in the second argument.
269 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
271 bool *Fast) const override;
273 EVT getOptimalMemOpType(uint64_t Size,
274 unsigned DstAlign, unsigned SrcAlign,
275 bool IsMemset, bool ZeroMemset,
277 MachineFunction &MF) const override;
279 using TargetLowering::isZExtFree;
280 bool isZExtFree(SDValue Val, EVT VT2) const override;
282 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
284 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
287 /// isLegalAddressingMode - Return true if the addressing mode represented
288 /// by AM is legal for this target, for a load/store of the specified type.
289 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
290 Type *Ty, unsigned AS) const override;
291 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
293 /// isLegalICmpImmediate - Return true if the specified immediate is legal
294 /// icmp immediate, that is the target has icmp instructions which can
295 /// compare a register against the immediate without having to materialize
296 /// the immediate into a register.
297 bool isLegalICmpImmediate(int64_t Imm) const override;
299 /// isLegalAddImmediate - Return true if the specified immediate is legal
300 /// add immediate, that is the target has add instructions which can
301 /// add a register and the immediate without having to materialize
302 /// the immediate into a register.
303 bool isLegalAddImmediate(int64_t Imm) const override;
305 /// getPreIndexedAddressParts - returns true by value, base pointer and
306 /// offset pointer and addressing mode by reference if the node's address
307 /// can be legally represented as pre-indexed load / store address.
308 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
309 ISD::MemIndexedMode &AM,
310 SelectionDAG &DAG) const override;
312 /// getPostIndexedAddressParts - returns true by value, base pointer and
313 /// offset pointer and addressing mode by reference if this node can be
314 /// combined with a load / store to form a post-indexed load / store.
315 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
316 SDValue &Offset, ISD::MemIndexedMode &AM,
317 SelectionDAG &DAG) const override;
319 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
321 const SelectionDAG &DAG,
322 unsigned Depth) const override;
325 bool ExpandInlineAsm(CallInst *CI) const override;
327 ConstraintType getConstraintType(StringRef Constraint) const override;
329 /// Examine constraint string and operand type and determine a weight value.
330 /// The operand object must already have been set up with the operand type.
331 ConstraintWeight getSingleConstraintMatchWeight(
332 AsmOperandInfo &info, const char *constraint) const override;
334 std::pair<unsigned, const TargetRegisterClass *>
335 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
336 StringRef Constraint, MVT VT) const override;
338 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
339 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
340 /// true it means one of the asm constraint of the inline asm instruction
341 /// being processed is 'm'.
342 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
343 std::vector<SDValue> &Ops,
344 SelectionDAG &DAG) const override;
347 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
348 if (ConstraintCode == "Q")
349 return InlineAsm::Constraint_Q;
350 else if (ConstraintCode == "o")
351 return InlineAsm::Constraint_o;
352 else if (ConstraintCode.size() == 2) {
353 if (ConstraintCode[0] == 'U') {
354 switch(ConstraintCode[1]) {
358 return InlineAsm::Constraint_Um;
360 return InlineAsm::Constraint_Un;
362 return InlineAsm::Constraint_Uq;
364 return InlineAsm::Constraint_Us;
366 return InlineAsm::Constraint_Ut;
368 return InlineAsm::Constraint_Uv;
370 return InlineAsm::Constraint_Uy;
374 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
377 const ARMSubtarget* getSubtarget() const {
381 /// getRegClassFor - Return the register class that should be used for the
382 /// specified value type.
383 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
385 /// Returns true if a cast between SrcAS and DestAS is a noop.
386 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
387 // Addrspacecasts are always noops.
391 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
392 unsigned &PrefAlign) const override;
394 /// createFastISel - This method returns a target specific FastISel object,
395 /// or null if the target does not support "fast" ISel.
396 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
397 const TargetLibraryInfo *libInfo) const override;
399 Sched::Preference getSchedulingPreference(SDNode *N) const override;
402 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
403 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
405 /// isFPImmLegal - Returns true if the target can instruction select the
406 /// specified FP immediate natively. If false, the legalizer will
407 /// materialize the FP immediate as a load from a constant pool.
408 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
410 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
412 unsigned Intrinsic) const override;
414 /// \brief Returns true if it is beneficial to convert a load of a constant
415 /// to just the constant itself.
416 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
417 Type *Ty) const override;
419 /// \brief Returns true if an argument of type Ty needs to be passed in a
420 /// contiguous block of registers in calling convention CallConv.
421 bool functionArgumentNeedsConsecutiveRegisters(
422 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
424 /// If a physical register, this returns the register that receives the
425 /// exception address on entry to an EH pad.
427 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
429 /// If a physical register, this returns the register that receives the
430 /// exception typeid on entry to a landing pad.
432 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
434 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
435 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
436 AtomicOrdering Ord) const override;
437 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
438 Value *Addr, AtomicOrdering Ord) const override;
440 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
442 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
443 bool IsStore, bool IsLoad) const override;
444 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
445 bool IsStore, bool IsLoad) const override;
447 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
449 bool lowerInterleavedLoad(LoadInst *LI,
450 ArrayRef<ShuffleVectorInst *> Shuffles,
451 ArrayRef<unsigned> Indices,
452 unsigned Factor) const override;
453 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
454 unsigned Factor) const override;
456 TargetLoweringBase::AtomicExpansionKind
457 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
458 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
459 TargetLoweringBase::AtomicExpansionKind
460 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
461 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
463 bool useLoadStackGuardNode() const override;
465 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
466 unsigned &Cost) const override;
468 bool isCheapToSpeculateCttz() const override;
469 bool isCheapToSpeculateCtlz() const override;
472 std::pair<const TargetRegisterClass *, uint8_t>
473 findRepresentativeClass(const TargetRegisterInfo *TRI,
474 MVT VT) const override;
477 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
478 /// make the right decision when generating code for different targets.
479 const ARMSubtarget *Subtarget;
481 const TargetRegisterInfo *RegInfo;
483 const InstrItineraryData *Itins;
485 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
487 unsigned ARMPCLabelIndex;
489 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
490 void addDRTypeForNEON(MVT VT);
491 void addQRTypeForNEON(MVT VT);
492 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
494 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
495 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
496 SDValue Chain, SDValue &Arg,
497 RegsToPassVector &RegsToPass,
498 CCValAssign &VA, CCValAssign &NextVA,
500 SmallVectorImpl<SDValue> &MemOpChains,
501 ISD::ArgFlagsTy Flags) const;
502 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
503 SDValue &Root, SelectionDAG &DAG,
506 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
507 bool isVarArg) const;
508 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
509 bool isVarArg) const;
510 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
511 SDLoc dl, SelectionDAG &DAG,
512 const CCValAssign &VA,
513 ISD::ArgFlagsTy Flags) const;
514 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
515 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
516 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
517 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
518 const ARMSubtarget *Subtarget) const;
519 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
520 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
521 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
522 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
523 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
524 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
525 SelectionDAG &DAG) const;
526 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
528 TLSModel::Model model) const;
529 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
530 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
531 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
532 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
533 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
534 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
535 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
536 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
537 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
538 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
539 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
540 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
541 const ARMSubtarget *ST) const;
542 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
543 const ARMSubtarget *ST) const;
544 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
545 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
546 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
547 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
548 SmallVectorImpl<SDValue> &Results) const;
549 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
550 SDValue &Chain) const;
551 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
552 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
553 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
554 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
555 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
556 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
558 unsigned getRegisterByName(const char* RegName, EVT VT,
559 SelectionDAG &DAG) const override;
561 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
562 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
563 /// expanded to FMAs when this method returns true, otherwise fmuladd is
564 /// expanded to fmul + fadd.
566 /// ARM supports both fused and unfused multiply-add operations; we already
567 /// lower a pair of fmul and fadd to the latter so it's not clear that there
568 /// would be a gain or that the gain would be worthwhile enough to risk
569 /// correctness bugs.
570 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
572 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
574 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
575 CallingConv::ID CallConv, bool isVarArg,
576 const SmallVectorImpl<ISD::InputArg> &Ins,
577 SDLoc dl, SelectionDAG &DAG,
578 SmallVectorImpl<SDValue> &InVals,
579 bool isThisReturn, SDValue ThisVal) const;
582 LowerFormalArguments(SDValue Chain,
583 CallingConv::ID CallConv, bool isVarArg,
584 const SmallVectorImpl<ISD::InputArg> &Ins,
585 SDLoc dl, SelectionDAG &DAG,
586 SmallVectorImpl<SDValue> &InVals) const override;
588 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
589 SDLoc dl, SDValue &Chain,
590 const Value *OrigArg,
591 unsigned InRegsParamRecordIdx,
593 unsigned ArgSize) const;
595 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
596 SDLoc dl, SDValue &Chain,
598 unsigned TotalArgRegsSaveSize,
599 bool ForceMutable = false) const;
602 LowerCall(TargetLowering::CallLoweringInfo &CLI,
603 SmallVectorImpl<SDValue> &InVals) const override;
605 /// HandleByVal - Target-specific cleanup for ByVal support.
606 void HandleByVal(CCState *, unsigned &, unsigned) const override;
608 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
609 /// for tail call optimization. Targets which want to do tail call
610 /// optimization should implement this function.
611 bool IsEligibleForTailCallOptimization(SDValue Callee,
612 CallingConv::ID CalleeCC,
614 bool isCalleeStructRet,
615 bool isCallerStructRet,
616 const SmallVectorImpl<ISD::OutputArg> &Outs,
617 const SmallVectorImpl<SDValue> &OutVals,
618 const SmallVectorImpl<ISD::InputArg> &Ins,
619 SelectionDAG& DAG) const;
621 bool CanLowerReturn(CallingConv::ID CallConv,
622 MachineFunction &MF, bool isVarArg,
623 const SmallVectorImpl<ISD::OutputArg> &Outs,
624 LLVMContext &Context) const override;
627 LowerReturn(SDValue Chain,
628 CallingConv::ID CallConv, bool isVarArg,
629 const SmallVectorImpl<ISD::OutputArg> &Outs,
630 const SmallVectorImpl<SDValue> &OutVals,
631 SDLoc dl, SelectionDAG &DAG) const override;
633 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
635 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
637 SDValue getCMOV(SDLoc dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
638 SDValue ARMcc, SDValue CCR, SDValue Cmp,
639 SelectionDAG &DAG) const;
640 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
641 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
642 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
643 SelectionDAG &DAG, SDLoc dl) const;
644 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
646 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
648 void SetupEntryBlockForSjLj(MachineInstr *MI,
649 MachineBasicBlock *MBB,
650 MachineBasicBlock *DispatchBB, int FI) const;
652 void EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const;
654 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
656 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
657 MachineBasicBlock *MBB) const;
659 MachineBasicBlock *EmitLowered__chkstk(MachineInstr *MI,
660 MachineBasicBlock *MBB) const;
661 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr *MI,
662 MachineBasicBlock *MBB) const;
665 enum NEONModImmType {
672 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
673 const TargetLibraryInfo *libInfo);
677 #endif // ARMISELLOWERING_H