1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
27 class ARMConstantPoolValue;
30 // ARM Specific DAG Nodes
32 // Start the numbering where the builtin ops and target ops leave off.
33 FIRST_NUMBER = ISD::BUILTIN_OP_END,
35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
36 // TargetExternalSymbol, and TargetGlobalAddress.
37 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
39 CALL, // Function call.
40 CALL_PRED, // Function call that's predicable.
41 CALL_NOLINK, // Function call with branch not branch-and-link.
42 tCALL, // Thumb function call.
43 BRCOND, // Conditional branch.
44 BR_JT, // Jumptable branch.
45 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
46 RET_FLAG, // Return with a flag operand.
48 PIC_ADD, // Add with a PC operand and a PIC label.
50 CMP, // ARM compare instructions.
51 CMPZ, // ARM compare that sets only Z flag.
52 CMPFP, // ARM VFP compare instruction, sets FPSCR.
53 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
54 FMSTAT, // ARM fmstat instruction.
55 CMOV, // ARM conditional move instructions.
56 CNEG, // ARM conditional negate instructions.
60 RBIT, // ARM bitreverse instruction
62 FTOSI, // FP to sint within a FP register.
63 FTOUI, // FP to uint within a FP register.
64 SITOF, // sint to FP within a FP register.
65 UITOF, // uint to FP within a FP register.
67 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
68 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
69 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
71 VMOVRRD, // double to two gprs.
72 VMOVDRR, // Two gprs to double.
74 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
75 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
76 EH_SJLJ_DISPATCHSETUP, // SjLj exception handling dispatch setup.
78 TC_RETURN, // Tail call return pseudo.
82 DYN_ALLOC, // Dynamic allocation on the stack.
84 MEMBARRIER, // Memory barrier (DMB)
85 MEMBARRIER_MCR, // Memory barrier (MCR)
87 VCEQ, // Vector compare equal.
88 VCGE, // Vector compare greater than or equal.
89 VCGEU, // Vector compare unsigned greater than or equal.
90 VCGT, // Vector compare greater than.
91 VCGTU, // Vector compare unsigned greater than.
92 VTST, // Vector test bits.
94 // Vector shift by immediate:
96 VSHRs, // ...right (signed)
97 VSHRu, // ...right (unsigned)
98 VSHLLs, // ...left long (signed)
99 VSHLLu, // ...left long (unsigned)
100 VSHLLi, // ...left long (with maximum shift count)
101 VSHRN, // ...right narrow
103 // Vector rounding shift by immediate:
104 VRSHRs, // ...right (signed)
105 VRSHRu, // ...right (unsigned)
106 VRSHRN, // ...right narrow
108 // Vector saturating shift by immediate:
109 VQSHLs, // ...left (signed)
110 VQSHLu, // ...left (unsigned)
111 VQSHLsu, // ...left (signed to unsigned)
112 VQSHRNs, // ...right narrow (signed)
113 VQSHRNu, // ...right narrow (unsigned)
114 VQSHRNsu, // ...right narrow (signed to unsigned)
116 // Vector saturating rounding shift by immediate:
117 VQRSHRNs, // ...right narrow (signed)
118 VQRSHRNu, // ...right narrow (unsigned)
119 VQRSHRNsu, // ...right narrow (signed to unsigned)
121 // Vector shift and insert:
125 // Vector get lane (VMOV scalar to ARM core register)
126 // (These are used for 8- and 16-bit element types only.)
127 VGETLANEu, // zero-extend vector extract element
128 VGETLANEs, // sign-extend vector extract element
130 // Vector move immediate and move negated immediate:
140 VREV64, // reverse elements within 64-bit doublewords
141 VREV32, // reverse elements within 32-bit words
142 VREV16, // reverse elements within 16-bit halfwords
143 VZIP, // zip (interleave)
144 VUZP, // unzip (deinterleave)
147 // Vector multiply long:
149 VMULLu, // ...unsigned
151 // Operands of the standard BUILD_VECTOR node are not legalized, which
152 // is fine if BUILD_VECTORs are always lowered to shuffles or other
153 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
154 // operands need to be legalized. Define an ARM-specific version of
155 // BUILD_VECTOR for this purpose.
158 // Floating-point max and min:
167 /// Define some predicates that are used for node matching.
169 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
170 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
171 /// instruction, returns its 8-bit integer representation. Otherwise,
173 int getVFPf32Imm(const APFloat &FPImm);
174 int getVFPf64Imm(const APFloat &FPImm);
175 bool isBitFieldInvertedMask(unsigned v);
178 //===--------------------------------------------------------------------===//
179 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
181 class ARMTargetLowering : public TargetLowering {
183 explicit ARMTargetLowering(TargetMachine &TM);
185 virtual unsigned getJumpTableEncoding(void) const;
187 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
189 /// ReplaceNodeResults - Replace the results of node with an illegal result
190 /// type with new values built out of custom code.
192 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
193 SelectionDAG &DAG) const;
195 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
197 virtual const char *getTargetNodeName(unsigned Opcode) const;
199 virtual MachineBasicBlock *
200 EmitInstrWithCustomInserter(MachineInstr *MI,
201 MachineBasicBlock *MBB) const;
203 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
204 /// unaligned memory accesses. of the specified type.
205 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
206 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
208 /// isLegalAddressingMode - Return true if the addressing mode represented
209 /// by AM is legal for this target, for a load/store of the specified type.
210 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
211 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
213 /// isLegalICmpImmediate - Return true if the specified immediate is legal
214 /// icmp immediate, that is the target has icmp instructions which can
215 /// compare a register against the immediate without having to materialize
216 /// the immediate into a register.
217 virtual bool isLegalICmpImmediate(int64_t Imm) const;
219 /// getPreIndexedAddressParts - returns true by value, base pointer and
220 /// offset pointer and addressing mode by reference if the node's address
221 /// can be legally represented as pre-indexed load / store address.
222 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
224 ISD::MemIndexedMode &AM,
225 SelectionDAG &DAG) const;
227 /// getPostIndexedAddressParts - returns true by value, base pointer and
228 /// offset pointer and addressing mode by reference if this node can be
229 /// combined with a load / store to form a post-indexed load / store.
230 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
231 SDValue &Base, SDValue &Offset,
232 ISD::MemIndexedMode &AM,
233 SelectionDAG &DAG) const;
235 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
239 const SelectionDAG &DAG,
240 unsigned Depth) const;
243 ConstraintType getConstraintType(const std::string &Constraint) const;
245 /// Examine constraint string and operand type and determine a weight value.
246 /// The operand object must already have been set up with the operand type.
247 ConstraintWeight getSingleConstraintMatchWeight(
248 AsmOperandInfo &info, const char *constraint) const;
250 std::pair<unsigned, const TargetRegisterClass*>
251 getRegForInlineAsmConstraint(const std::string &Constraint,
253 std::vector<unsigned>
254 getRegClassForInlineAsmConstraint(const std::string &Constraint,
257 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
258 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
259 /// true it means one of the asm constraint of the inline asm instruction
260 /// being processed is 'm'.
261 virtual void LowerAsmOperandForConstraint(SDValue Op,
262 char ConstraintLetter,
263 std::vector<SDValue> &Ops,
264 SelectionDAG &DAG) const;
266 const ARMSubtarget* getSubtarget() const {
270 /// getRegClassFor - Return the register class that should be used for the
271 /// specified value type.
272 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
274 /// getFunctionAlignment - Return the Log2 alignment of this function.
275 virtual unsigned getFunctionAlignment(const Function *F) const;
277 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
278 /// be used for loads / stores from the global.
279 virtual unsigned getMaximalGlobalOffset() const;
281 /// createFastISel - This method returns a target specific FastISel object,
282 /// or null if the target does not support "fast" ISel.
283 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
285 Sched::Preference getSchedulingPreference(SDNode *N) const;
287 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
288 MachineFunction &MF) const;
290 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
291 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
293 /// isFPImmLegal - Returns true if the target can instruction select the
294 /// specified FP immediate natively. If false, the legalizer will
295 /// materialize the FP immediate as a load from a constant pool.
296 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
298 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
300 unsigned Intrinsic) const;
302 std::pair<const TargetRegisterClass*, uint8_t>
303 findRepresentativeClass(EVT VT) const;
306 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
307 /// make the right decision when generating code for different targets.
308 const ARMSubtarget *Subtarget;
310 const TargetRegisterInfo *RegInfo;
312 const InstrItineraryData *Itins;
314 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
316 unsigned ARMPCLabelIndex;
318 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
319 void addDRTypeForNEON(EVT VT);
320 void addQRTypeForNEON(EVT VT);
322 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
323 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
324 SDValue Chain, SDValue &Arg,
325 RegsToPassVector &RegsToPass,
326 CCValAssign &VA, CCValAssign &NextVA,
328 SmallVector<SDValue, 8> &MemOpChains,
329 ISD::ArgFlagsTy Flags) const;
330 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
331 SDValue &Root, SelectionDAG &DAG,
334 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
335 bool isVarArg) const;
336 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
337 DebugLoc dl, SelectionDAG &DAG,
338 const CCValAssign &VA,
339 ISD::ArgFlagsTy Flags) const;
340 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
341 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
342 SDValue LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) const;
343 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
344 const ARMSubtarget *Subtarget) const;
345 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
346 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
347 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
348 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
349 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
350 SelectionDAG &DAG) const;
351 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
352 SelectionDAG &DAG) const;
353 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
354 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
355 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
356 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
357 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
358 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
359 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
360 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
361 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
362 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
363 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
365 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
366 CallingConv::ID CallConv, bool isVarArg,
367 const SmallVectorImpl<ISD::InputArg> &Ins,
368 DebugLoc dl, SelectionDAG &DAG,
369 SmallVectorImpl<SDValue> &InVals) const;
372 LowerFormalArguments(SDValue Chain,
373 CallingConv::ID CallConv, bool isVarArg,
374 const SmallVectorImpl<ISD::InputArg> &Ins,
375 DebugLoc dl, SelectionDAG &DAG,
376 SmallVectorImpl<SDValue> &InVals) const;
379 LowerCall(SDValue Chain, SDValue Callee,
380 CallingConv::ID CallConv, bool isVarArg,
382 const SmallVectorImpl<ISD::OutputArg> &Outs,
383 const SmallVectorImpl<SDValue> &OutVals,
384 const SmallVectorImpl<ISD::InputArg> &Ins,
385 DebugLoc dl, SelectionDAG &DAG,
386 SmallVectorImpl<SDValue> &InVals) const;
388 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
389 /// for tail call optimization. Targets which want to do tail call
390 /// optimization should implement this function.
391 bool IsEligibleForTailCallOptimization(SDValue Callee,
392 CallingConv::ID CalleeCC,
394 bool isCalleeStructRet,
395 bool isCallerStructRet,
396 const SmallVectorImpl<ISD::OutputArg> &Outs,
397 const SmallVectorImpl<SDValue> &OutVals,
398 const SmallVectorImpl<ISD::InputArg> &Ins,
399 SelectionDAG& DAG) const;
401 LowerReturn(SDValue Chain,
402 CallingConv::ID CallConv, bool isVarArg,
403 const SmallVectorImpl<ISD::OutputArg> &Outs,
404 const SmallVectorImpl<SDValue> &OutVals,
405 DebugLoc dl, SelectionDAG &DAG) const;
407 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
408 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
409 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
410 SelectionDAG &DAG, DebugLoc dl) const;
412 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
414 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
415 MachineBasicBlock *BB,
416 unsigned Size) const;
417 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
418 MachineBasicBlock *BB,
420 unsigned BinOpcode) const;
425 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
429 #endif // ARMISELLOWERING_H