1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
24 class ARMConstantPoolValue;
27 // ARM Specific DAG Nodes
29 // Start the numbering where the builting ops and target ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
32 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
33 // TargetExternalSymbol, and TargetGlobalAddress.
34 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
36 CALL, // Function call.
37 CALL_PRED, // Function call that's predicable.
38 CALL_NOLINK, // Function call with branch not branch-and-link.
39 tCALL, // Thumb function call.
40 BRCOND, // Conditional branch.
41 BR_JT, // Jumptable branch.
42 RET_FLAG, // Return with a flag operand.
44 PIC_ADD, // Add with a PC operand and a PIC label.
46 CMP, // ARM compare instructions.
47 CMPNZ, // ARM compare that uses only N or Z flags.
48 CMPFP, // ARM VFP compare instruction, sets FPSCR.
49 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
50 FMSTAT, // ARM fmstat instruction.
51 CMOV, // ARM conditional move instructions.
52 CNEG, // ARM conditional negate instructions.
54 FTOSI, // FP to sint within a FP register.
55 FTOUI, // FP to uint within a FP register.
56 SITOF, // sint to FP within a FP register.
57 UITOF, // uint to FP within a FP register.
59 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
60 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
61 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
63 FMRRD, // double to two gprs.
64 FMDRR, // Two gprs to double.
70 //===----------------------------------------------------------------------===//
71 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
73 class ARMTargetLowering : public TargetLowering {
74 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
76 explicit ARMTargetLowering(TargetMachine &TM);
78 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
80 /// ReplaceNodeResults - Replace the results of node with an illegal result
81 /// type with new values built out of custom code.
83 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
86 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
88 virtual const char *getTargetNodeName(unsigned Opcode) const;
90 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
91 MachineBasicBlock *MBB) const;
93 /// isLegalAddressingMode - Return true if the addressing mode represented
94 /// by AM is legal for this target, for a load/store of the specified type.
95 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
97 /// getPreIndexedAddressParts - returns true by value, base pointer and
98 /// offset pointer and addressing mode by reference if the node's address
99 /// can be legally represented as pre-indexed load / store address.
100 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
102 ISD::MemIndexedMode &AM,
103 SelectionDAG &DAG) const;
105 /// getPostIndexedAddressParts - returns true by value, base pointer and
106 /// offset pointer and addressing mode by reference if this node can be
107 /// combined with a load / store to form a post-indexed load / store.
108 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
109 SDValue &Base, SDValue &Offset,
110 ISD::MemIndexedMode &AM,
111 SelectionDAG &DAG) const;
113 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
117 const SelectionDAG &DAG,
118 unsigned Depth) const;
119 ConstraintType getConstraintType(const std::string &Constraint) const;
120 std::pair<unsigned, const TargetRegisterClass*>
121 getRegForInlineAsmConstraint(const std::string &Constraint,
123 std::vector<unsigned>
124 getRegClassForInlineAsmConstraint(const std::string &Constraint,
127 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
128 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
129 /// true it means one of the asm constraint of the inline asm instruction
130 /// being processed is 'm'.
131 virtual void LowerAsmOperandForConstraint(SDValue Op,
132 char ConstraintLetter,
134 std::vector<SDValue> &Ops,
135 SelectionDAG &DAG) const;
137 virtual const ARMSubtarget* getSubtarget() {
142 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
143 /// make the right decision when generating code for different targets.
144 const ARMSubtarget *Subtarget;
146 /// ARMPCLabelIndex - Keep track the number of ARM PC labels created.
148 unsigned ARMPCLabelIndex;
150 SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
151 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
152 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
153 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
154 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
156 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
158 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
159 SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
160 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
162 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
164 SDValue Dst, SDValue Src,
165 SDValue Size, unsigned Align,
167 const Value *DstSV, uint64_t DstSVOff,
168 const Value *SrcSV, uint64_t SrcSVOff);
172 #endif // ARMISELLOWERING_H