1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
27 class ARMConstantPoolValue;
30 // ARM Specific DAG Nodes
32 // Start the numbering where the builtin ops and target ops leave off.
33 FIRST_NUMBER = ISD::BUILTIN_OP_END,
35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
36 // TargetExternalSymbol, and TargetGlobalAddress.
37 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
39 CALL, // Function call.
40 CALL_PRED, // Function call that's predicable.
41 CALL_NOLINK, // Function call with branch not branch-and-link.
42 tCALL, // Thumb function call.
43 BRCOND, // Conditional branch.
44 BR_JT, // Jumptable branch.
45 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
46 RET_FLAG, // Return with a flag operand.
48 PIC_ADD, // Add with a PC operand and a PIC label.
50 CMP, // ARM compare instructions.
51 CMPZ, // ARM compare that sets only Z flag.
52 CMPFP, // ARM VFP compare instruction, sets FPSCR.
53 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
54 FMSTAT, // ARM fmstat instruction.
55 CMOV, // ARM conditional move instructions.
56 CNEG, // ARM conditional negate instructions.
60 RBIT, // ARM bitreverse instruction
62 FTOSI, // FP to sint within a FP register.
63 FTOUI, // FP to uint within a FP register.
64 SITOF, // sint to FP within a FP register.
65 UITOF, // uint to FP within a FP register.
67 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
68 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
69 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
71 VMOVRRD, // double to two gprs.
72 VMOVDRR, // Two gprs to double.
74 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
75 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
76 EH_SJLJ_DISPATCHSETUP, // SjLj exception handling dispatch setup.
78 TC_RETURN, // Tail call return pseudo.
82 DYN_ALLOC, // Dynamic allocation on the stack.
84 MEMBARRIER, // Memory barrier (DMB)
85 MEMBARRIER_MCR, // Memory barrier (MCR)
89 VCEQ, // Vector compare equal.
90 VCGE, // Vector compare greater than or equal.
91 VCGEU, // Vector compare unsigned greater than or equal.
92 VCGT, // Vector compare greater than.
93 VCGTU, // Vector compare unsigned greater than.
94 VTST, // Vector test bits.
96 // Vector shift by immediate:
98 VSHRs, // ...right (signed)
99 VSHRu, // ...right (unsigned)
100 VSHLLs, // ...left long (signed)
101 VSHLLu, // ...left long (unsigned)
102 VSHLLi, // ...left long (with maximum shift count)
103 VSHRN, // ...right narrow
105 // Vector rounding shift by immediate:
106 VRSHRs, // ...right (signed)
107 VRSHRu, // ...right (unsigned)
108 VRSHRN, // ...right narrow
110 // Vector saturating shift by immediate:
111 VQSHLs, // ...left (signed)
112 VQSHLu, // ...left (unsigned)
113 VQSHLsu, // ...left (signed to unsigned)
114 VQSHRNs, // ...right narrow (signed)
115 VQSHRNu, // ...right narrow (unsigned)
116 VQSHRNsu, // ...right narrow (signed to unsigned)
118 // Vector saturating rounding shift by immediate:
119 VQRSHRNs, // ...right narrow (signed)
120 VQRSHRNu, // ...right narrow (unsigned)
121 VQRSHRNsu, // ...right narrow (signed to unsigned)
123 // Vector shift and insert:
127 // Vector get lane (VMOV scalar to ARM core register)
128 // (These are used for 8- and 16-bit element types only.)
129 VGETLANEu, // zero-extend vector extract element
130 VGETLANEs, // sign-extend vector extract element
132 // Vector move immediate and move negated immediate:
142 VREV64, // reverse elements within 64-bit doublewords
143 VREV32, // reverse elements within 32-bit words
144 VREV16, // reverse elements within 16-bit halfwords
145 VZIP, // zip (interleave)
146 VUZP, // unzip (deinterleave)
149 // Vector multiply long:
151 VMULLu, // ...unsigned
153 // Operands of the standard BUILD_VECTOR node are not legalized, which
154 // is fine if BUILD_VECTORs are always lowered to shuffles or other
155 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
156 // operands need to be legalized. Define an ARM-specific version of
157 // BUILD_VECTOR for this purpose.
160 // Floating-point max and min:
167 // Vector OR with immediate
169 // Vector AND with NOT of immediate
174 /// Define some predicates that are used for node matching.
176 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
177 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
178 /// instruction, returns its 8-bit integer representation. Otherwise,
180 int getVFPf32Imm(const APFloat &FPImm);
181 int getVFPf64Imm(const APFloat &FPImm);
182 bool isBitFieldInvertedMask(unsigned v);
185 //===--------------------------------------------------------------------===//
186 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
188 class ARMTargetLowering : public TargetLowering {
190 explicit ARMTargetLowering(TargetMachine &TM);
192 virtual unsigned getJumpTableEncoding(void) const;
194 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
196 /// ReplaceNodeResults - Replace the results of node with an illegal result
197 /// type with new values built out of custom code.
199 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
200 SelectionDAG &DAG) const;
202 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
204 virtual const char *getTargetNodeName(unsigned Opcode) const;
206 virtual MachineBasicBlock *
207 EmitInstrWithCustomInserter(MachineInstr *MI,
208 MachineBasicBlock *MBB) const;
210 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
211 /// unaligned memory accesses. of the specified type.
212 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
213 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
215 /// isLegalAddressingMode - Return true if the addressing mode represented
216 /// by AM is legal for this target, for a load/store of the specified type.
217 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
218 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
220 /// isLegalICmpImmediate - Return true if the specified immediate is legal
221 /// icmp immediate, that is the target has icmp instructions which can
222 /// compare a register against the immediate without having to materialize
223 /// the immediate into a register.
224 virtual bool isLegalICmpImmediate(int64_t Imm) const;
226 /// getPreIndexedAddressParts - returns true by value, base pointer and
227 /// offset pointer and addressing mode by reference if the node's address
228 /// can be legally represented as pre-indexed load / store address.
229 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
231 ISD::MemIndexedMode &AM,
232 SelectionDAG &DAG) const;
234 /// getPostIndexedAddressParts - returns true by value, base pointer and
235 /// offset pointer and addressing mode by reference if this node can be
236 /// combined with a load / store to form a post-indexed load / store.
237 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
238 SDValue &Base, SDValue &Offset,
239 ISD::MemIndexedMode &AM,
240 SelectionDAG &DAG) const;
242 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
246 const SelectionDAG &DAG,
247 unsigned Depth) const;
250 ConstraintType getConstraintType(const std::string &Constraint) const;
252 /// Examine constraint string and operand type and determine a weight value.
253 /// The operand object must already have been set up with the operand type.
254 ConstraintWeight getSingleConstraintMatchWeight(
255 AsmOperandInfo &info, const char *constraint) const;
257 std::pair<unsigned, const TargetRegisterClass*>
258 getRegForInlineAsmConstraint(const std::string &Constraint,
260 std::vector<unsigned>
261 getRegClassForInlineAsmConstraint(const std::string &Constraint,
264 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
265 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
266 /// true it means one of the asm constraint of the inline asm instruction
267 /// being processed is 'm'.
268 virtual void LowerAsmOperandForConstraint(SDValue Op,
269 char ConstraintLetter,
270 std::vector<SDValue> &Ops,
271 SelectionDAG &DAG) const;
273 const ARMSubtarget* getSubtarget() const {
277 /// getRegClassFor - Return the register class that should be used for the
278 /// specified value type.
279 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
281 /// getFunctionAlignment - Return the Log2 alignment of this function.
282 virtual unsigned getFunctionAlignment(const Function *F) const;
284 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
285 /// be used for loads / stores from the global.
286 virtual unsigned getMaximalGlobalOffset() const;
288 /// createFastISel - This method returns a target specific FastISel object,
289 /// or null if the target does not support "fast" ISel.
290 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
292 Sched::Preference getSchedulingPreference(SDNode *N) const;
294 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
295 MachineFunction &MF) const;
297 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
298 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
300 /// isFPImmLegal - Returns true if the target can instruction select the
301 /// specified FP immediate natively. If false, the legalizer will
302 /// materialize the FP immediate as a load from a constant pool.
303 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
305 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
307 unsigned Intrinsic) const;
309 std::pair<const TargetRegisterClass*, uint8_t>
310 findRepresentativeClass(EVT VT) const;
313 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
314 /// make the right decision when generating code for different targets.
315 const ARMSubtarget *Subtarget;
317 const TargetRegisterInfo *RegInfo;
319 const InstrItineraryData *Itins;
321 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
323 unsigned ARMPCLabelIndex;
325 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
326 void addDRTypeForNEON(EVT VT);
327 void addQRTypeForNEON(EVT VT);
329 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
330 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
331 SDValue Chain, SDValue &Arg,
332 RegsToPassVector &RegsToPass,
333 CCValAssign &VA, CCValAssign &NextVA,
335 SmallVector<SDValue, 8> &MemOpChains,
336 ISD::ArgFlagsTy Flags) const;
337 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
338 SDValue &Root, SelectionDAG &DAG,
341 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
342 bool isVarArg) const;
343 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
344 DebugLoc dl, SelectionDAG &DAG,
345 const CCValAssign &VA,
346 ISD::ArgFlagsTy Flags) const;
347 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
348 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
349 SDValue LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) const;
350 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
351 const ARMSubtarget *Subtarget) const;
352 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
353 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
354 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
355 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
356 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
357 SelectionDAG &DAG) const;
358 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
359 SelectionDAG &DAG) const;
360 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
361 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
362 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
363 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
364 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
365 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
366 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
367 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
368 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
369 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
370 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
372 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
373 CallingConv::ID CallConv, bool isVarArg,
374 const SmallVectorImpl<ISD::InputArg> &Ins,
375 DebugLoc dl, SelectionDAG &DAG,
376 SmallVectorImpl<SDValue> &InVals) const;
379 LowerFormalArguments(SDValue Chain,
380 CallingConv::ID CallConv, bool isVarArg,
381 const SmallVectorImpl<ISD::InputArg> &Ins,
382 DebugLoc dl, SelectionDAG &DAG,
383 SmallVectorImpl<SDValue> &InVals) const;
386 LowerCall(SDValue Chain, SDValue Callee,
387 CallingConv::ID CallConv, bool isVarArg,
389 const SmallVectorImpl<ISD::OutputArg> &Outs,
390 const SmallVectorImpl<SDValue> &OutVals,
391 const SmallVectorImpl<ISD::InputArg> &Ins,
392 DebugLoc dl, SelectionDAG &DAG,
393 SmallVectorImpl<SDValue> &InVals) const;
395 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
396 /// for tail call optimization. Targets which want to do tail call
397 /// optimization should implement this function.
398 bool IsEligibleForTailCallOptimization(SDValue Callee,
399 CallingConv::ID CalleeCC,
401 bool isCalleeStructRet,
402 bool isCallerStructRet,
403 const SmallVectorImpl<ISD::OutputArg> &Outs,
404 const SmallVectorImpl<SDValue> &OutVals,
405 const SmallVectorImpl<ISD::InputArg> &Ins,
406 SelectionDAG& DAG) const;
408 LowerReturn(SDValue Chain,
409 CallingConv::ID CallConv, bool isVarArg,
410 const SmallVectorImpl<ISD::OutputArg> &Outs,
411 const SmallVectorImpl<SDValue> &OutVals,
412 DebugLoc dl, SelectionDAG &DAG) const;
414 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
415 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
416 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
417 SelectionDAG &DAG, DebugLoc dl) const;
419 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
421 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
422 MachineBasicBlock *BB,
423 unsigned Size) const;
424 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
425 MachineBasicBlock *BB,
427 unsigned BinOpcode) const;
431 enum NEONModImmType {
439 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
443 #endif // ARMISELLOWERING_H