1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
23 class ARMConstantPoolValue;
27 // ARM Specific DAG Nodes
29 // Start the numbering where the builting ops and target ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
32 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
33 // TargetExternalSymbol, and TargetGlobalAddress.
34 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
36 CALL, // Function call.
37 CALL_PRED, // Function call that's predicable.
38 CALL_NOLINK, // Function call with branch not branch-and-link.
39 tCALL, // Thumb function call.
40 BRCOND, // Conditional branch.
41 BR_JT, // Jumptable branch.
42 RET_FLAG, // Return with a flag operand.
44 PIC_ADD, // Add with a PC operand and a PIC label.
46 CMP, // ARM compare instructions.
47 CMPNZ, // ARM compare that uses only N or Z flags.
48 CMPFP, // ARM VFP compare instruction, sets FPSCR.
49 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
50 FMSTAT, // ARM fmstat instruction.
51 CMOV, // ARM conditional move instructions.
52 CNEG, // ARM conditional negate instructions.
54 FTOSI, // FP to sint within a FP register.
55 FTOUI, // FP to uint within a FP register.
56 SITOF, // sint to FP within a FP register.
57 UITOF, // uint to FP within a FP register.
59 MULHILOU, // Lo,Hi = umul LHS, RHS.
60 MULHILOS, // Lo,Hi = smul LHS, RHS.
62 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
63 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
64 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
66 FMRRD, // double to two gprs.
67 FMDRR, // Two gprs to double.
73 //===----------------------------------------------------------------------===//
74 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
76 class ARMTargetLowering : public TargetLowering {
77 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
79 explicit ARMTargetLowering(TargetMachine &TM);
81 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
82 virtual const char *getTargetNodeName(unsigned Opcode) const;
84 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
85 MachineBasicBlock *MBB);
87 /// isLegalAddressingMode - Return true if the addressing mode represented
88 /// by AM is legal for this target, for a load/store of the specified type.
89 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
91 /// getPreIndexedAddressParts - returns true by value, base pointer and
92 /// offset pointer and addressing mode by reference if the node's address
93 /// can be legally represented as pre-indexed load / store address.
94 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
96 ISD::MemIndexedMode &AM,
99 /// getPostIndexedAddressParts - returns true by value, base pointer and
100 /// offset pointer and addressing mode by reference if this node can be
101 /// combined with a load / store to form a post-indexed load / store.
102 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
103 SDOperand &Base, SDOperand &Offset,
104 ISD::MemIndexedMode &AM,
107 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
111 const SelectionDAG &DAG,
112 unsigned Depth) const;
113 ConstraintType getConstraintType(const std::string &Constraint) const;
114 std::pair<unsigned, const TargetRegisterClass*>
115 getRegForInlineAsmConstraint(const std::string &Constraint,
116 MVT::ValueType VT) const;
117 std::vector<unsigned>
118 getRegClassForInlineAsmConstraint(const std::string &Constraint,
119 MVT::ValueType VT) const;
121 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
122 /// make the right decision when generating code for different targets.
123 const ARMSubtarget *Subtarget;
125 /// ARMPCLabelIndex - Keep track the number of ARM PC labels created.
127 unsigned ARMPCLabelIndex;
129 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
130 SDOperand LowerGlobalAddressDarwin(SDOperand Op, SelectionDAG &DAG);
131 SDOperand LowerGlobalAddressELF(SDOperand Op, SelectionDAG &DAG);
132 SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
133 SDOperand LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
135 SDOperand LowerToTLSExecModels(GlobalAddressSDNode *GA,
137 SDOperand LowerGLOBAL_OFFSET_TABLE(SDOperand Op, SelectionDAG &DAG);
138 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
139 SDOperand LowerBR_JT(SDOperand Op, SelectionDAG &DAG);
140 SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG);
144 #endif // ARMISELLOWERING_H