1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
19 #include "ARMSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
28 class ARMConstantPoolValue;
31 // ARM Specific DAG Nodes
33 // Start the numbering where the builtin ops and target ops leave off.
34 FIRST_NUMBER = ISD::BUILTIN_OP_END,
36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
37 // TargetExternalSymbol, and TargetGlobalAddress.
38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
44 // Add pseudo op to model memcpy for struct byval.
47 CALL, // Function call.
48 CALL_PRED, // Function call that's predicable.
49 CALL_NOLINK, // Function call with branch not branch-and-link.
50 tCALL, // Thumb function call.
51 BRCOND, // Conditional branch.
52 BR_JT, // Jumptable branch.
53 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
54 RET_FLAG, // Return with a flag operand.
56 PIC_ADD, // Add with a PC operand and a PIC label.
58 CMP, // ARM compare instructions.
59 CMN, // ARM CMN instructions.
60 CMPZ, // ARM compare that sets only Z flag.
61 CMPFP, // ARM VFP compare instruction, sets FPSCR.
62 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
63 FMSTAT, // ARM fmstat instruction.
65 CMOV, // ARM conditional move instructions.
69 RBIT, // ARM bitreverse instruction
71 FTOSI, // FP to sint within a FP register.
72 FTOUI, // FP to uint within a FP register.
73 SITOF, // sint to FP within a FP register.
74 UITOF, // uint to FP within a FP register.
76 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
77 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
78 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
80 ADDC, // Add with carry
81 ADDE, // Add using carry
82 SUBC, // Sub with carry
83 SUBE, // Sub using carry
85 VMOVRRD, // double to two gprs.
86 VMOVDRR, // Two gprs to double.
88 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
89 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
91 TC_RETURN, // Tail call return pseudo.
95 DYN_ALLOC, // Dynamic allocation on the stack.
97 MEMBARRIER_MCR, // Memory barrier (MCR)
101 VCEQ, // Vector compare equal.
102 VCEQZ, // Vector compare equal to zero.
103 VCGE, // Vector compare greater than or equal.
104 VCGEZ, // Vector compare greater than or equal to zero.
105 VCLEZ, // Vector compare less than or equal to zero.
106 VCGEU, // Vector compare unsigned greater than or equal.
107 VCGT, // Vector compare greater than.
108 VCGTZ, // Vector compare greater than zero.
109 VCLTZ, // Vector compare less than zero.
110 VCGTU, // Vector compare unsigned greater than.
111 VTST, // Vector test bits.
113 // Vector shift by immediate:
115 VSHRs, // ...right (signed)
116 VSHRu, // ...right (unsigned)
117 VSHLLs, // ...left long (signed)
118 VSHLLu, // ...left long (unsigned)
119 VSHLLi, // ...left long (with maximum shift count)
120 VSHRN, // ...right narrow
122 // Vector rounding shift by immediate:
123 VRSHRs, // ...right (signed)
124 VRSHRu, // ...right (unsigned)
125 VRSHRN, // ...right narrow
127 // Vector saturating shift by immediate:
128 VQSHLs, // ...left (signed)
129 VQSHLu, // ...left (unsigned)
130 VQSHLsu, // ...left (signed to unsigned)
131 VQSHRNs, // ...right narrow (signed)
132 VQSHRNu, // ...right narrow (unsigned)
133 VQSHRNsu, // ...right narrow (signed to unsigned)
135 // Vector saturating rounding shift by immediate:
136 VQRSHRNs, // ...right narrow (signed)
137 VQRSHRNu, // ...right narrow (unsigned)
138 VQRSHRNsu, // ...right narrow (signed to unsigned)
140 // Vector shift and insert:
144 // Vector get lane (VMOV scalar to ARM core register)
145 // (These are used for 8- and 16-bit element types only.)
146 VGETLANEu, // zero-extend vector extract element
147 VGETLANEs, // sign-extend vector extract element
149 // Vector move immediate and move negated immediate:
153 // Vector move f32 immediate:
162 VREV64, // reverse elements within 64-bit doublewords
163 VREV32, // reverse elements within 32-bit words
164 VREV16, // reverse elements within 16-bit halfwords
165 VZIP, // zip (interleave)
166 VUZP, // unzip (deinterleave)
168 VTBL1, // 1-register shuffle with mask
169 VTBL2, // 2-register shuffle with mask
171 // Vector multiply long:
173 VMULLu, // ...unsigned
175 UMLAL, // 64bit Unsigned Accumulate Multiply
176 SMLAL, // 64bit Signed Accumulate Multiply
178 // Operands of the standard BUILD_VECTOR node are not legalized, which
179 // is fine if BUILD_VECTORs are always lowered to shuffles or other
180 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
181 // operands need to be legalized. Define an ARM-specific version of
182 // BUILD_VECTOR for this purpose.
185 // Floating-point max and min:
194 // Vector OR with immediate
196 // Vector AND with NOT of immediate
199 // Vector bitwise select
202 // Vector load N-element structure to all lanes:
203 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
207 // NEON loads with post-increment base updates:
219 // NEON stores with post-increment base updates:
228 // 64-bit atomic ops (value split into two registers)
244 /// Define some predicates that are used for node matching.
246 bool isBitFieldInvertedMask(unsigned v);
249 //===--------------------------------------------------------------------===//
250 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
252 class ARMTargetLowering : public TargetLowering {
254 explicit ARMTargetLowering(TargetMachine &TM);
256 virtual unsigned getJumpTableEncoding() const;
258 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
260 /// ReplaceNodeResults - Replace the results of node with an illegal result
261 /// type with new values built out of custom code.
263 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
264 SelectionDAG &DAG) const;
266 virtual const char *getTargetNodeName(unsigned Opcode) const;
268 virtual bool isSelectSupported(SelectSupportKind Kind) const {
269 // ARM does not support scalar condition selects on vectors.
270 return (Kind != ScalarCondVectorVal);
273 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
274 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
276 virtual MachineBasicBlock *
277 EmitInstrWithCustomInserter(MachineInstr *MI,
278 MachineBasicBlock *MBB) const;
281 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
283 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
284 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
286 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
288 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
289 /// unaligned memory accesses of the specified type. Returns whether it
290 /// is "fast" by reference in the second argument.
291 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
293 virtual EVT getOptimalMemOpType(uint64_t Size,
294 unsigned DstAlign, unsigned SrcAlign,
295 bool IsMemset, bool ZeroMemset,
297 MachineFunction &MF) const;
299 using TargetLowering::isZExtFree;
300 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
302 virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const;
305 /// isLegalAddressingMode - Return true if the addressing mode represented
306 /// by AM is legal for this target, for a load/store of the specified type.
307 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
308 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
310 /// isLegalICmpImmediate - Return true if the specified immediate is legal
311 /// icmp immediate, that is the target has icmp instructions which can
312 /// compare a register against the immediate without having to materialize
313 /// the immediate into a register.
314 virtual bool isLegalICmpImmediate(int64_t Imm) const;
316 /// isLegalAddImmediate - Return true if the specified immediate is legal
317 /// add immediate, that is the target has add instructions which can
318 /// add a register and the immediate without having to materialize
319 /// the immediate into a register.
320 virtual bool isLegalAddImmediate(int64_t Imm) const;
322 /// getPreIndexedAddressParts - returns true by value, base pointer and
323 /// offset pointer and addressing mode by reference if the node's address
324 /// can be legally represented as pre-indexed load / store address.
325 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
327 ISD::MemIndexedMode &AM,
328 SelectionDAG &DAG) const;
330 /// getPostIndexedAddressParts - returns true by value, base pointer and
331 /// offset pointer and addressing mode by reference if this node can be
332 /// combined with a load / store to form a post-indexed load / store.
333 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
334 SDValue &Base, SDValue &Offset,
335 ISD::MemIndexedMode &AM,
336 SelectionDAG &DAG) const;
338 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
341 const SelectionDAG &DAG,
342 unsigned Depth) const;
345 virtual bool ExpandInlineAsm(CallInst *CI) const;
347 ConstraintType getConstraintType(const std::string &Constraint) const;
349 /// Examine constraint string and operand type and determine a weight value.
350 /// The operand object must already have been set up with the operand type.
351 ConstraintWeight getSingleConstraintMatchWeight(
352 AsmOperandInfo &info, const char *constraint) const;
354 std::pair<unsigned, const TargetRegisterClass*>
355 getRegForInlineAsmConstraint(const std::string &Constraint,
358 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
359 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
360 /// true it means one of the asm constraint of the inline asm instruction
361 /// being processed is 'm'.
362 virtual void LowerAsmOperandForConstraint(SDValue Op,
363 std::string &Constraint,
364 std::vector<SDValue> &Ops,
365 SelectionDAG &DAG) const;
367 const ARMSubtarget* getSubtarget() const {
371 /// getRegClassFor - Return the register class that should be used for the
372 /// specified value type.
373 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const;
375 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
376 /// be used for loads / stores from the global.
377 virtual unsigned getMaximalGlobalOffset() const;
379 /// createFastISel - This method returns a target specific FastISel object,
380 /// or null if the target does not support "fast" ISel.
381 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
382 const TargetLibraryInfo *libInfo) const;
384 Sched::Preference getSchedulingPreference(SDNode *N) const;
386 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
387 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
389 /// isFPImmLegal - Returns true if the target can instruction select the
390 /// specified FP immediate natively. If false, the legalizer will
391 /// materialize the FP immediate as a load from a constant pool.
392 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
394 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
396 unsigned Intrinsic) const;
398 std::pair<const TargetRegisterClass*, uint8_t>
399 findRepresentativeClass(MVT VT) const;
402 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
403 /// make the right decision when generating code for different targets.
404 const ARMSubtarget *Subtarget;
406 const TargetRegisterInfo *RegInfo;
408 const InstrItineraryData *Itins;
410 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
412 unsigned ARMPCLabelIndex;
414 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
415 void addDRTypeForNEON(MVT VT);
416 void addQRTypeForNEON(MVT VT);
418 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
419 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
420 SDValue Chain, SDValue &Arg,
421 RegsToPassVector &RegsToPass,
422 CCValAssign &VA, CCValAssign &NextVA,
424 SmallVectorImpl<SDValue> &MemOpChains,
425 ISD::ArgFlagsTy Flags) const;
426 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
427 SDValue &Root, SelectionDAG &DAG,
430 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
431 bool isVarArg) const;
432 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
433 SDLoc dl, SelectionDAG &DAG,
434 const CCValAssign &VA,
435 ISD::ArgFlagsTy Flags) const;
436 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
437 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
439 const ARMSubtarget *Subtarget) const;
440 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
441 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
442 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
443 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
444 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
445 SelectionDAG &DAG) const;
446 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
448 TLSModel::Model model) const;
449 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
450 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
451 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
452 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
453 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
454 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
455 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
456 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
457 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
458 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
459 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
460 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
461 const ARMSubtarget *ST) const;
462 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
463 const ARMSubtarget *ST) const;
464 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
466 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
467 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
468 /// expanded to FMAs when this method returns true, otherwise fmuladd is
469 /// expanded to fmul + fadd.
471 /// ARM supports both fused and unfused multiply-add operations; we already
472 /// lower a pair of fmul and fadd to the latter so it's not clear that there
473 /// would be a gain or that the gain would be worthwhile enough to risk
474 /// correctness bugs.
475 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const { return false; }
477 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
479 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
480 CallingConv::ID CallConv, bool isVarArg,
481 const SmallVectorImpl<ISD::InputArg> &Ins,
482 SDLoc dl, SelectionDAG &DAG,
483 SmallVectorImpl<SDValue> &InVals,
484 bool isThisReturn, SDValue ThisVal) const;
487 LowerFormalArguments(SDValue Chain,
488 CallingConv::ID CallConv, bool isVarArg,
489 const SmallVectorImpl<ISD::InputArg> &Ins,
490 SDLoc dl, SelectionDAG &DAG,
491 SmallVectorImpl<SDValue> &InVals) const;
493 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
494 SDLoc dl, SDValue &Chain,
495 const Value *OrigArg,
496 unsigned InRegsParamRecordIdx,
497 unsigned OffsetFromOrigArg,
500 bool ForceMutable) const;
502 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
503 SDLoc dl, SDValue &Chain,
505 bool ForceMutable = false) const;
507 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
508 unsigned InRegsParamRecordIdx,
510 unsigned &ArgRegsSize,
511 unsigned &ArgRegsSaveSize) const;
514 LowerCall(TargetLowering::CallLoweringInfo &CLI,
515 SmallVectorImpl<SDValue> &InVals) const;
517 /// HandleByVal - Target-specific cleanup for ByVal support.
518 virtual void HandleByVal(CCState *, unsigned &, unsigned) const;
520 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
521 /// for tail call optimization. Targets which want to do tail call
522 /// optimization should implement this function.
523 bool IsEligibleForTailCallOptimization(SDValue Callee,
524 CallingConv::ID CalleeCC,
526 bool isCalleeStructRet,
527 bool isCallerStructRet,
528 const SmallVectorImpl<ISD::OutputArg> &Outs,
529 const SmallVectorImpl<SDValue> &OutVals,
530 const SmallVectorImpl<ISD::InputArg> &Ins,
531 SelectionDAG& DAG) const;
533 virtual bool CanLowerReturn(CallingConv::ID CallConv,
534 MachineFunction &MF, bool isVarArg,
535 const SmallVectorImpl<ISD::OutputArg> &Outs,
536 LLVMContext &Context) const;
539 LowerReturn(SDValue Chain,
540 CallingConv::ID CallConv, bool isVarArg,
541 const SmallVectorImpl<ISD::OutputArg> &Outs,
542 const SmallVectorImpl<SDValue> &OutVals,
543 SDLoc dl, SelectionDAG &DAG) const;
545 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
547 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
549 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
550 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
551 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
552 SelectionDAG &DAG, SDLoc dl) const;
553 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
555 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
557 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
558 MachineBasicBlock *BB,
559 unsigned Size) const;
560 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
561 MachineBasicBlock *BB,
563 unsigned BinOpcode) const;
564 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
565 MachineBasicBlock *BB,
568 bool NeedsCarry = false,
569 bool IsCmpxchg = false,
570 bool IsMinMax = false,
571 ARMCC::CondCodes CC = ARMCC::AL) const;
572 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
573 MachineBasicBlock *BB,
576 ARMCC::CondCodes Cond) const;
578 void SetupEntryBlockForSjLj(MachineInstr *MI,
579 MachineBasicBlock *MBB,
580 MachineBasicBlock *DispatchBB, int FI) const;
582 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
583 MachineBasicBlock *MBB) const;
585 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
587 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
588 MachineBasicBlock *MBB) const;
591 enum NEONModImmType {
599 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
600 const TargetLibraryInfo *libInfo);
604 #endif // ARMISELLOWERING_H