1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
25 class ARMConstantPoolValue;
28 // ARM Specific DAG Nodes
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
34 // TargetExternalSymbol, and TargetGlobalAddress.
35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
37 CALL, // Function call.
38 CALL_PRED, // Function call that's predicable.
39 CALL_NOLINK, // Function call with branch not branch-and-link.
40 tCALL, // Thumb function call.
41 BRCOND, // Conditional branch.
42 BR_JT, // Jumptable branch.
43 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
44 RET_FLAG, // Return with a flag operand.
46 PIC_ADD, // Add with a PC operand and a PIC label.
48 CMP, // ARM compare instructions.
49 CMPZ, // ARM compare that sets only Z flag.
50 CMPFP, // ARM VFP compare instruction, sets FPSCR.
51 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
52 FMSTAT, // ARM fmstat instruction.
53 CMOV, // ARM conditional move instructions.
54 CNEG, // ARM conditional negate instructions.
56 FTOSI, // FP to sint within a FP register.
57 FTOUI, // FP to uint within a FP register.
58 SITOF, // sint to FP within a FP register.
59 UITOF, // uint to FP within a FP register.
61 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
62 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
63 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
65 FMRRD, // double to two gprs.
66 FMDRR, // Two gprs to double.
68 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
69 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
73 DYN_ALLOC, // Dynamic allocation on the stack.
75 VCEQ, // Vector compare equal.
76 VCGE, // Vector compare greater than or equal.
77 VCGEU, // Vector compare unsigned greater than or equal.
78 VCGT, // Vector compare greater than.
79 VCGTU, // Vector compare unsigned greater than.
80 VTST, // Vector test bits.
82 // Vector shift by immediate:
84 VSHRs, // ...right (signed)
85 VSHRu, // ...right (unsigned)
86 VSHLLs, // ...left long (signed)
87 VSHLLu, // ...left long (unsigned)
88 VSHLLi, // ...left long (with maximum shift count)
89 VSHRN, // ...right narrow
91 // Vector rounding shift by immediate:
92 VRSHRs, // ...right (signed)
93 VRSHRu, // ...right (unsigned)
94 VRSHRN, // ...right narrow
96 // Vector saturating shift by immediate:
97 VQSHLs, // ...left (signed)
98 VQSHLu, // ...left (unsigned)
99 VQSHLsu, // ...left (signed to unsigned)
100 VQSHRNs, // ...right narrow (signed)
101 VQSHRNu, // ...right narrow (unsigned)
102 VQSHRNsu, // ...right narrow (signed to unsigned)
104 // Vector saturating rounding shift by immediate:
105 VQRSHRNs, // ...right narrow (signed)
106 VQRSHRNu, // ...right narrow (unsigned)
107 VQRSHRNsu, // ...right narrow (signed to unsigned)
109 // Vector shift and insert:
113 // Vector get lane (VMOV scalar to ARM core register)
114 // (These are used for 8- and 16-bit element types only.)
115 VGETLANEu, // zero-extend vector extract element
116 VGETLANEs, // sign-extend vector extract element
122 // Vector load/store with (de)interleaving
132 VREV64, // reverse elements within 64-bit doublewords
133 VREV32, // reverse elements within 32-bit words
134 VREV16, // reverse elements within 16-bit halfwords
142 /// Define some predicates that are used for node matching.
144 /// getVMOVImm - If this is a build_vector of constants which can be
145 /// formed by using a VMOV instruction of the specified element size,
146 /// return the constant being splatted. The ByteSize field indicates the
147 /// number of bytes of each element [1248].
148 SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
151 //===--------------------------------------------------------------------===//
152 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
154 class ARMTargetLowering : public TargetLowering {
155 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
157 explicit ARMTargetLowering(TargetMachine &TM);
159 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
161 /// ReplaceNodeResults - Replace the results of node with an illegal result
162 /// type with new values built out of custom code.
164 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
167 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
169 virtual const char *getTargetNodeName(unsigned Opcode) const;
171 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
172 MachineBasicBlock *MBB) const;
174 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
175 /// unaligned memory accesses. of the specified type.
176 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
177 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
179 /// isLegalAddressingMode - Return true if the addressing mode represented
180 /// by AM is legal for this target, for a load/store of the specified type.
181 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
182 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
184 /// getPreIndexedAddressParts - returns true by value, base pointer and
185 /// offset pointer and addressing mode by reference if the node's address
186 /// can be legally represented as pre-indexed load / store address.
187 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
189 ISD::MemIndexedMode &AM,
190 SelectionDAG &DAG) const;
192 /// getPostIndexedAddressParts - returns true by value, base pointer and
193 /// offset pointer and addressing mode by reference if this node can be
194 /// combined with a load / store to form a post-indexed load / store.
195 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
196 SDValue &Base, SDValue &Offset,
197 ISD::MemIndexedMode &AM,
198 SelectionDAG &DAG) const;
200 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
204 const SelectionDAG &DAG,
205 unsigned Depth) const;
208 ConstraintType getConstraintType(const std::string &Constraint) const;
209 std::pair<unsigned, const TargetRegisterClass*>
210 getRegForInlineAsmConstraint(const std::string &Constraint,
212 std::vector<unsigned>
213 getRegClassForInlineAsmConstraint(const std::string &Constraint,
216 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
217 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
218 /// true it means one of the asm constraint of the inline asm instruction
219 /// being processed is 'm'.
220 virtual void LowerAsmOperandForConstraint(SDValue Op,
221 char ConstraintLetter,
223 std::vector<SDValue> &Ops,
224 SelectionDAG &DAG) const;
226 virtual const ARMSubtarget* getSubtarget() {
230 /// getFunctionAlignment - Return the Log2 alignment of this function.
231 virtual unsigned getFunctionAlignment(const Function *F) const;
233 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
235 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
236 /// make the right decision when generating code for different targets.
237 const ARMSubtarget *Subtarget;
239 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
241 unsigned ARMPCLabelIndex;
243 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
244 void addDRTypeForNEON(EVT VT);
245 void addQRTypeForNEON(EVT VT);
247 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
248 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
249 SDValue Chain, SDValue &Arg,
250 RegsToPassVector &RegsToPass,
251 CCValAssign &VA, CCValAssign &NextVA,
253 SmallVector<SDValue, 8> &MemOpChains,
254 ISD::ArgFlagsTy Flags);
255 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
256 SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
258 CCAssignFn *CCAssignFnForNode(unsigned CC, bool Return, bool isVarArg) const;
259 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
260 DebugLoc dl, SelectionDAG &DAG,
261 const CCValAssign &VA,
262 ISD::ArgFlagsTy Flags);
263 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG);
264 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
265 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
266 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
267 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
268 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
270 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
272 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
273 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
274 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
275 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
277 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
279 SDValue Dst, SDValue Src,
280 SDValue Size, unsigned Align,
282 const Value *DstSV, uint64_t DstSVOff,
283 const Value *SrcSV, uint64_t SrcSVOff);
284 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
285 unsigned CallConv, bool isVarArg,
286 const SmallVectorImpl<ISD::InputArg> &Ins,
287 DebugLoc dl, SelectionDAG &DAG,
288 SmallVectorImpl<SDValue> &InVals);
291 LowerFormalArguments(SDValue Chain,
292 unsigned CallConv, bool isVarArg,
293 const SmallVectorImpl<ISD::InputArg> &Ins,
294 DebugLoc dl, SelectionDAG &DAG,
295 SmallVectorImpl<SDValue> &InVals);
298 LowerCall(SDValue Chain, SDValue Callee,
299 unsigned CallConv, bool isVarArg,
301 const SmallVectorImpl<ISD::OutputArg> &Outs,
302 const SmallVectorImpl<ISD::InputArg> &Ins,
303 DebugLoc dl, SelectionDAG &DAG,
304 SmallVectorImpl<SDValue> &InVals);
307 LowerReturn(SDValue Chain,
308 unsigned CallConv, bool isVarArg,
309 const SmallVectorImpl<ISD::OutputArg> &Outs,
310 DebugLoc dl, SelectionDAG &DAG);
314 #endif // ARMISELLOWERING_H