1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
24 class ARMConstantPoolValue;
27 // ARM Specific DAG Nodes
29 // Start the numbering where the builting ops and target ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
32 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
33 // TargetExternalSymbol, and TargetGlobalAddress.
34 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
36 CALL, // Function call.
37 CALL_PRED, // Function call that's predicable.
38 CALL_NOLINK, // Function call with branch not branch-and-link.
39 tCALL, // Thumb function call.
40 BRCOND, // Conditional branch.
41 BR_JT, // Jumptable branch.
42 RET_FLAG, // Return with a flag operand.
44 PIC_ADD, // Add with a PC operand and a PIC label.
46 CMP, // ARM compare instructions.
47 CMPNZ, // ARM compare that uses only N or Z flags.
48 CMPFP, // ARM VFP compare instruction, sets FPSCR.
49 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
50 FMSTAT, // ARM fmstat instruction.
51 CMOV, // ARM conditional move instructions.
52 CNEG, // ARM conditional negate instructions.
54 FTOSI, // FP to sint within a FP register.
55 FTOUI, // FP to uint within a FP register.
56 SITOF, // sint to FP within a FP register.
57 UITOF, // uint to FP within a FP register.
59 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
60 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
61 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
63 FMRRD, // double to two gprs.
64 FMDRR, // Two gprs to double.
70 //===----------------------------------------------------------------------===//
71 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
73 class ARMTargetLowering : public TargetLowering {
74 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
76 explicit ARMTargetLowering(TargetMachine &TM);
78 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
79 virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
81 virtual const char *getTargetNodeName(unsigned Opcode) const;
83 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
84 MachineBasicBlock *MBB);
86 /// isLegalAddressingMode - Return true if the addressing mode represented
87 /// by AM is legal for this target, for a load/store of the specified type.
88 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
90 /// getPreIndexedAddressParts - returns true by value, base pointer and
91 /// offset pointer and addressing mode by reference if the node's address
92 /// can be legally represented as pre-indexed load / store address.
93 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
95 ISD::MemIndexedMode &AM,
98 /// getPostIndexedAddressParts - returns true by value, base pointer and
99 /// offset pointer and addressing mode by reference if this node can be
100 /// combined with a load / store to form a post-indexed load / store.
101 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
102 SDOperand &Base, SDOperand &Offset,
103 ISD::MemIndexedMode &AM,
106 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
110 const SelectionDAG &DAG,
111 unsigned Depth) const;
112 ConstraintType getConstraintType(const std::string &Constraint) const;
113 std::pair<unsigned, const TargetRegisterClass*>
114 getRegForInlineAsmConstraint(const std::string &Constraint,
115 MVT::ValueType VT) const;
116 std::vector<unsigned>
117 getRegClassForInlineAsmConstraint(const std::string &Constraint,
118 MVT::ValueType VT) const;
120 virtual const TargetSubtarget* getSubtarget() {
121 return static_cast<const TargetSubtarget*>(Subtarget);
125 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
126 /// make the right decision when generating code for different targets.
127 const ARMSubtarget *Subtarget;
129 /// ARMPCLabelIndex - Keep track the number of ARM PC labels created.
131 unsigned ARMPCLabelIndex;
133 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
134 SDOperand LowerGlobalAddressDarwin(SDOperand Op, SelectionDAG &DAG);
135 SDOperand LowerGlobalAddressELF(SDOperand Op, SelectionDAG &DAG);
136 SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
137 SDOperand LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
139 SDOperand LowerToTLSExecModels(GlobalAddressSDNode *GA,
141 SDOperand LowerGLOBAL_OFFSET_TABLE(SDOperand Op, SelectionDAG &DAG);
142 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
143 SDOperand LowerBR_JT(SDOperand Op, SelectionDAG &DAG);
144 SDOperand LowerMEMCPYInline(SDOperand Chain, SDOperand Dest,
145 SDOperand Source, unsigned Size,
146 unsigned Align, SelectionDAG &DAG);
152 #endif // ARMISELLOWERING_H