1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
19 #include "ARMSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
28 class ARMConstantPoolValue;
31 // ARM Specific DAG Nodes
33 // Start the numbering where the builtin ops and target ops leave off.
34 FIRST_NUMBER = ISD::BUILTIN_OP_END,
36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
37 // TargetExternalSymbol, and TargetGlobalAddress.
38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
44 // Add pseudo op to model memcpy for struct byval.
47 CALL, // Function call.
48 CALL_PRED, // Function call that's predicable.
49 CALL_NOLINK, // Function call with branch not branch-and-link.
50 tCALL, // Thumb function call.
51 BRCOND, // Conditional branch.
52 BR_JT, // Jumptable branch.
53 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
54 RET_FLAG, // Return with a flag operand.
56 PIC_ADD, // Add with a PC operand and a PIC label.
58 CMP, // ARM compare instructions.
59 CMN, // ARM CMN instructions.
60 CMPZ, // ARM compare that sets only Z flag.
61 CMPFP, // ARM VFP compare instruction, sets FPSCR.
62 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
63 FMSTAT, // ARM fmstat instruction.
65 CMOV, // ARM conditional move instructions.
69 RBIT, // ARM bitreverse instruction
71 FTOSI, // FP to sint within a FP register.
72 FTOUI, // FP to uint within a FP register.
73 SITOF, // sint to FP within a FP register.
74 UITOF, // uint to FP within a FP register.
76 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
77 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
78 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
80 ADDC, // Add with carry
81 ADDE, // Add using carry
82 SUBC, // Sub with carry
83 SUBE, // Sub using carry
85 VMOVRRD, // double to two gprs.
86 VMOVDRR, // Two gprs to double.
88 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
89 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
91 TC_RETURN, // Tail call return pseudo.
95 DYN_ALLOC, // Dynamic allocation on the stack.
97 MEMBARRIER, // Memory barrier (DMB)
98 MEMBARRIER_MCR, // Memory barrier (MCR)
102 VCEQ, // Vector compare equal.
103 VCEQZ, // Vector compare equal to zero.
104 VCGE, // Vector compare greater than or equal.
105 VCGEZ, // Vector compare greater than or equal to zero.
106 VCLEZ, // Vector compare less than or equal to zero.
107 VCGEU, // Vector compare unsigned greater than or equal.
108 VCGT, // Vector compare greater than.
109 VCGTZ, // Vector compare greater than zero.
110 VCLTZ, // Vector compare less than zero.
111 VCGTU, // Vector compare unsigned greater than.
112 VTST, // Vector test bits.
114 // Vector shift by immediate:
116 VSHRs, // ...right (signed)
117 VSHRu, // ...right (unsigned)
118 VSHLLs, // ...left long (signed)
119 VSHLLu, // ...left long (unsigned)
120 VSHLLi, // ...left long (with maximum shift count)
121 VSHRN, // ...right narrow
123 // Vector rounding shift by immediate:
124 VRSHRs, // ...right (signed)
125 VRSHRu, // ...right (unsigned)
126 VRSHRN, // ...right narrow
128 // Vector saturating shift by immediate:
129 VQSHLs, // ...left (signed)
130 VQSHLu, // ...left (unsigned)
131 VQSHLsu, // ...left (signed to unsigned)
132 VQSHRNs, // ...right narrow (signed)
133 VQSHRNu, // ...right narrow (unsigned)
134 VQSHRNsu, // ...right narrow (signed to unsigned)
136 // Vector saturating rounding shift by immediate:
137 VQRSHRNs, // ...right narrow (signed)
138 VQRSHRNu, // ...right narrow (unsigned)
139 VQRSHRNsu, // ...right narrow (signed to unsigned)
141 // Vector shift and insert:
145 // Vector get lane (VMOV scalar to ARM core register)
146 // (These are used for 8- and 16-bit element types only.)
147 VGETLANEu, // zero-extend vector extract element
148 VGETLANEs, // sign-extend vector extract element
150 // Vector move immediate and move negated immediate:
154 // Vector move f32 immediate:
163 VREV64, // reverse elements within 64-bit doublewords
164 VREV32, // reverse elements within 32-bit words
165 VREV16, // reverse elements within 16-bit halfwords
166 VZIP, // zip (interleave)
167 VUZP, // unzip (deinterleave)
169 VTBL1, // 1-register shuffle with mask
170 VTBL2, // 2-register shuffle with mask
172 // Vector multiply long:
174 VMULLu, // ...unsigned
176 UMLAL, // 64bit Unsigned Accumulate Multiply
177 SMLAL, // 64bit Signed Accumulate Multiply
179 // Operands of the standard BUILD_VECTOR node are not legalized, which
180 // is fine if BUILD_VECTORs are always lowered to shuffles or other
181 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
182 // operands need to be legalized. Define an ARM-specific version of
183 // BUILD_VECTOR for this purpose.
186 // Floating-point max and min:
195 // Vector OR with immediate
197 // Vector AND with NOT of immediate
200 // Vector bitwise select
203 // Vector load N-element structure to all lanes:
204 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
208 // NEON loads with post-increment base updates:
220 // NEON stores with post-increment base updates:
229 // 64-bit atomic ops (value split into two registers)
245 /// Define some predicates that are used for node matching.
247 bool isBitFieldInvertedMask(unsigned v);
250 //===--------------------------------------------------------------------===//
251 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
253 class ARMTargetLowering : public TargetLowering {
255 explicit ARMTargetLowering(TargetMachine &TM);
257 virtual unsigned getJumpTableEncoding() const;
259 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
261 /// ReplaceNodeResults - Replace the results of node with an illegal result
262 /// type with new values built out of custom code.
264 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
265 SelectionDAG &DAG) const;
267 virtual const char *getTargetNodeName(unsigned Opcode) const;
269 virtual bool isSelectSupported(SelectSupportKind Kind) const {
270 // ARM does not support scalar condition selects on vectors.
271 return (Kind != ScalarCondVectorVal);
274 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
275 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
277 virtual MachineBasicBlock *
278 EmitInstrWithCustomInserter(MachineInstr *MI,
279 MachineBasicBlock *MBB) const;
282 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
284 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
285 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
287 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
289 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
290 /// unaligned memory accesses of the specified type. Returns whether it
291 /// is "fast" by reference in the second argument.
292 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
294 virtual EVT getOptimalMemOpType(uint64_t Size,
295 unsigned DstAlign, unsigned SrcAlign,
296 bool IsMemset, bool ZeroMemset,
298 MachineFunction &MF) const;
300 using TargetLowering::isZExtFree;
301 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
303 virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const;
306 /// isLegalAddressingMode - Return true if the addressing mode represented
307 /// by AM is legal for this target, for a load/store of the specified type.
308 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
309 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
311 /// isLegalICmpImmediate - Return true if the specified immediate is legal
312 /// icmp immediate, that is the target has icmp instructions which can
313 /// compare a register against the immediate without having to materialize
314 /// the immediate into a register.
315 virtual bool isLegalICmpImmediate(int64_t Imm) const;
317 /// isLegalAddImmediate - Return true if the specified immediate is legal
318 /// add immediate, that is the target has add instructions which can
319 /// add a register and the immediate without having to materialize
320 /// the immediate into a register.
321 virtual bool isLegalAddImmediate(int64_t Imm) const;
323 /// getPreIndexedAddressParts - returns true by value, base pointer and
324 /// offset pointer and addressing mode by reference if the node's address
325 /// can be legally represented as pre-indexed load / store address.
326 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
328 ISD::MemIndexedMode &AM,
329 SelectionDAG &DAG) const;
331 /// getPostIndexedAddressParts - returns true by value, base pointer and
332 /// offset pointer and addressing mode by reference if this node can be
333 /// combined with a load / store to form a post-indexed load / store.
334 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
335 SDValue &Base, SDValue &Offset,
336 ISD::MemIndexedMode &AM,
337 SelectionDAG &DAG) const;
339 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
342 const SelectionDAG &DAG,
343 unsigned Depth) const;
346 virtual bool ExpandInlineAsm(CallInst *CI) const;
348 ConstraintType getConstraintType(const std::string &Constraint) const;
350 /// Examine constraint string and operand type and determine a weight value.
351 /// The operand object must already have been set up with the operand type.
352 ConstraintWeight getSingleConstraintMatchWeight(
353 AsmOperandInfo &info, const char *constraint) const;
355 std::pair<unsigned, const TargetRegisterClass*>
356 getRegForInlineAsmConstraint(const std::string &Constraint,
359 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
360 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
361 /// true it means one of the asm constraint of the inline asm instruction
362 /// being processed is 'm'.
363 virtual void LowerAsmOperandForConstraint(SDValue Op,
364 std::string &Constraint,
365 std::vector<SDValue> &Ops,
366 SelectionDAG &DAG) const;
368 const ARMSubtarget* getSubtarget() const {
372 /// getRegClassFor - Return the register class that should be used for the
373 /// specified value type.
374 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const;
376 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
377 /// be used for loads / stores from the global.
378 virtual unsigned getMaximalGlobalOffset() const;
380 /// createFastISel - This method returns a target specific FastISel object,
381 /// or null if the target does not support "fast" ISel.
382 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
383 const TargetLibraryInfo *libInfo) const;
385 Sched::Preference getSchedulingPreference(SDNode *N) const;
387 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
388 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
390 /// isFPImmLegal - Returns true if the target can instruction select the
391 /// specified FP immediate natively. If false, the legalizer will
392 /// materialize the FP immediate as a load from a constant pool.
393 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
395 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
397 unsigned Intrinsic) const;
399 std::pair<const TargetRegisterClass*, uint8_t>
400 findRepresentativeClass(MVT VT) const;
403 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
404 /// make the right decision when generating code for different targets.
405 const ARMSubtarget *Subtarget;
407 const TargetRegisterInfo *RegInfo;
409 const InstrItineraryData *Itins;
411 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
413 unsigned ARMPCLabelIndex;
415 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
416 void addDRTypeForNEON(MVT VT);
417 void addQRTypeForNEON(MVT VT);
419 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
420 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
421 SDValue Chain, SDValue &Arg,
422 RegsToPassVector &RegsToPass,
423 CCValAssign &VA, CCValAssign &NextVA,
425 SmallVectorImpl<SDValue> &MemOpChains,
426 ISD::ArgFlagsTy Flags) const;
427 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
428 SDValue &Root, SelectionDAG &DAG,
431 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
432 bool isVarArg) const;
433 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
434 SDLoc dl, SelectionDAG &DAG,
435 const CCValAssign &VA,
436 ISD::ArgFlagsTy Flags) const;
437 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
439 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
440 const ARMSubtarget *Subtarget) const;
441 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
442 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
443 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
444 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
445 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
446 SelectionDAG &DAG) const;
447 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
449 TLSModel::Model model) const;
450 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
451 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
452 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
453 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
454 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
455 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
456 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
457 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
458 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
459 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
460 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
461 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
462 const ARMSubtarget *ST) const;
463 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
464 const ARMSubtarget *ST) const;
465 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
467 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
468 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
469 /// expanded to FMAs when this method returns true, otherwise fmuladd is
470 /// expanded to fmul + fadd.
472 /// ARM supports both fused and unfused multiply-add operations; we already
473 /// lower a pair of fmul and fadd to the latter so it's not clear that there
474 /// would be a gain or that the gain would be worthwhile enough to risk
475 /// correctness bugs.
476 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const { return false; }
478 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
480 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
481 CallingConv::ID CallConv, bool isVarArg,
482 const SmallVectorImpl<ISD::InputArg> &Ins,
483 SDLoc dl, SelectionDAG &DAG,
484 SmallVectorImpl<SDValue> &InVals,
485 bool isThisReturn, SDValue ThisVal) const;
488 LowerFormalArguments(SDValue Chain,
489 CallingConv::ID CallConv, bool isVarArg,
490 const SmallVectorImpl<ISD::InputArg> &Ins,
491 SDLoc dl, SelectionDAG &DAG,
492 SmallVectorImpl<SDValue> &InVals) const;
494 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
495 SDLoc dl, SDValue &Chain,
496 const Value *OrigArg,
497 unsigned InRegsParamRecordIdx,
498 unsigned OffsetFromOrigArg,
501 bool ForceMutable) const;
503 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
504 SDLoc dl, SDValue &Chain,
506 bool ForceMutable = false) const;
508 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
509 unsigned InRegsParamRecordIdx,
511 unsigned &ArgRegsSize,
512 unsigned &ArgRegsSaveSize) const;
515 LowerCall(TargetLowering::CallLoweringInfo &CLI,
516 SmallVectorImpl<SDValue> &InVals) const;
518 /// HandleByVal - Target-specific cleanup for ByVal support.
519 virtual void HandleByVal(CCState *, unsigned &, unsigned) const;
521 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
522 /// for tail call optimization. Targets which want to do tail call
523 /// optimization should implement this function.
524 bool IsEligibleForTailCallOptimization(SDValue Callee,
525 CallingConv::ID CalleeCC,
527 bool isCalleeStructRet,
528 bool isCallerStructRet,
529 const SmallVectorImpl<ISD::OutputArg> &Outs,
530 const SmallVectorImpl<SDValue> &OutVals,
531 const SmallVectorImpl<ISD::InputArg> &Ins,
532 SelectionDAG& DAG) const;
534 virtual bool CanLowerReturn(CallingConv::ID CallConv,
535 MachineFunction &MF, bool isVarArg,
536 const SmallVectorImpl<ISD::OutputArg> &Outs,
537 LLVMContext &Context) const;
540 LowerReturn(SDValue Chain,
541 CallingConv::ID CallConv, bool isVarArg,
542 const SmallVectorImpl<ISD::OutputArg> &Outs,
543 const SmallVectorImpl<SDValue> &OutVals,
544 SDLoc dl, SelectionDAG &DAG) const;
546 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
548 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
550 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
551 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
552 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
553 SelectionDAG &DAG, SDLoc dl) const;
554 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
556 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
558 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
559 MachineBasicBlock *BB,
560 unsigned Size) const;
561 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
562 MachineBasicBlock *BB,
564 unsigned BinOpcode) const;
565 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
566 MachineBasicBlock *BB,
569 bool NeedsCarry = false,
570 bool IsCmpxchg = false,
571 bool IsMinMax = false,
572 ARMCC::CondCodes CC = ARMCC::AL) const;
573 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
574 MachineBasicBlock *BB,
577 ARMCC::CondCodes Cond) const;
579 void SetupEntryBlockForSjLj(MachineInstr *MI,
580 MachineBasicBlock *MBB,
581 MachineBasicBlock *DispatchBB, int FI) const;
583 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
584 MachineBasicBlock *MBB) const;
586 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
588 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
589 MachineBasicBlock *MBB) const;
592 enum NEONModImmType {
600 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
601 const TargetLibraryInfo *libInfo);
605 #endif // ARMISELLOWERING_H