1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
27 class ARMConstantPoolValue;
30 // ARM Specific DAG Nodes
32 // Start the numbering where the builtin ops and target ops leave off.
33 FIRST_NUMBER = ISD::BUILTIN_OP_END,
35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
36 // TargetExternalSymbol, and TargetGlobalAddress.
37 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
39 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
41 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
52 PIC_ADD, // Add with a PC operand and a PIC label.
54 CMP, // ARM compare instructions.
55 CMPZ, // ARM compare that sets only Z flag.
56 CMPFP, // ARM VFP compare instruction, sets FPSCR.
57 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
58 FMSTAT, // ARM fmstat instruction.
59 CMOV, // ARM conditional move instructions.
63 RBIT, // ARM bitreverse instruction
65 FTOSI, // FP to sint within a FP register.
66 FTOUI, // FP to uint within a FP register.
67 SITOF, // sint to FP within a FP register.
68 UITOF, // uint to FP within a FP register.
70 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
71 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
72 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
74 VMOVRRD, // double to two gprs.
75 VMOVDRR, // Two gprs to double.
77 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
78 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
79 EH_SJLJ_DISPATCHSETUP, // SjLj exception handling dispatch setup.
81 TC_RETURN, // Tail call return pseudo.
85 DYN_ALLOC, // Dynamic allocation on the stack.
87 MEMBARRIER, // Memory barrier (DMB)
88 MEMBARRIER_MCR, // Memory barrier (MCR)
92 VCEQ, // Vector compare equal.
93 VCEQZ, // Vector compare equal to zero.
94 VCGE, // Vector compare greater than or equal.
95 VCGEZ, // Vector compare greater than or equal to zero.
96 VCLEZ, // Vector compare less than or equal to zero.
97 VCGEU, // Vector compare unsigned greater than or equal.
98 VCGT, // Vector compare greater than.
99 VCGTZ, // Vector compare greater than zero.
100 VCLTZ, // Vector compare less than zero.
101 VCGTU, // Vector compare unsigned greater than.
102 VTST, // Vector test bits.
104 // Vector shift by immediate:
106 VSHRs, // ...right (signed)
107 VSHRu, // ...right (unsigned)
108 VSHLLs, // ...left long (signed)
109 VSHLLu, // ...left long (unsigned)
110 VSHLLi, // ...left long (with maximum shift count)
111 VSHRN, // ...right narrow
113 // Vector rounding shift by immediate:
114 VRSHRs, // ...right (signed)
115 VRSHRu, // ...right (unsigned)
116 VRSHRN, // ...right narrow
118 // Vector saturating shift by immediate:
119 VQSHLs, // ...left (signed)
120 VQSHLu, // ...left (unsigned)
121 VQSHLsu, // ...left (signed to unsigned)
122 VQSHRNs, // ...right narrow (signed)
123 VQSHRNu, // ...right narrow (unsigned)
124 VQSHRNsu, // ...right narrow (signed to unsigned)
126 // Vector saturating rounding shift by immediate:
127 VQRSHRNs, // ...right narrow (signed)
128 VQRSHRNu, // ...right narrow (unsigned)
129 VQRSHRNsu, // ...right narrow (signed to unsigned)
131 // Vector shift and insert:
135 // Vector get lane (VMOV scalar to ARM core register)
136 // (These are used for 8- and 16-bit element types only.)
137 VGETLANEu, // zero-extend vector extract element
138 VGETLANEs, // sign-extend vector extract element
140 // Vector move immediate and move negated immediate:
150 VREV64, // reverse elements within 64-bit doublewords
151 VREV32, // reverse elements within 32-bit words
152 VREV16, // reverse elements within 16-bit halfwords
153 VZIP, // zip (interleave)
154 VUZP, // unzip (deinterleave)
156 VTBL1, // 1-register shuffle with mask
157 VTBL2, // 2-register shuffle with mask
159 // Vector multiply long:
161 VMULLu, // ...unsigned
163 // Operands of the standard BUILD_VECTOR node are not legalized, which
164 // is fine if BUILD_VECTORs are always lowered to shuffles or other
165 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
166 // operands need to be legalized. Define an ARM-specific version of
167 // BUILD_VECTOR for this purpose.
170 // Floating-point max and min:
177 // Vector OR with immediate
179 // Vector AND with NOT of immediate
182 // Vector load N-element structure to all lanes:
183 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
187 // NEON loads with post-increment base updates:
199 // NEON stores with post-increment base updates:
210 /// Define some predicates that are used for node matching.
212 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
213 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
214 /// instruction, returns its 8-bit integer representation. Otherwise,
216 int getVFPf32Imm(const APFloat &FPImm);
217 int getVFPf64Imm(const APFloat &FPImm);
218 bool isBitFieldInvertedMask(unsigned v);
221 //===--------------------------------------------------------------------===//
222 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
224 class ARMTargetLowering : public TargetLowering {
226 explicit ARMTargetLowering(TargetMachine &TM);
228 virtual unsigned getJumpTableEncoding(void) const;
230 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
232 /// ReplaceNodeResults - Replace the results of node with an illegal result
233 /// type with new values built out of custom code.
235 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
236 SelectionDAG &DAG) const;
238 virtual const char *getTargetNodeName(unsigned Opcode) const;
240 virtual MachineBasicBlock *
241 EmitInstrWithCustomInserter(MachineInstr *MI,
242 MachineBasicBlock *MBB) const;
244 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
246 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
248 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
249 /// unaligned memory accesses. of the specified type.
250 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
251 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
253 /// isLegalAddressingMode - Return true if the addressing mode represented
254 /// by AM is legal for this target, for a load/store of the specified type.
255 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
256 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
258 /// isLegalICmpImmediate - Return true if the specified immediate is legal
259 /// icmp immediate, that is the target has icmp instructions which can
260 /// compare a register against the immediate without having to materialize
261 /// the immediate into a register.
262 virtual bool isLegalICmpImmediate(int64_t Imm) const;
264 /// getPreIndexedAddressParts - returns true by value, base pointer and
265 /// offset pointer and addressing mode by reference if the node's address
266 /// can be legally represented as pre-indexed load / store address.
267 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
269 ISD::MemIndexedMode &AM,
270 SelectionDAG &DAG) const;
272 /// getPostIndexedAddressParts - returns true by value, base pointer and
273 /// offset pointer and addressing mode by reference if this node can be
274 /// combined with a load / store to form a post-indexed load / store.
275 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
276 SDValue &Base, SDValue &Offset,
277 ISD::MemIndexedMode &AM,
278 SelectionDAG &DAG) const;
280 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
284 const SelectionDAG &DAG,
285 unsigned Depth) const;
288 virtual bool ExpandInlineAsm(CallInst *CI) const;
290 ConstraintType getConstraintType(const std::string &Constraint) const;
292 /// Examine constraint string and operand type and determine a weight value.
293 /// The operand object must already have been set up with the operand type.
294 ConstraintWeight getSingleConstraintMatchWeight(
295 AsmOperandInfo &info, const char *constraint) const;
297 std::pair<unsigned, const TargetRegisterClass*>
298 getRegForInlineAsmConstraint(const std::string &Constraint,
300 std::vector<unsigned>
301 getRegClassForInlineAsmConstraint(const std::string &Constraint,
304 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
305 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
306 /// true it means one of the asm constraint of the inline asm instruction
307 /// being processed is 'm'.
308 virtual void LowerAsmOperandForConstraint(SDValue Op,
309 char ConstraintLetter,
310 std::vector<SDValue> &Ops,
311 SelectionDAG &DAG) const;
313 const ARMSubtarget* getSubtarget() const {
317 /// getRegClassFor - Return the register class that should be used for the
318 /// specified value type.
319 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
321 /// getFunctionAlignment - Return the Log2 alignment of this function.
322 virtual unsigned getFunctionAlignment(const Function *F) const;
324 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
325 /// be used for loads / stores from the global.
326 virtual unsigned getMaximalGlobalOffset() const;
328 /// createFastISel - This method returns a target specific FastISel object,
329 /// or null if the target does not support "fast" ISel.
330 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
332 Sched::Preference getSchedulingPreference(SDNode *N) const;
334 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
335 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
337 /// isFPImmLegal - Returns true if the target can instruction select the
338 /// specified FP immediate natively. If false, the legalizer will
339 /// materialize the FP immediate as a load from a constant pool.
340 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
342 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
344 unsigned Intrinsic) const;
346 std::pair<const TargetRegisterClass*, uint8_t>
347 findRepresentativeClass(EVT VT) const;
350 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
351 /// make the right decision when generating code for different targets.
352 const ARMSubtarget *Subtarget;
354 const TargetRegisterInfo *RegInfo;
356 const InstrItineraryData *Itins;
358 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
360 unsigned ARMPCLabelIndex;
362 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
363 void addDRTypeForNEON(EVT VT);
364 void addQRTypeForNEON(EVT VT);
366 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
367 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
368 SDValue Chain, SDValue &Arg,
369 RegsToPassVector &RegsToPass,
370 CCValAssign &VA, CCValAssign &NextVA,
372 SmallVector<SDValue, 8> &MemOpChains,
373 ISD::ArgFlagsTy Flags) const;
374 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
375 SDValue &Root, SelectionDAG &DAG,
378 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
379 bool isVarArg) const;
380 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
381 DebugLoc dl, SelectionDAG &DAG,
382 const CCValAssign &VA,
383 ISD::ArgFlagsTy Flags) const;
384 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
385 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
386 SDValue LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) const;
387 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
388 const ARMSubtarget *Subtarget) const;
389 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
390 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
391 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
392 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
393 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
394 SelectionDAG &DAG) const;
395 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
396 SelectionDAG &DAG) const;
397 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
398 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
399 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
400 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
401 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
402 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
403 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
404 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
405 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
406 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
407 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
408 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
409 const ARMSubtarget *ST) const;
411 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
413 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
414 CallingConv::ID CallConv, bool isVarArg,
415 const SmallVectorImpl<ISD::InputArg> &Ins,
416 DebugLoc dl, SelectionDAG &DAG,
417 SmallVectorImpl<SDValue> &InVals) const;
420 LowerFormalArguments(SDValue Chain,
421 CallingConv::ID CallConv, bool isVarArg,
422 const SmallVectorImpl<ISD::InputArg> &Ins,
423 DebugLoc dl, SelectionDAG &DAG,
424 SmallVectorImpl<SDValue> &InVals) const;
427 LowerCall(SDValue Chain, SDValue Callee,
428 CallingConv::ID CallConv, bool isVarArg,
430 const SmallVectorImpl<ISD::OutputArg> &Outs,
431 const SmallVectorImpl<SDValue> &OutVals,
432 const SmallVectorImpl<ISD::InputArg> &Ins,
433 DebugLoc dl, SelectionDAG &DAG,
434 SmallVectorImpl<SDValue> &InVals) const;
436 /// HandleByVal - Target-specific cleanup for ByVal support.
437 virtual void HandleByVal(CCState *) const;
439 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
440 /// for tail call optimization. Targets which want to do tail call
441 /// optimization should implement this function.
442 bool IsEligibleForTailCallOptimization(SDValue Callee,
443 CallingConv::ID CalleeCC,
445 bool isCalleeStructRet,
446 bool isCallerStructRet,
447 const SmallVectorImpl<ISD::OutputArg> &Outs,
448 const SmallVectorImpl<SDValue> &OutVals,
449 const SmallVectorImpl<ISD::InputArg> &Ins,
450 SelectionDAG& DAG) const;
452 LowerReturn(SDValue Chain,
453 CallingConv::ID CallConv, bool isVarArg,
454 const SmallVectorImpl<ISD::OutputArg> &Outs,
455 const SmallVectorImpl<SDValue> &OutVals,
456 DebugLoc dl, SelectionDAG &DAG) const;
458 virtual bool isUsedByReturnOnly(SDNode *N) const;
460 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
461 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
462 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
463 SelectionDAG &DAG, DebugLoc dl) const;
464 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
466 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
468 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
469 MachineBasicBlock *BB,
470 unsigned Size) const;
471 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
472 MachineBasicBlock *BB,
474 unsigned BinOpcode) const;
478 enum NEONModImmType {
486 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
490 #endif // ARMISELLOWERING_H