1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/FastISel.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
26 class ARMConstantPoolValue;
29 // ARM Specific DAG Nodes
31 // Start the numbering where the builtin ops and target ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
36 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
38 CALL, // Function call.
39 CALL_PRED, // Function call that's predicable.
40 CALL_NOLINK, // Function call with branch not branch-and-link.
41 tCALL, // Thumb function call.
42 BRCOND, // Conditional branch.
43 BR_JT, // Jumptable branch.
44 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
45 RET_FLAG, // Return with a flag operand.
47 PIC_ADD, // Add with a PC operand and a PIC label.
49 CMP, // ARM compare instructions.
50 CMPZ, // ARM compare that sets only Z flag.
51 CMPFP, // ARM VFP compare instruction, sets FPSCR.
52 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
53 FMSTAT, // ARM fmstat instruction.
54 CMOV, // ARM conditional move instructions.
55 CNEG, // ARM conditional negate instructions.
59 RBIT, // ARM bitreverse instruction
61 FTOSI, // FP to sint within a FP register.
62 FTOUI, // FP to uint within a FP register.
63 SITOF, // sint to FP within a FP register.
64 UITOF, // uint to FP within a FP register.
66 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
67 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
68 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
70 VMOVRRD, // double to two gprs.
71 VMOVDRR, // Two gprs to double.
73 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
74 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
76 TC_RETURN, // Tail call return pseudo.
80 DYN_ALLOC, // Dynamic allocation on the stack.
82 MEMBARRIER, // Memory barrier
83 SYNCBARRIER, // Memory sync barrier
85 VCEQ, // Vector compare equal.
86 VCGE, // Vector compare greater than or equal.
87 VCGEU, // Vector compare unsigned greater than or equal.
88 VCGT, // Vector compare greater than.
89 VCGTU, // Vector compare unsigned greater than.
90 VTST, // Vector test bits.
92 // Vector shift by immediate:
94 VSHRs, // ...right (signed)
95 VSHRu, // ...right (unsigned)
96 VSHLLs, // ...left long (signed)
97 VSHLLu, // ...left long (unsigned)
98 VSHLLi, // ...left long (with maximum shift count)
99 VSHRN, // ...right narrow
101 // Vector rounding shift by immediate:
102 VRSHRs, // ...right (signed)
103 VRSHRu, // ...right (unsigned)
104 VRSHRN, // ...right narrow
106 // Vector saturating shift by immediate:
107 VQSHLs, // ...left (signed)
108 VQSHLu, // ...left (unsigned)
109 VQSHLsu, // ...left (signed to unsigned)
110 VQSHRNs, // ...right narrow (signed)
111 VQSHRNu, // ...right narrow (unsigned)
112 VQSHRNsu, // ...right narrow (signed to unsigned)
114 // Vector saturating rounding shift by immediate:
115 VQRSHRNs, // ...right narrow (signed)
116 VQRSHRNu, // ...right narrow (unsigned)
117 VQRSHRNsu, // ...right narrow (signed to unsigned)
119 // Vector shift and insert:
123 // Vector get lane (VMOV scalar to ARM core register)
124 // (These are used for 8- and 16-bit element types only.)
125 VGETLANEu, // zero-extend vector extract element
126 VGETLANEs, // sign-extend vector extract element
128 // Vector move immediate and move negated immediate:
138 VREV64, // reverse elements within 64-bit doublewords
139 VREV32, // reverse elements within 32-bit words
140 VREV16, // reverse elements within 16-bit halfwords
141 VZIP, // zip (interleave)
142 VUZP, // unzip (deinterleave)
145 // Operands of the standard BUILD_VECTOR node are not legalized, which
146 // is fine if BUILD_VECTORs are always lowered to shuffles or other
147 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
148 // operands need to be legalized. Define an ARM-specific version of
149 // BUILD_VECTOR for this purpose.
152 // Floating-point max and min:
161 /// Define some predicates that are used for node matching.
163 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
164 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
165 /// instruction, returns its 8-bit integer representation. Otherwise,
167 int getVFPf32Imm(const APFloat &FPImm);
168 int getVFPf64Imm(const APFloat &FPImm);
169 bool isBitFieldInvertedMask(unsigned v);
172 //===--------------------------------------------------------------------===//
173 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
175 class ARMTargetLowering : public TargetLowering {
177 explicit ARMTargetLowering(TargetMachine &TM);
179 virtual unsigned getJumpTableEncoding(void) const;
181 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
183 /// ReplaceNodeResults - Replace the results of node with an illegal result
184 /// type with new values built out of custom code.
186 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
187 SelectionDAG &DAG) const;
189 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
191 virtual const char *getTargetNodeName(unsigned Opcode) const;
193 virtual MachineBasicBlock *
194 EmitInstrWithCustomInserter(MachineInstr *MI,
195 MachineBasicBlock *MBB) const;
197 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
198 /// unaligned memory accesses. of the specified type.
199 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
200 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
202 /// isLegalAddressingMode - Return true if the addressing mode represented
203 /// by AM is legal for this target, for a load/store of the specified type.
204 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
205 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
207 /// isLegalICmpImmediate - Return true if the specified immediate is legal
208 /// icmp immediate, that is the target has icmp instructions which can
209 /// compare a register against the immediate without having to materialize
210 /// the immediate into a register.
211 virtual bool isLegalICmpImmediate(int64_t Imm) const;
213 /// getPreIndexedAddressParts - returns true by value, base pointer and
214 /// offset pointer and addressing mode by reference if the node's address
215 /// can be legally represented as pre-indexed load / store address.
216 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
218 ISD::MemIndexedMode &AM,
219 SelectionDAG &DAG) const;
221 /// getPostIndexedAddressParts - returns true by value, base pointer and
222 /// offset pointer and addressing mode by reference if this node can be
223 /// combined with a load / store to form a post-indexed load / store.
224 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
225 SDValue &Base, SDValue &Offset,
226 ISD::MemIndexedMode &AM,
227 SelectionDAG &DAG) const;
229 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
233 const SelectionDAG &DAG,
234 unsigned Depth) const;
237 ConstraintType getConstraintType(const std::string &Constraint) const;
238 std::pair<unsigned, const TargetRegisterClass*>
239 getRegForInlineAsmConstraint(const std::string &Constraint,
241 std::vector<unsigned>
242 getRegClassForInlineAsmConstraint(const std::string &Constraint,
245 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
246 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
247 /// true it means one of the asm constraint of the inline asm instruction
248 /// being processed is 'm'.
249 virtual void LowerAsmOperandForConstraint(SDValue Op,
250 char ConstraintLetter,
251 std::vector<SDValue> &Ops,
252 SelectionDAG &DAG) const;
254 const ARMSubtarget* getSubtarget() const {
258 /// getRegClassFor - Return the register class that should be used for the
259 /// specified value type.
260 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
262 /// getFunctionAlignment - Return the Log2 alignment of this function.
263 virtual unsigned getFunctionAlignment(const Function *F) const;
265 /// createFastISel - This method returns a target specific FastISel object,
266 /// or null if the target does not support "fast" ISel.
267 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
269 Sched::Preference getSchedulingPreference(SDNode *N) const;
271 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
272 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
274 /// isFPImmLegal - Returns true if the target can instruction select the
275 /// specified FP immediate natively. If false, the legalizer will
276 /// materialize the FP immediate as a load from a constant pool.
277 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
280 std::pair<const TargetRegisterClass*, uint8_t>
281 findRepresentativeClass(EVT VT) const;
284 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
285 /// make the right decision when generating code for different targets.
286 const ARMSubtarget *Subtarget;
288 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
290 unsigned ARMPCLabelIndex;
292 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
293 void addDRTypeForNEON(EVT VT);
294 void addQRTypeForNEON(EVT VT);
296 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
297 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
298 SDValue Chain, SDValue &Arg,
299 RegsToPassVector &RegsToPass,
300 CCValAssign &VA, CCValAssign &NextVA,
302 SmallVector<SDValue, 8> &MemOpChains,
303 ISD::ArgFlagsTy Flags) const;
304 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
305 SDValue &Root, SelectionDAG &DAG,
308 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
309 bool isVarArg) const;
310 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
311 DebugLoc dl, SelectionDAG &DAG,
312 const CCValAssign &VA,
313 ISD::ArgFlagsTy Flags) const;
314 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
315 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
316 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
317 const ARMSubtarget *Subtarget) const;
318 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
319 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
320 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
321 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
322 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
323 SelectionDAG &DAG) const;
324 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
325 SelectionDAG &DAG) const;
326 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
327 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
328 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
329 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
330 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
331 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
332 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
333 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
334 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
335 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
337 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
338 CallingConv::ID CallConv, bool isVarArg,
339 const SmallVectorImpl<ISD::InputArg> &Ins,
340 DebugLoc dl, SelectionDAG &DAG,
341 SmallVectorImpl<SDValue> &InVals) const;
344 LowerFormalArguments(SDValue Chain,
345 CallingConv::ID CallConv, bool isVarArg,
346 const SmallVectorImpl<ISD::InputArg> &Ins,
347 DebugLoc dl, SelectionDAG &DAG,
348 SmallVectorImpl<SDValue> &InVals) const;
351 LowerCall(SDValue Chain, SDValue Callee,
352 CallingConv::ID CallConv, bool isVarArg,
354 const SmallVectorImpl<ISD::OutputArg> &Outs,
355 const SmallVectorImpl<SDValue> &OutVals,
356 const SmallVectorImpl<ISD::InputArg> &Ins,
357 DebugLoc dl, SelectionDAG &DAG,
358 SmallVectorImpl<SDValue> &InVals) const;
360 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
361 /// for tail call optimization. Targets which want to do tail call
362 /// optimization should implement this function.
363 bool IsEligibleForTailCallOptimization(SDValue Callee,
364 CallingConv::ID CalleeCC,
366 bool isCalleeStructRet,
367 bool isCallerStructRet,
368 const SmallVectorImpl<ISD::OutputArg> &Outs,
369 const SmallVectorImpl<SDValue> &OutVals,
370 const SmallVectorImpl<ISD::InputArg> &Ins,
371 SelectionDAG& DAG) const;
373 LowerReturn(SDValue Chain,
374 CallingConv::ID CallConv, bool isVarArg,
375 const SmallVectorImpl<ISD::OutputArg> &Outs,
376 const SmallVectorImpl<SDValue> &OutVals,
377 DebugLoc dl, SelectionDAG &DAG) const;
379 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
380 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
381 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
382 SelectionDAG &DAG, DebugLoc dl) const;
384 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
386 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
387 MachineBasicBlock *BB,
388 unsigned Size) const;
389 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
390 MachineBasicBlock *BB,
392 unsigned BinOpcode) const;
397 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
401 #endif // ARMISELLOWERING_H