1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // the instruction has a Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 class AddrMode<bits<5> val> {
91 def AddrModeNone : AddrMode<0>;
92 def AddrMode1 : AddrMode<1>;
93 def AddrMode2 : AddrMode<2>;
94 def AddrMode3 : AddrMode<3>;
95 def AddrMode4 : AddrMode<4>;
96 def AddrMode5 : AddrMode<5>;
97 def AddrMode6 : AddrMode<6>;
98 def AddrModeT1_1 : AddrMode<7>;
99 def AddrModeT1_2 : AddrMode<8>;
100 def AddrModeT1_4 : AddrMode<9>;
101 def AddrModeT1_s : AddrMode<10>;
102 def AddrModeT2_i12 : AddrMode<11>;
103 def AddrModeT2_i8 : AddrMode<12>;
104 def AddrModeT2_so : AddrMode<13>;
105 def AddrModeT2_pc : AddrMode<14>;
106 def AddrModeT2_i8s4 : AddrMode<15>;
107 def AddrMode_i12 : AddrMode<16>;
110 class SizeFlagVal<bits<3> val> {
113 def SizeInvalid : SizeFlagVal<0>; // Unset.
114 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
115 def Size8Bytes : SizeFlagVal<2>;
116 def Size4Bytes : SizeFlagVal<3>;
117 def Size2Bytes : SizeFlagVal<4>;
119 // Load / store index mode.
120 class IndexMode<bits<2> val> {
123 def IndexModeNone : IndexMode<0>;
124 def IndexModePre : IndexMode<1>;
125 def IndexModePost : IndexMode<2>;
126 def IndexModeUpd : IndexMode<3>;
128 // Instruction execution domain.
129 class Domain<bits<2> val> {
132 def GenericDomain : Domain<0>;
133 def VFPDomain : Domain<1>; // Instructions in VFP domain only
134 def NeonDomain : Domain<2>; // Instructions in Neon domain only
135 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
137 //===----------------------------------------------------------------------===//
139 // ARM special operands.
142 def CondCodeOperand : AsmOperandClass {
143 let Name = "CondCode";
144 let SuperClasses = [];
147 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
148 // register whose default is 0 (no register).
149 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
150 (ops (i32 14), (i32 zero_reg))> {
151 let PrintMethod = "printPredicateOperand";
152 let ParserMatchClass = CondCodeOperand;
155 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
156 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
157 string EncoderMethod = "getCCOutOpValue";
158 let PrintMethod = "printSBitModifierOperand";
161 // Same as cc_out except it defaults to setting CPSR.
162 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
163 string EncoderMethod = "getCCOutOpValue";
164 let PrintMethod = "printSBitModifierOperand";
167 // ARM special operands for disassembly only.
169 def setend_op : Operand<i32> {
170 let PrintMethod = "printSetendOperand";
173 def cps_opt : Operand<i32> {
174 let PrintMethod = "printCPSOptionOperand";
177 def msr_mask : Operand<i32> {
178 let PrintMethod = "printMSRMaskOperand";
181 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
182 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
183 def neg_zero : Operand<i32> {
184 let PrintMethod = "printNegZeroOperand";
187 //===----------------------------------------------------------------------===//
189 // ARM Instruction templates.
192 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
193 Format f, Domain d, string cstr, InstrItinClass itin>
195 let Namespace = "ARM";
200 bits<2> IndexModeBits = IM.Value;
202 bits<6> Form = F.Value;
204 bit isUnaryDataProc = 0;
205 bit canXformTo16Bit = 0;
207 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
208 let TSFlags{4-0} = AM.Value;
209 let TSFlags{7-5} = SZ.Value;
210 let TSFlags{9-8} = IndexModeBits;
211 let TSFlags{15-10} = Form;
212 let TSFlags{16} = isUnaryDataProc;
213 let TSFlags{17} = canXformTo16Bit;
214 let TSFlags{19-18} = D.Value;
216 let Constraints = cstr;
217 let Itinerary = itin;
224 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
225 Format f, Domain d, string cstr, InstrItinClass itin>
226 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
228 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
229 // on by adding flavors to specific instructions.
230 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
231 Format f, Domain d, string cstr, InstrItinClass itin>
232 : InstTemplate<am, sz, im, f, d, cstr, itin>;
234 class PseudoInst<dag oops, dag iops, InstrItinClass itin,
235 string asm, list<dag> pattern>
236 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
238 let OutOperandList = oops;
239 let InOperandList = iops;
241 let Pattern = pattern;
244 // Almost all ARM instructions are predicable.
245 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
246 IndexMode im, Format f, InstrItinClass itin,
247 string opc, string asm, string cstr,
249 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
252 let OutOperandList = oops;
253 let InOperandList = !con(iops, (ins pred:$p));
254 let AsmString = !strconcat(opc, "${p}", asm);
255 let Pattern = pattern;
256 list<Predicate> Predicates = [IsARM];
259 // A few are not predicable
260 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
261 IndexMode im, Format f, InstrItinClass itin,
262 string opc, string asm, string cstr,
264 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
265 let OutOperandList = oops;
266 let InOperandList = iops;
267 let AsmString = !strconcat(opc, asm);
268 let Pattern = pattern;
269 let isPredicable = 0;
270 list<Predicate> Predicates = [IsARM];
273 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
274 // operand since by default it's a zero register. It will become an implicit def
275 // once it's "flipped".
276 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
277 IndexMode im, Format f, InstrItinClass itin,
278 string opc, string asm, string cstr,
280 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
281 bits<4> p; // Predicate operand
282 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
286 let OutOperandList = oops;
287 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
288 let AsmString = !strconcat(opc, "${s}${p}", asm);
289 let Pattern = pattern;
290 list<Predicate> Predicates = [IsARM];
294 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
295 IndexMode im, Format f, InstrItinClass itin,
296 string asm, string cstr, list<dag> pattern>
297 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
298 let OutOperandList = oops;
299 let InOperandList = iops;
301 let Pattern = pattern;
302 list<Predicate> Predicates = [IsARM];
305 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
306 string opc, string asm, list<dag> pattern>
307 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
308 opc, asm, "", pattern>;
309 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
310 string opc, string asm, list<dag> pattern>
311 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
312 opc, asm, "", pattern>;
313 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
314 string asm, list<dag> pattern>
315 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
317 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
318 string opc, string asm, list<dag> pattern>
319 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
320 opc, asm, "", pattern>;
322 // Ctrl flow instructions
323 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
324 string opc, string asm, list<dag> pattern>
325 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
326 opc, asm, "", pattern> {
327 let Inst{27-24} = opcod;
329 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
330 string asm, list<dag> pattern>
331 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
333 let Inst{27-24} = opcod;
335 class ABXIx2<dag oops, dag iops, InstrItinClass itin,
336 string asm, list<dag> pattern>
337 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, Pseudo, itin,
340 // BR_JT instructions
341 class JTI<dag oops, dag iops, InstrItinClass itin,
342 string asm, list<dag> pattern>
343 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
346 // Atomic load/store instructions
347 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
348 string opc, string asm, list<dag> pattern>
349 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
350 opc, asm, "", pattern> {
353 let Inst{27-23} = 0b00011;
354 let Inst{22-21} = opcod;
356 let Inst{19-16} = Rn;
357 let Inst{15-12} = Rt;
358 let Inst{11-0} = 0b111110011111;
360 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
361 string opc, string asm, list<dag> pattern>
362 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
363 opc, asm, "", pattern> {
367 let Inst{27-23} = 0b00011;
368 let Inst{22-21} = opcod;
370 let Inst{19-16} = Rn;
371 let Inst{15-12} = Rd;
372 let Inst{11-4} = 0b11111001;
375 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
376 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
380 let Inst{27-23} = 0b00010;
382 let Inst{21-20} = 0b00;
383 let Inst{19-16} = Rn;
384 let Inst{15-12} = Rt;
385 let Inst{11-4} = 0b00001001;
389 // addrmode1 instructions
390 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
391 string opc, string asm, list<dag> pattern>
392 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
393 opc, asm, "", pattern> {
394 let Inst{24-21} = opcod;
395 let Inst{27-26} = 0b00;
397 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
398 string opc, string asm, list<dag> pattern>
399 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
400 opc, asm, "", pattern> {
401 let Inst{24-21} = opcod;
402 let Inst{27-26} = 0b00;
404 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
405 string asm, list<dag> pattern>
406 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
408 let Inst{24-21} = opcod;
409 let Inst{27-26} = 0b00;
411 class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
412 string opc, string asm, list<dag> pattern>
413 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
414 opc, asm, "", pattern>;
417 // addrmode2 loads and stores
418 class AI2<dag oops, dag iops, Format f, InstrItinClass itin,
419 string opc, string asm, list<dag> pattern>
420 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
421 opc, asm, "", pattern> {
422 let Inst{27-26} = 0b01;
428 class AIldst1<bits<3> op, bit opc22, bit isLd, dag oops, dag iops, AddrMode am,
429 Format f, InstrItinClass itin, string opc, string asm,
431 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
433 let Inst{27-25} = op;
434 let Inst{24} = 1; // 24 == P
436 let Inst{22} = opc22;
437 let Inst{21} = 0; // 21 == W
440 // LDRH/LDRSB/LDRSH/LDRD
441 class AIldr2<bits<4> op, bit opc22, bit opc20, dag oops, dag iops, AddrMode am,
442 Format f, InstrItinClass itin, string opc, string asm,
444 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
446 let Inst{27-25} = 0b000;
447 let Inst{24} = 1; // 24 == P
449 let Inst{22} = opc22;
450 let Inst{21} = 0; // 21 == W
451 let Inst{20} = opc20;
459 class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
460 string opc, string asm, list<dag> pattern>
461 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
462 opc, asm, "", pattern> {
463 let Inst{20} = 1; // L bit
464 let Inst{21} = 0; // W bit
465 let Inst{22} = 0; // B bit
466 let Inst{24} = 1; // P bit
467 let Inst{27-26} = 0b01;
469 class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
470 string asm, list<dag> pattern>
471 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
473 let Inst{20} = 1; // L bit
474 let Inst{21} = 0; // W bit
475 let Inst{22} = 0; // B bit
476 let Inst{24} = 1; // P bit
477 let Inst{27-26} = 0b01;
479 class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
480 string opc, string asm, list<dag> pattern>
481 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
482 opc, asm, "", pattern> {
483 let Inst{20} = 1; // L bit
484 let Inst{21} = 0; // W bit
485 let Inst{22} = 1; // B bit
486 let Inst{24} = 1; // P bit
487 let Inst{27-26} = 0b01;
489 class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
490 string asm, list<dag> pattern>
491 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
493 let Inst{20} = 1; // L bit
494 let Inst{21} = 0; // W bit
495 let Inst{22} = 1; // B bit
496 let Inst{24} = 1; // P bit
497 let Inst{27-26} = 0b01;
501 class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
502 string opc, string asm, list<dag> pattern>
503 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
504 opc, asm, "", pattern> {
505 let Inst{20} = 0; // L bit
506 let Inst{21} = 0; // W bit
507 let Inst{22} = 0; // B bit
508 let Inst{24} = 1; // P bit
509 let Inst{27-26} = 0b01;
511 class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
512 string asm, list<dag> pattern>
513 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
515 let Inst{20} = 0; // L bit
516 let Inst{21} = 0; // W bit
517 let Inst{22} = 0; // B bit
518 let Inst{24} = 1; // P bit
519 let Inst{27-26} = 0b01;
521 class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
522 string opc, string asm, list<dag> pattern>
523 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
524 opc, asm, "", pattern> {
525 let Inst{20} = 0; // L bit
526 let Inst{21} = 0; // W bit
527 let Inst{22} = 1; // B bit
528 let Inst{24} = 1; // P bit
529 let Inst{27-26} = 0b01;
531 class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
532 string asm, list<dag> pattern>
533 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
535 let Inst{20} = 0; // L bit
536 let Inst{21} = 0; // W bit
537 let Inst{22} = 1; // B bit
538 let Inst{24} = 1; // P bit
539 let Inst{27-26} = 0b01;
543 class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
544 string opc, string asm, string cstr, list<dag> pattern>
545 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
546 opc, asm, cstr, pattern> {
547 let Inst{20} = 1; // L bit
548 let Inst{21} = 1; // W bit
549 let Inst{22} = 0; // B bit
550 let Inst{24} = 1; // P bit
551 let Inst{27-26} = 0b01;
553 class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
554 string opc, string asm, string cstr, list<dag> pattern>
555 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
556 opc, asm, cstr, pattern> {
557 let Inst{20} = 1; // L bit
558 let Inst{21} = 1; // W bit
559 let Inst{22} = 1; // B bit
560 let Inst{24} = 1; // P bit
561 let Inst{27-26} = 0b01;
564 // Pre-indexed stores
565 class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
566 string opc, string asm, string cstr, list<dag> pattern>
567 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
568 opc, asm, cstr, pattern> {
569 let Inst{20} = 0; // L bit
570 let Inst{21} = 1; // W bit
571 let Inst{22} = 0; // B bit
572 let Inst{24} = 1; // P bit
573 let Inst{27-26} = 0b01;
575 class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
576 string opc, string asm, string cstr, list<dag> pattern>
577 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
578 opc, asm, cstr, pattern> {
579 let Inst{20} = 0; // L bit
580 let Inst{21} = 1; // W bit
581 let Inst{22} = 1; // B bit
582 let Inst{24} = 1; // P bit
583 let Inst{27-26} = 0b01;
586 // Post-indexed loads
587 class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
588 string opc, string asm, string cstr, list<dag> pattern>
589 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
590 opc, asm, cstr,pattern> {
591 let Inst{20} = 1; // L bit
592 let Inst{21} = 0; // W bit
593 let Inst{22} = 0; // B bit
594 let Inst{24} = 0; // P bit
595 let Inst{27-26} = 0b01;
597 class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
598 string opc, string asm, string cstr, list<dag> pattern>
599 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
600 opc, asm, cstr,pattern> {
601 let Inst{20} = 1; // L bit
602 let Inst{21} = 0; // W bit
603 let Inst{22} = 1; // B bit
604 let Inst{24} = 0; // P bit
605 let Inst{27-26} = 0b01;
608 // Post-indexed stores
609 class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
610 string opc, string asm, string cstr, list<dag> pattern>
611 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
612 opc, asm, cstr,pattern> {
613 let Inst{20} = 0; // L bit
614 let Inst{21} = 0; // W bit
615 let Inst{22} = 0; // B bit
616 let Inst{24} = 0; // P bit
617 let Inst{27-26} = 0b01;
619 class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
620 string opc, string asm, string cstr, list<dag> pattern>
621 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
622 opc, asm, cstr,pattern> {
623 let Inst{20} = 0; // L bit
624 let Inst{21} = 0; // W bit
625 let Inst{22} = 1; // B bit
626 let Inst{24} = 0; // P bit
627 let Inst{27-26} = 0b01;
630 // addrmode3 instructions
631 class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
632 string opc, string asm, list<dag> pattern>
633 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
634 opc, asm, "", pattern>;
635 class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
636 string asm, list<dag> pattern>
637 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
641 class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
642 string opc, string asm, list<dag> pattern>
643 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
644 opc, asm, "", pattern> {
646 let Inst{5} = 1; // H bit
647 let Inst{6} = 0; // S bit
649 let Inst{20} = 1; // L bit
650 let Inst{21} = 0; // W bit
651 let Inst{24} = 1; // P bit
652 let Inst{27-25} = 0b000;
654 class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
655 string asm, list<dag> pattern>
656 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
659 let Inst{5} = 1; // H bit
660 let Inst{6} = 0; // S bit
662 let Inst{20} = 1; // L bit
663 let Inst{21} = 0; // W bit
664 let Inst{24} = 1; // P bit
666 class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
667 string opc, string asm, list<dag> pattern>
668 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
669 opc, asm, "", pattern> {
671 let Inst{5} = 1; // H bit
672 let Inst{6} = 1; // S bit
674 let Inst{20} = 1; // L bit
675 let Inst{21} = 0; // W bit
676 let Inst{24} = 1; // P bit
677 let Inst{27-25} = 0b000;
679 class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
680 string asm, list<dag> pattern>
681 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
684 let Inst{5} = 1; // H bit
685 let Inst{6} = 1; // S bit
687 let Inst{20} = 1; // L bit
688 let Inst{21} = 0; // W bit
689 let Inst{24} = 1; // P bit
691 class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
692 string opc, string asm, list<dag> pattern>
693 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
694 opc, asm, "", pattern> {
696 let Inst{5} = 0; // H bit
697 let Inst{6} = 1; // S bit
699 let Inst{20} = 1; // L bit
700 let Inst{21} = 0; // W bit
701 let Inst{24} = 1; // P bit
702 let Inst{27-25} = 0b000;
704 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
705 string asm, list<dag> pattern>
706 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
709 let Inst{5} = 0; // H bit
710 let Inst{6} = 1; // S bit
712 let Inst{20} = 1; // L bit
713 let Inst{21} = 0; // W bit
714 let Inst{24} = 1; // P bit
716 class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
717 string opc, string asm, list<dag> pattern>
718 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
719 opc, asm, "", pattern> {
721 let Inst{5} = 0; // H bit
722 let Inst{6} = 1; // S bit
724 let Inst{20} = 0; // L bit
725 let Inst{21} = 0; // W bit
726 let Inst{24} = 1; // P bit
727 let Inst{27-25} = 0b000;
731 class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
732 string opc, string asm, list<dag> pattern>
733 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
734 opc, asm, "", pattern> {
736 let Inst{5} = 1; // H bit
737 let Inst{6} = 0; // S bit
739 let Inst{20} = 0; // L bit
740 let Inst{21} = 0; // W bit
741 let Inst{24} = 1; // P bit
742 let Inst{27-25} = 0b000;
744 class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
745 string asm, list<dag> pattern>
746 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
749 let Inst{5} = 1; // H bit
750 let Inst{6} = 0; // S bit
752 let Inst{20} = 0; // L bit
753 let Inst{21} = 0; // W bit
754 let Inst{24} = 1; // P bit
756 class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
757 string opc, string asm, list<dag> pattern>
758 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
759 opc, asm, "", pattern> {
761 let Inst{5} = 1; // H bit
762 let Inst{6} = 1; // S bit
764 let Inst{20} = 0; // L bit
765 let Inst{21} = 0; // W bit
766 let Inst{24} = 1; // P bit
767 let Inst{27-25} = 0b000;
771 class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
772 string opc, string asm, string cstr, list<dag> pattern>
773 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
774 opc, asm, cstr, pattern> {
776 let Inst{5} = 1; // H bit
777 let Inst{6} = 0; // S bit
779 let Inst{20} = 1; // L bit
780 let Inst{21} = 1; // W bit
781 let Inst{24} = 1; // P bit
782 let Inst{27-25} = 0b000;
784 class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
785 string opc, string asm, string cstr, list<dag> pattern>
786 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
787 opc, asm, cstr, pattern> {
789 let Inst{5} = 1; // H bit
790 let Inst{6} = 1; // S bit
792 let Inst{20} = 1; // L bit
793 let Inst{21} = 1; // W bit
794 let Inst{24} = 1; // P bit
795 let Inst{27-25} = 0b000;
797 class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
798 string opc, string asm, string cstr, list<dag> pattern>
799 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
800 opc, asm, cstr, pattern> {
802 let Inst{5} = 0; // H bit
803 let Inst{6} = 1; // S bit
805 let Inst{20} = 1; // L bit
806 let Inst{21} = 1; // W bit
807 let Inst{24} = 1; // P bit
808 let Inst{27-25} = 0b000;
810 class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin,
811 string opc, string asm, string cstr, list<dag> pattern>
812 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
813 opc, asm, cstr, pattern> {
815 let Inst{5} = 0; // H bit
816 let Inst{6} = 1; // S bit
818 let Inst{20} = 0; // L bit
819 let Inst{21} = 1; // W bit
820 let Inst{24} = 1; // P bit
821 let Inst{27-25} = 0b000;
825 // Pre-indexed stores
826 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
827 string opc, string asm, string cstr, list<dag> pattern>
828 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
829 opc, asm, cstr, pattern> {
831 let Inst{5} = 1; // H bit
832 let Inst{6} = 0; // S bit
834 let Inst{20} = 0; // L bit
835 let Inst{21} = 1; // W bit
836 let Inst{24} = 1; // P bit
837 let Inst{27-25} = 0b000;
839 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
840 string opc, string asm, string cstr, list<dag> pattern>
841 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
842 opc, asm, cstr, pattern> {
844 let Inst{5} = 1; // H bit
845 let Inst{6} = 1; // S bit
847 let Inst{20} = 0; // L bit
848 let Inst{21} = 1; // W bit
849 let Inst{24} = 1; // P bit
850 let Inst{27-25} = 0b000;
853 // Post-indexed loads
854 class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
855 string opc, string asm, string cstr, list<dag> pattern>
856 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
857 opc, asm, cstr,pattern> {
859 let Inst{5} = 1; // H bit
860 let Inst{6} = 0; // S bit
862 let Inst{20} = 1; // L bit
863 let Inst{21} = 0; // W bit
864 let Inst{24} = 0; // P bit
865 let Inst{27-25} = 0b000;
867 class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
868 string opc, string asm, string cstr, list<dag> pattern>
869 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
870 opc, asm, cstr,pattern> {
872 let Inst{5} = 1; // H bit
873 let Inst{6} = 1; // S bit
875 let Inst{20} = 1; // L bit
876 let Inst{21} = 0; // W bit
877 let Inst{24} = 0; // P bit
878 let Inst{27-25} = 0b000;
880 class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
881 string opc, string asm, string cstr, list<dag> pattern>
882 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
883 opc, asm, cstr,pattern> {
885 let Inst{5} = 0; // H bit
886 let Inst{6} = 1; // S bit
888 let Inst{20} = 1; // L bit
889 let Inst{21} = 0; // W bit
890 let Inst{24} = 0; // P bit
891 let Inst{27-25} = 0b000;
893 class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin,
894 string opc, string asm, string cstr, list<dag> pattern>
895 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
896 opc, asm, cstr, pattern> {
898 let Inst{5} = 0; // H bit
899 let Inst{6} = 1; // S bit
901 let Inst{20} = 0; // L bit
902 let Inst{21} = 0; // W bit
903 let Inst{24} = 0; // P bit
904 let Inst{27-25} = 0b000;
907 // Post-indexed stores
908 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
909 string opc, string asm, string cstr, list<dag> pattern>
910 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
911 opc, asm, cstr,pattern> {
913 let Inst{5} = 1; // H bit
914 let Inst{6} = 0; // S bit
916 let Inst{20} = 0; // L bit
917 let Inst{21} = 0; // W bit
918 let Inst{24} = 0; // P bit
919 let Inst{27-25} = 0b000;
921 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
922 string opc, string asm, string cstr, list<dag> pattern>
923 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
924 opc, asm, cstr, pattern> {
926 let Inst{5} = 1; // H bit
927 let Inst{6} = 1; // S bit
929 let Inst{20} = 0; // L bit
930 let Inst{21} = 0; // W bit
931 let Inst{24} = 0; // P bit
932 let Inst{27-25} = 0b000;
935 // addrmode4 instructions
936 class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
937 string asm, string cstr, list<dag> pattern>
938 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
939 asm, cstr, pattern> {
940 let Inst{20} = 1; // L bit
941 let Inst{22} = 0; // S bit
942 let Inst{27-25} = 0b100;
944 class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
945 string asm, string cstr, list<dag> pattern>
946 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
947 asm, cstr, pattern> {
948 let Inst{20} = 0; // L bit
949 let Inst{22} = 0; // S bit
950 let Inst{27-25} = 0b100;
953 // Unsigned multiply, multiply-accumulate instructions.
954 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
955 string opc, string asm, list<dag> pattern>
956 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
957 opc, asm, "", pattern> {
958 let Inst{7-4} = 0b1001;
959 let Inst{20} = 0; // S bit
960 let Inst{27-21} = opcod;
962 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
963 string opc, string asm, list<dag> pattern>
964 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
965 opc, asm, "", pattern> {
966 let Inst{7-4} = 0b1001;
967 let Inst{27-21} = opcod;
970 // Most significant word multiply
971 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
972 InstrItinClass itin, string opc, string asm, list<dag> pattern>
973 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
974 opc, asm, "", pattern> {
978 let Inst{7-4} = opc7_4;
980 let Inst{27-21} = opcod;
981 let Inst{19-16} = Rd;
985 // MSW multiple w/ Ra operand
986 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
987 InstrItinClass itin, string opc, string asm, list<dag> pattern>
988 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
990 let Inst{15-12} = Ra;
993 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
994 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
995 InstrItinClass itin, string opc, string asm, list<dag> pattern>
996 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
997 opc, asm, "", pattern> {
1003 let Inst{27-21} = opcod;
1004 let Inst{6-5} = bit6_5;
1005 let Inst{11-8} = Rm;
1008 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
1009 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1010 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
1012 let Inst{19-16} = Rd;
1015 // AMulxyI with Ra operand
1016 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
1017 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1018 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
1020 let Inst{15-12} = Ra;
1023 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
1024 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1025 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
1028 let Inst{19-16} = RdHi;
1029 let Inst{15-12} = RdLo;
1032 // Extend instructions.
1033 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
1034 string opc, string asm, list<dag> pattern>
1035 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
1036 opc, asm, "", pattern> {
1037 // All AExtI instructions have Rd and Rm register operands.
1040 let Inst{15-12} = Rd;
1042 let Inst{7-4} = 0b0111;
1043 let Inst{9-8} = 0b00;
1044 let Inst{27-20} = opcod;
1047 // Misc Arithmetic instructions.
1048 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
1049 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1050 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
1051 opc, asm, "", pattern> {
1054 let Inst{27-20} = opcod;
1055 let Inst{19-16} = 0b1111;
1056 let Inst{15-12} = Rd;
1057 let Inst{11-8} = 0b1111;
1058 let Inst{7-4} = opc7_4;
1063 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
1064 string opc, string asm, list<dag> pattern>
1065 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
1066 opc, asm, "", pattern> {
1071 let Inst{27-20} = opcod;
1072 let Inst{19-16} = Rn;
1073 let Inst{15-12} = Rd;
1074 let Inst{11-7} = sh{7-3};
1076 let Inst{5-4} = 0b01;
1080 //===----------------------------------------------------------------------===//
1082 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
1083 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
1084 list<Predicate> Predicates = [IsARM];
1086 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
1087 list<Predicate> Predicates = [IsARM, HasV5TE];
1089 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
1090 list<Predicate> Predicates = [IsARM, HasV6];
1093 //===----------------------------------------------------------------------===//
1095 // Thumb Instruction Format Definitions.
1098 // TI - Thumb instruction.
1100 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1101 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1102 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1103 let OutOperandList = oops;
1104 let InOperandList = iops;
1105 let AsmString = asm;
1106 let Pattern = pattern;
1107 list<Predicate> Predicates = [IsThumb];
1110 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
1111 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
1113 // Two-address instructions
1114 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
1116 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
1119 // tBL, tBX 32-bit instructions
1120 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
1121 dag oops, dag iops, InstrItinClass itin, string asm,
1123 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
1125 let Inst{31-27} = opcod1;
1126 let Inst{15-14} = opcod2;
1127 let Inst{12} = opcod3;
1130 // BR_JT instructions
1131 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
1133 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1136 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1137 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1138 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1139 let OutOperandList = oops;
1140 let InOperandList = iops;
1141 let AsmString = asm;
1142 let Pattern = pattern;
1143 list<Predicate> Predicates = [IsThumb1Only];
1146 class T1I<dag oops, dag iops, InstrItinClass itin,
1147 string asm, list<dag> pattern>
1148 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
1149 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
1150 string asm, list<dag> pattern>
1151 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1152 class T1JTI<dag oops, dag iops, InstrItinClass itin,
1153 string asm, list<dag> pattern>
1154 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1156 // Two-address instructions
1157 class T1It<dag oops, dag iops, InstrItinClass itin,
1158 string asm, string cstr, list<dag> pattern>
1159 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
1160 asm, cstr, pattern>;
1162 // Thumb1 instruction that can either be predicated or set CPSR.
1163 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1164 InstrItinClass itin,
1165 string opc, string asm, string cstr, list<dag> pattern>
1166 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1167 let OutOperandList = !con(oops, (outs s_cc_out:$s));
1168 let InOperandList = !con(iops, (ins pred:$p));
1169 let AsmString = !strconcat(opc, "${s}${p}", asm);
1170 let Pattern = pattern;
1171 list<Predicate> Predicates = [IsThumb1Only];
1174 class T1sI<dag oops, dag iops, InstrItinClass itin,
1175 string opc, string asm, list<dag> pattern>
1176 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1178 // Two-address instructions
1179 class T1sIt<dag oops, dag iops, InstrItinClass itin,
1180 string opc, string asm, list<dag> pattern>
1181 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1182 "$lhs = $dst", pattern>;
1184 // Thumb1 instruction that can be predicated.
1185 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1186 InstrItinClass itin,
1187 string opc, string asm, string cstr, list<dag> pattern>
1188 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1189 let OutOperandList = oops;
1190 let InOperandList = !con(iops, (ins pred:$p));
1191 let AsmString = !strconcat(opc, "${p}", asm);
1192 let Pattern = pattern;
1193 list<Predicate> Predicates = [IsThumb1Only];
1196 class T1pI<dag oops, dag iops, InstrItinClass itin,
1197 string opc, string asm, list<dag> pattern>
1198 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1200 // Two-address instructions
1201 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1202 string opc, string asm, list<dag> pattern>
1203 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1204 "$lhs = $dst", pattern>;
1206 class T1pI1<dag oops, dag iops, InstrItinClass itin,
1207 string opc, string asm, list<dag> pattern>
1208 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
1209 class T1pI2<dag oops, dag iops, InstrItinClass itin,
1210 string opc, string asm, list<dag> pattern>
1211 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
1212 class T1pI4<dag oops, dag iops, InstrItinClass itin,
1213 string opc, string asm, list<dag> pattern>
1214 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
1215 class T1pIs<dag oops, dag iops,
1216 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1217 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
1219 class Encoding16 : Encoding {
1220 let Inst{31-16} = 0x0000;
1223 // A6.2 16-bit Thumb instruction encoding
1224 class T1Encoding<bits<6> opcode> : Encoding16 {
1225 let Inst{15-10} = opcode;
1228 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1229 class T1General<bits<5> opcode> : Encoding16 {
1230 let Inst{15-14} = 0b00;
1231 let Inst{13-9} = opcode;
1234 // A6.2.2 Data-processing encoding.
1235 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1236 let Inst{15-10} = 0b010000;
1237 let Inst{9-6} = opcode;
1240 // A6.2.3 Special data instructions and branch and exchange encoding.
1241 class T1Special<bits<4> opcode> : Encoding16 {
1242 let Inst{15-10} = 0b010001;
1243 let Inst{9-6} = opcode;
1246 // A6.2.4 Load/store single data item encoding.
1247 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1248 let Inst{15-12} = opA;
1249 let Inst{11-9} = opB;
1251 class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
1252 class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
1253 class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
1254 class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
1255 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1257 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1258 class T1Misc<bits<7> opcode> : Encoding16 {
1259 let Inst{15-12} = 0b1011;
1260 let Inst{11-5} = opcode;
1263 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1264 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1265 InstrItinClass itin,
1266 string opc, string asm, string cstr, list<dag> pattern>
1267 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1268 let OutOperandList = oops;
1269 let InOperandList = !con(iops, (ins pred:$p));
1270 let AsmString = !strconcat(opc, "${p}", asm);
1271 let Pattern = pattern;
1272 list<Predicate> Predicates = [IsThumb2];
1275 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1276 // input operand since by default it's a zero register. It will become an
1277 // implicit def once it's "flipped".
1279 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1281 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1282 InstrItinClass itin,
1283 string opc, string asm, string cstr, list<dag> pattern>
1284 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1285 let OutOperandList = oops;
1286 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1287 let AsmString = !strconcat(opc, "${s}${p}", asm);
1288 let Pattern = pattern;
1289 list<Predicate> Predicates = [IsThumb2];
1293 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1294 InstrItinClass itin,
1295 string asm, string cstr, list<dag> pattern>
1296 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1297 let OutOperandList = oops;
1298 let InOperandList = iops;
1299 let AsmString = asm;
1300 let Pattern = pattern;
1301 list<Predicate> Predicates = [IsThumb2];
1304 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1305 InstrItinClass itin,
1306 string asm, string cstr, list<dag> pattern>
1307 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1308 let OutOperandList = oops;
1309 let InOperandList = iops;
1310 let AsmString = asm;
1311 let Pattern = pattern;
1312 list<Predicate> Predicates = [IsThumb1Only];
1315 class T2I<dag oops, dag iops, InstrItinClass itin,
1316 string opc, string asm, list<dag> pattern>
1317 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1318 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1319 string opc, string asm, list<dag> pattern>
1320 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
1321 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1322 string opc, string asm, list<dag> pattern>
1323 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1324 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1325 string opc, string asm, list<dag> pattern>
1326 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1327 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1328 string opc, string asm, list<dag> pattern>
1329 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1330 class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
1331 string opc, string asm, list<dag> pattern>
1332 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1334 let Inst{31-27} = 0b11101;
1335 let Inst{26-25} = 0b00;
1337 let Inst{23} = ?; // The U bit.
1340 let Inst{20} = load;
1343 class T2sI<dag oops, dag iops, InstrItinClass itin,
1344 string opc, string asm, list<dag> pattern>
1345 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1347 class T2XI<dag oops, dag iops, InstrItinClass itin,
1348 string asm, list<dag> pattern>
1349 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1350 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1351 string asm, list<dag> pattern>
1352 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1354 class T2Ix2<dag oops, dag iops, InstrItinClass itin,
1355 string opc, string asm, list<dag> pattern>
1356 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
1358 // Two-address instructions
1359 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1360 string asm, string cstr, list<dag> pattern>
1361 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1363 // T2Iidxldst - Thumb2 indexed load / store instructions.
1364 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1366 AddrMode am, IndexMode im, InstrItinClass itin,
1367 string opc, string asm, string cstr, list<dag> pattern>
1368 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1369 let OutOperandList = oops;
1370 let InOperandList = !con(iops, (ins pred:$p));
1371 let AsmString = !strconcat(opc, "${p}", asm);
1372 let Pattern = pattern;
1373 list<Predicate> Predicates = [IsThumb2];
1374 let Inst{31-27} = 0b11111;
1375 let Inst{26-25} = 0b00;
1376 let Inst{24} = signed;
1378 let Inst{22-21} = opcod;
1379 let Inst{20} = load;
1381 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1382 let Inst{10} = pre; // The P bit.
1383 let Inst{8} = 1; // The W bit.
1386 // Helper class for disassembly only
1387 // A6.3.16 & A6.3.17
1388 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1389 class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
1390 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1391 : T2I<oops, iops, itin, opc, asm, pattern> {
1392 let Inst{31-27} = 0b11111;
1393 let Inst{26-24} = 0b011;
1394 let Inst{23} = long;
1395 let Inst{22-20} = op22_20;
1396 let Inst{7-4} = op7_4;
1399 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1400 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1401 list<Predicate> Predicates = [IsThumb1Only, HasV5T];
1404 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1405 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1406 list<Predicate> Predicates = [IsThumb1Only];
1409 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1410 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1411 list<Predicate> Predicates = [IsThumb2];
1414 //===----------------------------------------------------------------------===//
1416 //===----------------------------------------------------------------------===//
1417 // ARM VFP Instruction templates.
1420 // Almost all VFP instructions are predicable.
1421 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1422 IndexMode im, Format f, InstrItinClass itin,
1423 string opc, string asm, string cstr, list<dag> pattern>
1424 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1426 let Inst{31-28} = p;
1427 let OutOperandList = oops;
1428 let InOperandList = !con(iops, (ins pred:$p));
1429 let AsmString = !strconcat(opc, "${p}", asm);
1430 let Pattern = pattern;
1431 list<Predicate> Predicates = [HasVFP2];
1435 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1436 IndexMode im, Format f, InstrItinClass itin,
1437 string asm, string cstr, list<dag> pattern>
1438 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1439 let OutOperandList = oops;
1440 let InOperandList = iops;
1441 let AsmString = asm;
1442 let Pattern = pattern;
1443 list<Predicate> Predicates = [HasVFP2];
1446 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1447 string opc, string asm, list<dag> pattern>
1448 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1449 opc, asm, "", pattern>;
1451 // ARM VFP addrmode5 loads and stores
1452 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1453 InstrItinClass itin,
1454 string opc, string asm, list<dag> pattern>
1455 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1456 VFPLdStFrm, itin, opc, asm, "", pattern> {
1457 // TODO: Mark the instructions with the appropriate subtarget info.
1458 let Inst{27-24} = opcod1;
1459 let Inst{21-20} = opcod2;
1460 let Inst{11-9} = 0b101;
1461 let Inst{8} = 1; // Double precision
1463 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1464 let D = VFPNeonDomain;
1467 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1468 InstrItinClass itin,
1469 string opc, string asm, list<dag> pattern>
1470 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1471 VFPLdStFrm, itin, opc, asm, "", pattern> {
1472 // TODO: Mark the instructions with the appropriate subtarget info.
1473 let Inst{27-24} = opcod1;
1474 let Inst{21-20} = opcod2;
1475 let Inst{11-9} = 0b101;
1476 let Inst{8} = 0; // Single precision
1479 // VFP Load / store multiple pseudo instructions.
1480 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1482 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain,
1484 let OutOperandList = oops;
1485 let InOperandList = !con(iops, (ins pred:$p));
1486 let Pattern = pattern;
1487 list<Predicate> Predicates = [HasVFP2];
1490 // Load / store multiple
1491 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1492 string asm, string cstr, list<dag> pattern>
1493 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1494 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1495 // TODO: Mark the instructions with the appropriate subtarget info.
1496 let Inst{27-25} = 0b110;
1497 let Inst{11-9} = 0b101;
1498 let Inst{8} = 1; // Double precision
1500 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1501 let D = VFPNeonDomain;
1504 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1505 string asm, string cstr, list<dag> pattern>
1506 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1507 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1508 // TODO: Mark the instructions with the appropriate subtarget info.
1509 let Inst{27-25} = 0b110;
1510 let Inst{11-9} = 0b101;
1511 let Inst{8} = 0; // Single precision
1514 // Double precision, unary
1515 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1516 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1517 string asm, list<dag> pattern>
1518 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1519 let Inst{27-23} = opcod1;
1520 let Inst{21-20} = opcod2;
1521 let Inst{19-16} = opcod3;
1522 let Inst{11-9} = 0b101;
1523 let Inst{8} = 1; // Double precision
1524 let Inst{7-6} = opcod4;
1525 let Inst{4} = opcod5;
1528 // Double precision, binary
1529 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1530 dag iops, InstrItinClass itin, string opc, string asm,
1532 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1533 let Inst{27-23} = opcod1;
1534 let Inst{21-20} = opcod2;
1535 let Inst{11-9} = 0b101;
1536 let Inst{8} = 1; // Double precision
1541 // Double precision, binary, VML[AS] (for additional predicate)
1542 class ADbI_vmlX<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1543 dag iops, InstrItinClass itin, string opc, string asm,
1545 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1546 let Inst{27-23} = opcod1;
1547 let Inst{21-20} = opcod2;
1548 let Inst{11-9} = 0b101;
1549 let Inst{8} = 1; // Double precision
1552 list<Predicate> Predicates = [HasVFP2, UseVMLx];
1555 // Single precision, unary
1556 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1557 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1558 string asm, list<dag> pattern>
1559 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1560 let Inst{27-23} = opcod1;
1561 let Inst{21-20} = opcod2;
1562 let Inst{19-16} = opcod3;
1563 let Inst{11-9} = 0b101;
1564 let Inst{8} = 0; // Single precision
1565 let Inst{7-6} = opcod4;
1566 let Inst{4} = opcod5;
1569 // Single precision unary, if no NEON
1570 // Same as ASuI except not available if NEON is enabled
1571 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1572 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1573 string asm, list<dag> pattern>
1574 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1576 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1579 // Single precision, binary
1580 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1581 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1582 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1583 let Inst{27-23} = opcod1;
1584 let Inst{21-20} = opcod2;
1585 let Inst{11-9} = 0b101;
1586 let Inst{8} = 0; // Single precision
1591 // Single precision binary, if no NEON
1592 // Same as ASbI except not available if NEON is enabled
1593 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1594 dag iops, InstrItinClass itin, string opc, string asm,
1596 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1597 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1600 // VFP conversion instructions
1601 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1602 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1604 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1605 let Inst{27-23} = opcod1;
1606 let Inst{21-20} = opcod2;
1607 let Inst{19-16} = opcod3;
1608 let Inst{11-8} = opcod4;
1613 // VFP conversion between floating-point and fixed-point
1614 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1615 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1617 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1618 // size (fixed-point number): sx == 0 ? 16 : 32
1619 let Inst{7} = op5; // sx
1622 // VFP conversion instructions, if no NEON
1623 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1624 dag oops, dag iops, InstrItinClass itin,
1625 string opc, string asm, list<dag> pattern>
1626 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1628 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1631 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1632 InstrItinClass itin,
1633 string opc, string asm, list<dag> pattern>
1634 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1635 let Inst{27-20} = opcod1;
1636 let Inst{11-8} = opcod2;
1640 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1641 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1642 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1644 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1645 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1646 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1648 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1649 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1650 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1652 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1653 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1654 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1656 //===----------------------------------------------------------------------===//
1658 //===----------------------------------------------------------------------===//
1659 // ARM NEON Instruction templates.
1662 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1663 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1665 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1666 let OutOperandList = oops;
1667 let InOperandList = !con(iops, (ins pred:$p));
1668 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1669 let Pattern = pattern;
1670 list<Predicate> Predicates = [HasNEON];
1673 // Same as NeonI except it does not have a "data type" specifier.
1674 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1675 InstrItinClass itin, string opc, string asm, string cstr,
1677 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1678 let OutOperandList = oops;
1679 let InOperandList = !con(iops, (ins pred:$p));
1680 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1681 let Pattern = pattern;
1682 list<Predicate> Predicates = [HasNEON];
1685 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1686 dag oops, dag iops, InstrItinClass itin,
1687 string opc, string dt, string asm, string cstr, list<dag> pattern>
1688 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1690 let Inst{31-24} = 0b11110100;
1691 let Inst{23} = op23;
1692 let Inst{21-20} = op21_20;
1693 let Inst{11-8} = op11_8;
1694 let Inst{7-4} = op7_4;
1697 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1698 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1700 let OutOperandList = oops;
1701 let InOperandList = !con(iops, (ins pred:$p));
1702 list<Predicate> Predicates = [HasNEON];
1705 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1707 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1709 let OutOperandList = oops;
1710 let InOperandList = !con(iops, (ins pred:$p));
1711 let Pattern = pattern;
1712 list<Predicate> Predicates = [HasNEON];
1715 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1716 string opc, string dt, string asm, string cstr, list<dag> pattern>
1717 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1719 let Inst{31-25} = 0b1111001;
1722 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1723 string opc, string asm, string cstr, list<dag> pattern>
1724 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1726 let Inst{31-25} = 0b1111001;
1729 // NEON "one register and a modified immediate" format.
1730 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1732 dag oops, dag iops, InstrItinClass itin,
1733 string opc, string dt, string asm, string cstr,
1735 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1736 let Inst{23} = op23;
1737 let Inst{21-19} = op21_19;
1738 let Inst{11-8} = op11_8;
1744 // Instruction operands.
1748 let Inst{15-12} = Vd{3-0};
1749 let Inst{22} = Vd{4};
1750 let Inst{24} = SIMM{7};
1751 let Inst{18-16} = SIMM{6-4};
1752 let Inst{3-0} = SIMM{3-0};
1755 // NEON 2 vector register format.
1756 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1757 bits<5> op11_7, bit op6, bit op4,
1758 dag oops, dag iops, InstrItinClass itin,
1759 string opc, string dt, string asm, string cstr, list<dag> pattern>
1760 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1761 let Inst{24-23} = op24_23;
1762 let Inst{21-20} = op21_20;
1763 let Inst{19-18} = op19_18;
1764 let Inst{17-16} = op17_16;
1765 let Inst{11-7} = op11_7;
1769 // Instruction operands.
1773 let Inst{15-12} = Vd{3-0};
1774 let Inst{22} = Vd{4};
1775 let Inst{3-0} = Vm{3-0};
1776 let Inst{5} = Vm{4};
1779 // Same as N2V except it doesn't have a datatype suffix.
1780 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1781 bits<5> op11_7, bit op6, bit op4,
1782 dag oops, dag iops, InstrItinClass itin,
1783 string opc, string asm, string cstr, list<dag> pattern>
1784 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1785 let Inst{24-23} = op24_23;
1786 let Inst{21-20} = op21_20;
1787 let Inst{19-18} = op19_18;
1788 let Inst{17-16} = op17_16;
1789 let Inst{11-7} = op11_7;
1793 // Instruction operands.
1797 let Inst{15-12} = Vd{3-0};
1798 let Inst{22} = Vd{4};
1799 let Inst{3-0} = Vm{3-0};
1800 let Inst{5} = Vm{4};
1803 // NEON 2 vector register with immediate.
1804 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1805 dag oops, dag iops, Format f, InstrItinClass itin,
1806 string opc, string dt, string asm, string cstr, list<dag> pattern>
1807 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1808 let Inst{24} = op24;
1809 let Inst{23} = op23;
1810 let Inst{11-8} = op11_8;
1815 // Instruction operands.
1820 let Inst{15-12} = Vd{3-0};
1821 let Inst{22} = Vd{4};
1822 let Inst{3-0} = Vm{3-0};
1823 let Inst{5} = Vm{4};
1824 let Inst{21-16} = SIMM{5-0};
1827 // NEON 3 vector register format.
1828 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1829 dag oops, dag iops, Format f, InstrItinClass itin,
1830 string opc, string dt, string asm, string cstr, list<dag> pattern>
1831 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1832 let Inst{24} = op24;
1833 let Inst{23} = op23;
1834 let Inst{21-20} = op21_20;
1835 let Inst{11-8} = op11_8;
1839 // Instruction operands.
1844 let Inst{15-12} = Vd{3-0};
1845 let Inst{22} = Vd{4};
1846 let Inst{19-16} = Vn{3-0};
1847 let Inst{7} = Vn{4};
1848 let Inst{3-0} = Vm{3-0};
1849 let Inst{5} = Vm{4};
1852 // Same as N3V except it doesn't have a data type suffix.
1853 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1855 dag oops, dag iops, Format f, InstrItinClass itin,
1856 string opc, string asm, string cstr, list<dag> pattern>
1857 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1858 let Inst{24} = op24;
1859 let Inst{23} = op23;
1860 let Inst{21-20} = op21_20;
1861 let Inst{11-8} = op11_8;
1865 // Instruction operands.
1870 let Inst{15-12} = Vd{3-0};
1871 let Inst{22} = Vd{4};
1872 let Inst{19-16} = Vn{3-0};
1873 let Inst{7} = Vn{4};
1874 let Inst{3-0} = Vm{3-0};
1875 let Inst{5} = Vm{4};
1878 // NEON VMOVs between scalar and core registers.
1879 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1880 dag oops, dag iops, Format f, InstrItinClass itin,
1881 string opc, string dt, string asm, list<dag> pattern>
1882 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain,
1884 let Inst{27-20} = opcod1;
1885 let Inst{11-8} = opcod2;
1886 let Inst{6-5} = opcod3;
1889 let OutOperandList = oops;
1890 let InOperandList = !con(iops, (ins pred:$p));
1891 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1892 let Pattern = pattern;
1893 list<Predicate> Predicates = [HasNEON];
1900 let Inst{31-28} = p{3-0};
1902 let Inst{19-16} = V{3-0};
1903 let Inst{15-12} = R{3-0};
1905 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1906 dag oops, dag iops, InstrItinClass itin,
1907 string opc, string dt, string asm, list<dag> pattern>
1908 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1909 opc, dt, asm, pattern>;
1910 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1911 dag oops, dag iops, InstrItinClass itin,
1912 string opc, string dt, string asm, list<dag> pattern>
1913 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1914 opc, dt, asm, pattern>;
1915 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1916 dag oops, dag iops, InstrItinClass itin,
1917 string opc, string dt, string asm, list<dag> pattern>
1918 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1919 opc, dt, asm, pattern>;
1921 // Vector Duplicate Lane (from scalar to all elements)
1922 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1923 InstrItinClass itin, string opc, string dt, string asm,
1925 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1926 let Inst{24-23} = 0b11;
1927 let Inst{21-20} = 0b11;
1928 let Inst{19-16} = op19_16;
1929 let Inst{11-7} = 0b11000;
1937 let Inst{22} = Vd{4};
1938 let Inst{15-12} = Vd{3-0};
1939 let Inst{5} = Vm{4};
1940 let Inst{3-0} = Vm{3-0};
1943 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1944 // for single-precision FP.
1945 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1946 list<Predicate> Predicates = [HasNEON,UseNEONForFP];