1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm : Format<2>;
24 def MulSMLAW : Format<3>;
25 def MulSMULW : Format<4>;
26 def MulSMLA : Format<5>;
27 def MulSMUL : Format<6>;
28 def Branch : Format<7>;
29 def BranchMisc : Format<8>;
31 def DPRdIm : Format<9>;
32 def DPRdReg : Format<10>;
33 def DPRdSoReg : Format<11>;
34 def DPRdMisc : Format<12>;
35 def DPRnIm : Format<13>;
36 def DPRnReg : Format<14>;
37 def DPRnSoReg : Format<15>;
38 def DPRIm : Format<16>;
39 def DPRReg : Format<17>;
40 def DPRSoReg : Format<18>;
41 def DPRImS : Format<19>;
42 def DPRRegS : Format<20>;
43 def DPRSoRegS : Format<21>;
45 def LdFrm : Format<22>;
46 def StFrm : Format<23>;
48 def ArithMisc : Format<24>;
49 def ThumbFrm : Format<25>;
50 def VFPFrm : Format<26>;
53 //===----------------------------------------------------------------------===//
55 // ARM Instruction templates.
58 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
59 Format f, string cstr>
63 let Namespace = "ARM";
65 bits<4> Opcode = opcod;
67 bits<4> AddrModeBits = AM.Value;
70 bits<3> SizeFlag = SZ.Value;
73 bits<2> IndexModeBits = IM.Value;
76 bits<5> Form = F.Value;
78 let Constraints = cstr;
81 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
82 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
83 let OutOperandList = oops;
84 let InOperandList = iops;
86 let Pattern = pattern;
89 // Almost all ARM instructions are predicable.
90 class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
91 IndexMode im, Format f, string opc, string asm, string cstr,
93 : InstARM<opcod, am, sz, im, f, cstr> {
94 let OutOperandList = oops;
95 let InOperandList = !con(iops, (ops pred:$p));
96 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
97 let Pattern = pattern;
98 list<Predicate> Predicates = [IsARM];
101 // Same as I except it can optionally modify CPSR. Note it's modeled as
102 // an input operand since by default it's a zero register. It will
103 // become an implicit def once it's "flipped".
104 class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
105 IndexMode im, Format f, string opc, string asm, string cstr,
107 : InstARM<opcod, am, sz, im, f, cstr> {
108 let OutOperandList = oops;
109 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
110 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
111 let Pattern = pattern;
112 list<Predicate> Predicates = [IsARM];
116 class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
117 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
118 : InstARM<opcod, am, sz, im, f, cstr> {
119 let OutOperandList = oops;
120 let InOperandList = iops;
122 let Pattern = pattern;
123 list<Predicate> Predicates = [IsARM];
126 class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
127 string asm, list<dag> pattern>
128 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
130 class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
131 string asm, list<dag> pattern>
132 : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
134 class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
136 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
138 class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
140 : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
143 // addrmode1 instructions
144 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
145 string asm, list<dag> pattern>
146 : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
148 let Inst{21-24} = opcod;
151 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
152 string asm, list<dag> pattern>
153 : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
156 let Inst{21-24} = opcod;
159 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
161 : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
164 let Inst{21-24} = opcod;
167 class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
168 string asm, list<dag> pattern>
169 : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
173 // addrmode2 loads and stores
174 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
175 string asm, list<dag> pattern>
176 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
180 class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
182 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
186 class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
187 string asm, list<dag> pattern>
188 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
189 let Inst{20} = 1; // L bit
190 let Inst{21} = 0; // W bit
191 let Inst{22} = 0; // B bit
192 let Inst{24} = 1; // P bit
194 class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
196 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
198 let Inst{20} = 1; // L bit
199 let Inst{21} = 0; // W bit
200 let Inst{22} = 0; // B bit
201 let Inst{24} = 1; // P bit
203 class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
204 string asm, list<dag> pattern>
205 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
206 let Inst{20} = 1; // L bit
207 let Inst{21} = 0; // W bit
208 let Inst{22} = 1; // B bit
209 let Inst{24} = 1; // P bit
211 class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
213 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
215 let Inst{20} = 1; // L bit
216 let Inst{21} = 0; // W bit
217 let Inst{22} = 1; // B bit
218 let Inst{24} = 1; // P bit
222 class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
223 string asm, list<dag> pattern>
224 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
225 let Inst{20} = 0; // L bit
226 let Inst{21} = 0; // W bit
227 let Inst{22} = 0; // B bit
228 let Inst{24} = 1; // P bit
230 class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
232 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
234 let Inst{20} = 0; // L bit
235 let Inst{21} = 0; // W bit
236 let Inst{22} = 0; // B bit
237 let Inst{24} = 1; // P bit
239 class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
240 string asm, list<dag> pattern>
241 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
242 let Inst{20} = 0; // L bit
243 let Inst{21} = 0; // W bit
244 let Inst{22} = 1; // B bit
245 let Inst{24} = 1; // P bit
247 class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
249 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
251 let Inst{20} = 0; // L bit
252 let Inst{21} = 0; // W bit
253 let Inst{22} = 1; // B bit
254 let Inst{24} = 1; // P bit
258 class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
259 string asm, string cstr, list<dag> pattern>
260 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
261 asm, cstr, pattern> {
262 let Inst{20} = 1; // L bit
263 let Inst{21} = 1; // W bit
264 let Inst{22} = 0; // B bit
265 let Inst{24} = 1; // P bit
267 class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
268 string asm, string cstr, list<dag> pattern>
269 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
270 asm, cstr, pattern> {
271 let Inst{20} = 1; // L bit
272 let Inst{21} = 1; // W bit
273 let Inst{22} = 1; // B bit
274 let Inst{24} = 1; // P bit
277 // Pre-indexed stores
278 class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
279 string asm, string cstr, list<dag> pattern>
280 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
281 asm, cstr, pattern> {
282 let Inst{20} = 0; // L bit
283 let Inst{21} = 1; // W bit
284 let Inst{22} = 0; // B bit
285 let Inst{24} = 1; // P bit
287 class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
288 string asm, string cstr, list<dag> pattern>
289 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
290 asm, cstr, pattern> {
291 let Inst{20} = 0; // L bit
292 let Inst{21} = 1; // W bit
293 let Inst{22} = 1; // B bit
294 let Inst{24} = 1; // P bit
297 // Post-indexed loads
298 class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
299 string asm, string cstr, list<dag> pattern>
300 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
302 let Inst{20} = 1; // L bit
303 let Inst{21} = 0; // W bit
304 let Inst{22} = 0; // B bit
305 let Inst{24} = 0; // P bit
307 class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
308 string asm, string cstr, list<dag> pattern>
309 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
311 let Inst{20} = 1; // L bit
312 let Inst{21} = 0; // W bit
313 let Inst{22} = 1; // B bit
314 let Inst{24} = 0; // P bit
317 // Post-indexed stores
318 class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
319 string asm, string cstr, list<dag> pattern>
320 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
322 let Inst{20} = 0; // L bit
323 let Inst{21} = 0; // W bit
324 let Inst{22} = 0; // B bit
325 let Inst{24} = 0; // P bit
327 class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
328 string asm, string cstr, list<dag> pattern>
329 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
331 let Inst{20} = 0; // L bit
332 let Inst{21} = 0; // W bit
333 let Inst{22} = 1; // B bit
334 let Inst{24} = 0; // P bit
337 // addrmode3 instructions
338 class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
339 string asm, list<dag> pattern>
340 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
342 class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
344 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
348 class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
349 string asm, list<dag> pattern>
350 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
353 let Inst{5} = 1; // H bit
354 let Inst{6} = 0; // S bit
356 let Inst{20} = 1; // L bit
357 let Inst{21} = 0; // W bit
358 let Inst{24} = 1; // P bit
360 class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
362 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
365 let Inst{5} = 1; // H bit
366 let Inst{6} = 0; // S bit
368 let Inst{20} = 1; // L bit
369 let Inst{21} = 0; // W bit
370 let Inst{24} = 1; // P bit
372 class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
373 string asm, list<dag> pattern>
374 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
377 let Inst{5} = 1; // H bit
378 let Inst{6} = 1; // S bit
380 let Inst{20} = 1; // L bit
381 let Inst{21} = 0; // W bit
382 let Inst{24} = 1; // P bit
384 class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
386 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
389 let Inst{5} = 1; // H bit
390 let Inst{6} = 1; // S bit
392 let Inst{20} = 1; // L bit
393 let Inst{21} = 0; // W bit
394 let Inst{24} = 1; // P bit
396 class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
397 string asm, list<dag> pattern>
398 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
401 let Inst{5} = 0; // H bit
402 let Inst{6} = 1; // S bit
404 let Inst{20} = 1; // L bit
405 let Inst{21} = 0; // W bit
406 let Inst{24} = 1; // P bit
408 class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
410 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
413 let Inst{5} = 0; // H bit
414 let Inst{6} = 1; // S bit
416 let Inst{20} = 1; // L bit
417 let Inst{21} = 0; // W bit
418 let Inst{24} = 1; // P bit
420 class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
421 string asm, list<dag> pattern>
422 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
425 let Inst{5} = 0; // H bit
426 let Inst{6} = 1; // S bit
428 let Inst{20} = 0; // L bit
429 let Inst{21} = 0; // W bit
430 let Inst{24} = 1; // P bit
434 class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
435 string asm, list<dag> pattern>
436 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
439 let Inst{5} = 1; // H bit
440 let Inst{6} = 0; // S bit
442 let Inst{20} = 0; // L bit
443 let Inst{21} = 0; // W bit
444 let Inst{24} = 1; // P bit
446 class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm,
448 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
451 let Inst{5} = 1; // H bit
452 let Inst{6} = 0; // S bit
454 let Inst{20} = 0; // L bit
455 let Inst{21} = 0; // W bit
456 let Inst{24} = 1; // P bit
458 class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
459 string asm, list<dag> pattern>
460 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
463 let Inst{5} = 1; // H bit
464 let Inst{6} = 1; // S bit
466 let Inst{20} = 0; // L bit
467 let Inst{21} = 0; // W bit
468 let Inst{24} = 1; // P bit
472 class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
473 string asm, string cstr, list<dag> pattern>
474 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
475 asm, cstr, pattern> {
477 let Inst{5} = 1; // H bit
478 let Inst{6} = 0; // S bit
480 let Inst{20} = 1; // L bit
481 let Inst{21} = 1; // W bit
482 let Inst{24} = 1; // P bit
484 class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
485 string asm, string cstr, list<dag> pattern>
486 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
487 asm, cstr, pattern> {
489 let Inst{5} = 1; // H bit
490 let Inst{6} = 1; // S bit
492 let Inst{20} = 1; // L bit
493 let Inst{21} = 1; // W bit
494 let Inst{24} = 1; // P bit
496 class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
497 string asm, string cstr, list<dag> pattern>
498 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
499 asm, cstr, pattern> {
501 let Inst{5} = 0; // H bit
502 let Inst{6} = 1; // S bit
504 let Inst{20} = 1; // L bit
505 let Inst{21} = 1; // W bit
506 let Inst{24} = 1; // P bit
509 // Pre-indexed stores
510 class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
511 string asm, string cstr, list<dag> pattern>
512 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
513 asm, cstr, pattern> {
515 let Inst{5} = 1; // H bit
516 let Inst{6} = 0; // S bit
518 let Inst{20} = 0; // L bit
519 let Inst{21} = 1; // W bit
520 let Inst{24} = 1; // P bit
523 // Post-indexed loads
524 class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
525 string asm, string cstr, list<dag> pattern>
526 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
529 let Inst{5} = 1; // H bit
530 let Inst{6} = 0; // S bit
532 let Inst{20} = 1; // L bit
533 let Inst{21} = 1; // W bit
534 let Inst{24} = 0; // P bit
536 class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
537 string asm, string cstr, list<dag> pattern>
538 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
541 let Inst{5} = 1; // H bit
542 let Inst{6} = 1; // S bit
544 let Inst{20} = 1; // L bit
545 let Inst{21} = 1; // W bit
546 let Inst{24} = 0; // P bit
548 class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
549 string asm, string cstr, list<dag> pattern>
550 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
553 let Inst{5} = 0; // H bit
554 let Inst{6} = 1; // S bit
556 let Inst{20} = 1; // L bit
557 let Inst{21} = 1; // W bit
558 let Inst{24} = 0; // P bit
561 // Post-indexed stores
562 class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
563 string asm, string cstr, list<dag> pattern>
564 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
567 let Inst{5} = 1; // H bit
568 let Inst{6} = 0; // S bit
570 let Inst{20} = 0; // L bit
571 let Inst{21} = 1; // W bit
572 let Inst{24} = 0; // P bit
576 // addrmode4 instructions
577 class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
578 string asm, list<dag> pattern>
579 : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
581 let Inst{25-27} = 0x4;
583 class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm,
585 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
587 let Inst{20} = 1; // L bit
588 let Inst{22} = 0; // S bit
589 let Inst{25-27} = 0x4;
591 class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm,
593 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
595 let Inst{20} = 1; // L bit
596 let Inst{22} = 1; // S bit
597 let Inst{25-27} = 0x4;
599 class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
601 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
603 let Inst{20} = 0; // L bit
604 let Inst{22} = 0; // S bit
605 let Inst{25-27} = 0x4;
609 // BR_JT instructions
610 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
611 : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
613 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
614 : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
616 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
617 : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
621 //===----------------------------------------------------------------------===//
623 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
624 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
625 list<Predicate> Predicates = [IsARM];
627 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
628 list<Predicate> Predicates = [IsARM, HasV5TE];
630 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
631 list<Predicate> Predicates = [IsARM, HasV6];
634 //===----------------------------------------------------------------------===//
636 // Thumb Instruction Format Definitions.
640 // TI - Thumb instruction.
642 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
643 string asm, string cstr, list<dag> pattern>
644 // FIXME: Set all opcodes to 0 for now.
645 : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
646 let OutOperandList = outs;
647 let InOperandList = ins;
649 let Pattern = pattern;
650 list<Predicate> Predicates = [IsThumb];
653 class TI<dag outs, dag ins, string asm, list<dag> pattern>
654 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
655 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
656 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
657 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
658 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
659 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
660 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
661 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
662 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
664 // Two-address instructions
665 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
666 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
668 // BL, BLX(1) are translated by assembler into two instructions
669 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
670 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
672 // BR_JT instructions
673 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
674 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
677 //===----------------------------------------------------------------------===//
680 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
681 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
682 list<Predicate> Predicates = [IsThumb];
685 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
686 list<Predicate> Predicates = [IsThumb, HasV5T];