1 //===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
71 def DPSoRegImmFrm : Format<42>;
75 // The instruction has an Rn register operand.
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
77 // it doesn't have a Rn operand.
78 class UnaryDP { bit isUnaryDataProc = 1; }
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
82 class Xform16Bit { bit canXformTo16Bit = 1; }
84 //===----------------------------------------------------------------------===//
85 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 // FIXME: Once the JIT is MC-ized, these can go away.
90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>;
102 def AddrModeT1_4 : AddrMode<9>;
103 def AddrModeT1_s : AddrMode<10>;
104 def AddrModeT2_i12 : AddrMode<11>;
105 def AddrModeT2_i8 : AddrMode<12>;
106 def AddrModeT2_so : AddrMode<13>;
107 def AddrModeT2_pc : AddrMode<14>;
108 def AddrModeT2_i8s4 : AddrMode<15>;
109 def AddrMode_i12 : AddrMode<16>;
111 // Load / store index mode.
112 class IndexMode<bits<2> val> {
115 def IndexModeNone : IndexMode<0>;
116 def IndexModePre : IndexMode<1>;
117 def IndexModePost : IndexMode<2>;
118 def IndexModeUpd : IndexMode<3>;
120 // Instruction execution domain.
121 class Domain<bits<3> val> {
124 def GenericDomain : Domain<0>;
125 def VFPDomain : Domain<1>; // Instructions in VFP domain only
126 def NeonDomain : Domain<2>; // Instructions in Neon domain only
127 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
128 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
130 //===----------------------------------------------------------------------===//
131 // ARM special operands.
134 // ARM imod and iflag operands, used only by the CPS instruction.
135 def imod_op : Operand<i32> {
136 let PrintMethod = "printCPSIMod";
139 def ProcIFlagsOperand : AsmOperandClass {
140 let Name = "ProcIFlags";
141 let ParserMethod = "parseProcIFlagsOperand";
143 def iflags_op : Operand<i32> {
144 let PrintMethod = "printCPSIFlag";
145 let ParserMatchClass = ProcIFlagsOperand;
148 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
149 // register whose default is 0 (no register).
150 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
151 def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
152 (ops (i32 14), (i32 zero_reg))> {
153 let PrintMethod = "printPredicateOperand";
154 let ParserMatchClass = CondCodeOperand;
155 let DecoderMethod = "DecodePredicateOperand";
158 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
159 def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
160 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
161 let EncoderMethod = "getCCOutOpValue";
162 let PrintMethod = "printSBitModifierOperand";
163 let ParserMatchClass = CCOutOperand;
164 let DecoderMethod = "DecodeCCOutOperand";
167 // Same as cc_out except it defaults to setting CPSR.
168 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
169 let EncoderMethod = "getCCOutOpValue";
170 let PrintMethod = "printSBitModifierOperand";
171 let ParserMatchClass = CCOutOperand;
172 let DecoderMethod = "DecodeCCOutOperand";
175 // ARM special operands for disassembly only.
177 def SetEndAsmOperand : ImmAsmOperand {
178 let Name = "SetEndImm";
179 let ParserMethod = "parseSetEndImm";
181 def setend_op : Operand<i32> {
182 let PrintMethod = "printSetendOperand";
183 let ParserMatchClass = SetEndAsmOperand;
186 def MSRMaskOperand : AsmOperandClass {
187 let Name = "MSRMask";
188 let ParserMethod = "parseMSRMaskOperand";
190 def msr_mask : Operand<i32> {
191 let PrintMethod = "printMSRMaskOperand";
192 let DecoderMethod = "DecodeMSRMask";
193 let ParserMatchClass = MSRMaskOperand;
196 // Shift Right Immediate - A shift right immediate is encoded differently from
197 // other shift immediates. The imm6 field is encoded like so:
200 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
201 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
202 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
203 // 64 64 - <imm> is encoded in imm6<5:0>
204 def shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; }
205 def shr_imm8 : Operand<i32> {
206 let EncoderMethod = "getShiftRight8Imm";
207 let DecoderMethod = "DecodeShiftRight8Imm";
208 let ParserMatchClass = shr_imm8_asm_operand;
210 def shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; }
211 def shr_imm16 : Operand<i32> {
212 let EncoderMethod = "getShiftRight16Imm";
213 let DecoderMethod = "DecodeShiftRight16Imm";
214 let ParserMatchClass = shr_imm16_asm_operand;
216 def shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; }
217 def shr_imm32 : Operand<i32> {
218 let EncoderMethod = "getShiftRight32Imm";
219 let DecoderMethod = "DecodeShiftRight32Imm";
220 let ParserMatchClass = shr_imm32_asm_operand;
222 def shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; }
223 def shr_imm64 : Operand<i32> {
224 let EncoderMethod = "getShiftRight64Imm";
225 let DecoderMethod = "DecodeShiftRight64Imm";
226 let ParserMatchClass = shr_imm64_asm_operand;
229 //===----------------------------------------------------------------------===//
230 // ARM Assembler alias templates.
232 class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1>
233 : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>;
234 class tInstAlias<string Asm, dag Result, bit Emit = 0b1>
235 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>;
236 class t2InstAlias<string Asm, dag Result, bit Emit = 0b1>
237 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>;
238 class VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1>
239 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>;
240 class VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1>
241 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>;
242 class NEONInstAlias<string Asm, dag Result, bit Emit = 0b1>
243 : InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>;
246 class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
248 class NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
251 //===----------------------------------------------------------------------===//
252 // ARM Instruction templates.
256 class InstTemplate<AddrMode am, int sz, IndexMode im,
257 Format f, Domain d, string cstr, InstrItinClass itin>
259 let Namespace = "ARM";
264 bits<2> IndexModeBits = IM.Value;
266 bits<6> Form = F.Value;
268 bit isUnaryDataProc = 0;
269 bit canXformTo16Bit = 0;
270 // The instruction is a 16-bit flag setting Thumb instruction. Used
271 // by the parser to determine whether to require the 'S' suffix on the
272 // mnemonic (when not in an IT block) or preclude it (when in an IT block).
273 bit thumbArithFlagSetting = 0;
275 // If this is a pseudo instruction, mark it isCodeGenOnly.
276 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
278 // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
279 let TSFlags{4-0} = AM.Value;
280 let TSFlags{6-5} = IndexModeBits;
281 let TSFlags{12-7} = Form;
282 let TSFlags{13} = isUnaryDataProc;
283 let TSFlags{14} = canXformTo16Bit;
284 let TSFlags{17-15} = D.Value;
285 let TSFlags{18} = thumbArithFlagSetting;
287 let Constraints = cstr;
288 let Itinerary = itin;
293 // Mask of bits that cause an encoding to be UNPREDICTABLE.
294 // If a bit is set, then if the corresponding bit in the
295 // target encoding differs from its value in the "Inst" field,
296 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
297 field bits<32> Unpredictable = 0;
298 // SoftFail is the generic name for this field, but we alias it so
299 // as to make it more obvious what it means in ARM-land.
300 field bits<32> SoftFail = Unpredictable;
303 class InstARM<AddrMode am, int sz, IndexMode im,
304 Format f, Domain d, string cstr, InstrItinClass itin>
305 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
306 let DecoderNamespace = "ARM";
309 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
310 // on by adding flavors to specific instructions.
311 class InstThumb<AddrMode am, int sz, IndexMode im,
312 Format f, Domain d, string cstr, InstrItinClass itin>
313 : InstTemplate<am, sz, im, f, d, cstr, itin> {
314 let DecoderNamespace = "Thumb";
317 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
318 // These are aliases that require C++ handling to convert to the target
319 // instruction, while InstAliases can be handled directly by tblgen.
320 class AsmPseudoInst<string asm, dag iops>
321 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
323 let OutOperandList = (outs);
324 let InOperandList = iops;
326 let isCodeGenOnly = 0; // So we get asm matcher for it.
331 class ARMAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
333 class tAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
335 class t2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
336 Requires<[IsThumb2]>;
337 class VFP2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
339 class NEONAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
342 // Pseudo instructions for the code generator.
343 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
344 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
345 GenericDomain, "", itin> {
346 let OutOperandList = oops;
347 let InOperandList = iops;
348 let Pattern = pattern;
349 let isCodeGenOnly = 1;
353 // PseudoInst that's ARM-mode only.
354 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
356 : PseudoInst<oops, iops, itin, pattern> {
358 list<Predicate> Predicates = [IsARM];
361 // PseudoInst that's Thumb-mode only.
362 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
364 : PseudoInst<oops, iops, itin, pattern> {
366 list<Predicate> Predicates = [IsThumb];
369 // PseudoInst that's Thumb2-mode only.
370 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
372 : PseudoInst<oops, iops, itin, pattern> {
374 list<Predicate> Predicates = [IsThumb2];
377 class ARMPseudoExpand<dag oops, dag iops, int sz,
378 InstrItinClass itin, list<dag> pattern,
380 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
381 PseudoInstExpansion<Result>;
383 class tPseudoExpand<dag oops, dag iops, int sz,
384 InstrItinClass itin, list<dag> pattern,
386 : tPseudoInst<oops, iops, sz, itin, pattern>,
387 PseudoInstExpansion<Result>;
389 class t2PseudoExpand<dag oops, dag iops, int sz,
390 InstrItinClass itin, list<dag> pattern,
392 : t2PseudoInst<oops, iops, sz, itin, pattern>,
393 PseudoInstExpansion<Result>;
395 // Almost all ARM instructions are predicable.
396 class I<dag oops, dag iops, AddrMode am, int sz,
397 IndexMode im, Format f, InstrItinClass itin,
398 string opc, string asm, string cstr,
400 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
403 let OutOperandList = oops;
404 let InOperandList = !con(iops, (ins pred:$p));
405 let AsmString = !strconcat(opc, "${p}", asm);
406 let Pattern = pattern;
407 list<Predicate> Predicates = [IsARM];
410 // A few are not predicable
411 class InoP<dag oops, dag iops, AddrMode am, int sz,
412 IndexMode im, Format f, InstrItinClass itin,
413 string opc, string asm, string cstr,
415 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
416 let OutOperandList = oops;
417 let InOperandList = iops;
418 let AsmString = !strconcat(opc, asm);
419 let Pattern = pattern;
420 let isPredicable = 0;
421 list<Predicate> Predicates = [IsARM];
424 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
425 // operand since by default it's a zero register. It will become an implicit def
426 // once it's "flipped".
427 class sI<dag oops, dag iops, AddrMode am, int sz,
428 IndexMode im, Format f, InstrItinClass itin,
429 string opc, string asm, string cstr,
431 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
432 bits<4> p; // Predicate operand
433 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
437 let OutOperandList = oops;
438 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
439 let AsmString = !strconcat(opc, "${s}${p}", asm);
440 let Pattern = pattern;
441 list<Predicate> Predicates = [IsARM];
445 class XI<dag oops, dag iops, AddrMode am, int sz,
446 IndexMode im, Format f, InstrItinClass itin,
447 string asm, string cstr, list<dag> pattern>
448 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
449 let OutOperandList = oops;
450 let InOperandList = iops;
452 let Pattern = pattern;
453 list<Predicate> Predicates = [IsARM];
456 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
457 string opc, string asm, list<dag> pattern>
458 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
459 opc, asm, "", pattern>;
460 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
461 string opc, string asm, list<dag> pattern>
462 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
463 opc, asm, "", pattern>;
464 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
465 string asm, list<dag> pattern>
466 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
468 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
469 string opc, string asm, list<dag> pattern>
470 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
471 opc, asm, "", pattern>;
473 // Ctrl flow instructions
474 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
475 string opc, string asm, list<dag> pattern>
476 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
477 opc, asm, "", pattern> {
478 let Inst{27-24} = opcod;
480 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
481 string asm, list<dag> pattern>
482 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
484 let Inst{27-24} = opcod;
487 // BR_JT instructions
488 class JTI<dag oops, dag iops, InstrItinClass itin,
489 string asm, list<dag> pattern>
490 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
493 // Atomic load/store instructions
494 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
495 string opc, string asm, list<dag> pattern>
496 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
497 opc, asm, "", pattern> {
500 let Inst{27-23} = 0b00011;
501 let Inst{22-21} = opcod;
503 let Inst{19-16} = addr;
504 let Inst{15-12} = Rt;
505 let Inst{11-0} = 0b111110011111;
507 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
508 string opc, string asm, list<dag> pattern>
509 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
510 opc, asm, "", pattern> {
514 let Inst{27-23} = 0b00011;
515 let Inst{22-21} = opcod;
517 let Inst{19-16} = addr;
518 let Inst{15-12} = Rd;
519 let Inst{11-4} = 0b11111001;
522 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
523 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
527 let Inst{27-23} = 0b00010;
529 let Inst{21-20} = 0b00;
530 let Inst{19-16} = addr;
531 let Inst{15-12} = Rt;
532 let Inst{11-4} = 0b00001001;
535 let DecoderMethod = "DecodeSwap";
538 // addrmode1 instructions
539 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
540 string opc, string asm, list<dag> pattern>
541 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
542 opc, asm, "", pattern> {
543 let Inst{24-21} = opcod;
544 let Inst{27-26} = 0b00;
546 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
547 string opc, string asm, list<dag> pattern>
548 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
549 opc, asm, "", pattern> {
550 let Inst{24-21} = opcod;
551 let Inst{27-26} = 0b00;
553 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
554 string asm, list<dag> pattern>
555 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
557 let Inst{24-21} = opcod;
558 let Inst{27-26} = 0b00;
563 // LDR/LDRB/STR/STRB/...
564 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
565 Format f, InstrItinClass itin, string opc, string asm,
567 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
569 let Inst{27-25} = op;
570 let Inst{24} = 1; // 24 == P
572 let Inst{22} = isByte;
573 let Inst{21} = 0; // 21 == W
576 // Indexed load/stores
577 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
578 IndexMode im, Format f, InstrItinClass itin, string opc,
579 string asm, string cstr, list<dag> pattern>
580 : I<oops, iops, AddrMode2, 4, im, f, itin,
581 opc, asm, cstr, pattern> {
583 let Inst{27-26} = 0b01;
584 let Inst{24} = isPre; // P bit
585 let Inst{22} = isByte; // B bit
586 let Inst{21} = isPre; // W bit
587 let Inst{20} = isLd; // L bit
588 let Inst{15-12} = Rt;
590 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
591 IndexMode im, Format f, InstrItinClass itin, string opc,
592 string asm, string cstr, list<dag> pattern>
593 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
595 // AM2 store w/ two operands: (GPR, am2offset)
601 let Inst{23} = offset{12};
602 let Inst{19-16} = Rn;
603 let Inst{11-5} = offset{11-5};
605 let Inst{3-0} = offset{3-0};
608 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
609 IndexMode im, Format f, InstrItinClass itin, string opc,
610 string asm, string cstr, list<dag> pattern>
611 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
613 // AM2 store w/ two operands: (GPR, am2offset)
619 let Inst{23} = offset{12};
620 let Inst{19-16} = Rn;
621 let Inst{11-0} = offset{11-0};
625 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
626 // but for now use this class for STRT and STRBT.
627 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
628 IndexMode im, Format f, InstrItinClass itin, string opc,
629 string asm, string cstr, list<dag> pattern>
630 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
632 // AM2 store w/ two operands: (GPR, am2offset)
634 // {13} 1 == Rm, 0 == imm12
638 let Inst{25} = addr{13};
639 let Inst{23} = addr{12};
640 let Inst{19-16} = addr{17-14};
641 let Inst{11-0} = addr{11-0};
644 // addrmode3 instructions
645 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
646 InstrItinClass itin, string opc, string asm, list<dag> pattern>
647 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
648 opc, asm, "", pattern> {
651 let Inst{27-25} = 0b000;
652 let Inst{24} = 1; // P bit
653 let Inst{23} = addr{8}; // U bit
654 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
655 let Inst{21} = 0; // W bit
656 let Inst{20} = op20; // L bit
657 let Inst{19-16} = addr{12-9}; // Rn
658 let Inst{15-12} = Rt; // Rt
659 let Inst{11-8} = addr{7-4}; // imm7_4/zero
661 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
663 let DecoderMethod = "DecodeAddrMode3Instruction";
666 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
667 IndexMode im, Format f, InstrItinClass itin, string opc,
668 string asm, string cstr, list<dag> pattern>
669 : I<oops, iops, AddrMode3, 4, im, f, itin,
670 opc, asm, cstr, pattern> {
672 let Inst{27-25} = 0b000;
673 let Inst{24} = isPre; // P bit
674 let Inst{21} = isPre; // W bit
675 let Inst{20} = op20; // L bit
676 let Inst{15-12} = Rt; // Rt
680 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
681 // but for now use this class for LDRSBT, LDRHT, LDSHT.
682 class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
683 IndexMode im, Format f, InstrItinClass itin, string opc,
684 string asm, string cstr, list<dag> pattern>
685 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> {
686 // {13} 1 == imm8, 0 == Rm
693 let Inst{27-25} = 0b000;
694 let Inst{24} = 0; // P bit
696 let Inst{20} = isLoad; // L bit
697 let Inst{19-16} = addr; // Rn
698 let Inst{15-12} = Rt; // Rt
703 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
704 string opc, string asm, list<dag> pattern>
705 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
706 opc, asm, "", pattern> {
709 let Inst{27-25} = 0b000;
710 let Inst{24} = 1; // P bit
711 let Inst{23} = addr{8}; // U bit
712 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
713 let Inst{21} = 0; // W bit
714 let Inst{20} = 0; // L bit
715 let Inst{19-16} = addr{12-9}; // Rn
716 let Inst{15-12} = Rt; // Rt
717 let Inst{11-8} = addr{7-4}; // imm7_4/zero
719 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
720 let DecoderMethod = "DecodeAddrMode3Instruction";
723 // addrmode4 instructions
724 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
725 string asm, string cstr, list<dag> pattern>
726 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
731 let Inst{27-25} = 0b100;
732 let Inst{22} = 0; // S bit
733 let Inst{19-16} = Rn;
734 let Inst{15-0} = regs;
737 // Unsigned multiply, multiply-accumulate instructions.
738 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
739 string opc, string asm, list<dag> pattern>
740 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
741 opc, asm, "", pattern> {
742 let Inst{7-4} = 0b1001;
743 let Inst{20} = 0; // S bit
744 let Inst{27-21} = opcod;
746 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
747 string opc, string asm, list<dag> pattern>
748 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
749 opc, asm, "", pattern> {
750 let Inst{7-4} = 0b1001;
751 let Inst{27-21} = opcod;
754 // Most significant word multiply
755 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
756 InstrItinClass itin, string opc, string asm, list<dag> pattern>
757 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
758 opc, asm, "", pattern> {
762 let Inst{7-4} = opc7_4;
764 let Inst{27-21} = opcod;
765 let Inst{19-16} = Rd;
769 // MSW multiple w/ Ra operand
770 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
771 InstrItinClass itin, string opc, string asm, list<dag> pattern>
772 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
774 let Inst{15-12} = Ra;
777 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
778 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
779 InstrItinClass itin, string opc, string asm, list<dag> pattern>
780 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
781 opc, asm, "", pattern> {
787 let Inst{27-21} = opcod;
788 let Inst{6-5} = bit6_5;
792 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
793 InstrItinClass itin, string opc, string asm, list<dag> pattern>
794 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
796 let Inst{19-16} = Rd;
799 // AMulxyI with Ra operand
800 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
801 InstrItinClass itin, string opc, string asm, list<dag> pattern>
802 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
804 let Inst{15-12} = Ra;
807 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
808 InstrItinClass itin, string opc, string asm, list<dag> pattern>
809 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
812 let Inst{19-16} = RdHi;
813 let Inst{15-12} = RdLo;
816 // Extend instructions.
817 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
818 string opc, string asm, list<dag> pattern>
819 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
820 opc, asm, "", pattern> {
821 // All AExtI instructions have Rd and Rm register operands.
824 let Inst{15-12} = Rd;
826 let Inst{7-4} = 0b0111;
827 let Inst{9-8} = 0b00;
828 let Inst{27-20} = opcod;
831 // Misc Arithmetic instructions.
832 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
833 InstrItinClass itin, string opc, string asm, list<dag> pattern>
834 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
835 opc, asm, "", pattern> {
838 let Inst{27-20} = opcod;
839 let Inst{19-16} = 0b1111;
840 let Inst{15-12} = Rd;
841 let Inst{11-8} = 0b1111;
842 let Inst{7-4} = opc7_4;
847 def PKHLSLAsmOperand : ImmAsmOperand {
848 let Name = "PKHLSLImm";
849 let ParserMethod = "parsePKHLSLImm";
851 def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
852 let PrintMethod = "printPKHLSLShiftImm";
853 let ParserMatchClass = PKHLSLAsmOperand;
855 def PKHASRAsmOperand : AsmOperandClass {
856 let Name = "PKHASRImm";
857 let ParserMethod = "parsePKHASRImm";
859 def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
860 let PrintMethod = "printPKHASRShiftImm";
861 let ParserMatchClass = PKHASRAsmOperand;
864 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
865 string opc, string asm, list<dag> pattern>
866 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
867 opc, asm, "", pattern> {
872 let Inst{27-20} = opcod;
873 let Inst{19-16} = Rn;
874 let Inst{15-12} = Rd;
877 let Inst{5-4} = 0b01;
881 //===----------------------------------------------------------------------===//
883 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
884 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
885 list<Predicate> Predicates = [IsARM];
887 class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
888 list<Predicate> Predicates = [IsARM, HasV5T];
890 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
891 list<Predicate> Predicates = [IsARM, HasV5TE];
893 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
894 list<Predicate> Predicates = [IsARM, HasV6];
897 //===----------------------------------------------------------------------===//
898 // Thumb Instruction Format Definitions.
901 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
902 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
903 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
904 let OutOperandList = oops;
905 let InOperandList = iops;
907 let Pattern = pattern;
908 list<Predicate> Predicates = [IsThumb];
911 // TI - Thumb instruction.
912 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
913 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
915 // Two-address instructions
916 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
918 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
921 // tBL, tBX 32-bit instructions
922 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
923 dag oops, dag iops, InstrItinClass itin, string asm,
925 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
927 let Inst{31-27} = opcod1;
928 let Inst{15-14} = opcod2;
929 let Inst{12} = opcod3;
932 // BR_JT instructions
933 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
935 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
938 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
939 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
940 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
941 let OutOperandList = oops;
942 let InOperandList = iops;
944 let Pattern = pattern;
945 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
948 class T1I<dag oops, dag iops, InstrItinClass itin,
949 string asm, list<dag> pattern>
950 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
951 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
952 string asm, list<dag> pattern>
953 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
955 // Two-address instructions
956 class T1It<dag oops, dag iops, InstrItinClass itin,
957 string asm, string cstr, list<dag> pattern>
958 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
961 // Thumb1 instruction that can either be predicated or set CPSR.
962 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
964 string opc, string asm, string cstr, list<dag> pattern>
965 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
966 let OutOperandList = !con(oops, (outs s_cc_out:$s));
967 let InOperandList = !con(iops, (ins pred:$p));
968 let AsmString = !strconcat(opc, "${s}${p}", asm);
969 let Pattern = pattern;
970 let thumbArithFlagSetting = 1;
971 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
972 let DecoderNamespace = "ThumbSBit";
975 class T1sI<dag oops, dag iops, InstrItinClass itin,
976 string opc, string asm, list<dag> pattern>
977 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
979 // Two-address instructions
980 class T1sIt<dag oops, dag iops, InstrItinClass itin,
981 string opc, string asm, list<dag> pattern>
982 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
983 "$Rn = $Rdn", pattern>;
985 // Thumb1 instruction that can be predicated.
986 class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
988 string opc, string asm, string cstr, list<dag> pattern>
989 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
990 let OutOperandList = oops;
991 let InOperandList = !con(iops, (ins pred:$p));
992 let AsmString = !strconcat(opc, "${p}", asm);
993 let Pattern = pattern;
994 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
997 class T1pI<dag oops, dag iops, InstrItinClass itin,
998 string opc, string asm, list<dag> pattern>
999 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
1001 // Two-address instructions
1002 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1003 string opc, string asm, list<dag> pattern>
1004 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
1005 "$Rn = $Rdn", pattern>;
1007 class T1pIs<dag oops, dag iops,
1008 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1009 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
1011 class Encoding16 : Encoding {
1012 let Inst{31-16} = 0x0000;
1015 // A6.2 16-bit Thumb instruction encoding
1016 class T1Encoding<bits<6> opcode> : Encoding16 {
1017 let Inst{15-10} = opcode;
1020 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1021 class T1General<bits<5> opcode> : Encoding16 {
1022 let Inst{15-14} = 0b00;
1023 let Inst{13-9} = opcode;
1026 // A6.2.2 Data-processing encoding.
1027 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1028 let Inst{15-10} = 0b010000;
1029 let Inst{9-6} = opcode;
1032 // A6.2.3 Special data instructions and branch and exchange encoding.
1033 class T1Special<bits<4> opcode> : Encoding16 {
1034 let Inst{15-10} = 0b010001;
1035 let Inst{9-6} = opcode;
1038 // A6.2.4 Load/store single data item encoding.
1039 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1040 let Inst{15-12} = opA;
1041 let Inst{11-9} = opB;
1043 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1045 class T1BranchCond<bits<4> opcode> : Encoding16 {
1046 let Inst{15-12} = opcode;
1049 // Helper classes to encode Thumb1 loads and stores. For immediates, the
1050 // following bits are used for "opA" (see A6.2.4):
1052 // 0b0110 => Immediate, 4 bytes
1053 // 0b1000 => Immediate, 2 bytes
1054 // 0b0111 => Immediate, 1 byte
1055 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1056 InstrItinClass itin, string opc, string asm,
1058 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1059 T1LoadStore<0b0101, opcode> {
1062 let Inst{8-6} = addr{5-3}; // Rm
1063 let Inst{5-3} = addr{2-0}; // Rn
1066 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1067 InstrItinClass itin, string opc, string asm,
1069 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1070 T1LoadStore<opA, {opB,?,?}> {
1073 let Inst{10-6} = addr{7-3}; // imm5
1074 let Inst{5-3} = addr{2-0}; // Rn
1078 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1079 class T1Misc<bits<7> opcode> : Encoding16 {
1080 let Inst{15-12} = 0b1011;
1081 let Inst{11-5} = opcode;
1084 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1085 class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
1086 InstrItinClass itin,
1087 string opc, string asm, string cstr, list<dag> pattern>
1088 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1089 let OutOperandList = oops;
1090 let InOperandList = !con(iops, (ins pred:$p));
1091 let AsmString = !strconcat(opc, "${p}", asm);
1092 let Pattern = pattern;
1093 list<Predicate> Predicates = [IsThumb2];
1094 let DecoderNamespace = "Thumb2";
1097 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1098 // input operand since by default it's a zero register. It will become an
1099 // implicit def once it's "flipped".
1101 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1103 class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
1104 InstrItinClass itin,
1105 string opc, string asm, string cstr, list<dag> pattern>
1106 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1107 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1110 let OutOperandList = oops;
1111 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1112 let AsmString = !strconcat(opc, "${s}${p}", asm);
1113 let Pattern = pattern;
1114 list<Predicate> Predicates = [IsThumb2];
1115 let DecoderNamespace = "Thumb2";
1119 class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
1120 InstrItinClass itin,
1121 string asm, string cstr, list<dag> pattern>
1122 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1123 let OutOperandList = oops;
1124 let InOperandList = iops;
1125 let AsmString = asm;
1126 let Pattern = pattern;
1127 list<Predicate> Predicates = [IsThumb2];
1128 let DecoderNamespace = "Thumb2";
1131 class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
1132 InstrItinClass itin,
1133 string asm, string cstr, list<dag> pattern>
1134 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1135 let OutOperandList = oops;
1136 let InOperandList = iops;
1137 let AsmString = asm;
1138 let Pattern = pattern;
1139 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1140 let DecoderNamespace = "Thumb";
1143 class T2I<dag oops, dag iops, InstrItinClass itin,
1144 string opc, string asm, list<dag> pattern>
1145 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1146 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1147 string opc, string asm, list<dag> pattern>
1148 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
1149 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1150 string opc, string asm, list<dag> pattern>
1151 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
1152 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1153 string opc, string asm, list<dag> pattern>
1154 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
1155 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1156 string opc, string asm, list<dag> pattern>
1157 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
1158 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1159 string opc, string asm, string cstr, list<dag> pattern>
1160 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1165 let Inst{31-25} = 0b1110100;
1167 let Inst{23} = addr{8};
1170 let Inst{20} = isLoad;
1171 let Inst{19-16} = addr{12-9};
1172 let Inst{15-12} = Rt{3-0};
1173 let Inst{11-8} = Rt2{3-0};
1174 let Inst{7-0} = addr{7-0};
1176 class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops,
1177 InstrItinClass itin, string opc, string asm, string cstr,
1179 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1185 let Inst{31-25} = 0b1110100;
1187 let Inst{23} = imm{8};
1190 let Inst{20} = isLoad;
1191 let Inst{19-16} = addr;
1192 let Inst{15-12} = Rt{3-0};
1193 let Inst{11-8} = Rt2{3-0};
1194 let Inst{7-0} = imm{7-0};
1197 class T2sI<dag oops, dag iops, InstrItinClass itin,
1198 string opc, string asm, list<dag> pattern>
1199 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1201 class T2XI<dag oops, dag iops, InstrItinClass itin,
1202 string asm, list<dag> pattern>
1203 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1204 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1205 string asm, list<dag> pattern>
1206 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1208 // Move to/from coprocessor instructions
1209 class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern>
1210 : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> {
1211 let Inst{31-28} = opc;
1214 // Two-address instructions
1215 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1216 string asm, string cstr, list<dag> pattern>
1217 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
1219 // T2Ipreldst - Thumb2 pre-indexed load / store instructions.
1220 class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre,
1222 AddrMode am, IndexMode im, InstrItinClass itin,
1223 string opc, string asm, string cstr, list<dag> pattern>
1224 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1225 let OutOperandList = oops;
1226 let InOperandList = !con(iops, (ins pred:$p));
1227 let AsmString = !strconcat(opc, "${p}", asm);
1228 let Pattern = pattern;
1229 list<Predicate> Predicates = [IsThumb2];
1230 let DecoderNamespace = "Thumb2";
1234 let Inst{31-27} = 0b11111;
1235 let Inst{26-25} = 0b00;
1236 let Inst{24} = signed;
1238 let Inst{22-21} = opcod;
1239 let Inst{20} = load;
1240 let Inst{19-16} = addr{12-9};
1241 let Inst{15-12} = Rt{3-0};
1243 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1244 let Inst{10} = pre; // The P bit.
1245 let Inst{9} = addr{8}; // Sign bit
1246 let Inst{8} = 1; // The W bit.
1247 let Inst{7-0} = addr{7-0};
1249 let DecoderMethod = "DecodeT2LdStPre";
1252 // T2Ipostldst - Thumb2 post-indexed load / store instructions.
1253 class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre,
1255 AddrMode am, IndexMode im, InstrItinClass itin,
1256 string opc, string asm, string cstr, list<dag> pattern>
1257 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1258 let OutOperandList = oops;
1259 let InOperandList = !con(iops, (ins pred:$p));
1260 let AsmString = !strconcat(opc, "${p}", asm);
1261 let Pattern = pattern;
1262 list<Predicate> Predicates = [IsThumb2];
1263 let DecoderNamespace = "Thumb2";
1268 let Inst{31-27} = 0b11111;
1269 let Inst{26-25} = 0b00;
1270 let Inst{24} = signed;
1272 let Inst{22-21} = opcod;
1273 let Inst{20} = load;
1274 let Inst{19-16} = Rn;
1275 let Inst{15-12} = Rt{3-0};
1277 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1278 let Inst{10} = pre; // The P bit.
1279 let Inst{9} = offset{8}; // Sign bit
1280 let Inst{8} = 1; // The W bit.
1281 let Inst{7-0} = offset{7-0};
1283 let DecoderMethod = "DecodeT2LdStPre";
1286 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1287 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1288 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1291 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1292 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1293 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1296 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1297 class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1298 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1301 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1302 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1303 list<Predicate> Predicates = [IsThumb2];
1306 //===----------------------------------------------------------------------===//
1308 //===----------------------------------------------------------------------===//
1309 // ARM VFP Instruction templates.
1312 // Almost all VFP instructions are predicable.
1313 class VFPI<dag oops, dag iops, AddrMode am, int sz,
1314 IndexMode im, Format f, InstrItinClass itin,
1315 string opc, string asm, string cstr, list<dag> pattern>
1316 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1318 let Inst{31-28} = p;
1319 let OutOperandList = oops;
1320 let InOperandList = !con(iops, (ins pred:$p));
1321 let AsmString = !strconcat(opc, "${p}", asm);
1322 let Pattern = pattern;
1323 let PostEncoderMethod = "VFPThumb2PostEncoder";
1324 let DecoderNamespace = "VFP";
1325 list<Predicate> Predicates = [HasVFP2];
1329 class VFPXI<dag oops, dag iops, AddrMode am, int sz,
1330 IndexMode im, Format f, InstrItinClass itin,
1331 string asm, string cstr, list<dag> pattern>
1332 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1334 let Inst{31-28} = p;
1335 let OutOperandList = oops;
1336 let InOperandList = iops;
1337 let AsmString = asm;
1338 let Pattern = pattern;
1339 let PostEncoderMethod = "VFPThumb2PostEncoder";
1340 let DecoderNamespace = "VFP";
1341 list<Predicate> Predicates = [HasVFP2];
1344 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1345 string opc, string asm, list<dag> pattern>
1346 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
1347 opc, asm, "", pattern> {
1348 let PostEncoderMethod = "VFPThumb2PostEncoder";
1351 // ARM VFP addrmode5 loads and stores
1352 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1353 InstrItinClass itin,
1354 string opc, string asm, list<dag> pattern>
1355 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1356 VFPLdStFrm, itin, opc, asm, "", pattern> {
1357 // Instruction operands.
1361 // Encode instruction operands.
1362 let Inst{23} = addr{8}; // U (add = (U == '1'))
1363 let Inst{22} = Dd{4};
1364 let Inst{19-16} = addr{12-9}; // Rn
1365 let Inst{15-12} = Dd{3-0};
1366 let Inst{7-0} = addr{7-0}; // imm8
1368 // TODO: Mark the instructions with the appropriate subtarget info.
1369 let Inst{27-24} = opcod1;
1370 let Inst{21-20} = opcod2;
1371 let Inst{11-9} = 0b101;
1372 let Inst{8} = 1; // Double precision
1374 // Loads & stores operate on both NEON and VFP pipelines.
1375 let D = VFPNeonDomain;
1378 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1379 InstrItinClass itin,
1380 string opc, string asm, list<dag> pattern>
1381 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1382 VFPLdStFrm, itin, opc, asm, "", pattern> {
1383 // Instruction operands.
1387 // Encode instruction operands.
1388 let Inst{23} = addr{8}; // U (add = (U == '1'))
1389 let Inst{22} = Sd{0};
1390 let Inst{19-16} = addr{12-9}; // Rn
1391 let Inst{15-12} = Sd{4-1};
1392 let Inst{7-0} = addr{7-0}; // imm8
1394 // TODO: Mark the instructions with the appropriate subtarget info.
1395 let Inst{27-24} = opcod1;
1396 let Inst{21-20} = opcod2;
1397 let Inst{11-9} = 0b101;
1398 let Inst{8} = 0; // Single precision
1400 // Loads & stores operate on both NEON and VFP pipelines.
1401 let D = VFPNeonDomain;
1404 // VFP Load / store multiple pseudo instructions.
1405 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1407 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1409 let OutOperandList = oops;
1410 let InOperandList = !con(iops, (ins pred:$p));
1411 let Pattern = pattern;
1412 list<Predicate> Predicates = [HasVFP2];
1415 // Load / store multiple
1416 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1417 string asm, string cstr, list<dag> pattern>
1418 : VFPXI<oops, iops, AddrMode4, 4, im,
1419 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1420 // Instruction operands.
1424 // Encode instruction operands.
1425 let Inst{19-16} = Rn;
1426 let Inst{22} = regs{12};
1427 let Inst{15-12} = regs{11-8};
1428 let Inst{7-0} = regs{7-0};
1430 // TODO: Mark the instructions with the appropriate subtarget info.
1431 let Inst{27-25} = 0b110;
1432 let Inst{11-9} = 0b101;
1433 let Inst{8} = 1; // Double precision
1436 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1437 string asm, string cstr, list<dag> pattern>
1438 : VFPXI<oops, iops, AddrMode4, 4, im,
1439 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1440 // Instruction operands.
1444 // Encode instruction operands.
1445 let Inst{19-16} = Rn;
1446 let Inst{22} = regs{8};
1447 let Inst{15-12} = regs{12-9};
1448 let Inst{7-0} = regs{7-0};
1450 // TODO: Mark the instructions with the appropriate subtarget info.
1451 let Inst{27-25} = 0b110;
1452 let Inst{11-9} = 0b101;
1453 let Inst{8} = 0; // Single precision
1456 // Double precision, unary
1457 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1458 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1459 string asm, list<dag> pattern>
1460 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1461 // Instruction operands.
1465 // Encode instruction operands.
1466 let Inst{3-0} = Dm{3-0};
1467 let Inst{5} = Dm{4};
1468 let Inst{15-12} = Dd{3-0};
1469 let Inst{22} = Dd{4};
1471 let Inst{27-23} = opcod1;
1472 let Inst{21-20} = opcod2;
1473 let Inst{19-16} = opcod3;
1474 let Inst{11-9} = 0b101;
1475 let Inst{8} = 1; // Double precision
1476 let Inst{7-6} = opcod4;
1477 let Inst{4} = opcod5;
1480 // Double precision, binary
1481 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1482 dag iops, InstrItinClass itin, string opc, string asm,
1484 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1485 // Instruction operands.
1490 // Encode instruction operands.
1491 let Inst{3-0} = Dm{3-0};
1492 let Inst{5} = Dm{4};
1493 let Inst{19-16} = Dn{3-0};
1494 let Inst{7} = Dn{4};
1495 let Inst{15-12} = Dd{3-0};
1496 let Inst{22} = Dd{4};
1498 let Inst{27-23} = opcod1;
1499 let Inst{21-20} = opcod2;
1500 let Inst{11-9} = 0b101;
1501 let Inst{8} = 1; // Double precision
1506 // Single precision, unary
1507 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1508 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1509 string asm, list<dag> pattern>
1510 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1511 // Instruction operands.
1515 // Encode instruction operands.
1516 let Inst{3-0} = Sm{4-1};
1517 let Inst{5} = Sm{0};
1518 let Inst{15-12} = Sd{4-1};
1519 let Inst{22} = Sd{0};
1521 let Inst{27-23} = opcod1;
1522 let Inst{21-20} = opcod2;
1523 let Inst{19-16} = opcod3;
1524 let Inst{11-9} = 0b101;
1525 let Inst{8} = 0; // Single precision
1526 let Inst{7-6} = opcod4;
1527 let Inst{4} = opcod5;
1530 // Single precision unary, if no NEON. Same as ASuI except not available if
1532 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1533 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1534 string asm, list<dag> pattern>
1535 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1537 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1540 // Single precision, binary
1541 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1542 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1543 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1544 // Instruction operands.
1549 // Encode instruction operands.
1550 let Inst{3-0} = Sm{4-1};
1551 let Inst{5} = Sm{0};
1552 let Inst{19-16} = Sn{4-1};
1553 let Inst{7} = Sn{0};
1554 let Inst{15-12} = Sd{4-1};
1555 let Inst{22} = Sd{0};
1557 let Inst{27-23} = opcod1;
1558 let Inst{21-20} = opcod2;
1559 let Inst{11-9} = 0b101;
1560 let Inst{8} = 0; // Single precision
1565 // Single precision binary, if no NEON. Same as ASbI except not available if
1567 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1568 dag iops, InstrItinClass itin, string opc, string asm,
1570 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1571 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1573 // Instruction operands.
1578 // Encode instruction operands.
1579 let Inst{3-0} = Sm{4-1};
1580 let Inst{5} = Sm{0};
1581 let Inst{19-16} = Sn{4-1};
1582 let Inst{7} = Sn{0};
1583 let Inst{15-12} = Sd{4-1};
1584 let Inst{22} = Sd{0};
1587 // VFP conversion instructions
1588 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1589 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1591 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1592 let Inst{27-23} = opcod1;
1593 let Inst{21-20} = opcod2;
1594 let Inst{19-16} = opcod3;
1595 let Inst{11-8} = opcod4;
1600 // VFP conversion between floating-point and fixed-point
1601 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1602 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1604 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1606 // size (fixed-point number): sx == 0 ? 16 : 32
1607 let Inst{7} = op5; // sx
1608 let Inst{5} = fbits{0};
1609 let Inst{3-0} = fbits{4-1};
1612 // VFP conversion instructions, if no NEON
1613 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1614 dag oops, dag iops, InstrItinClass itin,
1615 string opc, string asm, list<dag> pattern>
1616 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1618 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1621 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1622 InstrItinClass itin,
1623 string opc, string asm, list<dag> pattern>
1624 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1625 let Inst{27-20} = opcod1;
1626 let Inst{11-8} = opcod2;
1630 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1631 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1632 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1634 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1635 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1636 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1638 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1639 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1640 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1642 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1643 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1644 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1646 //===----------------------------------------------------------------------===//
1648 //===----------------------------------------------------------------------===//
1649 // ARM NEON Instruction templates.
1652 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1653 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1655 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1656 let OutOperandList = oops;
1657 let InOperandList = !con(iops, (ins pred:$p));
1658 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1659 let Pattern = pattern;
1660 list<Predicate> Predicates = [HasNEON];
1661 let DecoderNamespace = "NEON";
1664 // Same as NeonI except it does not have a "data type" specifier.
1665 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1666 InstrItinClass itin, string opc, string asm, string cstr,
1668 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1669 let OutOperandList = oops;
1670 let InOperandList = !con(iops, (ins pred:$p));
1671 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1672 let Pattern = pattern;
1673 list<Predicate> Predicates = [HasNEON];
1674 let DecoderNamespace = "NEON";
1677 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1678 dag oops, dag iops, InstrItinClass itin,
1679 string opc, string dt, string asm, string cstr, list<dag> pattern>
1680 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1682 let Inst{31-24} = 0b11110100;
1683 let Inst{23} = op23;
1684 let Inst{21-20} = op21_20;
1685 let Inst{11-8} = op11_8;
1686 let Inst{7-4} = op7_4;
1688 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1689 let DecoderNamespace = "NEONLoadStore";
1695 let Inst{22} = Vd{4};
1696 let Inst{15-12} = Vd{3-0};
1697 let Inst{19-16} = Rn{3-0};
1698 let Inst{3-0} = Rm{3-0};
1701 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1702 dag oops, dag iops, InstrItinClass itin,
1703 string opc, string dt, string asm, string cstr, list<dag> pattern>
1704 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1705 dt, asm, cstr, pattern> {
1709 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1710 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1712 let OutOperandList = oops;
1713 let InOperandList = !con(iops, (ins pred:$p));
1714 list<Predicate> Predicates = [HasNEON];
1717 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1719 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1721 let OutOperandList = oops;
1722 let InOperandList = !con(iops, (ins pred:$p));
1723 let Pattern = pattern;
1724 list<Predicate> Predicates = [HasNEON];
1727 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1728 string opc, string dt, string asm, string cstr, list<dag> pattern>
1729 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1731 let Inst{31-25} = 0b1111001;
1732 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1733 let DecoderNamespace = "NEONData";
1736 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1737 string opc, string asm, string cstr, list<dag> pattern>
1738 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1740 let Inst{31-25} = 0b1111001;
1741 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1742 let DecoderNamespace = "NEONData";
1745 // NEON "one register and a modified immediate" format.
1746 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1748 dag oops, dag iops, InstrItinClass itin,
1749 string opc, string dt, string asm, string cstr,
1751 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1752 let Inst{23} = op23;
1753 let Inst{21-19} = op21_19;
1754 let Inst{11-8} = op11_8;
1760 // Instruction operands.
1764 let Inst{15-12} = Vd{3-0};
1765 let Inst{22} = Vd{4};
1766 let Inst{24} = SIMM{7};
1767 let Inst{18-16} = SIMM{6-4};
1768 let Inst{3-0} = SIMM{3-0};
1769 let DecoderMethod = "DecodeNEONModImmInstruction";
1772 // NEON 2 vector register format.
1773 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1774 bits<5> op11_7, bit op6, bit op4,
1775 dag oops, dag iops, InstrItinClass itin,
1776 string opc, string dt, string asm, string cstr, list<dag> pattern>
1777 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1778 let Inst{24-23} = op24_23;
1779 let Inst{21-20} = op21_20;
1780 let Inst{19-18} = op19_18;
1781 let Inst{17-16} = op17_16;
1782 let Inst{11-7} = op11_7;
1786 // Instruction operands.
1790 let Inst{15-12} = Vd{3-0};
1791 let Inst{22} = Vd{4};
1792 let Inst{3-0} = Vm{3-0};
1793 let Inst{5} = Vm{4};
1796 // Same as N2V except it doesn't have a datatype suffix.
1797 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1798 bits<5> op11_7, bit op6, bit op4,
1799 dag oops, dag iops, InstrItinClass itin,
1800 string opc, string asm, string cstr, list<dag> pattern>
1801 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1802 let Inst{24-23} = op24_23;
1803 let Inst{21-20} = op21_20;
1804 let Inst{19-18} = op19_18;
1805 let Inst{17-16} = op17_16;
1806 let Inst{11-7} = op11_7;
1810 // Instruction operands.
1814 let Inst{15-12} = Vd{3-0};
1815 let Inst{22} = Vd{4};
1816 let Inst{3-0} = Vm{3-0};
1817 let Inst{5} = Vm{4};
1820 // NEON 2 vector register with immediate.
1821 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1822 dag oops, dag iops, Format f, InstrItinClass itin,
1823 string opc, string dt, string asm, string cstr, list<dag> pattern>
1824 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1825 let Inst{24} = op24;
1826 let Inst{23} = op23;
1827 let Inst{11-8} = op11_8;
1832 // Instruction operands.
1837 let Inst{15-12} = Vd{3-0};
1838 let Inst{22} = Vd{4};
1839 let Inst{3-0} = Vm{3-0};
1840 let Inst{5} = Vm{4};
1841 let Inst{21-16} = SIMM{5-0};
1844 // NEON 3 vector register format.
1846 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1847 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1848 string opc, string dt, string asm, string cstr,
1850 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1851 let Inst{24} = op24;
1852 let Inst{23} = op23;
1853 let Inst{21-20} = op21_20;
1854 let Inst{11-8} = op11_8;
1859 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1860 dag oops, dag iops, Format f, InstrItinClass itin,
1861 string opc, string dt, string asm, string cstr, list<dag> pattern>
1862 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1863 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1865 // Instruction operands.
1870 let Inst{15-12} = Vd{3-0};
1871 let Inst{22} = Vd{4};
1872 let Inst{19-16} = Vn{3-0};
1873 let Inst{7} = Vn{4};
1874 let Inst{3-0} = Vm{3-0};
1875 let Inst{5} = Vm{4};
1878 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1879 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1880 string opc, string dt, string asm, string cstr,
1882 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1883 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1885 // Instruction operands.
1891 let Inst{15-12} = Vd{3-0};
1892 let Inst{22} = Vd{4};
1893 let Inst{19-16} = Vn{3-0};
1894 let Inst{7} = Vn{4};
1895 let Inst{3-0} = Vm{3-0};
1899 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1900 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1901 string opc, string dt, string asm, string cstr,
1903 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1904 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1906 // Instruction operands.
1912 let Inst{15-12} = Vd{3-0};
1913 let Inst{22} = Vd{4};
1914 let Inst{19-16} = Vn{3-0};
1915 let Inst{7} = Vn{4};
1916 let Inst{2-0} = Vm{2-0};
1917 let Inst{5} = lane{1};
1918 let Inst{3} = lane{0};
1921 // Same as N3V except it doesn't have a data type suffix.
1922 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1924 dag oops, dag iops, Format f, InstrItinClass itin,
1925 string opc, string asm, string cstr, list<dag> pattern>
1926 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1927 let Inst{24} = op24;
1928 let Inst{23} = op23;
1929 let Inst{21-20} = op21_20;
1930 let Inst{11-8} = op11_8;
1934 // Instruction operands.
1939 let Inst{15-12} = Vd{3-0};
1940 let Inst{22} = Vd{4};
1941 let Inst{19-16} = Vn{3-0};
1942 let Inst{7} = Vn{4};
1943 let Inst{3-0} = Vm{3-0};
1944 let Inst{5} = Vm{4};
1947 // NEON VMOVs between scalar and core registers.
1948 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1949 dag oops, dag iops, Format f, InstrItinClass itin,
1950 string opc, string dt, string asm, list<dag> pattern>
1951 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
1953 let Inst{27-20} = opcod1;
1954 let Inst{11-8} = opcod2;
1955 let Inst{6-5} = opcod3;
1957 // A8.6.303, A8.6.328, A8.6.329
1958 let Inst{3-0} = 0b0000;
1960 let OutOperandList = oops;
1961 let InOperandList = !con(iops, (ins pred:$p));
1962 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1963 let Pattern = pattern;
1964 list<Predicate> Predicates = [HasNEON];
1966 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1967 let DecoderNamespace = "NEONDup";
1974 let Inst{31-28} = p{3-0};
1976 let Inst{19-16} = V{3-0};
1977 let Inst{15-12} = R{3-0};
1979 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1980 dag oops, dag iops, InstrItinClass itin,
1981 string opc, string dt, string asm, list<dag> pattern>
1982 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1983 opc, dt, asm, pattern>;
1984 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1985 dag oops, dag iops, InstrItinClass itin,
1986 string opc, string dt, string asm, list<dag> pattern>
1987 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1988 opc, dt, asm, pattern>;
1989 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1990 dag oops, dag iops, InstrItinClass itin,
1991 string opc, string dt, string asm, list<dag> pattern>
1992 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1993 opc, dt, asm, pattern>;
1995 // Vector Duplicate Lane (from scalar to all elements)
1996 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1997 InstrItinClass itin, string opc, string dt, string asm,
1999 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
2000 let Inst{24-23} = 0b11;
2001 let Inst{21-20} = 0b11;
2002 let Inst{19-16} = op19_16;
2003 let Inst{11-7} = 0b11000;
2010 let Inst{22} = Vd{4};
2011 let Inst{15-12} = Vd{3-0};
2012 let Inst{5} = Vm{4};
2013 let Inst{3-0} = Vm{3-0};
2016 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
2017 // for single-precision FP.
2018 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
2019 list<Predicate> Predicates = [HasNEON,UseNEONForFP];
2022 // VFP/NEON Instruction aliases for type suffices.
2023 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
2024 InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>;
2026 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
2027 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
2028 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
2029 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
2030 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
2033 multiclass NEONDTAnyInstAlias<string opc, string asm, dag Result> {
2034 let Predicates = [HasNEON] in {
2035 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
2036 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
2037 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
2038 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
2042 // The same alias classes using AsmPseudo instead, for the more complex
2043 // stuff in NEON that InstAlias can't quite handle.
2044 // Note that we can't use anonymous defm references here like we can
2045 // above, as we care about the ultimate instruction enum names generated, unlike
2046 // for instalias defs.
2047 class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
2048 AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>;
2050 // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.
2051 def : TokenAlias<".s8", ".i8">;
2052 def : TokenAlias<".u8", ".i8">;
2053 def : TokenAlias<".s16", ".i16">;
2054 def : TokenAlias<".u16", ".i16">;
2055 def : TokenAlias<".s32", ".i32">;
2056 def : TokenAlias<".u32", ".i32">;
2057 def : TokenAlias<".s64", ".i64">;
2058 def : TokenAlias<".u64", ".i64">;
2060 def : TokenAlias<".i8", ".8">;
2061 def : TokenAlias<".i16", ".16">;
2062 def : TokenAlias<".i32", ".32">;
2063 def : TokenAlias<".i64", ".64">;
2065 def : TokenAlias<".p8", ".8">;
2066 def : TokenAlias<".p16", ".16">;
2068 def : TokenAlias<".f32", ".32">;
2069 def : TokenAlias<".f64", ".64">;
2070 def : TokenAlias<".f", ".f32">;
2071 def : TokenAlias<".d", ".f64">;