1 //===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // The instruction has an Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
87 // FIXME: Once the JIT is MC-ized, these can go away.
89 class AddrMode<bits<5> val> {
92 def AddrModeNone : AddrMode<0>;
93 def AddrMode1 : AddrMode<1>;
94 def AddrMode2 : AddrMode<2>;
95 def AddrMode3 : AddrMode<3>;
96 def AddrMode4 : AddrMode<4>;
97 def AddrMode5 : AddrMode<5>;
98 def AddrMode6 : AddrMode<6>;
99 def AddrModeT1_1 : AddrMode<7>;
100 def AddrModeT1_2 : AddrMode<8>;
101 def AddrModeT1_4 : AddrMode<9>;
102 def AddrModeT1_s : AddrMode<10>;
103 def AddrModeT2_i12 : AddrMode<11>;
104 def AddrModeT2_i8 : AddrMode<12>;
105 def AddrModeT2_so : AddrMode<13>;
106 def AddrModeT2_pc : AddrMode<14>;
107 def AddrModeT2_i8s4 : AddrMode<15>;
108 def AddrMode_i12 : AddrMode<16>;
110 // Load / store index mode.
111 class IndexMode<bits<2> val> {
114 def IndexModeNone : IndexMode<0>;
115 def IndexModePre : IndexMode<1>;
116 def IndexModePost : IndexMode<2>;
117 def IndexModeUpd : IndexMode<3>;
119 // Instruction execution domain.
120 class Domain<bits<3> val> {
123 def GenericDomain : Domain<0>;
124 def VFPDomain : Domain<1>; // Instructions in VFP domain only
125 def NeonDomain : Domain<2>; // Instructions in Neon domain only
126 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
127 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
129 //===----------------------------------------------------------------------===//
130 // ARM special operands.
133 def CondCodeOperand : AsmOperandClass {
134 let Name = "CondCode";
135 let SuperClasses = [];
138 def CCOutOperand : AsmOperandClass {
140 let SuperClasses = [];
143 def MemBarrierOptOperand : AsmOperandClass {
144 let Name = "MemBarrierOpt";
145 let SuperClasses = [];
146 let ParserMethod = "tryParseMemBarrierOptOperand";
149 def ProcIFlagsOperand : AsmOperandClass {
150 let Name = "ProcIFlags";
151 let SuperClasses = [];
152 let ParserMethod = "tryParseProcIFlagsOperand";
155 def MSRMaskOperand : AsmOperandClass {
156 let Name = "MSRMask";
157 let SuperClasses = [];
158 let ParserMethod = "tryParseMSRMaskOperand";
161 // ARM imod and iflag operands, used only by the CPS instruction.
162 def imod_op : Operand<i32> {
163 let PrintMethod = "printCPSIMod";
166 def iflags_op : Operand<i32> {
167 let PrintMethod = "printCPSIFlag";
168 let ParserMatchClass = ProcIFlagsOperand;
171 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
172 // register whose default is 0 (no register).
173 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
174 (ops (i32 14), (i32 zero_reg))> {
175 let PrintMethod = "printPredicateOperand";
176 let ParserMatchClass = CondCodeOperand;
179 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
180 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
181 let EncoderMethod = "getCCOutOpValue";
182 let PrintMethod = "printSBitModifierOperand";
183 let ParserMatchClass = CCOutOperand;
186 // Same as cc_out except it defaults to setting CPSR.
187 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
188 let EncoderMethod = "getCCOutOpValue";
189 let PrintMethod = "printSBitModifierOperand";
190 let ParserMatchClass = CCOutOperand;
193 // ARM special operands for disassembly only.
195 def setend_op : Operand<i32> {
196 let PrintMethod = "printSetendOperand";
199 def msr_mask : Operand<i32> {
200 let PrintMethod = "printMSRMaskOperand";
201 let ParserMatchClass = MSRMaskOperand;
204 // Shift Right Immediate - A shift right immediate is encoded differently from
205 // other shift immediates. The imm6 field is encoded like so:
208 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
209 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
210 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
211 // 64 64 - <imm> is encoded in imm6<5:0>
212 def shr_imm8 : Operand<i32> {
213 let EncoderMethod = "getShiftRight8Imm";
215 def shr_imm16 : Operand<i32> {
216 let EncoderMethod = "getShiftRight16Imm";
218 def shr_imm32 : Operand<i32> {
219 let EncoderMethod = "getShiftRight32Imm";
221 def shr_imm64 : Operand<i32> {
222 let EncoderMethod = "getShiftRight64Imm";
225 //===----------------------------------------------------------------------===//
226 // ARM Instruction templates.
229 class InstTemplate<AddrMode am, int sz, IndexMode im,
230 Format f, Domain d, string cstr, InstrItinClass itin>
232 let Namespace = "ARM";
237 bits<2> IndexModeBits = IM.Value;
239 bits<6> Form = F.Value;
241 bit isUnaryDataProc = 0;
242 bit canXformTo16Bit = 0;
244 // If this is a pseudo instruction, mark it isCodeGenOnly.
245 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
247 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
248 let TSFlags{4-0} = AM.Value;
249 let TSFlags{6-5} = IndexModeBits;
250 let TSFlags{12-7} = Form;
251 let TSFlags{13} = isUnaryDataProc;
252 let TSFlags{14} = canXformTo16Bit;
253 let TSFlags{17-15} = D.Value;
255 let Constraints = cstr;
256 let Itinerary = itin;
263 class InstARM<AddrMode am, int sz, IndexMode im,
264 Format f, Domain d, string cstr, InstrItinClass itin>
265 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
267 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
268 // on by adding flavors to specific instructions.
269 class InstThumb<AddrMode am, int sz, IndexMode im,
270 Format f, Domain d, string cstr, InstrItinClass itin>
271 : InstTemplate<am, sz, im, f, d, cstr, itin>;
273 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
274 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
275 GenericDomain, "", itin> {
276 let OutOperandList = oops;
277 let InOperandList = iops;
278 let Pattern = pattern;
279 let isCodeGenOnly = 1;
283 // PseudoInst that's ARM-mode only.
284 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
286 : PseudoInst<oops, iops, itin, pattern> {
288 list<Predicate> Predicates = [IsARM];
291 // PseudoInst that's Thumb-mode only.
292 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
294 : PseudoInst<oops, iops, itin, pattern> {
296 list<Predicate> Predicates = [IsThumb];
299 // PseudoInst that's Thumb2-mode only.
300 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
302 : PseudoInst<oops, iops, itin, pattern> {
304 list<Predicate> Predicates = [IsThumb2];
307 class ARMPseudoExpand<dag oops, dag iops, int sz,
308 InstrItinClass itin, list<dag> pattern,
310 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
311 PseudoInstExpansion<Result>;
313 class tPseudoExpand<dag oops, dag iops, int sz,
314 InstrItinClass itin, list<dag> pattern,
316 : tPseudoInst<oops, iops, sz, itin, pattern>,
317 PseudoInstExpansion<Result>;
319 class t2PseudoExpand<dag oops, dag iops, int sz,
320 InstrItinClass itin, list<dag> pattern,
322 : t2PseudoInst<oops, iops, sz, itin, pattern>,
323 PseudoInstExpansion<Result>;
325 // Almost all ARM instructions are predicable.
326 class I<dag oops, dag iops, AddrMode am, int sz,
327 IndexMode im, Format f, InstrItinClass itin,
328 string opc, string asm, string cstr,
330 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
333 let OutOperandList = oops;
334 let InOperandList = !con(iops, (ins pred:$p));
335 let AsmString = !strconcat(opc, "${p}", asm);
336 let Pattern = pattern;
337 list<Predicate> Predicates = [IsARM];
340 // A few are not predicable
341 class InoP<dag oops, dag iops, AddrMode am, int sz,
342 IndexMode im, Format f, InstrItinClass itin,
343 string opc, string asm, string cstr,
345 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
346 let OutOperandList = oops;
347 let InOperandList = iops;
348 let AsmString = !strconcat(opc, asm);
349 let Pattern = pattern;
350 let isPredicable = 0;
351 list<Predicate> Predicates = [IsARM];
354 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
355 // operand since by default it's a zero register. It will become an implicit def
356 // once it's "flipped".
357 class sI<dag oops, dag iops, AddrMode am, int sz,
358 IndexMode im, Format f, InstrItinClass itin,
359 string opc, string asm, string cstr,
361 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
362 bits<4> p; // Predicate operand
363 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
367 let OutOperandList = oops;
368 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
369 let AsmString = !strconcat(opc, "${s}${p}", asm);
370 let Pattern = pattern;
371 list<Predicate> Predicates = [IsARM];
375 class XI<dag oops, dag iops, AddrMode am, int sz,
376 IndexMode im, Format f, InstrItinClass itin,
377 string asm, string cstr, list<dag> pattern>
378 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
379 let OutOperandList = oops;
380 let InOperandList = iops;
382 let Pattern = pattern;
383 list<Predicate> Predicates = [IsARM];
386 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
387 string opc, string asm, list<dag> pattern>
388 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
389 opc, asm, "", pattern>;
390 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
391 string opc, string asm, list<dag> pattern>
392 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
393 opc, asm, "", pattern>;
394 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
395 string asm, list<dag> pattern>
396 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
398 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
399 string opc, string asm, list<dag> pattern>
400 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
401 opc, asm, "", pattern>;
403 // Ctrl flow instructions
404 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
405 string opc, string asm, list<dag> pattern>
406 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
407 opc, asm, "", pattern> {
408 let Inst{27-24} = opcod;
410 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
411 string asm, list<dag> pattern>
412 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
414 let Inst{27-24} = opcod;
417 // BR_JT instructions
418 class JTI<dag oops, dag iops, InstrItinClass itin,
419 string asm, list<dag> pattern>
420 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
423 // Atomic load/store instructions
424 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
425 string opc, string asm, list<dag> pattern>
426 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
427 opc, asm, "", pattern> {
430 let Inst{27-23} = 0b00011;
431 let Inst{22-21} = opcod;
433 let Inst{19-16} = Rn;
434 let Inst{15-12} = Rt;
435 let Inst{11-0} = 0b111110011111;
437 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
438 string opc, string asm, list<dag> pattern>
439 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
440 opc, asm, "", pattern> {
444 let Inst{27-23} = 0b00011;
445 let Inst{22-21} = opcod;
447 let Inst{19-16} = addr;
448 let Inst{15-12} = Rd;
449 let Inst{11-4} = 0b11111001;
452 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
453 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
457 let Inst{27-23} = 0b00010;
459 let Inst{21-20} = 0b00;
460 let Inst{19-16} = Rn;
461 let Inst{15-12} = Rt;
462 let Inst{11-4} = 0b00001001;
466 // addrmode1 instructions
467 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
468 string opc, string asm, list<dag> pattern>
469 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
470 opc, asm, "", pattern> {
471 let Inst{24-21} = opcod;
472 let Inst{27-26} = 0b00;
474 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
475 string opc, string asm, list<dag> pattern>
476 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
477 opc, asm, "", pattern> {
478 let Inst{24-21} = opcod;
479 let Inst{27-26} = 0b00;
481 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
482 string asm, list<dag> pattern>
483 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
485 let Inst{24-21} = opcod;
486 let Inst{27-26} = 0b00;
491 // LDR/LDRB/STR/STRB/...
492 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
493 Format f, InstrItinClass itin, string opc, string asm,
495 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
497 let Inst{27-25} = op;
498 let Inst{24} = 1; // 24 == P
500 let Inst{22} = isByte;
501 let Inst{21} = 0; // 21 == W
504 // Indexed load/stores
505 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
506 IndexMode im, Format f, InstrItinClass itin, string opc,
507 string asm, string cstr, list<dag> pattern>
508 : I<oops, iops, AddrMode2, 4, im, f, itin,
509 opc, asm, cstr, pattern> {
511 let Inst{27-26} = 0b01;
512 let Inst{24} = isPre; // P bit
513 let Inst{22} = isByte; // B bit
514 let Inst{21} = isPre; // W bit
515 let Inst{20} = isLd; // L bit
516 let Inst{15-12} = Rt;
518 class AI2stridx<bit isByte, bit isPre, dag oops, dag iops,
519 IndexMode im, Format f, InstrItinClass itin, string opc,
520 string asm, string cstr, list<dag> pattern>
521 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
523 // AM2 store w/ two operands: (GPR, am2offset)
524 // {13} 1 == Rm, 0 == imm12
529 let Inst{25} = offset{13};
530 let Inst{23} = offset{12};
531 let Inst{19-16} = Rn;
532 let Inst{11-0} = offset{11-0};
534 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
535 // but for now use this class for STRT and STRBT.
536 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
537 IndexMode im, Format f, InstrItinClass itin, string opc,
538 string asm, string cstr, list<dag> pattern>
539 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
541 // AM2 store w/ two operands: (GPR, am2offset)
543 // {13} 1 == Rm, 0 == imm12
547 let Inst{25} = addr{13};
548 let Inst{23} = addr{12};
549 let Inst{19-16} = addr{17-14};
550 let Inst{11-0} = addr{11-0};
553 // addrmode3 instructions
554 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
555 InstrItinClass itin, string opc, string asm, list<dag> pattern>
556 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
557 opc, asm, "", pattern> {
560 let Inst{27-25} = 0b000;
561 let Inst{24} = 1; // P bit
562 let Inst{23} = addr{8}; // U bit
563 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
564 let Inst{21} = 0; // W bit
565 let Inst{20} = op20; // L bit
566 let Inst{19-16} = addr{12-9}; // Rn
567 let Inst{15-12} = Rt; // Rt
568 let Inst{11-8} = addr{7-4}; // imm7_4/zero
570 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
573 class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
574 IndexMode im, Format f, InstrItinClass itin, string opc,
575 string asm, string cstr, list<dag> pattern>
576 : I<oops, iops, AddrMode3, 4, im, f, itin,
577 opc, asm, cstr, pattern> {
579 let Inst{27-25} = 0b000;
580 let Inst{24} = isPre; // P bit
581 let Inst{21} = isPre; // W bit
582 let Inst{20} = op20; // L bit
583 let Inst{15-12} = Rt; // Rt
587 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
588 // but for now use this class for LDRSBT, LDRHT, LDSHT.
589 class AI3ldstidxT<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
590 IndexMode im, Format f, InstrItinClass itin, string opc,
591 string asm, string cstr, list<dag> pattern>
592 : I<oops, iops, AddrMode3, 4, im, f, itin,
593 opc, asm, cstr, pattern> {
594 // {13} 1 == imm8, 0 == Rm
601 let Inst{27-25} = 0b000;
602 let Inst{24} = isPre; // P bit
603 let Inst{23} = addr{8}; // U bit
604 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
605 let Inst{20} = op20; // L bit
606 let Inst{19-16} = addr{12-9}; // Rn
607 let Inst{15-12} = Rt; // Rt
608 let Inst{11-8} = addr{7-4}; // imm7_4/zero
610 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
611 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode3";
614 class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
615 IndexMode im, Format f, InstrItinClass itin, string opc,
616 string asm, string cstr, list<dag> pattern>
617 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
619 // AM3 store w/ two operands: (GPR, am3offset)
623 let Inst{27-25} = 0b000;
624 let Inst{23} = offset{8};
625 let Inst{22} = offset{9};
626 let Inst{19-16} = Rn;
627 let Inst{15-12} = Rt; // Rt
628 let Inst{11-8} = offset{7-4}; // imm7_4/zero
630 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
634 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
635 string opc, string asm, list<dag> pattern>
636 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
637 opc, asm, "", pattern> {
640 let Inst{27-25} = 0b000;
641 let Inst{24} = 1; // P bit
642 let Inst{23} = addr{8}; // U bit
643 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
644 let Inst{21} = 0; // W bit
645 let Inst{20} = 0; // L bit
646 let Inst{19-16} = addr{12-9}; // Rn
647 let Inst{15-12} = Rt; // Rt
648 let Inst{11-8} = addr{7-4}; // imm7_4/zero
650 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
653 // Pre-indexed stores
654 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
655 string opc, string asm, string cstr, list<dag> pattern>
656 : I<oops, iops, AddrMode3, 4, IndexModePre, f, itin,
657 opc, asm, cstr, pattern> {
659 let Inst{5} = 1; // H bit
660 let Inst{6} = 0; // S bit
662 let Inst{20} = 0; // L bit
663 let Inst{21} = 1; // W bit
664 let Inst{24} = 1; // P bit
665 let Inst{27-25} = 0b000;
667 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
668 string opc, string asm, string cstr, list<dag> pattern>
669 : I<oops, iops, AddrMode3, 4, IndexModePre, f, itin,
670 opc, asm, cstr, pattern> {
672 let Inst{5} = 1; // H bit
673 let Inst{6} = 1; // S bit
675 let Inst{20} = 0; // L bit
676 let Inst{21} = 1; // W bit
677 let Inst{24} = 1; // P bit
678 let Inst{27-25} = 0b000;
681 // Post-indexed stores
682 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
683 string opc, string asm, string cstr, list<dag> pattern>
684 : I<oops, iops, AddrMode3, 4, IndexModePost, f, itin,
685 opc, asm, cstr,pattern> {
686 // {13} 1 == imm8, 0 == Rm
693 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
695 let Inst{5} = 1; // H bit
696 let Inst{6} = 0; // S bit
698 let Inst{11-8} = addr{7-4}; // imm7_4/zero
699 let Inst{15-12} = Rt; // Rt
700 let Inst{19-16} = addr{12-9}; // Rn
701 let Inst{20} = 0; // L bit
702 let Inst{21} = 0; // W bit
703 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
704 let Inst{23} = addr{8}; // U bit
705 let Inst{24} = 0; // P bit
706 let Inst{27-25} = 0b000;
708 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
709 string opc, string asm, string cstr, list<dag> pattern>
710 : I<oops, iops, AddrMode3, 4, IndexModePost, f, itin,
711 opc, asm, cstr, pattern> {
713 let Inst{5} = 1; // H bit
714 let Inst{6} = 1; // S bit
716 let Inst{20} = 0; // L bit
717 let Inst{21} = 0; // W bit
718 let Inst{24} = 0; // P bit
719 let Inst{27-25} = 0b000;
722 // addrmode4 instructions
723 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
724 string asm, string cstr, list<dag> pattern>
725 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
730 let Inst{27-25} = 0b100;
731 let Inst{22} = 0; // S bit
732 let Inst{19-16} = Rn;
733 let Inst{15-0} = regs;
736 // Unsigned multiply, multiply-accumulate instructions.
737 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
738 string opc, string asm, list<dag> pattern>
739 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
740 opc, asm, "", pattern> {
741 let Inst{7-4} = 0b1001;
742 let Inst{20} = 0; // S bit
743 let Inst{27-21} = opcod;
745 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
746 string opc, string asm, list<dag> pattern>
747 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
748 opc, asm, "", pattern> {
749 let Inst{7-4} = 0b1001;
750 let Inst{27-21} = opcod;
753 // Most significant word multiply
754 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
755 InstrItinClass itin, string opc, string asm, list<dag> pattern>
756 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
757 opc, asm, "", pattern> {
761 let Inst{7-4} = opc7_4;
763 let Inst{27-21} = opcod;
764 let Inst{19-16} = Rd;
768 // MSW multiple w/ Ra operand
769 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
770 InstrItinClass itin, string opc, string asm, list<dag> pattern>
771 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
773 let Inst{15-12} = Ra;
776 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
777 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
778 InstrItinClass itin, string opc, string asm, list<dag> pattern>
779 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
780 opc, asm, "", pattern> {
786 let Inst{27-21} = opcod;
787 let Inst{6-5} = bit6_5;
791 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
792 InstrItinClass itin, string opc, string asm, list<dag> pattern>
793 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
795 let Inst{19-16} = Rd;
798 // AMulxyI with Ra operand
799 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
800 InstrItinClass itin, string opc, string asm, list<dag> pattern>
801 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
803 let Inst{15-12} = Ra;
806 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
807 InstrItinClass itin, string opc, string asm, list<dag> pattern>
808 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
811 let Inst{19-16} = RdHi;
812 let Inst{15-12} = RdLo;
815 // Extend instructions.
816 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
817 string opc, string asm, list<dag> pattern>
818 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
819 opc, asm, "", pattern> {
820 // All AExtI instructions have Rd and Rm register operands.
823 let Inst{15-12} = Rd;
825 let Inst{7-4} = 0b0111;
826 let Inst{9-8} = 0b00;
827 let Inst{27-20} = opcod;
830 // Misc Arithmetic instructions.
831 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
832 InstrItinClass itin, string opc, string asm, list<dag> pattern>
833 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
834 opc, asm, "", pattern> {
837 let Inst{27-20} = opcod;
838 let Inst{19-16} = 0b1111;
839 let Inst{15-12} = Rd;
840 let Inst{11-8} = 0b1111;
841 let Inst{7-4} = opc7_4;
846 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
847 string opc, string asm, list<dag> pattern>
848 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
849 opc, asm, "", pattern> {
854 let Inst{27-20} = opcod;
855 let Inst{19-16} = Rn;
856 let Inst{15-12} = Rd;
857 let Inst{11-7} = sh{7-3};
859 let Inst{5-4} = 0b01;
863 //===----------------------------------------------------------------------===//
865 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
866 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
867 list<Predicate> Predicates = [IsARM];
869 class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
870 list<Predicate> Predicates = [IsARM, HasV5T];
872 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
873 list<Predicate> Predicates = [IsARM, HasV5TE];
875 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
876 list<Predicate> Predicates = [IsARM, HasV6];
879 //===----------------------------------------------------------------------===//
880 // Thumb Instruction Format Definitions.
883 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
884 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
885 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
886 let OutOperandList = oops;
887 let InOperandList = iops;
889 let Pattern = pattern;
890 list<Predicate> Predicates = [IsThumb];
893 // TI - Thumb instruction.
894 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
895 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
897 // Two-address instructions
898 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
900 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
903 // tBL, tBX 32-bit instructions
904 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
905 dag oops, dag iops, InstrItinClass itin, string asm,
907 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
909 let Inst{31-27} = opcod1;
910 let Inst{15-14} = opcod2;
911 let Inst{12} = opcod3;
914 // BR_JT instructions
915 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
917 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
920 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
921 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
922 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
923 let OutOperandList = oops;
924 let InOperandList = iops;
926 let Pattern = pattern;
927 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
930 class T1I<dag oops, dag iops, InstrItinClass itin,
931 string asm, list<dag> pattern>
932 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
933 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
934 string asm, list<dag> pattern>
935 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
937 // Two-address instructions
938 class T1It<dag oops, dag iops, InstrItinClass itin,
939 string asm, string cstr, list<dag> pattern>
940 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
943 // Thumb1 instruction that can either be predicated or set CPSR.
944 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
946 string opc, string asm, string cstr, list<dag> pattern>
947 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
948 let OutOperandList = !con(oops, (outs s_cc_out:$s));
949 let InOperandList = !con(iops, (ins pred:$p));
950 let AsmString = !strconcat(opc, "${s}${p}", asm);
951 let Pattern = pattern;
952 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
955 class T1sI<dag oops, dag iops, InstrItinClass itin,
956 string opc, string asm, list<dag> pattern>
957 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
959 // Two-address instructions
960 class T1sIt<dag oops, dag iops, InstrItinClass itin,
961 string opc, string asm, list<dag> pattern>
962 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
963 "$Rn = $Rdn", pattern>;
965 // Thumb1 instruction that can be predicated.
966 class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
968 string opc, string asm, string cstr, list<dag> pattern>
969 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
970 let OutOperandList = oops;
971 let InOperandList = !con(iops, (ins pred:$p));
972 let AsmString = !strconcat(opc, "${p}", asm);
973 let Pattern = pattern;
974 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
977 class T1pI<dag oops, dag iops, InstrItinClass itin,
978 string opc, string asm, list<dag> pattern>
979 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
981 // Two-address instructions
982 class T1pIt<dag oops, dag iops, InstrItinClass itin,
983 string opc, string asm, list<dag> pattern>
984 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
985 "$Rn = $Rdn", pattern>;
987 class T1pIs<dag oops, dag iops,
988 InstrItinClass itin, string opc, string asm, list<dag> pattern>
989 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
991 class Encoding16 : Encoding {
992 let Inst{31-16} = 0x0000;
995 // A6.2 16-bit Thumb instruction encoding
996 class T1Encoding<bits<6> opcode> : Encoding16 {
997 let Inst{15-10} = opcode;
1000 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1001 class T1General<bits<5> opcode> : Encoding16 {
1002 let Inst{15-14} = 0b00;
1003 let Inst{13-9} = opcode;
1006 // A6.2.2 Data-processing encoding.
1007 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1008 let Inst{15-10} = 0b010000;
1009 let Inst{9-6} = opcode;
1012 // A6.2.3 Special data instructions and branch and exchange encoding.
1013 class T1Special<bits<4> opcode> : Encoding16 {
1014 let Inst{15-10} = 0b010001;
1015 let Inst{9-6} = opcode;
1018 // A6.2.4 Load/store single data item encoding.
1019 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1020 let Inst{15-12} = opA;
1021 let Inst{11-9} = opB;
1023 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1025 class T1BranchCond<bits<4> opcode> : Encoding16 {
1026 let Inst{15-12} = opcode;
1029 // Helper classes to encode Thumb1 loads and stores. For immediates, the
1030 // following bits are used for "opA" (see A6.2.4):
1032 // 0b0110 => Immediate, 4 bytes
1033 // 0b1000 => Immediate, 2 bytes
1034 // 0b0111 => Immediate, 1 byte
1035 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1036 InstrItinClass itin, string opc, string asm,
1038 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1039 T1LoadStore<0b0101, opcode> {
1042 let Inst{8-6} = addr{5-3}; // Rm
1043 let Inst{5-3} = addr{2-0}; // Rn
1046 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1047 InstrItinClass itin, string opc, string asm,
1049 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1050 T1LoadStore<opA, {opB,?,?}> {
1053 let Inst{10-6} = addr{7-3}; // imm5
1054 let Inst{5-3} = addr{2-0}; // Rn
1058 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1059 class T1Misc<bits<7> opcode> : Encoding16 {
1060 let Inst{15-12} = 0b1011;
1061 let Inst{11-5} = opcode;
1064 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1065 class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
1066 InstrItinClass itin,
1067 string opc, string asm, string cstr, list<dag> pattern>
1068 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1069 let OutOperandList = oops;
1070 let InOperandList = !con(iops, (ins pred:$p));
1071 let AsmString = !strconcat(opc, "${p}", asm);
1072 let Pattern = pattern;
1073 list<Predicate> Predicates = [IsThumb2];
1076 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1077 // input operand since by default it's a zero register. It will become an
1078 // implicit def once it's "flipped".
1080 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1082 class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
1083 InstrItinClass itin,
1084 string opc, string asm, string cstr, list<dag> pattern>
1085 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1086 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1089 let OutOperandList = oops;
1090 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1091 let AsmString = !strconcat(opc, "${s}${p}", asm);
1092 let Pattern = pattern;
1093 list<Predicate> Predicates = [IsThumb2];
1097 class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
1098 InstrItinClass itin,
1099 string asm, string cstr, list<dag> pattern>
1100 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1101 let OutOperandList = oops;
1102 let InOperandList = iops;
1103 let AsmString = asm;
1104 let Pattern = pattern;
1105 list<Predicate> Predicates = [IsThumb2];
1108 class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
1109 InstrItinClass itin,
1110 string asm, string cstr, list<dag> pattern>
1111 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1112 let OutOperandList = oops;
1113 let InOperandList = iops;
1114 let AsmString = asm;
1115 let Pattern = pattern;
1116 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1119 class T2I<dag oops, dag iops, InstrItinClass itin,
1120 string opc, string asm, list<dag> pattern>
1121 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1122 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1123 string opc, string asm, list<dag> pattern>
1124 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
1125 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1126 string opc, string asm, list<dag> pattern>
1127 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
1128 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1129 string opc, string asm, list<dag> pattern>
1130 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
1131 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1132 string opc, string asm, list<dag> pattern>
1133 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
1134 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1135 string opc, string asm, list<dag> pattern>
1136 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, "",
1141 let Inst{31-25} = 0b1110100;
1143 let Inst{23} = addr{8};
1146 let Inst{20} = isLoad;
1147 let Inst{19-16} = addr{12-9};
1148 let Inst{15-12} = Rt{3-0};
1149 let Inst{11-8} = Rt2{3-0};
1150 let Inst{7-0} = addr{7-0};
1153 class T2sI<dag oops, dag iops, InstrItinClass itin,
1154 string opc, string asm, list<dag> pattern>
1155 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1157 class T2XI<dag oops, dag iops, InstrItinClass itin,
1158 string asm, list<dag> pattern>
1159 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1160 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1161 string asm, list<dag> pattern>
1162 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1164 // Move to/from coprocessor instructions
1165 class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern>
1166 : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> {
1167 let Inst{31-28} = opc;
1170 // Two-address instructions
1171 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1172 string asm, string cstr, list<dag> pattern>
1173 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
1175 // T2Iidxldst - Thumb2 indexed load / store instructions.
1176 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1178 AddrMode am, IndexMode im, InstrItinClass itin,
1179 string opc, string asm, string cstr, list<dag> pattern>
1180 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1181 let OutOperandList = oops;
1182 let InOperandList = !con(iops, (ins pred:$p));
1183 let AsmString = !strconcat(opc, "${p}", asm);
1184 let Pattern = pattern;
1185 list<Predicate> Predicates = [IsThumb2];
1186 let Inst{31-27} = 0b11111;
1187 let Inst{26-25} = 0b00;
1188 let Inst{24} = signed;
1190 let Inst{22-21} = opcod;
1191 let Inst{20} = load;
1193 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1194 let Inst{10} = pre; // The P bit.
1195 let Inst{8} = 1; // The W bit.
1198 let Inst{7-0} = addr{7-0};
1199 let Inst{9} = addr{8}; // Sign bit
1203 let Inst{15-12} = Rt{3-0};
1204 let Inst{19-16} = Rn{3-0};
1207 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1208 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1209 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1212 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1213 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1214 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1217 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1218 class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1219 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1222 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1223 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1224 list<Predicate> Predicates = [IsThumb2];
1227 //===----------------------------------------------------------------------===//
1229 //===----------------------------------------------------------------------===//
1230 // ARM VFP Instruction templates.
1233 // Almost all VFP instructions are predicable.
1234 class VFPI<dag oops, dag iops, AddrMode am, int sz,
1235 IndexMode im, Format f, InstrItinClass itin,
1236 string opc, string asm, string cstr, list<dag> pattern>
1237 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1239 let Inst{31-28} = p;
1240 let OutOperandList = oops;
1241 let InOperandList = !con(iops, (ins pred:$p));
1242 let AsmString = !strconcat(opc, "${p}", asm);
1243 let Pattern = pattern;
1244 let PostEncoderMethod = "VFPThumb2PostEncoder";
1245 list<Predicate> Predicates = [HasVFP2];
1249 class VFPXI<dag oops, dag iops, AddrMode am, int sz,
1250 IndexMode im, Format f, InstrItinClass itin,
1251 string asm, string cstr, list<dag> pattern>
1252 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1254 let Inst{31-28} = p;
1255 let OutOperandList = oops;
1256 let InOperandList = iops;
1257 let AsmString = asm;
1258 let Pattern = pattern;
1259 let PostEncoderMethod = "VFPThumb2PostEncoder";
1260 list<Predicate> Predicates = [HasVFP2];
1263 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1264 string opc, string asm, list<dag> pattern>
1265 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
1266 opc, asm, "", pattern> {
1267 let PostEncoderMethod = "VFPThumb2PostEncoder";
1270 // ARM VFP addrmode5 loads and stores
1271 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1272 InstrItinClass itin,
1273 string opc, string asm, list<dag> pattern>
1274 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1275 VFPLdStFrm, itin, opc, asm, "", pattern> {
1276 // Instruction operands.
1280 // Encode instruction operands.
1281 let Inst{23} = addr{8}; // U (add = (U == '1'))
1282 let Inst{22} = Dd{4};
1283 let Inst{19-16} = addr{12-9}; // Rn
1284 let Inst{15-12} = Dd{3-0};
1285 let Inst{7-0} = addr{7-0}; // imm8
1287 // TODO: Mark the instructions with the appropriate subtarget info.
1288 let Inst{27-24} = opcod1;
1289 let Inst{21-20} = opcod2;
1290 let Inst{11-9} = 0b101;
1291 let Inst{8} = 1; // Double precision
1293 // Loads & stores operate on both NEON and VFP pipelines.
1294 let D = VFPNeonDomain;
1297 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1298 InstrItinClass itin,
1299 string opc, string asm, list<dag> pattern>
1300 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1301 VFPLdStFrm, itin, opc, asm, "", pattern> {
1302 // Instruction operands.
1306 // Encode instruction operands.
1307 let Inst{23} = addr{8}; // U (add = (U == '1'))
1308 let Inst{22} = Sd{0};
1309 let Inst{19-16} = addr{12-9}; // Rn
1310 let Inst{15-12} = Sd{4-1};
1311 let Inst{7-0} = addr{7-0}; // imm8
1313 // TODO: Mark the instructions with the appropriate subtarget info.
1314 let Inst{27-24} = opcod1;
1315 let Inst{21-20} = opcod2;
1316 let Inst{11-9} = 0b101;
1317 let Inst{8} = 0; // Single precision
1319 // Loads & stores operate on both NEON and VFP pipelines.
1320 let D = VFPNeonDomain;
1323 // VFP Load / store multiple pseudo instructions.
1324 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1326 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1328 let OutOperandList = oops;
1329 let InOperandList = !con(iops, (ins pred:$p));
1330 let Pattern = pattern;
1331 list<Predicate> Predicates = [HasVFP2];
1334 // Load / store multiple
1335 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1336 string asm, string cstr, list<dag> pattern>
1337 : VFPXI<oops, iops, AddrMode4, 4, im,
1338 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1339 // Instruction operands.
1343 // Encode instruction operands.
1344 let Inst{19-16} = Rn;
1345 let Inst{22} = regs{12};
1346 let Inst{15-12} = regs{11-8};
1347 let Inst{7-0} = regs{7-0};
1349 // TODO: Mark the instructions with the appropriate subtarget info.
1350 let Inst{27-25} = 0b110;
1351 let Inst{11-9} = 0b101;
1352 let Inst{8} = 1; // Double precision
1355 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1356 string asm, string cstr, list<dag> pattern>
1357 : VFPXI<oops, iops, AddrMode4, 4, im,
1358 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1359 // Instruction operands.
1363 // Encode instruction operands.
1364 let Inst{19-16} = Rn;
1365 let Inst{22} = regs{8};
1366 let Inst{15-12} = regs{12-9};
1367 let Inst{7-0} = regs{7-0};
1369 // TODO: Mark the instructions with the appropriate subtarget info.
1370 let Inst{27-25} = 0b110;
1371 let Inst{11-9} = 0b101;
1372 let Inst{8} = 0; // Single precision
1375 // Double precision, unary
1376 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1377 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1378 string asm, list<dag> pattern>
1379 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1380 // Instruction operands.
1384 // Encode instruction operands.
1385 let Inst{3-0} = Dm{3-0};
1386 let Inst{5} = Dm{4};
1387 let Inst{15-12} = Dd{3-0};
1388 let Inst{22} = Dd{4};
1390 let Inst{27-23} = opcod1;
1391 let Inst{21-20} = opcod2;
1392 let Inst{19-16} = opcod3;
1393 let Inst{11-9} = 0b101;
1394 let Inst{8} = 1; // Double precision
1395 let Inst{7-6} = opcod4;
1396 let Inst{4} = opcod5;
1399 // Double precision, binary
1400 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1401 dag iops, InstrItinClass itin, string opc, string asm,
1403 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1404 // Instruction operands.
1409 // Encode instruction operands.
1410 let Inst{3-0} = Dm{3-0};
1411 let Inst{5} = Dm{4};
1412 let Inst{19-16} = Dn{3-0};
1413 let Inst{7} = Dn{4};
1414 let Inst{15-12} = Dd{3-0};
1415 let Inst{22} = Dd{4};
1417 let Inst{27-23} = opcod1;
1418 let Inst{21-20} = opcod2;
1419 let Inst{11-9} = 0b101;
1420 let Inst{8} = 1; // Double precision
1425 // Single precision, unary
1426 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1427 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1428 string asm, list<dag> pattern>
1429 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1430 // Instruction operands.
1434 // Encode instruction operands.
1435 let Inst{3-0} = Sm{4-1};
1436 let Inst{5} = Sm{0};
1437 let Inst{15-12} = Sd{4-1};
1438 let Inst{22} = Sd{0};
1440 let Inst{27-23} = opcod1;
1441 let Inst{21-20} = opcod2;
1442 let Inst{19-16} = opcod3;
1443 let Inst{11-9} = 0b101;
1444 let Inst{8} = 0; // Single precision
1445 let Inst{7-6} = opcod4;
1446 let Inst{4} = opcod5;
1449 // Single precision unary, if no NEON. Same as ASuI except not available if
1451 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1452 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1453 string asm, list<dag> pattern>
1454 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1456 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1459 // Single precision, binary
1460 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1461 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1462 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1463 // Instruction operands.
1468 // Encode instruction operands.
1469 let Inst{3-0} = Sm{4-1};
1470 let Inst{5} = Sm{0};
1471 let Inst{19-16} = Sn{4-1};
1472 let Inst{7} = Sn{0};
1473 let Inst{15-12} = Sd{4-1};
1474 let Inst{22} = Sd{0};
1476 let Inst{27-23} = opcod1;
1477 let Inst{21-20} = opcod2;
1478 let Inst{11-9} = 0b101;
1479 let Inst{8} = 0; // Single precision
1484 // Single precision binary, if no NEON. Same as ASbI except not available if
1486 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1487 dag iops, InstrItinClass itin, string opc, string asm,
1489 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1490 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1492 // Instruction operands.
1497 // Encode instruction operands.
1498 let Inst{3-0} = Sm{4-1};
1499 let Inst{5} = Sm{0};
1500 let Inst{19-16} = Sn{4-1};
1501 let Inst{7} = Sn{0};
1502 let Inst{15-12} = Sd{4-1};
1503 let Inst{22} = Sd{0};
1506 // VFP conversion instructions
1507 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1508 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1510 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1511 let Inst{27-23} = opcod1;
1512 let Inst{21-20} = opcod2;
1513 let Inst{19-16} = opcod3;
1514 let Inst{11-8} = opcod4;
1519 // VFP conversion between floating-point and fixed-point
1520 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1521 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1523 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1524 // size (fixed-point number): sx == 0 ? 16 : 32
1525 let Inst{7} = op5; // sx
1528 // VFP conversion instructions, if no NEON
1529 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1530 dag oops, dag iops, InstrItinClass itin,
1531 string opc, string asm, list<dag> pattern>
1532 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1534 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1537 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1538 InstrItinClass itin,
1539 string opc, string asm, list<dag> pattern>
1540 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1541 let Inst{27-20} = opcod1;
1542 let Inst{11-8} = opcod2;
1546 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1547 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1548 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1550 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1551 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1552 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1554 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1555 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1556 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1558 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1559 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1560 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1562 //===----------------------------------------------------------------------===//
1564 //===----------------------------------------------------------------------===//
1565 // ARM NEON Instruction templates.
1568 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1569 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1571 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1572 let OutOperandList = oops;
1573 let InOperandList = !con(iops, (ins pred:$p));
1574 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1575 let Pattern = pattern;
1576 list<Predicate> Predicates = [HasNEON];
1579 // Same as NeonI except it does not have a "data type" specifier.
1580 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1581 InstrItinClass itin, string opc, string asm, string cstr,
1583 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1584 let OutOperandList = oops;
1585 let InOperandList = !con(iops, (ins pred:$p));
1586 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1587 let Pattern = pattern;
1588 list<Predicate> Predicates = [HasNEON];
1591 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1592 dag oops, dag iops, InstrItinClass itin,
1593 string opc, string dt, string asm, string cstr, list<dag> pattern>
1594 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1596 let Inst{31-24} = 0b11110100;
1597 let Inst{23} = op23;
1598 let Inst{21-20} = op21_20;
1599 let Inst{11-8} = op11_8;
1600 let Inst{7-4} = op7_4;
1602 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1608 let Inst{22} = Vd{4};
1609 let Inst{15-12} = Vd{3-0};
1610 let Inst{19-16} = Rn{3-0};
1611 let Inst{3-0} = Rm{3-0};
1614 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1615 dag oops, dag iops, InstrItinClass itin,
1616 string opc, string dt, string asm, string cstr, list<dag> pattern>
1617 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1618 dt, asm, cstr, pattern> {
1622 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1623 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1625 let OutOperandList = oops;
1626 let InOperandList = !con(iops, (ins pred:$p));
1627 list<Predicate> Predicates = [HasNEON];
1630 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1632 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1634 let OutOperandList = oops;
1635 let InOperandList = !con(iops, (ins pred:$p));
1636 let Pattern = pattern;
1637 list<Predicate> Predicates = [HasNEON];
1640 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1641 string opc, string dt, string asm, string cstr, list<dag> pattern>
1642 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1644 let Inst{31-25} = 0b1111001;
1645 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1648 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1649 string opc, string asm, string cstr, list<dag> pattern>
1650 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1652 let Inst{31-25} = 0b1111001;
1653 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1656 // NEON "one register and a modified immediate" format.
1657 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1659 dag oops, dag iops, InstrItinClass itin,
1660 string opc, string dt, string asm, string cstr,
1662 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1663 let Inst{23} = op23;
1664 let Inst{21-19} = op21_19;
1665 let Inst{11-8} = op11_8;
1671 // Instruction operands.
1675 let Inst{15-12} = Vd{3-0};
1676 let Inst{22} = Vd{4};
1677 let Inst{24} = SIMM{7};
1678 let Inst{18-16} = SIMM{6-4};
1679 let Inst{3-0} = SIMM{3-0};
1682 // NEON 2 vector register format.
1683 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1684 bits<5> op11_7, bit op6, bit op4,
1685 dag oops, dag iops, InstrItinClass itin,
1686 string opc, string dt, string asm, string cstr, list<dag> pattern>
1687 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1688 let Inst{24-23} = op24_23;
1689 let Inst{21-20} = op21_20;
1690 let Inst{19-18} = op19_18;
1691 let Inst{17-16} = op17_16;
1692 let Inst{11-7} = op11_7;
1696 // Instruction operands.
1700 let Inst{15-12} = Vd{3-0};
1701 let Inst{22} = Vd{4};
1702 let Inst{3-0} = Vm{3-0};
1703 let Inst{5} = Vm{4};
1706 // Same as N2V except it doesn't have a datatype suffix.
1707 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1708 bits<5> op11_7, bit op6, bit op4,
1709 dag oops, dag iops, InstrItinClass itin,
1710 string opc, string asm, string cstr, list<dag> pattern>
1711 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1712 let Inst{24-23} = op24_23;
1713 let Inst{21-20} = op21_20;
1714 let Inst{19-18} = op19_18;
1715 let Inst{17-16} = op17_16;
1716 let Inst{11-7} = op11_7;
1720 // Instruction operands.
1724 let Inst{15-12} = Vd{3-0};
1725 let Inst{22} = Vd{4};
1726 let Inst{3-0} = Vm{3-0};
1727 let Inst{5} = Vm{4};
1730 // NEON 2 vector register with immediate.
1731 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1732 dag oops, dag iops, Format f, InstrItinClass itin,
1733 string opc, string dt, string asm, string cstr, list<dag> pattern>
1734 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1735 let Inst{24} = op24;
1736 let Inst{23} = op23;
1737 let Inst{11-8} = op11_8;
1742 // Instruction operands.
1747 let Inst{15-12} = Vd{3-0};
1748 let Inst{22} = Vd{4};
1749 let Inst{3-0} = Vm{3-0};
1750 let Inst{5} = Vm{4};
1751 let Inst{21-16} = SIMM{5-0};
1754 // NEON 3 vector register format.
1756 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1757 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1758 string opc, string dt, string asm, string cstr,
1760 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1761 let Inst{24} = op24;
1762 let Inst{23} = op23;
1763 let Inst{21-20} = op21_20;
1764 let Inst{11-8} = op11_8;
1769 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1770 dag oops, dag iops, Format f, InstrItinClass itin,
1771 string opc, string dt, string asm, string cstr, list<dag> pattern>
1772 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1773 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1775 // Instruction operands.
1780 let Inst{15-12} = Vd{3-0};
1781 let Inst{22} = Vd{4};
1782 let Inst{19-16} = Vn{3-0};
1783 let Inst{7} = Vn{4};
1784 let Inst{3-0} = Vm{3-0};
1785 let Inst{5} = Vm{4};
1788 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1789 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1790 string opc, string dt, string asm, string cstr,
1792 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1793 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1795 // Instruction operands.
1801 let Inst{15-12} = Vd{3-0};
1802 let Inst{22} = Vd{4};
1803 let Inst{19-16} = Vn{3-0};
1804 let Inst{7} = Vn{4};
1805 let Inst{3-0} = Vm{3-0};
1809 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1810 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1811 string opc, string dt, string asm, string cstr,
1813 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1814 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1816 // Instruction operands.
1822 let Inst{15-12} = Vd{3-0};
1823 let Inst{22} = Vd{4};
1824 let Inst{19-16} = Vn{3-0};
1825 let Inst{7} = Vn{4};
1826 let Inst{2-0} = Vm{2-0};
1827 let Inst{5} = lane{1};
1828 let Inst{3} = lane{0};
1831 // Same as N3V except it doesn't have a data type suffix.
1832 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1834 dag oops, dag iops, Format f, InstrItinClass itin,
1835 string opc, string asm, string cstr, list<dag> pattern>
1836 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1837 let Inst{24} = op24;
1838 let Inst{23} = op23;
1839 let Inst{21-20} = op21_20;
1840 let Inst{11-8} = op11_8;
1844 // Instruction operands.
1849 let Inst{15-12} = Vd{3-0};
1850 let Inst{22} = Vd{4};
1851 let Inst{19-16} = Vn{3-0};
1852 let Inst{7} = Vn{4};
1853 let Inst{3-0} = Vm{3-0};
1854 let Inst{5} = Vm{4};
1857 // NEON VMOVs between scalar and core registers.
1858 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1859 dag oops, dag iops, Format f, InstrItinClass itin,
1860 string opc, string dt, string asm, list<dag> pattern>
1861 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
1863 let Inst{27-20} = opcod1;
1864 let Inst{11-8} = opcod2;
1865 let Inst{6-5} = opcod3;
1867 // A8.6.303, A8.6.328, A8.6.329
1868 let Inst{3-0} = 0b0000;
1870 let OutOperandList = oops;
1871 let InOperandList = !con(iops, (ins pred:$p));
1872 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1873 let Pattern = pattern;
1874 list<Predicate> Predicates = [HasNEON];
1876 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1883 let Inst{31-28} = p{3-0};
1885 let Inst{19-16} = V{3-0};
1886 let Inst{15-12} = R{3-0};
1888 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1889 dag oops, dag iops, InstrItinClass itin,
1890 string opc, string dt, string asm, list<dag> pattern>
1891 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1892 opc, dt, asm, pattern>;
1893 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1894 dag oops, dag iops, InstrItinClass itin,
1895 string opc, string dt, string asm, list<dag> pattern>
1896 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1897 opc, dt, asm, pattern>;
1898 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1899 dag oops, dag iops, InstrItinClass itin,
1900 string opc, string dt, string asm, list<dag> pattern>
1901 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1902 opc, dt, asm, pattern>;
1904 // Vector Duplicate Lane (from scalar to all elements)
1905 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1906 InstrItinClass itin, string opc, string dt, string asm,
1908 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1909 let Inst{24-23} = 0b11;
1910 let Inst{21-20} = 0b11;
1911 let Inst{19-16} = op19_16;
1912 let Inst{11-7} = 0b11000;
1920 let Inst{22} = Vd{4};
1921 let Inst{15-12} = Vd{3-0};
1922 let Inst{5} = Vm{4};
1923 let Inst{3-0} = Vm{3-0};
1926 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1927 // for single-precision FP.
1928 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1929 list<Predicate> Predicates = [HasNEON,UseNEONForFP];