1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // the instruction has a Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 class AddrMode<bits<5> val> {
91 def AddrModeNone : AddrMode<0>;
92 def AddrMode1 : AddrMode<1>;
93 def AddrMode2 : AddrMode<2>;
94 def AddrMode3 : AddrMode<3>;
95 def AddrMode4 : AddrMode<4>;
96 def AddrMode5 : AddrMode<5>;
97 def AddrMode6 : AddrMode<6>;
98 def AddrModeT1_1 : AddrMode<7>;
99 def AddrModeT1_2 : AddrMode<8>;
100 def AddrModeT1_4 : AddrMode<9>;
101 def AddrModeT1_s : AddrMode<10>;
102 def AddrModeT2_i12 : AddrMode<11>;
103 def AddrModeT2_i8 : AddrMode<12>;
104 def AddrModeT2_so : AddrMode<13>;
105 def AddrModeT2_pc : AddrMode<14>;
106 def AddrModeT2_i8s4 : AddrMode<15>;
107 def AddrMode_i12 : AddrMode<16>;
110 class SizeFlagVal<bits<3> val> {
113 def SizeInvalid : SizeFlagVal<0>; // Unset.
114 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
115 def Size8Bytes : SizeFlagVal<2>;
116 def Size4Bytes : SizeFlagVal<3>;
117 def Size2Bytes : SizeFlagVal<4>;
119 // Load / store index mode.
120 class IndexMode<bits<2> val> {
123 def IndexModeNone : IndexMode<0>;
124 def IndexModePre : IndexMode<1>;
125 def IndexModePost : IndexMode<2>;
126 def IndexModeUpd : IndexMode<3>;
128 // Instruction execution domain.
129 class Domain<bits<2> val> {
132 def GenericDomain : Domain<0>;
133 def VFPDomain : Domain<1>; // Instructions in VFP domain only
134 def NeonDomain : Domain<2>; // Instructions in Neon domain only
135 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
137 //===----------------------------------------------------------------------===//
139 // ARM special operands.
142 def CondCodeOperand : AsmOperandClass {
143 let Name = "CondCode";
144 let SuperClasses = [];
147 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
148 // register whose default is 0 (no register).
149 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
150 (ops (i32 14), (i32 zero_reg))> {
151 let PrintMethod = "printPredicateOperand";
152 let ParserMatchClass = CondCodeOperand;
155 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
156 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
157 let EncoderMethod = "getCCOutOpValue";
158 let PrintMethod = "printSBitModifierOperand";
161 // Same as cc_out except it defaults to setting CPSR.
162 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
163 let EncoderMethod = "getCCOutOpValue";
164 let PrintMethod = "printSBitModifierOperand";
167 // ARM special operands for disassembly only.
169 def setend_op : Operand<i32> {
170 let PrintMethod = "printSetendOperand";
173 def cps_opt : Operand<i32> {
174 let PrintMethod = "printCPSOptionOperand";
177 def msr_mask : Operand<i32> {
178 let PrintMethod = "printMSRMaskOperand";
181 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
182 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
183 def neg_zero : Operand<i32> {
184 let PrintMethod = "printNegZeroOperand";
187 //===----------------------------------------------------------------------===//
189 // ARM Instruction templates.
192 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
193 Format f, Domain d, string cstr, InstrItinClass itin>
195 let Namespace = "ARM";
200 bits<2> IndexModeBits = IM.Value;
202 bits<6> Form = F.Value;
204 bit isUnaryDataProc = 0;
205 bit canXformTo16Bit = 0;
207 // If this is a pseudo instruction, mark it isCodeGenOnly.
208 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
210 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
211 let TSFlags{4-0} = AM.Value;
212 let TSFlags{7-5} = SZ.Value;
213 let TSFlags{9-8} = IndexModeBits;
214 let TSFlags{15-10} = Form;
215 let TSFlags{16} = isUnaryDataProc;
216 let TSFlags{17} = canXformTo16Bit;
217 let TSFlags{19-18} = D.Value;
219 let Constraints = cstr;
220 let Itinerary = itin;
227 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
228 Format f, Domain d, string cstr, InstrItinClass itin>
229 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
231 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
232 // on by adding flavors to specific instructions.
233 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
234 Format f, Domain d, string cstr, InstrItinClass itin>
235 : InstTemplate<am, sz, im, f, d, cstr, itin>;
237 class PseudoInst<dag oops, dag iops, InstrItinClass itin,
238 string asm, list<dag> pattern>
239 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
241 let OutOperandList = oops;
242 let InOperandList = iops;
244 let Pattern = pattern;
247 // Almost all ARM instructions are predicable.
248 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
249 IndexMode im, Format f, InstrItinClass itin,
250 string opc, string asm, string cstr,
252 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
255 let OutOperandList = oops;
256 let InOperandList = !con(iops, (ins pred:$p));
257 let AsmString = !strconcat(opc, "${p}", asm);
258 let Pattern = pattern;
259 list<Predicate> Predicates = [IsARM];
262 // A few are not predicable
263 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
264 IndexMode im, Format f, InstrItinClass itin,
265 string opc, string asm, string cstr,
267 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
268 let OutOperandList = oops;
269 let InOperandList = iops;
270 let AsmString = !strconcat(opc, asm);
271 let Pattern = pattern;
272 let isPredicable = 0;
273 list<Predicate> Predicates = [IsARM];
276 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
277 // operand since by default it's a zero register. It will become an implicit def
278 // once it's "flipped".
279 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
280 IndexMode im, Format f, InstrItinClass itin,
281 string opc, string asm, string cstr,
283 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
284 bits<4> p; // Predicate operand
285 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
289 let OutOperandList = oops;
290 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
291 let AsmString = !strconcat(opc, "${s}${p}", asm);
292 let Pattern = pattern;
293 list<Predicate> Predicates = [IsARM];
297 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
298 IndexMode im, Format f, InstrItinClass itin,
299 string asm, string cstr, list<dag> pattern>
300 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
301 let OutOperandList = oops;
302 let InOperandList = iops;
304 let Pattern = pattern;
305 list<Predicate> Predicates = [IsARM];
308 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
309 string opc, string asm, list<dag> pattern>
310 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
311 opc, asm, "", pattern>;
312 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
313 string opc, string asm, list<dag> pattern>
314 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
315 opc, asm, "", pattern>;
316 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
317 string asm, list<dag> pattern>
318 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
320 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
321 string opc, string asm, list<dag> pattern>
322 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
323 opc, asm, "", pattern>;
325 // Ctrl flow instructions
326 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
327 string opc, string asm, list<dag> pattern>
328 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
329 opc, asm, "", pattern> {
330 let Inst{27-24} = opcod;
332 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
333 string asm, list<dag> pattern>
334 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
336 let Inst{27-24} = opcod;
338 class ABXIx2<dag oops, dag iops, InstrItinClass itin,
339 string asm, list<dag> pattern>
340 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, Pseudo, itin,
343 // BR_JT instructions
344 class JTI<dag oops, dag iops, InstrItinClass itin,
345 string asm, list<dag> pattern>
346 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
349 // Atomic load/store instructions
350 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
351 string opc, string asm, list<dag> pattern>
352 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
353 opc, asm, "", pattern> {
356 let Inst{27-23} = 0b00011;
357 let Inst{22-21} = opcod;
359 let Inst{19-16} = Rn;
360 let Inst{15-12} = Rt;
361 let Inst{11-0} = 0b111110011111;
363 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
364 string opc, string asm, list<dag> pattern>
365 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
366 opc, asm, "", pattern> {
370 let Inst{27-23} = 0b00011;
371 let Inst{22-21} = opcod;
373 let Inst{19-16} = Rn;
374 let Inst{15-12} = Rd;
375 let Inst{11-4} = 0b11111001;
378 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
379 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
383 let Inst{27-23} = 0b00010;
385 let Inst{21-20} = 0b00;
386 let Inst{19-16} = Rn;
387 let Inst{15-12} = Rt;
388 let Inst{11-4} = 0b00001001;
392 // addrmode1 instructions
393 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
394 string opc, string asm, list<dag> pattern>
395 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
396 opc, asm, "", pattern> {
397 let Inst{24-21} = opcod;
398 let Inst{27-26} = 0b00;
400 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
401 string opc, string asm, list<dag> pattern>
402 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
403 opc, asm, "", pattern> {
404 let Inst{24-21} = opcod;
405 let Inst{27-26} = 0b00;
407 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
408 string asm, list<dag> pattern>
409 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
411 let Inst{24-21} = opcod;
412 let Inst{27-26} = 0b00;
414 class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
415 string opc, string asm, list<dag> pattern>
416 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
417 opc, asm, "", pattern>;
423 class AIldst1<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
424 Format f, InstrItinClass itin, string opc, string asm,
426 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
428 let Inst{27-25} = op;
429 let Inst{24} = 1; // 24 == P
431 let Inst{22} = isByte;
432 let Inst{21} = 0; // 21 == W
435 // Indexed load/stores
436 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
437 IndexMode im, Format f, InstrItinClass itin, string opc,
438 string asm, string cstr, list<dag> pattern>
439 : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin,
440 opc, asm, cstr, pattern> {
442 let Inst{27-26} = 0b01;
443 let Inst{24} = isPre; // P bit
444 let Inst{22} = isByte; // B bit
445 let Inst{21} = isPre; // W bit
446 let Inst{20} = isLd; // L bit
447 let Inst{15-12} = Rt;
450 class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
451 string asm, list<dag> pattern>
452 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
454 let Inst{20} = 1; // L bit
455 let Inst{21} = 0; // W bit
456 let Inst{22} = 0; // B bit
457 let Inst{24} = 1; // P bit
458 let Inst{27-26} = 0b01;
460 class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
461 string asm, list<dag> pattern>
462 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
464 let Inst{20} = 1; // L bit
465 let Inst{21} = 0; // W bit
466 let Inst{22} = 1; // B bit
467 let Inst{24} = 1; // P bit
468 let Inst{27-26} = 0b01;
472 class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
473 string asm, list<dag> pattern>
474 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
476 let Inst{20} = 0; // L bit
477 let Inst{21} = 0; // W bit
478 let Inst{22} = 0; // B bit
479 let Inst{24} = 1; // P bit
480 let Inst{27-26} = 0b01;
482 class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
483 string asm, list<dag> pattern>
484 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
486 let Inst{20} = 0; // L bit
487 let Inst{21} = 0; // W bit
488 let Inst{22} = 1; // B bit
489 let Inst{24} = 1; // P bit
490 let Inst{27-26} = 0b01;
493 // addrmode3 instructions
494 class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
495 string opc, string asm, list<dag> pattern>
496 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
497 opc, asm, "", pattern>;
498 class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
499 string asm, list<dag> pattern>
500 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
504 class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
505 string opc, string asm, list<dag> pattern>
506 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
507 opc, asm, "", pattern> {
509 let Inst{5} = 1; // H bit
510 let Inst{6} = 0; // S bit
512 let Inst{20} = 1; // L bit
513 let Inst{21} = 0; // W bit
514 let Inst{24} = 1; // P bit
515 let Inst{27-25} = 0b000;
517 class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
518 string asm, list<dag> pattern>
519 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
522 let Inst{5} = 1; // H bit
523 let Inst{6} = 0; // S bit
525 let Inst{20} = 1; // L bit
526 let Inst{21} = 0; // W bit
527 let Inst{24} = 1; // P bit
529 class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
530 string opc, string asm, list<dag> pattern>
531 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
532 opc, asm, "", pattern> {
535 let Inst{27-25} = 0b000;
536 let Inst{24} = 1; // P bit
537 let Inst{23} = addr{8}; // U bit
538 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
539 let Inst{21} = 0; // W bit
540 let Inst{20} = 1; // L bit
541 let Inst{19-16} = addr{12-9}; // Rn
542 let Inst{15-12} = Rt; // Rt
543 let Inst{11-8} = addr{7-4}; // imm7_4/zero
544 let Inst{7-4} = 0b1111;
545 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
547 class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
548 string asm, list<dag> pattern>
549 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
552 let Inst{5} = 1; // H bit
553 let Inst{6} = 1; // S bit
555 let Inst{20} = 1; // L bit
556 let Inst{21} = 0; // W bit
557 let Inst{24} = 1; // P bit
559 class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
560 string opc, string asm, list<dag> pattern>
561 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
562 opc, asm, "", pattern> {
565 let Inst{27-25} = 0b000;
566 let Inst{24} = 1; // P bit
567 let Inst{23} = addr{8}; // U bit
568 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
569 let Inst{21} = 0; // W bit
570 let Inst{20} = 1; // L bit
571 let Inst{19-16} = addr{12-9}; // Rn
572 let Inst{15-12} = Rt; // Rt
573 let Inst{11-8} = addr{7-4}; // imm7_4/zero
574 let Inst{7-4} = 0b1101;
575 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
577 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
578 string asm, list<dag> pattern>
579 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
582 let Inst{5} = 0; // H bit
583 let Inst{6} = 1; // S bit
585 let Inst{20} = 1; // L bit
586 let Inst{21} = 0; // W bit
587 let Inst{24} = 1; // P bit
589 class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
590 string opc, string asm, list<dag> pattern>
591 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
592 opc, asm, "", pattern> {
594 let Inst{5} = 0; // H bit
595 let Inst{6} = 1; // S bit
597 let Inst{20} = 0; // L bit
598 let Inst{21} = 0; // W bit
599 let Inst{24} = 1; // P bit
600 let Inst{27-25} = 0b000;
604 class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
605 string opc, string asm, list<dag> pattern>
606 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
607 opc, asm, "", pattern> {
610 let Inst{27-25} = 0b000;
611 let Inst{24} = 1; // P bit
612 let Inst{23} = addr{8}; // U bit
613 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
614 let Inst{21} = 0; // W bit
615 let Inst{20} = 0; // L bit
616 let Inst{19-16} = addr{12-9}; // Rn
617 let Inst{15-12} = Rt; // Rt
618 let Inst{11-8} = addr{7-4}; // imm7_4/zero
619 let Inst{7-4} = 0b1011;
620 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
622 class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
623 string asm, list<dag> pattern>
624 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
627 let Inst{5} = 1; // H bit
628 let Inst{6} = 0; // S bit
630 let Inst{20} = 0; // L bit
631 let Inst{21} = 0; // W bit
632 let Inst{24} = 1; // P bit
634 class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
635 string opc, string asm, list<dag> pattern>
636 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
637 opc, asm, "", pattern> {
639 let Inst{5} = 1; // H bit
640 let Inst{6} = 1; // S bit
642 let Inst{20} = 0; // L bit
643 let Inst{21} = 0; // W bit
644 let Inst{24} = 1; // P bit
645 let Inst{27-25} = 0b000;
649 class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
650 string opc, string asm, string cstr, list<dag> pattern>
651 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
652 opc, asm, cstr, pattern> {
654 let Inst{5} = 1; // H bit
655 let Inst{6} = 0; // S bit
657 let Inst{20} = 1; // L bit
658 let Inst{21} = 1; // W bit
659 let Inst{24} = 1; // P bit
660 let Inst{27-25} = 0b000;
662 class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
663 string opc, string asm, string cstr, list<dag> pattern>
664 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
665 opc, asm, cstr, pattern> {
668 let Inst{27-25} = 0b000;
669 let Inst{24} = 1; // P bit
670 let Inst{23} = addr{8}; // U bit
671 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
672 let Inst{21} = 1; // W bit
673 let Inst{20} = 1; // L bit
674 let Inst{19-16} = addr{12-9}; // Rn
675 let Inst{15-12} = Rt; // Rt
676 let Inst{11-8} = addr{7-4}; // imm7_4/zero
677 let Inst{7-4} = 0b1111;
678 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
680 class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
681 string opc, string asm, string cstr, list<dag> pattern>
682 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
683 opc, asm, cstr, pattern> {
685 let Inst{5} = 0; // H bit
686 let Inst{6} = 1; // S bit
688 let Inst{20} = 1; // L bit
689 let Inst{21} = 1; // W bit
690 let Inst{24} = 1; // P bit
691 let Inst{27-25} = 0b000;
693 class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin,
694 string opc, string asm, string cstr, list<dag> pattern>
695 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
696 opc, asm, cstr, pattern> {
698 let Inst{5} = 0; // H bit
699 let Inst{6} = 1; // S bit
701 let Inst{20} = 0; // L bit
702 let Inst{21} = 1; // W bit
703 let Inst{24} = 1; // P bit
704 let Inst{27-25} = 0b000;
708 // Pre-indexed stores
709 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
710 string opc, string asm, string cstr, list<dag> pattern>
711 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
712 opc, asm, cstr, pattern> {
714 let Inst{5} = 1; // H bit
715 let Inst{6} = 0; // S bit
717 let Inst{20} = 0; // L bit
718 let Inst{21} = 1; // W bit
719 let Inst{24} = 1; // P bit
720 let Inst{27-25} = 0b000;
722 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
723 string opc, string asm, string cstr, list<dag> pattern>
724 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
725 opc, asm, cstr, pattern> {
727 let Inst{5} = 1; // H bit
728 let Inst{6} = 1; // S bit
730 let Inst{20} = 0; // L bit
731 let Inst{21} = 1; // W bit
732 let Inst{24} = 1; // P bit
733 let Inst{27-25} = 0b000;
736 // Post-indexed loads
737 class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
738 string opc, string asm, string cstr, list<dag> pattern>
739 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
740 opc, asm, cstr,pattern> {
742 let Inst{5} = 1; // H bit
743 let Inst{6} = 0; // S bit
745 let Inst{20} = 1; // L bit
746 let Inst{21} = 0; // W bit
747 let Inst{24} = 0; // P bit
748 let Inst{27-25} = 0b000;
750 class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
751 string opc, string asm, string cstr, list<dag> pattern>
752 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
753 opc, asm, cstr,pattern> {
757 let Inst{27-25} = 0b000;
758 let Inst{24} = 0; // P bit
759 let Inst{23} = offset{8}; // U bit
760 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
761 let Inst{21} = 0; // W bit
762 let Inst{20} = 1; // L bit
763 let Inst{19-16} = Rn; // Rn
764 let Inst{15-12} = Rt; // Rt
765 let Inst{11-8} = offset{7-4}; // imm7_4/zero
766 let Inst{7-4} = 0b1111;
767 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
769 class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
770 string opc, string asm, string cstr, list<dag> pattern>
771 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
772 opc, asm, cstr,pattern> {
774 let Inst{5} = 0; // H bit
775 let Inst{6} = 1; // S bit
777 let Inst{20} = 1; // L bit
778 let Inst{21} = 0; // W bit
779 let Inst{24} = 0; // P bit
780 let Inst{27-25} = 0b000;
782 class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin,
783 string opc, string asm, string cstr, list<dag> pattern>
784 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
785 opc, asm, cstr, pattern> {
787 let Inst{5} = 0; // H bit
788 let Inst{6} = 1; // S bit
790 let Inst{20} = 0; // L bit
791 let Inst{21} = 0; // W bit
792 let Inst{24} = 0; // P bit
793 let Inst{27-25} = 0b000;
796 // Post-indexed stores
797 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
798 string opc, string asm, string cstr, list<dag> pattern>
799 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
800 opc, asm, cstr,pattern> {
802 let Inst{5} = 1; // H bit
803 let Inst{6} = 0; // S bit
805 let Inst{20} = 0; // L bit
806 let Inst{21} = 0; // W bit
807 let Inst{24} = 0; // P bit
808 let Inst{27-25} = 0b000;
810 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
811 string opc, string asm, string cstr, list<dag> pattern>
812 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
813 opc, asm, cstr, pattern> {
815 let Inst{5} = 1; // H bit
816 let Inst{6} = 1; // S bit
818 let Inst{20} = 0; // L bit
819 let Inst{21} = 0; // W bit
820 let Inst{24} = 0; // P bit
821 let Inst{27-25} = 0b000;
824 // addrmode4 instructions
825 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
826 string asm, string cstr, list<dag> pattern>
827 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> {
832 let Inst{27-25} = 0b100;
833 let Inst{22} = 0; // S bit
834 let Inst{19-16} = Rn;
835 let Inst{15-0} = regs;
838 // Unsigned multiply, multiply-accumulate instructions.
839 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
840 string opc, string asm, list<dag> pattern>
841 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
842 opc, asm, "", pattern> {
843 let Inst{7-4} = 0b1001;
844 let Inst{20} = 0; // S bit
845 let Inst{27-21} = opcod;
847 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
848 string opc, string asm, list<dag> pattern>
849 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
850 opc, asm, "", pattern> {
851 let Inst{7-4} = 0b1001;
852 let Inst{27-21} = opcod;
855 // Most significant word multiply
856 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
857 InstrItinClass itin, string opc, string asm, list<dag> pattern>
858 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
859 opc, asm, "", pattern> {
863 let Inst{7-4} = opc7_4;
865 let Inst{27-21} = opcod;
866 let Inst{19-16} = Rd;
870 // MSW multiple w/ Ra operand
871 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
872 InstrItinClass itin, string opc, string asm, list<dag> pattern>
873 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
875 let Inst{15-12} = Ra;
878 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
879 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
880 InstrItinClass itin, string opc, string asm, list<dag> pattern>
881 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
882 opc, asm, "", pattern> {
888 let Inst{27-21} = opcod;
889 let Inst{6-5} = bit6_5;
893 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
894 InstrItinClass itin, string opc, string asm, list<dag> pattern>
895 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
897 let Inst{19-16} = Rd;
900 // AMulxyI with Ra operand
901 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
902 InstrItinClass itin, string opc, string asm, list<dag> pattern>
903 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
905 let Inst{15-12} = Ra;
908 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
909 InstrItinClass itin, string opc, string asm, list<dag> pattern>
910 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
913 let Inst{19-16} = RdHi;
914 let Inst{15-12} = RdLo;
917 // Extend instructions.
918 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
919 string opc, string asm, list<dag> pattern>
920 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
921 opc, asm, "", pattern> {
922 // All AExtI instructions have Rd and Rm register operands.
925 let Inst{15-12} = Rd;
927 let Inst{7-4} = 0b0111;
928 let Inst{9-8} = 0b00;
929 let Inst{27-20} = opcod;
932 // Misc Arithmetic instructions.
933 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
934 InstrItinClass itin, string opc, string asm, list<dag> pattern>
935 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
936 opc, asm, "", pattern> {
939 let Inst{27-20} = opcod;
940 let Inst{19-16} = 0b1111;
941 let Inst{15-12} = Rd;
942 let Inst{11-8} = 0b1111;
943 let Inst{7-4} = opc7_4;
948 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
949 string opc, string asm, list<dag> pattern>
950 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
951 opc, asm, "", pattern> {
956 let Inst{27-20} = opcod;
957 let Inst{19-16} = Rn;
958 let Inst{15-12} = Rd;
959 let Inst{11-7} = sh{7-3};
961 let Inst{5-4} = 0b01;
965 //===----------------------------------------------------------------------===//
967 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
968 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
969 list<Predicate> Predicates = [IsARM];
971 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
972 list<Predicate> Predicates = [IsARM, HasV5TE];
974 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
975 list<Predicate> Predicates = [IsARM, HasV6];
978 //===----------------------------------------------------------------------===//
980 // Thumb Instruction Format Definitions.
983 // TI - Thumb instruction.
985 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
986 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
987 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
988 let OutOperandList = oops;
989 let InOperandList = iops;
991 let Pattern = pattern;
992 list<Predicate> Predicates = [IsThumb];
995 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
996 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
998 // Two-address instructions
999 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
1001 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
1004 // tBL, tBX 32-bit instructions
1005 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
1006 dag oops, dag iops, InstrItinClass itin, string asm,
1008 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
1010 let Inst{31-27} = opcod1;
1011 let Inst{15-14} = opcod2;
1012 let Inst{12} = opcod3;
1015 // BR_JT instructions
1016 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
1018 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1021 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1022 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1023 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1024 let OutOperandList = oops;
1025 let InOperandList = iops;
1026 let AsmString = asm;
1027 let Pattern = pattern;
1028 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1031 class T1I<dag oops, dag iops, InstrItinClass itin,
1032 string asm, list<dag> pattern>
1033 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
1034 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
1035 string asm, list<dag> pattern>
1036 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1037 class T1JTI<dag oops, dag iops, InstrItinClass itin,
1038 string asm, list<dag> pattern>
1039 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1041 // Two-address instructions
1042 class T1It<dag oops, dag iops, InstrItinClass itin,
1043 string asm, string cstr, list<dag> pattern>
1044 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
1045 asm, cstr, pattern>;
1047 // Thumb1 instruction that can either be predicated or set CPSR.
1048 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1049 InstrItinClass itin,
1050 string opc, string asm, string cstr, list<dag> pattern>
1051 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1052 let OutOperandList = !con(oops, (outs s_cc_out:$s));
1053 let InOperandList = !con(iops, (ins pred:$p));
1054 let AsmString = !strconcat(opc, "${s}${p}", asm);
1055 let Pattern = pattern;
1056 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1059 class T1sI<dag oops, dag iops, InstrItinClass itin,
1060 string opc, string asm, list<dag> pattern>
1061 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1063 // Two-address instructions
1064 class T1sIt<dag oops, dag iops, InstrItinClass itin,
1065 string opc, string asm, list<dag> pattern>
1066 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1067 "$lhs = $dst", pattern>;
1069 // Thumb1 instruction that can be predicated.
1070 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1071 InstrItinClass itin,
1072 string opc, string asm, string cstr, list<dag> pattern>
1073 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1074 let OutOperandList = oops;
1075 let InOperandList = !con(iops, (ins pred:$p));
1076 let AsmString = !strconcat(opc, "${p}", asm);
1077 let Pattern = pattern;
1078 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1081 class T1pI<dag oops, dag iops, InstrItinClass itin,
1082 string opc, string asm, list<dag> pattern>
1083 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1085 // Two-address instructions
1086 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1087 string opc, string asm, list<dag> pattern>
1088 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1089 "$lhs = $dst", pattern>;
1091 class T1pI1<dag oops, dag iops, InstrItinClass itin,
1092 string opc, string asm, list<dag> pattern>
1093 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
1094 class T1pI2<dag oops, dag iops, InstrItinClass itin,
1095 string opc, string asm, list<dag> pattern>
1096 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
1097 class T1pI4<dag oops, dag iops, InstrItinClass itin,
1098 string opc, string asm, list<dag> pattern>
1099 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
1100 class T1pIs<dag oops, dag iops,
1101 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1102 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
1104 class Encoding16 : Encoding {
1105 let Inst{31-16} = 0x0000;
1108 // A6.2 16-bit Thumb instruction encoding
1109 class T1Encoding<bits<6> opcode> : Encoding16 {
1110 let Inst{15-10} = opcode;
1113 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1114 class T1General<bits<5> opcode> : Encoding16 {
1115 let Inst{15-14} = 0b00;
1116 let Inst{13-9} = opcode;
1119 // A6.2.2 Data-processing encoding.
1120 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1121 let Inst{15-10} = 0b010000;
1122 let Inst{9-6} = opcode;
1125 // A6.2.3 Special data instructions and branch and exchange encoding.
1126 class T1Special<bits<4> opcode> : Encoding16 {
1127 let Inst{15-10} = 0b010001;
1128 let Inst{9-6} = opcode;
1131 // A6.2.4 Load/store single data item encoding.
1132 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1133 let Inst{15-12} = opA;
1134 let Inst{11-9} = opB;
1136 class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
1137 class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
1138 class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
1139 class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
1140 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1142 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1143 class T1Misc<bits<7> opcode> : Encoding16 {
1144 let Inst{15-12} = 0b1011;
1145 let Inst{11-5} = opcode;
1148 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1149 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1150 InstrItinClass itin,
1151 string opc, string asm, string cstr, list<dag> pattern>
1152 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1153 let OutOperandList = oops;
1154 let InOperandList = !con(iops, (ins pred:$p));
1155 let AsmString = !strconcat(opc, "${p}", asm);
1156 let Pattern = pattern;
1157 list<Predicate> Predicates = [IsThumb2];
1160 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1161 // input operand since by default it's a zero register. It will become an
1162 // implicit def once it's "flipped".
1164 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1166 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1167 InstrItinClass itin,
1168 string opc, string asm, string cstr, list<dag> pattern>
1169 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1170 let OutOperandList = oops;
1171 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1172 let AsmString = !strconcat(opc, "${s}${p}", asm);
1173 let Pattern = pattern;
1174 list<Predicate> Predicates = [IsThumb2];
1178 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1179 InstrItinClass itin,
1180 string asm, string cstr, list<dag> pattern>
1181 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1182 let OutOperandList = oops;
1183 let InOperandList = iops;
1184 let AsmString = asm;
1185 let Pattern = pattern;
1186 list<Predicate> Predicates = [IsThumb2];
1189 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1190 InstrItinClass itin,
1191 string asm, string cstr, list<dag> pattern>
1192 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1193 let OutOperandList = oops;
1194 let InOperandList = iops;
1195 let AsmString = asm;
1196 let Pattern = pattern;
1197 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1200 class T2I<dag oops, dag iops, InstrItinClass itin,
1201 string opc, string asm, list<dag> pattern>
1202 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1203 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1204 string opc, string asm, list<dag> pattern>
1205 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
1206 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1207 string opc, string asm, list<dag> pattern>
1208 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1209 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1210 string opc, string asm, list<dag> pattern>
1211 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1212 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1213 string opc, string asm, list<dag> pattern>
1214 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1215 class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
1216 string opc, string asm, list<dag> pattern>
1217 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1219 let Inst{31-27} = 0b11101;
1220 let Inst{26-25} = 0b00;
1222 let Inst{23} = ?; // The U bit.
1225 let Inst{20} = load;
1228 class T2sI<dag oops, dag iops, InstrItinClass itin,
1229 string opc, string asm, list<dag> pattern>
1230 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1232 class T2XI<dag oops, dag iops, InstrItinClass itin,
1233 string asm, list<dag> pattern>
1234 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1235 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1236 string asm, list<dag> pattern>
1237 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1239 class T2Ix2<dag oops, dag iops, InstrItinClass itin,
1240 string opc, string asm, list<dag> pattern>
1241 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
1243 // Two-address instructions
1244 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1245 string asm, string cstr, list<dag> pattern>
1246 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1248 // T2Iidxldst - Thumb2 indexed load / store instructions.
1249 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1251 AddrMode am, IndexMode im, InstrItinClass itin,
1252 string opc, string asm, string cstr, list<dag> pattern>
1253 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1254 let OutOperandList = oops;
1255 let InOperandList = !con(iops, (ins pred:$p));
1256 let AsmString = !strconcat(opc, "${p}", asm);
1257 let Pattern = pattern;
1258 list<Predicate> Predicates = [IsThumb2];
1259 let Inst{31-27} = 0b11111;
1260 let Inst{26-25} = 0b00;
1261 let Inst{24} = signed;
1263 let Inst{22-21} = opcod;
1264 let Inst{20} = load;
1266 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1267 let Inst{10} = pre; // The P bit.
1268 let Inst{8} = 1; // The W bit.
1271 // Helper class for disassembly only
1272 // A6.3.16 & A6.3.17
1273 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1274 class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
1275 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1276 : T2I<oops, iops, itin, opc, asm, pattern> {
1277 let Inst{31-27} = 0b11111;
1278 let Inst{26-24} = 0b011;
1279 let Inst{23} = long;
1280 let Inst{22-20} = op22_20;
1281 let Inst{7-4} = op7_4;
1284 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1285 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1286 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1289 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1290 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1291 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1294 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1295 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1296 list<Predicate> Predicates = [IsThumb2];
1299 //===----------------------------------------------------------------------===//
1301 //===----------------------------------------------------------------------===//
1302 // ARM VFP Instruction templates.
1305 // Almost all VFP instructions are predicable.
1306 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1307 IndexMode im, Format f, InstrItinClass itin,
1308 string opc, string asm, string cstr, list<dag> pattern>
1309 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1311 let Inst{31-28} = p;
1312 let OutOperandList = oops;
1313 let InOperandList = !con(iops, (ins pred:$p));
1314 let AsmString = !strconcat(opc, "${p}", asm);
1315 let Pattern = pattern;
1316 list<Predicate> Predicates = [HasVFP2];
1320 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1321 IndexMode im, Format f, InstrItinClass itin,
1322 string asm, string cstr, list<dag> pattern>
1323 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1324 let OutOperandList = oops;
1325 let InOperandList = iops;
1326 let AsmString = asm;
1327 let Pattern = pattern;
1328 list<Predicate> Predicates = [HasVFP2];
1331 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1332 string opc, string asm, list<dag> pattern>
1333 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1334 opc, asm, "", pattern>;
1336 // ARM VFP addrmode5 loads and stores
1337 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1338 InstrItinClass itin,
1339 string opc, string asm, list<dag> pattern>
1340 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1341 VFPLdStFrm, itin, opc, asm, "", pattern> {
1342 // Instruction operands.
1346 // Encode instruction operands.
1347 let Inst{23} = addr{8}; // U (add = (U == '1'))
1348 let Inst{22} = Dd{4};
1349 let Inst{19-16} = addr{12-9}; // Rn
1350 let Inst{15-12} = Dd{3-0};
1351 let Inst{7-0} = addr{7-0}; // imm8
1353 // TODO: Mark the instructions with the appropriate subtarget info.
1354 let Inst{27-24} = opcod1;
1355 let Inst{21-20} = opcod2;
1356 let Inst{11-9} = 0b101;
1357 let Inst{8} = 1; // Double precision
1359 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1360 let D = VFPNeonDomain;
1363 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1364 InstrItinClass itin,
1365 string opc, string asm, list<dag> pattern>
1366 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1367 VFPLdStFrm, itin, opc, asm, "", pattern> {
1368 // Instruction operands.
1372 // Encode instruction operands.
1373 let Inst{23} = addr{8}; // U (add = (U == '1'))
1374 let Inst{22} = Sd{0};
1375 let Inst{19-16} = addr{12-9}; // Rn
1376 let Inst{15-12} = Sd{4-1};
1377 let Inst{7-0} = addr{7-0}; // imm8
1379 // TODO: Mark the instructions with the appropriate subtarget info.
1380 let Inst{27-24} = opcod1;
1381 let Inst{21-20} = opcod2;
1382 let Inst{11-9} = 0b101;
1383 let Inst{8} = 0; // Single precision
1386 // VFP Load / store multiple pseudo instructions.
1387 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1389 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain,
1391 let OutOperandList = oops;
1392 let InOperandList = !con(iops, (ins pred:$p));
1393 let Pattern = pattern;
1394 list<Predicate> Predicates = [HasVFP2];
1397 // Load / store multiple
1398 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1399 string asm, string cstr, list<dag> pattern>
1400 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1401 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1402 // TODO: Mark the instructions with the appropriate subtarget info.
1403 let Inst{27-25} = 0b110;
1404 let Inst{11-9} = 0b101;
1405 let Inst{8} = 1; // Double precision
1407 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1408 let D = VFPNeonDomain;
1411 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1412 string asm, string cstr, list<dag> pattern>
1413 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1414 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1415 // TODO: Mark the instructions with the appropriate subtarget info.
1416 let Inst{27-25} = 0b110;
1417 let Inst{11-9} = 0b101;
1418 let Inst{8} = 0; // Single precision
1421 // Double precision, unary
1422 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1423 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1424 string asm, list<dag> pattern>
1425 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1426 // Instruction operands.
1430 // Encode instruction operands.
1431 let Inst{3-0} = Dm{3-0};
1432 let Inst{5} = Dm{4};
1433 let Inst{15-12} = Dd{3-0};
1434 let Inst{22} = Dd{4};
1436 let Inst{27-23} = opcod1;
1437 let Inst{21-20} = opcod2;
1438 let Inst{19-16} = opcod3;
1439 let Inst{11-9} = 0b101;
1440 let Inst{8} = 1; // Double precision
1441 let Inst{7-6} = opcod4;
1442 let Inst{4} = opcod5;
1445 // Double precision, binary
1446 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1447 dag iops, InstrItinClass itin, string opc, string asm,
1449 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1450 // Instruction operands.
1455 // Encode instruction operands.
1456 let Inst{3-0} = Dm{3-0};
1457 let Inst{5} = Dm{4};
1458 let Inst{19-16} = Dn{3-0};
1459 let Inst{7} = Dn{4};
1460 let Inst{15-12} = Dd{3-0};
1461 let Inst{22} = Dd{4};
1463 let Inst{27-23} = opcod1;
1464 let Inst{21-20} = opcod2;
1465 let Inst{11-9} = 0b101;
1466 let Inst{8} = 1; // Double precision
1471 // Single precision, unary
1472 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1473 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1474 string asm, list<dag> pattern>
1475 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1476 // Instruction operands.
1480 // Encode instruction operands.
1481 let Inst{3-0} = Sm{4-1};
1482 let Inst{5} = Sm{0};
1483 let Inst{15-12} = Sd{4-1};
1484 let Inst{22} = Sd{0};
1486 let Inst{27-23} = opcod1;
1487 let Inst{21-20} = opcod2;
1488 let Inst{19-16} = opcod3;
1489 let Inst{11-9} = 0b101;
1490 let Inst{8} = 0; // Single precision
1491 let Inst{7-6} = opcod4;
1492 let Inst{4} = opcod5;
1495 // Single precision unary, if no NEON
1496 // Same as ASuI except not available if NEON is enabled
1497 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1498 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1499 string asm, list<dag> pattern>
1500 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1502 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1505 // Single precision, binary
1506 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1507 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1508 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1509 // Instruction operands.
1514 // Encode instruction operands.
1515 let Inst{3-0} = Sm{4-1};
1516 let Inst{5} = Sm{0};
1517 let Inst{19-16} = Sn{4-1};
1518 let Inst{7} = Sn{0};
1519 let Inst{15-12} = Sd{4-1};
1520 let Inst{22} = Sd{0};
1522 let Inst{27-23} = opcod1;
1523 let Inst{21-20} = opcod2;
1524 let Inst{11-9} = 0b101;
1525 let Inst{8} = 0; // Single precision
1530 // Single precision binary, if no NEON
1531 // Same as ASbI except not available if NEON is enabled
1532 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1533 dag iops, InstrItinClass itin, string opc, string asm,
1535 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1536 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1538 // Instruction operands.
1543 // Encode instruction operands.
1544 let Inst{3-0} = Sm{4-1};
1545 let Inst{5} = Sm{0};
1546 let Inst{19-16} = Sn{4-1};
1547 let Inst{7} = Sn{0};
1548 let Inst{15-12} = Sd{4-1};
1549 let Inst{22} = Sd{0};
1552 // VFP conversion instructions
1553 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1554 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1556 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1557 let Inst{27-23} = opcod1;
1558 let Inst{21-20} = opcod2;
1559 let Inst{19-16} = opcod3;
1560 let Inst{11-8} = opcod4;
1565 // VFP conversion between floating-point and fixed-point
1566 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1567 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1569 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1570 // size (fixed-point number): sx == 0 ? 16 : 32
1571 let Inst{7} = op5; // sx
1574 // VFP conversion instructions, if no NEON
1575 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1576 dag oops, dag iops, InstrItinClass itin,
1577 string opc, string asm, list<dag> pattern>
1578 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1580 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1583 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1584 InstrItinClass itin,
1585 string opc, string asm, list<dag> pattern>
1586 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1587 let Inst{27-20} = opcod1;
1588 let Inst{11-8} = opcod2;
1592 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1593 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1594 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1596 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1597 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1598 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1600 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1601 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1602 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1604 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1605 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1606 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1608 //===----------------------------------------------------------------------===//
1610 //===----------------------------------------------------------------------===//
1611 // ARM NEON Instruction templates.
1614 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1615 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1617 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1618 let OutOperandList = oops;
1619 let InOperandList = !con(iops, (ins pred:$p));
1620 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1621 let Pattern = pattern;
1622 list<Predicate> Predicates = [HasNEON];
1625 // Same as NeonI except it does not have a "data type" specifier.
1626 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1627 InstrItinClass itin, string opc, string asm, string cstr,
1629 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1630 let OutOperandList = oops;
1631 let InOperandList = !con(iops, (ins pred:$p));
1632 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1633 let Pattern = pattern;
1634 list<Predicate> Predicates = [HasNEON];
1637 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1638 dag oops, dag iops, InstrItinClass itin,
1639 string opc, string dt, string asm, string cstr, list<dag> pattern>
1640 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1642 let Inst{31-24} = 0b11110100;
1643 let Inst{23} = op23;
1644 let Inst{21-20} = op21_20;
1645 let Inst{11-8} = op11_8;
1646 let Inst{7-4} = op7_4;
1648 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1654 let Inst{22} = Vd{4};
1655 let Inst{15-12} = Vd{3-0};
1656 let Inst{19-16} = Rn{3-0};
1657 let Inst{3-0} = Rm{3-0};
1660 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1661 dag oops, dag iops, InstrItinClass itin,
1662 string opc, string dt, string asm, string cstr, list<dag> pattern>
1663 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1664 dt, asm, cstr, pattern> {
1668 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1669 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1671 let OutOperandList = oops;
1672 let InOperandList = !con(iops, (ins pred:$p));
1673 list<Predicate> Predicates = [HasNEON];
1676 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1678 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1680 let OutOperandList = oops;
1681 let InOperandList = !con(iops, (ins pred:$p));
1682 let Pattern = pattern;
1683 list<Predicate> Predicates = [HasNEON];
1686 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1687 string opc, string dt, string asm, string cstr, list<dag> pattern>
1688 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1690 let Inst{31-25} = 0b1111001;
1691 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1694 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1695 string opc, string asm, string cstr, list<dag> pattern>
1696 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1698 let Inst{31-25} = 0b1111001;
1701 // NEON "one register and a modified immediate" format.
1702 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1704 dag oops, dag iops, InstrItinClass itin,
1705 string opc, string dt, string asm, string cstr,
1707 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1708 let Inst{23} = op23;
1709 let Inst{21-19} = op21_19;
1710 let Inst{11-8} = op11_8;
1716 // Instruction operands.
1720 let Inst{15-12} = Vd{3-0};
1721 let Inst{22} = Vd{4};
1722 let Inst{24} = SIMM{7};
1723 let Inst{18-16} = SIMM{6-4};
1724 let Inst{3-0} = SIMM{3-0};
1727 // NEON 2 vector register format.
1728 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1729 bits<5> op11_7, bit op6, bit op4,
1730 dag oops, dag iops, InstrItinClass itin,
1731 string opc, string dt, string asm, string cstr, list<dag> pattern>
1732 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1733 let Inst{24-23} = op24_23;
1734 let Inst{21-20} = op21_20;
1735 let Inst{19-18} = op19_18;
1736 let Inst{17-16} = op17_16;
1737 let Inst{11-7} = op11_7;
1741 // Instruction operands.
1745 let Inst{15-12} = Vd{3-0};
1746 let Inst{22} = Vd{4};
1747 let Inst{3-0} = Vm{3-0};
1748 let Inst{5} = Vm{4};
1751 // Same as N2V except it doesn't have a datatype suffix.
1752 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1753 bits<5> op11_7, bit op6, bit op4,
1754 dag oops, dag iops, InstrItinClass itin,
1755 string opc, string asm, string cstr, list<dag> pattern>
1756 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1757 let Inst{24-23} = op24_23;
1758 let Inst{21-20} = op21_20;
1759 let Inst{19-18} = op19_18;
1760 let Inst{17-16} = op17_16;
1761 let Inst{11-7} = op11_7;
1765 // Instruction operands.
1769 let Inst{15-12} = Vd{3-0};
1770 let Inst{22} = Vd{4};
1771 let Inst{3-0} = Vm{3-0};
1772 let Inst{5} = Vm{4};
1775 // NEON 2 vector register with immediate.
1776 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1777 dag oops, dag iops, Format f, InstrItinClass itin,
1778 string opc, string dt, string asm, string cstr, list<dag> pattern>
1779 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1780 let Inst{24} = op24;
1781 let Inst{23} = op23;
1782 let Inst{11-8} = op11_8;
1787 // Instruction operands.
1792 let Inst{15-12} = Vd{3-0};
1793 let Inst{22} = Vd{4};
1794 let Inst{3-0} = Vm{3-0};
1795 let Inst{5} = Vm{4};
1796 let Inst{21-16} = SIMM{5-0};
1799 // NEON 3 vector register format.
1800 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1801 dag oops, dag iops, Format f, InstrItinClass itin,
1802 string opc, string dt, string asm, string cstr, list<dag> pattern>
1803 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1804 let Inst{24} = op24;
1805 let Inst{23} = op23;
1806 let Inst{21-20} = op21_20;
1807 let Inst{11-8} = op11_8;
1811 // Instruction operands.
1816 let Inst{15-12} = Vd{3-0};
1817 let Inst{22} = Vd{4};
1818 let Inst{19-16} = Vn{3-0};
1819 let Inst{7} = Vn{4};
1820 let Inst{3-0} = Vm{3-0};
1821 let Inst{5} = Vm{4};
1824 // Same as N3V except it doesn't have a data type suffix.
1825 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1827 dag oops, dag iops, Format f, InstrItinClass itin,
1828 string opc, string asm, string cstr, list<dag> pattern>
1829 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1830 let Inst{24} = op24;
1831 let Inst{23} = op23;
1832 let Inst{21-20} = op21_20;
1833 let Inst{11-8} = op11_8;
1837 // Instruction operands.
1842 let Inst{15-12} = Vd{3-0};
1843 let Inst{22} = Vd{4};
1844 let Inst{19-16} = Vn{3-0};
1845 let Inst{7} = Vn{4};
1846 let Inst{3-0} = Vm{3-0};
1847 let Inst{5} = Vm{4};
1850 // NEON VMOVs between scalar and core registers.
1851 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1852 dag oops, dag iops, Format f, InstrItinClass itin,
1853 string opc, string dt, string asm, list<dag> pattern>
1854 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain,
1856 let Inst{27-20} = opcod1;
1857 let Inst{11-8} = opcod2;
1858 let Inst{6-5} = opcod3;
1861 let OutOperandList = oops;
1862 let InOperandList = !con(iops, (ins pred:$p));
1863 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1864 let Pattern = pattern;
1865 list<Predicate> Predicates = [HasNEON];
1867 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1874 let Inst{31-28} = p{3-0};
1876 let Inst{19-16} = V{3-0};
1877 let Inst{15-12} = R{3-0};
1879 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1880 dag oops, dag iops, InstrItinClass itin,
1881 string opc, string dt, string asm, list<dag> pattern>
1882 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1883 opc, dt, asm, pattern>;
1884 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1885 dag oops, dag iops, InstrItinClass itin,
1886 string opc, string dt, string asm, list<dag> pattern>
1887 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1888 opc, dt, asm, pattern>;
1889 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1890 dag oops, dag iops, InstrItinClass itin,
1891 string opc, string dt, string asm, list<dag> pattern>
1892 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1893 opc, dt, asm, pattern>;
1895 // Vector Duplicate Lane (from scalar to all elements)
1896 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1897 InstrItinClass itin, string opc, string dt, string asm,
1899 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1900 let Inst{24-23} = 0b11;
1901 let Inst{21-20} = 0b11;
1902 let Inst{19-16} = op19_16;
1903 let Inst{11-7} = 0b11000;
1911 let Inst{22} = Vd{4};
1912 let Inst{15-12} = Vd{3-0};
1913 let Inst{5} = Vm{4};
1914 let Inst{3-0} = Vm{3-0};
1917 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1918 // for single-precision FP.
1919 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1920 list<Predicate> Predicates = [HasNEON,UseNEONForFP];