1 //===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
71 def DPSoRegImmFrm : Format<42>;
75 // The instruction has an Rn register operand.
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
77 // it doesn't have a Rn operand.
78 class UnaryDP { bit isUnaryDataProc = 1; }
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
82 class Xform16Bit { bit canXformTo16Bit = 1; }
84 //===----------------------------------------------------------------------===//
85 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 // FIXME: Once the JIT is MC-ized, these can go away.
90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>;
102 def AddrModeT1_4 : AddrMode<9>;
103 def AddrModeT1_s : AddrMode<10>;
104 def AddrModeT2_i12 : AddrMode<11>;
105 def AddrModeT2_i8 : AddrMode<12>;
106 def AddrModeT2_so : AddrMode<13>;
107 def AddrModeT2_pc : AddrMode<14>;
108 def AddrModeT2_i8s4 : AddrMode<15>;
109 def AddrMode_i12 : AddrMode<16>;
111 // Load / store index mode.
112 class IndexMode<bits<2> val> {
115 def IndexModeNone : IndexMode<0>;
116 def IndexModePre : IndexMode<1>;
117 def IndexModePost : IndexMode<2>;
118 def IndexModeUpd : IndexMode<3>;
120 // Instruction execution domain.
121 class Domain<bits<3> val> {
124 def GenericDomain : Domain<0>;
125 def VFPDomain : Domain<1>; // Instructions in VFP domain only
126 def NeonDomain : Domain<2>; // Instructions in Neon domain only
127 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
128 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
130 //===----------------------------------------------------------------------===//
131 // ARM special operands.
134 // ARM imod and iflag operands, used only by the CPS instruction.
135 def imod_op : Operand<i32> {
136 let PrintMethod = "printCPSIMod";
139 def ProcIFlagsOperand : AsmOperandClass {
140 let Name = "ProcIFlags";
141 let ParserMethod = "parseProcIFlagsOperand";
143 def iflags_op : Operand<i32> {
144 let PrintMethod = "printCPSIFlag";
145 let ParserMatchClass = ProcIFlagsOperand;
148 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
149 // register whose default is 0 (no register).
150 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
151 def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
152 (ops (i32 14), (i32 zero_reg))> {
153 let PrintMethod = "printPredicateOperand";
154 let ParserMatchClass = CondCodeOperand;
155 let DecoderMethod = "DecodePredicateOperand";
158 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
159 def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
160 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
161 let EncoderMethod = "getCCOutOpValue";
162 let PrintMethod = "printSBitModifierOperand";
163 let ParserMatchClass = CCOutOperand;
164 let DecoderMethod = "DecodeCCOutOperand";
167 // Same as cc_out except it defaults to setting CPSR.
168 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
169 let EncoderMethod = "getCCOutOpValue";
170 let PrintMethod = "printSBitModifierOperand";
171 let ParserMatchClass = CCOutOperand;
172 let DecoderMethod = "DecodeCCOutOperand";
175 // ARM special operands for disassembly only.
177 def SetEndAsmOperand : AsmOperandClass {
178 let Name = "SetEndImm";
179 let ParserMethod = "parseSetEndImm";
181 def setend_op : Operand<i32> {
182 let PrintMethod = "printSetendOperand";
183 let ParserMatchClass = SetEndAsmOperand;
186 def MSRMaskOperand : AsmOperandClass {
187 let Name = "MSRMask";
188 let ParserMethod = "parseMSRMaskOperand";
190 def msr_mask : Operand<i32> {
191 let PrintMethod = "printMSRMaskOperand";
192 let DecoderMethod = "DecodeMSRMask";
193 let ParserMatchClass = MSRMaskOperand;
196 // Shift Right Immediate - A shift right immediate is encoded differently from
197 // other shift immediates. The imm6 field is encoded like so:
200 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
201 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
202 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
203 // 64 64 - <imm> is encoded in imm6<5:0>
204 def shr_imm8 : Operand<i32> {
205 let EncoderMethod = "getShiftRight8Imm";
206 let DecoderMethod = "DecodeShiftRight8Imm";
208 def shr_imm16 : Operand<i32> {
209 let EncoderMethod = "getShiftRight16Imm";
210 let DecoderMethod = "DecodeShiftRight16Imm";
212 def shr_imm32 : Operand<i32> {
213 let EncoderMethod = "getShiftRight32Imm";
214 let DecoderMethod = "DecodeShiftRight32Imm";
216 def shr_imm64 : Operand<i32> {
217 let EncoderMethod = "getShiftRight64Imm";
218 let DecoderMethod = "DecodeShiftRight64Imm";
221 //===----------------------------------------------------------------------===//
222 // ARM Assembler alias templates.
224 class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1>
225 : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>;
226 class tInstAlias<string Asm, dag Result, bit Emit = 0b1>
227 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>;
228 class t2InstAlias<string Asm, dag Result, bit Emit = 0b1>
229 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>;
231 //===----------------------------------------------------------------------===//
232 // ARM Instruction templates.
236 class InstTemplate<AddrMode am, int sz, IndexMode im,
237 Format f, Domain d, string cstr, InstrItinClass itin>
239 let Namespace = "ARM";
244 bits<2> IndexModeBits = IM.Value;
246 bits<6> Form = F.Value;
248 bit isUnaryDataProc = 0;
249 bit canXformTo16Bit = 0;
250 // The instruction is a 16-bit flag setting Thumb instruction. Used
251 // by the parser to determine whether to require the 'S' suffix on the
252 // mnemonic (when not in an IT block) or preclude it (when in an IT block).
253 bit thumbArithFlagSetting = 0;
255 // If this is a pseudo instruction, mark it isCodeGenOnly.
256 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
258 // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
259 let TSFlags{4-0} = AM.Value;
260 let TSFlags{6-5} = IndexModeBits;
261 let TSFlags{12-7} = Form;
262 let TSFlags{13} = isUnaryDataProc;
263 let TSFlags{14} = canXformTo16Bit;
264 let TSFlags{17-15} = D.Value;
265 let TSFlags{18} = thumbArithFlagSetting;
267 let Constraints = cstr;
268 let Itinerary = itin;
275 class InstARM<AddrMode am, int sz, IndexMode im,
276 Format f, Domain d, string cstr, InstrItinClass itin>
277 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
278 let DecoderNamespace = "ARM";
281 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
282 // on by adding flavors to specific instructions.
283 class InstThumb<AddrMode am, int sz, IndexMode im,
284 Format f, Domain d, string cstr, InstrItinClass itin>
285 : InstTemplate<am, sz, im, f, d, cstr, itin> {
286 let DecoderNamespace = "Thumb";
289 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
290 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
291 GenericDomain, "", itin> {
292 let OutOperandList = oops;
293 let InOperandList = iops;
294 let Pattern = pattern;
295 let isCodeGenOnly = 1;
299 // PseudoInst that's ARM-mode only.
300 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
302 : PseudoInst<oops, iops, itin, pattern> {
304 list<Predicate> Predicates = [IsARM];
307 // PseudoInst that's Thumb-mode only.
308 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
310 : PseudoInst<oops, iops, itin, pattern> {
312 list<Predicate> Predicates = [IsThumb];
315 // PseudoInst that's Thumb2-mode only.
316 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
318 : PseudoInst<oops, iops, itin, pattern> {
320 list<Predicate> Predicates = [IsThumb2];
323 class ARMPseudoExpand<dag oops, dag iops, int sz,
324 InstrItinClass itin, list<dag> pattern,
326 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
327 PseudoInstExpansion<Result>;
329 class tPseudoExpand<dag oops, dag iops, int sz,
330 InstrItinClass itin, list<dag> pattern,
332 : tPseudoInst<oops, iops, sz, itin, pattern>,
333 PseudoInstExpansion<Result>;
335 class t2PseudoExpand<dag oops, dag iops, int sz,
336 InstrItinClass itin, list<dag> pattern,
338 : t2PseudoInst<oops, iops, sz, itin, pattern>,
339 PseudoInstExpansion<Result>;
341 // Almost all ARM instructions are predicable.
342 class I<dag oops, dag iops, AddrMode am, int sz,
343 IndexMode im, Format f, InstrItinClass itin,
344 string opc, string asm, string cstr,
346 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
349 let OutOperandList = oops;
350 let InOperandList = !con(iops, (ins pred:$p));
351 let AsmString = !strconcat(opc, "${p}", asm);
352 let Pattern = pattern;
353 list<Predicate> Predicates = [IsARM];
356 // A few are not predicable
357 class InoP<dag oops, dag iops, AddrMode am, int sz,
358 IndexMode im, Format f, InstrItinClass itin,
359 string opc, string asm, string cstr,
361 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
362 let OutOperandList = oops;
363 let InOperandList = iops;
364 let AsmString = !strconcat(opc, asm);
365 let Pattern = pattern;
366 let isPredicable = 0;
367 list<Predicate> Predicates = [IsARM];
370 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
371 // operand since by default it's a zero register. It will become an implicit def
372 // once it's "flipped".
373 class sI<dag oops, dag iops, AddrMode am, int sz,
374 IndexMode im, Format f, InstrItinClass itin,
375 string opc, string asm, string cstr,
377 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
378 bits<4> p; // Predicate operand
379 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
383 let OutOperandList = oops;
384 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
385 let AsmString = !strconcat(opc, "${s}${p}", asm);
386 let Pattern = pattern;
387 list<Predicate> Predicates = [IsARM];
391 class XI<dag oops, dag iops, AddrMode am, int sz,
392 IndexMode im, Format f, InstrItinClass itin,
393 string asm, string cstr, list<dag> pattern>
394 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
395 let OutOperandList = oops;
396 let InOperandList = iops;
398 let Pattern = pattern;
399 list<Predicate> Predicates = [IsARM];
402 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
403 string opc, string asm, list<dag> pattern>
404 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
405 opc, asm, "", pattern>;
406 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
407 string opc, string asm, list<dag> pattern>
408 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
409 opc, asm, "", pattern>;
410 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
411 string asm, list<dag> pattern>
412 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
414 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
415 string opc, string asm, list<dag> pattern>
416 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
417 opc, asm, "", pattern>;
419 // Ctrl flow instructions
420 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
421 string opc, string asm, list<dag> pattern>
422 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
423 opc, asm, "", pattern> {
424 let Inst{27-24} = opcod;
426 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
427 string asm, list<dag> pattern>
428 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
430 let Inst{27-24} = opcod;
433 // BR_JT instructions
434 class JTI<dag oops, dag iops, InstrItinClass itin,
435 string asm, list<dag> pattern>
436 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
439 // Atomic load/store instructions
440 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
441 string opc, string asm, list<dag> pattern>
442 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
443 opc, asm, "", pattern> {
446 let Inst{27-23} = 0b00011;
447 let Inst{22-21} = opcod;
449 let Inst{19-16} = addr;
450 let Inst{15-12} = Rt;
451 let Inst{11-0} = 0b111110011111;
453 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
454 string opc, string asm, list<dag> pattern>
455 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
456 opc, asm, "", pattern> {
460 let Inst{27-23} = 0b00011;
461 let Inst{22-21} = opcod;
463 let Inst{19-16} = addr;
464 let Inst{15-12} = Rd;
465 let Inst{11-4} = 0b11111001;
468 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
469 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
473 let Inst{27-23} = 0b00010;
475 let Inst{21-20} = 0b00;
476 let Inst{19-16} = addr;
477 let Inst{15-12} = Rt;
478 let Inst{11-4} = 0b00001001;
482 // addrmode1 instructions
483 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
484 string opc, string asm, list<dag> pattern>
485 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
486 opc, asm, "", pattern> {
487 let Inst{24-21} = opcod;
488 let Inst{27-26} = 0b00;
490 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
491 string opc, string asm, list<dag> pattern>
492 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
493 opc, asm, "", pattern> {
494 let Inst{24-21} = opcod;
495 let Inst{27-26} = 0b00;
497 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
498 string asm, list<dag> pattern>
499 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
501 let Inst{24-21} = opcod;
502 let Inst{27-26} = 0b00;
507 // LDR/LDRB/STR/STRB/...
508 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
509 Format f, InstrItinClass itin, string opc, string asm,
511 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
513 let Inst{27-25} = op;
514 let Inst{24} = 1; // 24 == P
516 let Inst{22} = isByte;
517 let Inst{21} = 0; // 21 == W
520 // Indexed load/stores
521 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
522 IndexMode im, Format f, InstrItinClass itin, string opc,
523 string asm, string cstr, list<dag> pattern>
524 : I<oops, iops, AddrMode2, 4, im, f, itin,
525 opc, asm, cstr, pattern> {
527 let Inst{27-26} = 0b01;
528 let Inst{24} = isPre; // P bit
529 let Inst{22} = isByte; // B bit
530 let Inst{21} = isPre; // W bit
531 let Inst{20} = isLd; // L bit
532 let Inst{15-12} = Rt;
534 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
535 IndexMode im, Format f, InstrItinClass itin, string opc,
536 string asm, string cstr, list<dag> pattern>
537 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
539 // AM2 store w/ two operands: (GPR, am2offset)
545 let Inst{23} = offset{12};
546 let Inst{19-16} = Rn;
547 let Inst{11-5} = offset{11-5};
549 let Inst{3-0} = offset{3-0};
552 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
553 IndexMode im, Format f, InstrItinClass itin, string opc,
554 string asm, string cstr, list<dag> pattern>
555 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
557 // AM2 store w/ two operands: (GPR, am2offset)
563 let Inst{23} = offset{12};
564 let Inst{19-16} = Rn;
565 let Inst{11-0} = offset{11-0};
569 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
570 // but for now use this class for STRT and STRBT.
571 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
572 IndexMode im, Format f, InstrItinClass itin, string opc,
573 string asm, string cstr, list<dag> pattern>
574 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
576 // AM2 store w/ two operands: (GPR, am2offset)
578 // {13} 1 == Rm, 0 == imm12
582 let Inst{25} = addr{13};
583 let Inst{23} = addr{12};
584 let Inst{19-16} = addr{17-14};
585 let Inst{11-0} = addr{11-0};
588 // addrmode3 instructions
589 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
590 InstrItinClass itin, string opc, string asm, list<dag> pattern>
591 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
592 opc, asm, "", pattern> {
595 let Inst{27-25} = 0b000;
596 let Inst{24} = 1; // P bit
597 let Inst{23} = addr{8}; // U bit
598 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
599 let Inst{21} = 0; // W bit
600 let Inst{20} = op20; // L bit
601 let Inst{19-16} = addr{12-9}; // Rn
602 let Inst{15-12} = Rt; // Rt
603 let Inst{11-8} = addr{7-4}; // imm7_4/zero
605 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
607 let DecoderMethod = "DecodeAddrMode3Instruction";
610 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
611 IndexMode im, Format f, InstrItinClass itin, string opc,
612 string asm, string cstr, list<dag> pattern>
613 : I<oops, iops, AddrMode3, 4, im, f, itin,
614 opc, asm, cstr, pattern> {
616 let Inst{27-25} = 0b000;
617 let Inst{24} = isPre; // P bit
618 let Inst{21} = isPre; // W bit
619 let Inst{20} = op20; // L bit
620 let Inst{15-12} = Rt; // Rt
624 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
625 // but for now use this class for LDRSBT, LDRHT, LDSHT.
626 class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
627 IndexMode im, Format f, InstrItinClass itin, string opc,
628 string asm, string cstr, list<dag> pattern>
629 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> {
630 // {13} 1 == imm8, 0 == Rm
637 let Inst{27-25} = 0b000;
638 let Inst{24} = 0; // P bit
640 let Inst{20} = isLoad; // L bit
641 let Inst{19-16} = addr; // Rn
642 let Inst{15-12} = Rt; // Rt
647 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
648 string opc, string asm, list<dag> pattern>
649 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
650 opc, asm, "", pattern> {
653 let Inst{27-25} = 0b000;
654 let Inst{24} = 1; // P bit
655 let Inst{23} = addr{8}; // U bit
656 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
657 let Inst{21} = 0; // W bit
658 let Inst{20} = 0; // L bit
659 let Inst{19-16} = addr{12-9}; // Rn
660 let Inst{15-12} = Rt; // Rt
661 let Inst{11-8} = addr{7-4}; // imm7_4/zero
663 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
664 let DecoderMethod = "DecodeAddrMode3Instruction";
667 // addrmode4 instructions
668 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
669 string asm, string cstr, list<dag> pattern>
670 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
675 let Inst{27-25} = 0b100;
676 let Inst{22} = 0; // S bit
677 let Inst{19-16} = Rn;
678 let Inst{15-0} = regs;
681 // Unsigned multiply, multiply-accumulate instructions.
682 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
683 string opc, string asm, list<dag> pattern>
684 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
685 opc, asm, "", pattern> {
686 let Inst{7-4} = 0b1001;
687 let Inst{20} = 0; // S bit
688 let Inst{27-21} = opcod;
690 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
691 string opc, string asm, list<dag> pattern>
692 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
693 opc, asm, "", pattern> {
694 let Inst{7-4} = 0b1001;
695 let Inst{27-21} = opcod;
698 // Most significant word multiply
699 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
700 InstrItinClass itin, string opc, string asm, list<dag> pattern>
701 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
702 opc, asm, "", pattern> {
706 let Inst{7-4} = opc7_4;
708 let Inst{27-21} = opcod;
709 let Inst{19-16} = Rd;
713 // MSW multiple w/ Ra operand
714 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
715 InstrItinClass itin, string opc, string asm, list<dag> pattern>
716 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
718 let Inst{15-12} = Ra;
721 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
722 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
723 InstrItinClass itin, string opc, string asm, list<dag> pattern>
724 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
725 opc, asm, "", pattern> {
731 let Inst{27-21} = opcod;
732 let Inst{6-5} = bit6_5;
736 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
737 InstrItinClass itin, string opc, string asm, list<dag> pattern>
738 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
740 let Inst{19-16} = Rd;
743 // AMulxyI with Ra operand
744 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
745 InstrItinClass itin, string opc, string asm, list<dag> pattern>
746 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
748 let Inst{15-12} = Ra;
751 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
752 InstrItinClass itin, string opc, string asm, list<dag> pattern>
753 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
756 let Inst{19-16} = RdHi;
757 let Inst{15-12} = RdLo;
760 // Extend instructions.
761 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
762 string opc, string asm, list<dag> pattern>
763 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
764 opc, asm, "", pattern> {
765 // All AExtI instructions have Rd and Rm register operands.
768 let Inst{15-12} = Rd;
770 let Inst{7-4} = 0b0111;
771 let Inst{9-8} = 0b00;
772 let Inst{27-20} = opcod;
775 // Misc Arithmetic instructions.
776 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
777 InstrItinClass itin, string opc, string asm, list<dag> pattern>
778 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
779 opc, asm, "", pattern> {
782 let Inst{27-20} = opcod;
783 let Inst{19-16} = 0b1111;
784 let Inst{15-12} = Rd;
785 let Inst{11-8} = 0b1111;
786 let Inst{7-4} = opc7_4;
791 def PKHLSLAsmOperand : AsmOperandClass {
792 let Name = "PKHLSLImm";
793 let ParserMethod = "parsePKHLSLImm";
795 def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
796 let PrintMethod = "printPKHLSLShiftImm";
797 let ParserMatchClass = PKHLSLAsmOperand;
799 def PKHASRAsmOperand : AsmOperandClass {
800 let Name = "PKHASRImm";
801 let ParserMethod = "parsePKHASRImm";
803 def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
804 let PrintMethod = "printPKHASRShiftImm";
805 let ParserMatchClass = PKHASRAsmOperand;
808 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
809 string opc, string asm, list<dag> pattern>
810 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
811 opc, asm, "", pattern> {
816 let Inst{27-20} = opcod;
817 let Inst{19-16} = Rn;
818 let Inst{15-12} = Rd;
821 let Inst{5-4} = 0b01;
825 //===----------------------------------------------------------------------===//
827 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
828 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
829 list<Predicate> Predicates = [IsARM];
831 class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
832 list<Predicate> Predicates = [IsARM, HasV5T];
834 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
835 list<Predicate> Predicates = [IsARM, HasV5TE];
837 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
838 list<Predicate> Predicates = [IsARM, HasV6];
841 //===----------------------------------------------------------------------===//
842 // Thumb Instruction Format Definitions.
845 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
846 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
847 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
848 let OutOperandList = oops;
849 let InOperandList = iops;
851 let Pattern = pattern;
852 list<Predicate> Predicates = [IsThumb];
855 // TI - Thumb instruction.
856 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
857 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
859 // Two-address instructions
860 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
862 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
865 // tBL, tBX 32-bit instructions
866 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
867 dag oops, dag iops, InstrItinClass itin, string asm,
869 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
871 let Inst{31-27} = opcod1;
872 let Inst{15-14} = opcod2;
873 let Inst{12} = opcod3;
876 // BR_JT instructions
877 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
879 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
882 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
883 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
884 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
885 let OutOperandList = oops;
886 let InOperandList = iops;
888 let Pattern = pattern;
889 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
892 class T1I<dag oops, dag iops, InstrItinClass itin,
893 string asm, list<dag> pattern>
894 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
895 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
896 string asm, list<dag> pattern>
897 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
899 // Two-address instructions
900 class T1It<dag oops, dag iops, InstrItinClass itin,
901 string asm, string cstr, list<dag> pattern>
902 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
905 // Thumb1 instruction that can either be predicated or set CPSR.
906 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
908 string opc, string asm, string cstr, list<dag> pattern>
909 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
910 let OutOperandList = !con(oops, (outs s_cc_out:$s));
911 let InOperandList = !con(iops, (ins pred:$p));
912 let AsmString = !strconcat(opc, "${s}${p}", asm);
913 let Pattern = pattern;
914 let thumbArithFlagSetting = 1;
915 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
916 let DecoderNamespace = "ThumbSBit";
919 class T1sI<dag oops, dag iops, InstrItinClass itin,
920 string opc, string asm, list<dag> pattern>
921 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
923 // Two-address instructions
924 class T1sIt<dag oops, dag iops, InstrItinClass itin,
925 string opc, string asm, list<dag> pattern>
926 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
927 "$Rn = $Rdn", pattern>;
929 // Thumb1 instruction that can be predicated.
930 class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
932 string opc, string asm, string cstr, list<dag> pattern>
933 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
934 let OutOperandList = oops;
935 let InOperandList = !con(iops, (ins pred:$p));
936 let AsmString = !strconcat(opc, "${p}", asm);
937 let Pattern = pattern;
938 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
941 class T1pI<dag oops, dag iops, InstrItinClass itin,
942 string opc, string asm, list<dag> pattern>
943 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
945 // Two-address instructions
946 class T1pIt<dag oops, dag iops, InstrItinClass itin,
947 string opc, string asm, list<dag> pattern>
948 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
949 "$Rn = $Rdn", pattern>;
951 class T1pIs<dag oops, dag iops,
952 InstrItinClass itin, string opc, string asm, list<dag> pattern>
953 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
955 class Encoding16 : Encoding {
956 let Inst{31-16} = 0x0000;
959 // A6.2 16-bit Thumb instruction encoding
960 class T1Encoding<bits<6> opcode> : Encoding16 {
961 let Inst{15-10} = opcode;
964 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
965 class T1General<bits<5> opcode> : Encoding16 {
966 let Inst{15-14} = 0b00;
967 let Inst{13-9} = opcode;
970 // A6.2.2 Data-processing encoding.
971 class T1DataProcessing<bits<4> opcode> : Encoding16 {
972 let Inst{15-10} = 0b010000;
973 let Inst{9-6} = opcode;
976 // A6.2.3 Special data instructions and branch and exchange encoding.
977 class T1Special<bits<4> opcode> : Encoding16 {
978 let Inst{15-10} = 0b010001;
979 let Inst{9-6} = opcode;
982 // A6.2.4 Load/store single data item encoding.
983 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
984 let Inst{15-12} = opA;
985 let Inst{11-9} = opB;
987 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
989 class T1BranchCond<bits<4> opcode> : Encoding16 {
990 let Inst{15-12} = opcode;
993 // Helper classes to encode Thumb1 loads and stores. For immediates, the
994 // following bits are used for "opA" (see A6.2.4):
996 // 0b0110 => Immediate, 4 bytes
997 // 0b1000 => Immediate, 2 bytes
998 // 0b0111 => Immediate, 1 byte
999 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1000 InstrItinClass itin, string opc, string asm,
1002 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1003 T1LoadStore<0b0101, opcode> {
1006 let Inst{8-6} = addr{5-3}; // Rm
1007 let Inst{5-3} = addr{2-0}; // Rn
1010 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1011 InstrItinClass itin, string opc, string asm,
1013 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1014 T1LoadStore<opA, {opB,?,?}> {
1017 let Inst{10-6} = addr{7-3}; // imm5
1018 let Inst{5-3} = addr{2-0}; // Rn
1022 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1023 class T1Misc<bits<7> opcode> : Encoding16 {
1024 let Inst{15-12} = 0b1011;
1025 let Inst{11-5} = opcode;
1028 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1029 class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
1030 InstrItinClass itin,
1031 string opc, string asm, string cstr, list<dag> pattern>
1032 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1033 let OutOperandList = oops;
1034 let InOperandList = !con(iops, (ins pred:$p));
1035 let AsmString = !strconcat(opc, "${p}", asm);
1036 let Pattern = pattern;
1037 list<Predicate> Predicates = [IsThumb2];
1038 let DecoderNamespace = "Thumb2";
1041 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1042 // input operand since by default it's a zero register. It will become an
1043 // implicit def once it's "flipped".
1045 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1047 class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
1048 InstrItinClass itin,
1049 string opc, string asm, string cstr, list<dag> pattern>
1050 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1051 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1054 let OutOperandList = oops;
1055 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1056 let AsmString = !strconcat(opc, "${s}${p}", asm);
1057 let Pattern = pattern;
1058 list<Predicate> Predicates = [IsThumb2];
1059 let DecoderNamespace = "Thumb2";
1063 class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
1064 InstrItinClass itin,
1065 string asm, string cstr, list<dag> pattern>
1066 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1067 let OutOperandList = oops;
1068 let InOperandList = iops;
1069 let AsmString = asm;
1070 let Pattern = pattern;
1071 list<Predicate> Predicates = [IsThumb2];
1072 let DecoderNamespace = "Thumb2";
1075 class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
1076 InstrItinClass itin,
1077 string asm, string cstr, list<dag> pattern>
1078 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1079 let OutOperandList = oops;
1080 let InOperandList = iops;
1081 let AsmString = asm;
1082 let Pattern = pattern;
1083 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1084 let DecoderNamespace = "Thumb";
1087 class T2I<dag oops, dag iops, InstrItinClass itin,
1088 string opc, string asm, list<dag> pattern>
1089 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1090 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1091 string opc, string asm, list<dag> pattern>
1092 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
1093 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1094 string opc, string asm, list<dag> pattern>
1095 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
1096 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1097 string opc, string asm, list<dag> pattern>
1098 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
1099 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1100 string opc, string asm, list<dag> pattern>
1101 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
1102 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1103 string opc, string asm, string cstr, list<dag> pattern>
1104 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1109 let Inst{31-25} = 0b1110100;
1111 let Inst{23} = addr{8};
1114 let Inst{20} = isLoad;
1115 let Inst{19-16} = addr{12-9};
1116 let Inst{15-12} = Rt{3-0};
1117 let Inst{11-8} = Rt2{3-0};
1118 let Inst{7-0} = addr{7-0};
1120 class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops,
1121 InstrItinClass itin, string opc, string asm, string cstr,
1123 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1129 let Inst{31-25} = 0b1110100;
1131 let Inst{23} = imm{8};
1134 let Inst{20} = isLoad;
1135 let Inst{19-16} = addr;
1136 let Inst{15-12} = Rt{3-0};
1137 let Inst{11-8} = Rt2{3-0};
1138 let Inst{7-0} = imm{7-0};
1141 class T2sI<dag oops, dag iops, InstrItinClass itin,
1142 string opc, string asm, list<dag> pattern>
1143 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1145 class T2XI<dag oops, dag iops, InstrItinClass itin,
1146 string asm, list<dag> pattern>
1147 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1148 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1149 string asm, list<dag> pattern>
1150 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1152 // Move to/from coprocessor instructions
1153 class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern>
1154 : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> {
1155 let Inst{31-28} = opc;
1158 // Two-address instructions
1159 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1160 string asm, string cstr, list<dag> pattern>
1161 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
1163 // T2Ipreldst - Thumb2 pre-indexed load / store instructions.
1164 class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre,
1166 AddrMode am, IndexMode im, InstrItinClass itin,
1167 string opc, string asm, string cstr, list<dag> pattern>
1168 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1169 let OutOperandList = oops;
1170 let InOperandList = !con(iops, (ins pred:$p));
1171 let AsmString = !strconcat(opc, "${p}", asm);
1172 let Pattern = pattern;
1173 list<Predicate> Predicates = [IsThumb2];
1174 let DecoderNamespace = "Thumb2";
1178 let Inst{31-27} = 0b11111;
1179 let Inst{26-25} = 0b00;
1180 let Inst{24} = signed;
1182 let Inst{22-21} = opcod;
1183 let Inst{20} = load;
1184 let Inst{19-16} = addr{12-9};
1185 let Inst{15-12} = Rt{3-0};
1187 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1188 let Inst{10} = pre; // The P bit.
1189 let Inst{9} = addr{8}; // Sign bit
1190 let Inst{8} = 1; // The W bit.
1191 let Inst{7-0} = addr{7-0};
1194 // T2Ipostldst - Thumb2 post-indexed load / store instructions.
1195 class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre,
1197 AddrMode am, IndexMode im, InstrItinClass itin,
1198 string opc, string asm, string cstr, list<dag> pattern>
1199 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1200 let OutOperandList = oops;
1201 let InOperandList = !con(iops, (ins pred:$p));
1202 let AsmString = !strconcat(opc, "${p}", asm);
1203 let Pattern = pattern;
1204 list<Predicate> Predicates = [IsThumb2];
1205 let DecoderNamespace = "Thumb2";
1210 let Inst{31-27} = 0b11111;
1211 let Inst{26-25} = 0b00;
1212 let Inst{24} = signed;
1214 let Inst{22-21} = opcod;
1215 let Inst{20} = load;
1216 let Inst{19-16} = Rn;
1217 let Inst{15-12} = Rt{3-0};
1219 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1220 let Inst{10} = pre; // The P bit.
1221 let Inst{9} = offset{8}; // Sign bit
1222 let Inst{8} = 1; // The W bit.
1223 let Inst{7-0} = offset{7-0};
1226 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1227 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1228 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1231 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1232 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1233 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1236 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1237 class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1238 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1241 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1242 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1243 list<Predicate> Predicates = [IsThumb2];
1246 //===----------------------------------------------------------------------===//
1248 //===----------------------------------------------------------------------===//
1249 // ARM VFP Instruction templates.
1252 // Almost all VFP instructions are predicable.
1253 class VFPI<dag oops, dag iops, AddrMode am, int sz,
1254 IndexMode im, Format f, InstrItinClass itin,
1255 string opc, string asm, string cstr, list<dag> pattern>
1256 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1258 let Inst{31-28} = p;
1259 let OutOperandList = oops;
1260 let InOperandList = !con(iops, (ins pred:$p));
1261 let AsmString = !strconcat(opc, "${p}", asm);
1262 let Pattern = pattern;
1263 let PostEncoderMethod = "VFPThumb2PostEncoder";
1264 let DecoderNamespace = "VFP";
1265 list<Predicate> Predicates = [HasVFP2];
1269 class VFPXI<dag oops, dag iops, AddrMode am, int sz,
1270 IndexMode im, Format f, InstrItinClass itin,
1271 string asm, string cstr, list<dag> pattern>
1272 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1274 let Inst{31-28} = p;
1275 let OutOperandList = oops;
1276 let InOperandList = iops;
1277 let AsmString = asm;
1278 let Pattern = pattern;
1279 let PostEncoderMethod = "VFPThumb2PostEncoder";
1280 let DecoderNamespace = "VFP";
1281 list<Predicate> Predicates = [HasVFP2];
1284 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1285 string opc, string asm, list<dag> pattern>
1286 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
1287 opc, asm, "", pattern> {
1288 let PostEncoderMethod = "VFPThumb2PostEncoder";
1291 // ARM VFP addrmode5 loads and stores
1292 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1293 InstrItinClass itin,
1294 string opc, string asm, list<dag> pattern>
1295 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1296 VFPLdStFrm, itin, opc, asm, "", pattern> {
1297 // Instruction operands.
1301 // Encode instruction operands.
1302 let Inst{23} = addr{8}; // U (add = (U == '1'))
1303 let Inst{22} = Dd{4};
1304 let Inst{19-16} = addr{12-9}; // Rn
1305 let Inst{15-12} = Dd{3-0};
1306 let Inst{7-0} = addr{7-0}; // imm8
1308 // TODO: Mark the instructions with the appropriate subtarget info.
1309 let Inst{27-24} = opcod1;
1310 let Inst{21-20} = opcod2;
1311 let Inst{11-9} = 0b101;
1312 let Inst{8} = 1; // Double precision
1314 // Loads & stores operate on both NEON and VFP pipelines.
1315 let D = VFPNeonDomain;
1318 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1319 InstrItinClass itin,
1320 string opc, string asm, list<dag> pattern>
1321 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1322 VFPLdStFrm, itin, opc, asm, "", pattern> {
1323 // Instruction operands.
1327 // Encode instruction operands.
1328 let Inst{23} = addr{8}; // U (add = (U == '1'))
1329 let Inst{22} = Sd{0};
1330 let Inst{19-16} = addr{12-9}; // Rn
1331 let Inst{15-12} = Sd{4-1};
1332 let Inst{7-0} = addr{7-0}; // imm8
1334 // TODO: Mark the instructions with the appropriate subtarget info.
1335 let Inst{27-24} = opcod1;
1336 let Inst{21-20} = opcod2;
1337 let Inst{11-9} = 0b101;
1338 let Inst{8} = 0; // Single precision
1340 // Loads & stores operate on both NEON and VFP pipelines.
1341 let D = VFPNeonDomain;
1344 // VFP Load / store multiple pseudo instructions.
1345 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1347 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1349 let OutOperandList = oops;
1350 let InOperandList = !con(iops, (ins pred:$p));
1351 let Pattern = pattern;
1352 list<Predicate> Predicates = [HasVFP2];
1355 // Load / store multiple
1356 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1357 string asm, string cstr, list<dag> pattern>
1358 : VFPXI<oops, iops, AddrMode4, 4, im,
1359 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1360 // Instruction operands.
1364 // Encode instruction operands.
1365 let Inst{19-16} = Rn;
1366 let Inst{22} = regs{12};
1367 let Inst{15-12} = regs{11-8};
1368 let Inst{7-0} = regs{7-0};
1370 // TODO: Mark the instructions with the appropriate subtarget info.
1371 let Inst{27-25} = 0b110;
1372 let Inst{11-9} = 0b101;
1373 let Inst{8} = 1; // Double precision
1376 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1377 string asm, string cstr, list<dag> pattern>
1378 : VFPXI<oops, iops, AddrMode4, 4, im,
1379 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1380 // Instruction operands.
1384 // Encode instruction operands.
1385 let Inst{19-16} = Rn;
1386 let Inst{22} = regs{8};
1387 let Inst{15-12} = regs{12-9};
1388 let Inst{7-0} = regs{7-0};
1390 // TODO: Mark the instructions with the appropriate subtarget info.
1391 let Inst{27-25} = 0b110;
1392 let Inst{11-9} = 0b101;
1393 let Inst{8} = 0; // Single precision
1396 // Double precision, unary
1397 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1398 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1399 string asm, list<dag> pattern>
1400 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1401 // Instruction operands.
1405 // Encode instruction operands.
1406 let Inst{3-0} = Dm{3-0};
1407 let Inst{5} = Dm{4};
1408 let Inst{15-12} = Dd{3-0};
1409 let Inst{22} = Dd{4};
1411 let Inst{27-23} = opcod1;
1412 let Inst{21-20} = opcod2;
1413 let Inst{19-16} = opcod3;
1414 let Inst{11-9} = 0b101;
1415 let Inst{8} = 1; // Double precision
1416 let Inst{7-6} = opcod4;
1417 let Inst{4} = opcod5;
1420 // Double precision, binary
1421 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1422 dag iops, InstrItinClass itin, string opc, string asm,
1424 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1425 // Instruction operands.
1430 // Encode instruction operands.
1431 let Inst{3-0} = Dm{3-0};
1432 let Inst{5} = Dm{4};
1433 let Inst{19-16} = Dn{3-0};
1434 let Inst{7} = Dn{4};
1435 let Inst{15-12} = Dd{3-0};
1436 let Inst{22} = Dd{4};
1438 let Inst{27-23} = opcod1;
1439 let Inst{21-20} = opcod2;
1440 let Inst{11-9} = 0b101;
1441 let Inst{8} = 1; // Double precision
1446 // Single precision, unary
1447 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1448 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1449 string asm, list<dag> pattern>
1450 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1451 // Instruction operands.
1455 // Encode instruction operands.
1456 let Inst{3-0} = Sm{4-1};
1457 let Inst{5} = Sm{0};
1458 let Inst{15-12} = Sd{4-1};
1459 let Inst{22} = Sd{0};
1461 let Inst{27-23} = opcod1;
1462 let Inst{21-20} = opcod2;
1463 let Inst{19-16} = opcod3;
1464 let Inst{11-9} = 0b101;
1465 let Inst{8} = 0; // Single precision
1466 let Inst{7-6} = opcod4;
1467 let Inst{4} = opcod5;
1470 // Single precision unary, if no NEON. Same as ASuI except not available if
1472 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1473 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1474 string asm, list<dag> pattern>
1475 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1477 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1480 // Single precision, binary
1481 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1482 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1483 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1484 // Instruction operands.
1489 // Encode instruction operands.
1490 let Inst{3-0} = Sm{4-1};
1491 let Inst{5} = Sm{0};
1492 let Inst{19-16} = Sn{4-1};
1493 let Inst{7} = Sn{0};
1494 let Inst{15-12} = Sd{4-1};
1495 let Inst{22} = Sd{0};
1497 let Inst{27-23} = opcod1;
1498 let Inst{21-20} = opcod2;
1499 let Inst{11-9} = 0b101;
1500 let Inst{8} = 0; // Single precision
1505 // Single precision binary, if no NEON. Same as ASbI except not available if
1507 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1508 dag iops, InstrItinClass itin, string opc, string asm,
1510 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1511 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1513 // Instruction operands.
1518 // Encode instruction operands.
1519 let Inst{3-0} = Sm{4-1};
1520 let Inst{5} = Sm{0};
1521 let Inst{19-16} = Sn{4-1};
1522 let Inst{7} = Sn{0};
1523 let Inst{15-12} = Sd{4-1};
1524 let Inst{22} = Sd{0};
1527 // VFP conversion instructions
1528 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1529 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1531 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1532 let Inst{27-23} = opcod1;
1533 let Inst{21-20} = opcod2;
1534 let Inst{19-16} = opcod3;
1535 let Inst{11-8} = opcod4;
1540 // VFP conversion between floating-point and fixed-point
1541 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1542 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1544 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1545 // size (fixed-point number): sx == 0 ? 16 : 32
1546 let Inst{7} = op5; // sx
1549 // VFP conversion instructions, if no NEON
1550 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1551 dag oops, dag iops, InstrItinClass itin,
1552 string opc, string asm, list<dag> pattern>
1553 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1555 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1558 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1559 InstrItinClass itin,
1560 string opc, string asm, list<dag> pattern>
1561 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1562 let Inst{27-20} = opcod1;
1563 let Inst{11-8} = opcod2;
1567 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1568 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1569 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1571 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1572 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1573 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1575 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1576 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1577 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1579 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1580 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1581 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1583 //===----------------------------------------------------------------------===//
1585 //===----------------------------------------------------------------------===//
1586 // ARM NEON Instruction templates.
1589 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1590 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1592 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1593 let OutOperandList = oops;
1594 let InOperandList = !con(iops, (ins pred:$p));
1595 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1596 let Pattern = pattern;
1597 list<Predicate> Predicates = [HasNEON];
1598 let DecoderNamespace = "NEON";
1601 // Same as NeonI except it does not have a "data type" specifier.
1602 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1603 InstrItinClass itin, string opc, string asm, string cstr,
1605 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1606 let OutOperandList = oops;
1607 let InOperandList = !con(iops, (ins pred:$p));
1608 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1609 let Pattern = pattern;
1610 list<Predicate> Predicates = [HasNEON];
1611 let DecoderNamespace = "NEON";
1614 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1615 dag oops, dag iops, InstrItinClass itin,
1616 string opc, string dt, string asm, string cstr, list<dag> pattern>
1617 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1619 let Inst{31-24} = 0b11110100;
1620 let Inst{23} = op23;
1621 let Inst{21-20} = op21_20;
1622 let Inst{11-8} = op11_8;
1623 let Inst{7-4} = op7_4;
1625 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1626 let DecoderNamespace = "NEONLoadStore";
1632 let Inst{22} = Vd{4};
1633 let Inst{15-12} = Vd{3-0};
1634 let Inst{19-16} = Rn{3-0};
1635 let Inst{3-0} = Rm{3-0};
1638 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1639 dag oops, dag iops, InstrItinClass itin,
1640 string opc, string dt, string asm, string cstr, list<dag> pattern>
1641 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1642 dt, asm, cstr, pattern> {
1646 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1647 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1649 let OutOperandList = oops;
1650 let InOperandList = !con(iops, (ins pred:$p));
1651 list<Predicate> Predicates = [HasNEON];
1654 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1656 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1658 let OutOperandList = oops;
1659 let InOperandList = !con(iops, (ins pred:$p));
1660 let Pattern = pattern;
1661 list<Predicate> Predicates = [HasNEON];
1664 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1665 string opc, string dt, string asm, string cstr, list<dag> pattern>
1666 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1668 let Inst{31-25} = 0b1111001;
1669 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1670 let DecoderNamespace = "NEONData";
1673 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1674 string opc, string asm, string cstr, list<dag> pattern>
1675 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1677 let Inst{31-25} = 0b1111001;
1678 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1679 let DecoderNamespace = "NEONData";
1682 // NEON "one register and a modified immediate" format.
1683 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1685 dag oops, dag iops, InstrItinClass itin,
1686 string opc, string dt, string asm, string cstr,
1688 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1689 let Inst{23} = op23;
1690 let Inst{21-19} = op21_19;
1691 let Inst{11-8} = op11_8;
1697 // Instruction operands.
1701 let Inst{15-12} = Vd{3-0};
1702 let Inst{22} = Vd{4};
1703 let Inst{24} = SIMM{7};
1704 let Inst{18-16} = SIMM{6-4};
1705 let Inst{3-0} = SIMM{3-0};
1706 let DecoderMethod = "DecodeNEONModImmInstruction";
1709 // NEON 2 vector register format.
1710 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1711 bits<5> op11_7, bit op6, bit op4,
1712 dag oops, dag iops, InstrItinClass itin,
1713 string opc, string dt, string asm, string cstr, list<dag> pattern>
1714 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1715 let Inst{24-23} = op24_23;
1716 let Inst{21-20} = op21_20;
1717 let Inst{19-18} = op19_18;
1718 let Inst{17-16} = op17_16;
1719 let Inst{11-7} = op11_7;
1723 // Instruction operands.
1727 let Inst{15-12} = Vd{3-0};
1728 let Inst{22} = Vd{4};
1729 let Inst{3-0} = Vm{3-0};
1730 let Inst{5} = Vm{4};
1733 // Same as N2V except it doesn't have a datatype suffix.
1734 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1735 bits<5> op11_7, bit op6, bit op4,
1736 dag oops, dag iops, InstrItinClass itin,
1737 string opc, string asm, string cstr, list<dag> pattern>
1738 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1739 let Inst{24-23} = op24_23;
1740 let Inst{21-20} = op21_20;
1741 let Inst{19-18} = op19_18;
1742 let Inst{17-16} = op17_16;
1743 let Inst{11-7} = op11_7;
1747 // Instruction operands.
1751 let Inst{15-12} = Vd{3-0};
1752 let Inst{22} = Vd{4};
1753 let Inst{3-0} = Vm{3-0};
1754 let Inst{5} = Vm{4};
1757 // NEON 2 vector register with immediate.
1758 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1759 dag oops, dag iops, Format f, InstrItinClass itin,
1760 string opc, string dt, string asm, string cstr, list<dag> pattern>
1761 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1762 let Inst{24} = op24;
1763 let Inst{23} = op23;
1764 let Inst{11-8} = op11_8;
1769 // Instruction operands.
1774 let Inst{15-12} = Vd{3-0};
1775 let Inst{22} = Vd{4};
1776 let Inst{3-0} = Vm{3-0};
1777 let Inst{5} = Vm{4};
1778 let Inst{21-16} = SIMM{5-0};
1781 // NEON 3 vector register format.
1783 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1784 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1785 string opc, string dt, string asm, string cstr,
1787 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1788 let Inst{24} = op24;
1789 let Inst{23} = op23;
1790 let Inst{21-20} = op21_20;
1791 let Inst{11-8} = op11_8;
1796 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1797 dag oops, dag iops, Format f, InstrItinClass itin,
1798 string opc, string dt, string asm, string cstr, list<dag> pattern>
1799 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1800 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1802 // Instruction operands.
1807 let Inst{15-12} = Vd{3-0};
1808 let Inst{22} = Vd{4};
1809 let Inst{19-16} = Vn{3-0};
1810 let Inst{7} = Vn{4};
1811 let Inst{3-0} = Vm{3-0};
1812 let Inst{5} = Vm{4};
1815 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1816 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1817 string opc, string dt, string asm, string cstr,
1819 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1820 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1822 // Instruction operands.
1828 let Inst{15-12} = Vd{3-0};
1829 let Inst{22} = Vd{4};
1830 let Inst{19-16} = Vn{3-0};
1831 let Inst{7} = Vn{4};
1832 let Inst{3-0} = Vm{3-0};
1836 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1837 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1838 string opc, string dt, string asm, string cstr,
1840 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1841 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1843 // Instruction operands.
1849 let Inst{15-12} = Vd{3-0};
1850 let Inst{22} = Vd{4};
1851 let Inst{19-16} = Vn{3-0};
1852 let Inst{7} = Vn{4};
1853 let Inst{2-0} = Vm{2-0};
1854 let Inst{5} = lane{1};
1855 let Inst{3} = lane{0};
1858 // Same as N3V except it doesn't have a data type suffix.
1859 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1861 dag oops, dag iops, Format f, InstrItinClass itin,
1862 string opc, string asm, string cstr, list<dag> pattern>
1863 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1864 let Inst{24} = op24;
1865 let Inst{23} = op23;
1866 let Inst{21-20} = op21_20;
1867 let Inst{11-8} = op11_8;
1871 // Instruction operands.
1876 let Inst{15-12} = Vd{3-0};
1877 let Inst{22} = Vd{4};
1878 let Inst{19-16} = Vn{3-0};
1879 let Inst{7} = Vn{4};
1880 let Inst{3-0} = Vm{3-0};
1881 let Inst{5} = Vm{4};
1884 // NEON VMOVs between scalar and core registers.
1885 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1886 dag oops, dag iops, Format f, InstrItinClass itin,
1887 string opc, string dt, string asm, list<dag> pattern>
1888 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
1890 let Inst{27-20} = opcod1;
1891 let Inst{11-8} = opcod2;
1892 let Inst{6-5} = opcod3;
1894 // A8.6.303, A8.6.328, A8.6.329
1895 let Inst{3-0} = 0b0000;
1897 let OutOperandList = oops;
1898 let InOperandList = !con(iops, (ins pred:$p));
1899 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1900 let Pattern = pattern;
1901 list<Predicate> Predicates = [HasNEON];
1903 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1904 let DecoderNamespace = "NEONDup";
1911 let Inst{31-28} = p{3-0};
1913 let Inst{19-16} = V{3-0};
1914 let Inst{15-12} = R{3-0};
1916 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1917 dag oops, dag iops, InstrItinClass itin,
1918 string opc, string dt, string asm, list<dag> pattern>
1919 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1920 opc, dt, asm, pattern>;
1921 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1922 dag oops, dag iops, InstrItinClass itin,
1923 string opc, string dt, string asm, list<dag> pattern>
1924 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1925 opc, dt, asm, pattern>;
1926 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1927 dag oops, dag iops, InstrItinClass itin,
1928 string opc, string dt, string asm, list<dag> pattern>
1929 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1930 opc, dt, asm, pattern>;
1932 // Vector Duplicate Lane (from scalar to all elements)
1933 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1934 InstrItinClass itin, string opc, string dt, string asm,
1936 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1937 let Inst{24-23} = 0b11;
1938 let Inst{21-20} = 0b11;
1939 let Inst{19-16} = op19_16;
1940 let Inst{11-7} = 0b11000;
1948 let Inst{22} = Vd{4};
1949 let Inst{15-12} = Vd{3-0};
1950 let Inst{5} = Vm{4};
1951 let Inst{3-0} = Vm{3-0};
1954 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1955 // for single-precision FP.
1956 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1957 list<Predicate> Predicates = [HasNEON,UseNEONForFP];