1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // the instruction has a Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 class AddrMode<bits<4> val> {
91 def AddrModeNone : AddrMode<0>;
92 def AddrMode1 : AddrMode<1>;
93 def AddrMode2 : AddrMode<2>;
94 def AddrMode3 : AddrMode<3>;
95 def AddrMode4 : AddrMode<4>;
96 def AddrMode5 : AddrMode<5>;
97 def AddrMode6 : AddrMode<6>;
98 def AddrModeT1_1 : AddrMode<7>;
99 def AddrModeT1_2 : AddrMode<8>;
100 def AddrModeT1_4 : AddrMode<9>;
101 def AddrModeT1_s : AddrMode<10>;
102 def AddrModeT2_i12 : AddrMode<11>;
103 def AddrModeT2_i8 : AddrMode<12>;
104 def AddrModeT2_so : AddrMode<13>;
105 def AddrModeT2_pc : AddrMode<14>;
106 def AddrModeT2_i8s4 : AddrMode<15>;
109 class SizeFlagVal<bits<3> val> {
112 def SizeInvalid : SizeFlagVal<0>; // Unset.
113 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
114 def Size8Bytes : SizeFlagVal<2>;
115 def Size4Bytes : SizeFlagVal<3>;
116 def Size2Bytes : SizeFlagVal<4>;
118 // Load / store index mode.
119 class IndexMode<bits<2> val> {
122 def IndexModeNone : IndexMode<0>;
123 def IndexModePre : IndexMode<1>;
124 def IndexModePost : IndexMode<2>;
125 def IndexModeUpd : IndexMode<3>;
127 // Instruction execution domain.
128 class Domain<bits<2> val> {
131 def GenericDomain : Domain<0>;
132 def VFPDomain : Domain<1>; // Instructions in VFP domain only
133 def NeonDomain : Domain<2>; // Instructions in Neon domain only
134 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
136 //===----------------------------------------------------------------------===//
138 // ARM special operands.
141 def CondCodeOperand : AsmOperandClass {
142 let Name = "CondCode";
143 let SuperClasses = [];
146 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
147 // register whose default is 0 (no register).
148 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
149 (ops (i32 14), (i32 zero_reg))> {
150 let PrintMethod = "printPredicateOperand";
151 let ParserMatchClass = CondCodeOperand;
154 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
155 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
156 let PrintMethod = "printSBitModifierOperand";
159 // Same as cc_out except it defaults to setting CPSR.
160 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
161 let PrintMethod = "printSBitModifierOperand";
164 // ARM special operands for disassembly only.
167 def cps_opt : Operand<i32> {
168 let PrintMethod = "printCPSOptionOperand";
171 def msr_mask : Operand<i32> {
172 let PrintMethod = "printMSRMaskOperand";
175 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
176 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
177 def neg_zero : Operand<i32> {
178 let PrintMethod = "printNegZeroOperand";
181 //===----------------------------------------------------------------------===//
183 // ARM Instruction templates.
186 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
187 Format f, Domain d, string cstr, InstrItinClass itin>
189 let Namespace = "ARM";
194 bits<2> IndexModeBits = IM.Value;
196 bits<6> Form = F.Value;
198 bit isUnaryDataProc = 0;
199 bit canXformTo16Bit = 0;
201 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
202 let TSFlags{3-0} = AM.Value;
203 let TSFlags{6-4} = SZ.Value;
204 let TSFlags{8-7} = IndexModeBits;
205 let TSFlags{14-9} = Form;
206 let TSFlags{15} = isUnaryDataProc;
207 let TSFlags{16} = canXformTo16Bit;
208 let TSFlags{18-17} = D.Value;
210 let Constraints = cstr;
211 let Itinerary = itin;
218 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
219 Format f, Domain d, string cstr, InstrItinClass itin>
220 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
222 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
223 // on by adding flavors to specific instructions.
224 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
225 Format f, Domain d, string cstr, InstrItinClass itin>
226 : InstTemplate<am, sz, im, f, d, cstr, itin>;
228 class PseudoInst<dag oops, dag iops, InstrItinClass itin,
229 string asm, list<dag> pattern>
230 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
232 let OutOperandList = oops;
233 let InOperandList = iops;
235 let Pattern = pattern;
238 // Almost all ARM instructions are predicable.
239 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
240 IndexMode im, Format f, InstrItinClass itin,
241 string opc, string asm, string cstr,
243 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
244 let OutOperandList = oops;
245 let InOperandList = !con(iops, (ins pred:$p));
246 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
247 let Pattern = pattern;
248 list<Predicate> Predicates = [IsARM];
251 // A few are not predicable
252 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
253 IndexMode im, Format f, InstrItinClass itin,
254 string opc, string asm, string cstr,
256 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
257 let OutOperandList = oops;
258 let InOperandList = iops;
259 let AsmString = !strconcat(opc, asm);
260 let Pattern = pattern;
261 let isPredicable = 0;
262 list<Predicate> Predicates = [IsARM];
265 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
266 // operand since by default it's a zero register. It will become an implicit def
267 // once it's "flipped".
268 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
269 IndexMode im, Format f, InstrItinClass itin,
270 string opc, string asm, string cstr,
272 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
273 let OutOperandList = oops;
274 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
275 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
276 let Pattern = pattern;
277 list<Predicate> Predicates = [IsARM];
281 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
282 IndexMode im, Format f, InstrItinClass itin,
283 string asm, string cstr, list<dag> pattern>
284 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
285 let OutOperandList = oops;
286 let InOperandList = iops;
288 let Pattern = pattern;
289 list<Predicate> Predicates = [IsARM];
292 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
293 string opc, string asm, list<dag> pattern>
294 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
295 opc, asm, "", pattern>;
296 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
297 string opc, string asm, list<dag> pattern>
298 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
299 opc, asm, "", pattern>;
300 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
301 string asm, list<dag> pattern>
302 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
304 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
305 string opc, string asm, list<dag> pattern>
306 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
307 opc, asm, "", pattern>;
309 // Ctrl flow instructions
310 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
311 string opc, string asm, list<dag> pattern>
312 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
313 opc, asm, "", pattern> {
314 let Inst{27-24} = opcod;
316 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
317 string asm, list<dag> pattern>
318 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
320 let Inst{27-24} = opcod;
322 class ABXIx2<dag oops, dag iops, InstrItinClass itin,
323 string asm, list<dag> pattern>
324 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, Pseudo, itin,
327 // BR_JT instructions
328 class JTI<dag oops, dag iops, InstrItinClass itin,
329 string asm, list<dag> pattern>
330 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
333 // Atomic load/store instructions
334 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
335 string opc, string asm, list<dag> pattern>
336 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
337 opc, asm, "", pattern> {
338 let Inst{27-23} = 0b00011;
339 let Inst{22-21} = opcod;
341 let Inst{11-0} = 0b111110011111;
343 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
344 string opc, string asm, list<dag> pattern>
345 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
346 opc, asm, "", pattern> {
347 let Inst{27-23} = 0b00011;
348 let Inst{22-21} = opcod;
350 let Inst{11-4} = 0b11111001;
353 // addrmode1 instructions
354 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
355 string opc, string asm, list<dag> pattern>
356 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
357 opc, asm, "", pattern> {
358 let Inst{24-21} = opcod;
359 let Inst{27-26} = 0b00;
361 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
362 string opc, string asm, list<dag> pattern>
363 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
364 opc, asm, "", pattern> {
365 let Inst{24-21} = opcod;
366 let Inst{27-26} = 0b00;
368 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
369 string asm, list<dag> pattern>
370 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
372 let Inst{24-21} = opcod;
373 let Inst{27-26} = 0b00;
375 class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
376 string opc, string asm, list<dag> pattern>
377 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
378 opc, asm, "", pattern>;
381 // addrmode2 loads and stores
382 class AI2<dag oops, dag iops, Format f, InstrItinClass itin,
383 string opc, string asm, list<dag> pattern>
384 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
385 opc, asm, "", pattern> {
386 let Inst{27-26} = 0b01;
390 class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
391 string opc, string asm, list<dag> pattern>
392 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
393 opc, asm, "", pattern> {
394 let Inst{20} = 1; // L bit
395 let Inst{21} = 0; // W bit
396 let Inst{22} = 0; // B bit
397 let Inst{24} = 1; // P bit
398 let Inst{27-26} = 0b01;
400 class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
401 string asm, list<dag> pattern>
402 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
404 let Inst{20} = 1; // L bit
405 let Inst{21} = 0; // W bit
406 let Inst{22} = 0; // B bit
407 let Inst{24} = 1; // P bit
408 let Inst{27-26} = 0b01;
410 class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
411 string opc, string asm, list<dag> pattern>
412 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
413 opc, asm, "", pattern> {
414 let Inst{20} = 1; // L bit
415 let Inst{21} = 0; // W bit
416 let Inst{22} = 1; // B bit
417 let Inst{24} = 1; // P bit
418 let Inst{27-26} = 0b01;
420 class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
421 string asm, list<dag> pattern>
422 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
424 let Inst{20} = 1; // L bit
425 let Inst{21} = 0; // W bit
426 let Inst{22} = 1; // B bit
427 let Inst{24} = 1; // P bit
428 let Inst{27-26} = 0b01;
432 class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
433 string opc, string asm, list<dag> pattern>
434 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
435 opc, asm, "", pattern> {
436 let Inst{20} = 0; // L bit
437 let Inst{21} = 0; // W bit
438 let Inst{22} = 0; // B bit
439 let Inst{24} = 1; // P bit
440 let Inst{27-26} = 0b01;
442 class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
443 string asm, list<dag> pattern>
444 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
446 let Inst{20} = 0; // L bit
447 let Inst{21} = 0; // W bit
448 let Inst{22} = 0; // B bit
449 let Inst{24} = 1; // P bit
450 let Inst{27-26} = 0b01;
452 class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
453 string opc, string asm, list<dag> pattern>
454 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
455 opc, asm, "", pattern> {
456 let Inst{20} = 0; // L bit
457 let Inst{21} = 0; // W bit
458 let Inst{22} = 1; // B bit
459 let Inst{24} = 1; // P bit
460 let Inst{27-26} = 0b01;
462 class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
463 string asm, list<dag> pattern>
464 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
466 let Inst{20} = 0; // L bit
467 let Inst{21} = 0; // W bit
468 let Inst{22} = 1; // B bit
469 let Inst{24} = 1; // P bit
470 let Inst{27-26} = 0b01;
474 class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
475 string opc, string asm, string cstr, list<dag> pattern>
476 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
477 opc, asm, cstr, pattern> {
478 let Inst{20} = 1; // L bit
479 let Inst{21} = 1; // W bit
480 let Inst{22} = 0; // B bit
481 let Inst{24} = 1; // P bit
482 let Inst{27-26} = 0b01;
484 class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
485 string opc, string asm, string cstr, list<dag> pattern>
486 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
487 opc, asm, cstr, pattern> {
488 let Inst{20} = 1; // L bit
489 let Inst{21} = 1; // W bit
490 let Inst{22} = 1; // B bit
491 let Inst{24} = 1; // P bit
492 let Inst{27-26} = 0b01;
495 // Pre-indexed stores
496 class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
497 string opc, string asm, string cstr, list<dag> pattern>
498 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
499 opc, asm, cstr, pattern> {
500 let Inst{20} = 0; // L bit
501 let Inst{21} = 1; // W bit
502 let Inst{22} = 0; // B bit
503 let Inst{24} = 1; // P bit
504 let Inst{27-26} = 0b01;
506 class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
507 string opc, string asm, string cstr, list<dag> pattern>
508 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
509 opc, asm, cstr, pattern> {
510 let Inst{20} = 0; // L bit
511 let Inst{21} = 1; // W bit
512 let Inst{22} = 1; // B bit
513 let Inst{24} = 1; // P bit
514 let Inst{27-26} = 0b01;
517 // Post-indexed loads
518 class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
519 string opc, string asm, string cstr, list<dag> pattern>
520 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
521 opc, asm, cstr,pattern> {
522 let Inst{20} = 1; // L bit
523 let Inst{21} = 0; // W bit
524 let Inst{22} = 0; // B bit
525 let Inst{24} = 0; // P bit
526 let Inst{27-26} = 0b01;
528 class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
529 string opc, string asm, string cstr, list<dag> pattern>
530 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
531 opc, asm, cstr,pattern> {
532 let Inst{20} = 1; // L bit
533 let Inst{21} = 0; // W bit
534 let Inst{22} = 1; // B bit
535 let Inst{24} = 0; // P bit
536 let Inst{27-26} = 0b01;
539 // Post-indexed stores
540 class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
541 string opc, string asm, string cstr, list<dag> pattern>
542 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
543 opc, asm, cstr,pattern> {
544 let Inst{20} = 0; // L bit
545 let Inst{21} = 0; // W bit
546 let Inst{22} = 0; // B bit
547 let Inst{24} = 0; // P bit
548 let Inst{27-26} = 0b01;
550 class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
551 string opc, string asm, string cstr, list<dag> pattern>
552 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
553 opc, asm, cstr,pattern> {
554 let Inst{20} = 0; // L bit
555 let Inst{21} = 0; // W bit
556 let Inst{22} = 1; // B bit
557 let Inst{24} = 0; // P bit
558 let Inst{27-26} = 0b01;
561 // addrmode3 instructions
562 class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
563 string opc, string asm, list<dag> pattern>
564 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
565 opc, asm, "", pattern>;
566 class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
567 string asm, list<dag> pattern>
568 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
572 class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
573 string opc, string asm, list<dag> pattern>
574 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
575 opc, asm, "", pattern> {
577 let Inst{5} = 1; // H bit
578 let Inst{6} = 0; // S bit
580 let Inst{20} = 1; // L bit
581 let Inst{21} = 0; // W bit
582 let Inst{24} = 1; // P bit
583 let Inst{27-25} = 0b000;
585 class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
586 string asm, list<dag> pattern>
587 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
590 let Inst{5} = 1; // H bit
591 let Inst{6} = 0; // S bit
593 let Inst{20} = 1; // L bit
594 let Inst{21} = 0; // W bit
595 let Inst{24} = 1; // P bit
597 class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
598 string opc, string asm, list<dag> pattern>
599 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
600 opc, asm, "", pattern> {
602 let Inst{5} = 1; // H bit
603 let Inst{6} = 1; // S bit
605 let Inst{20} = 1; // L bit
606 let Inst{21} = 0; // W bit
607 let Inst{24} = 1; // P bit
608 let Inst{27-25} = 0b000;
610 class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
611 string asm, list<dag> pattern>
612 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
615 let Inst{5} = 1; // H bit
616 let Inst{6} = 1; // S bit
618 let Inst{20} = 1; // L bit
619 let Inst{21} = 0; // W bit
620 let Inst{24} = 1; // P bit
622 class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
623 string opc, string asm, list<dag> pattern>
624 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
625 opc, asm, "", pattern> {
627 let Inst{5} = 0; // H bit
628 let Inst{6} = 1; // S bit
630 let Inst{20} = 1; // L bit
631 let Inst{21} = 0; // W bit
632 let Inst{24} = 1; // P bit
633 let Inst{27-25} = 0b000;
635 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
636 string asm, list<dag> pattern>
637 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
640 let Inst{5} = 0; // H bit
641 let Inst{6} = 1; // S bit
643 let Inst{20} = 1; // L bit
644 let Inst{21} = 0; // W bit
645 let Inst{24} = 1; // P bit
647 class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
648 string opc, string asm, list<dag> pattern>
649 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
650 opc, asm, "", pattern> {
652 let Inst{5} = 0; // H bit
653 let Inst{6} = 1; // S bit
655 let Inst{20} = 0; // L bit
656 let Inst{21} = 0; // W bit
657 let Inst{24} = 1; // P bit
658 let Inst{27-25} = 0b000;
662 class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
663 string opc, string asm, list<dag> pattern>
664 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
665 opc, asm, "", pattern> {
667 let Inst{5} = 1; // H bit
668 let Inst{6} = 0; // S bit
670 let Inst{20} = 0; // L bit
671 let Inst{21} = 0; // W bit
672 let Inst{24} = 1; // P bit
673 let Inst{27-25} = 0b000;
675 class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
676 string asm, list<dag> pattern>
677 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
680 let Inst{5} = 1; // H bit
681 let Inst{6} = 0; // S bit
683 let Inst{20} = 0; // L bit
684 let Inst{21} = 0; // W bit
685 let Inst{24} = 1; // P bit
687 class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
688 string opc, string asm, list<dag> pattern>
689 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
690 opc, asm, "", pattern> {
692 let Inst{5} = 1; // H bit
693 let Inst{6} = 1; // S bit
695 let Inst{20} = 0; // L bit
696 let Inst{21} = 0; // W bit
697 let Inst{24} = 1; // P bit
698 let Inst{27-25} = 0b000;
702 class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
703 string opc, string asm, string cstr, list<dag> pattern>
704 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
705 opc, asm, cstr, pattern> {
707 let Inst{5} = 1; // H bit
708 let Inst{6} = 0; // S bit
710 let Inst{20} = 1; // L bit
711 let Inst{21} = 1; // W bit
712 let Inst{24} = 1; // P bit
713 let Inst{27-25} = 0b000;
715 class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
716 string opc, string asm, string cstr, list<dag> pattern>
717 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
718 opc, asm, cstr, pattern> {
720 let Inst{5} = 1; // H bit
721 let Inst{6} = 1; // S bit
723 let Inst{20} = 1; // L bit
724 let Inst{21} = 1; // W bit
725 let Inst{24} = 1; // P bit
726 let Inst{27-25} = 0b000;
728 class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
729 string opc, string asm, string cstr, list<dag> pattern>
730 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
731 opc, asm, cstr, pattern> {
733 let Inst{5} = 0; // H bit
734 let Inst{6} = 1; // S bit
736 let Inst{20} = 1; // L bit
737 let Inst{21} = 1; // W bit
738 let Inst{24} = 1; // P bit
739 let Inst{27-25} = 0b000;
741 class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin,
742 string opc, string asm, string cstr, list<dag> pattern>
743 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
744 opc, asm, cstr, pattern> {
746 let Inst{5} = 0; // H bit
747 let Inst{6} = 1; // S bit
749 let Inst{20} = 0; // L bit
750 let Inst{21} = 1; // W bit
751 let Inst{24} = 1; // P bit
752 let Inst{27-25} = 0b000;
756 // Pre-indexed stores
757 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
758 string opc, string asm, string cstr, list<dag> pattern>
759 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
760 opc, asm, cstr, pattern> {
762 let Inst{5} = 1; // H bit
763 let Inst{6} = 0; // S bit
765 let Inst{20} = 0; // L bit
766 let Inst{21} = 1; // W bit
767 let Inst{24} = 1; // P bit
768 let Inst{27-25} = 0b000;
770 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
771 string opc, string asm, string cstr, list<dag> pattern>
772 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
773 opc, asm, cstr, pattern> {
775 let Inst{5} = 1; // H bit
776 let Inst{6} = 1; // S bit
778 let Inst{20} = 0; // L bit
779 let Inst{21} = 1; // W bit
780 let Inst{24} = 1; // P bit
781 let Inst{27-25} = 0b000;
784 // Post-indexed loads
785 class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
786 string opc, string asm, string cstr, list<dag> pattern>
787 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
788 opc, asm, cstr,pattern> {
790 let Inst{5} = 1; // H bit
791 let Inst{6} = 0; // S bit
793 let Inst{20} = 1; // L bit
794 let Inst{21} = 0; // W bit
795 let Inst{24} = 0; // P bit
796 let Inst{27-25} = 0b000;
798 class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
799 string opc, string asm, string cstr, list<dag> pattern>
800 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
801 opc, asm, cstr,pattern> {
803 let Inst{5} = 1; // H bit
804 let Inst{6} = 1; // S bit
806 let Inst{20} = 1; // L bit
807 let Inst{21} = 0; // W bit
808 let Inst{24} = 0; // P bit
809 let Inst{27-25} = 0b000;
811 class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
812 string opc, string asm, string cstr, list<dag> pattern>
813 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
814 opc, asm, cstr,pattern> {
816 let Inst{5} = 0; // H bit
817 let Inst{6} = 1; // S bit
819 let Inst{20} = 1; // L bit
820 let Inst{21} = 0; // W bit
821 let Inst{24} = 0; // P bit
822 let Inst{27-25} = 0b000;
824 class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin,
825 string opc, string asm, string cstr, list<dag> pattern>
826 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
827 opc, asm, cstr, pattern> {
829 let Inst{5} = 0; // H bit
830 let Inst{6} = 1; // S bit
832 let Inst{20} = 0; // L bit
833 let Inst{21} = 0; // W bit
834 let Inst{24} = 0; // P bit
835 let Inst{27-25} = 0b000;
838 // Post-indexed stores
839 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
840 string opc, string asm, string cstr, list<dag> pattern>
841 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
842 opc, asm, cstr,pattern> {
844 let Inst{5} = 1; // H bit
845 let Inst{6} = 0; // S bit
847 let Inst{20} = 0; // L bit
848 let Inst{21} = 0; // W bit
849 let Inst{24} = 0; // P bit
850 let Inst{27-25} = 0b000;
852 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
853 string opc, string asm, string cstr, list<dag> pattern>
854 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
855 opc, asm, cstr, pattern> {
857 let Inst{5} = 1; // H bit
858 let Inst{6} = 1; // S bit
860 let Inst{20} = 0; // L bit
861 let Inst{21} = 0; // W bit
862 let Inst{24} = 0; // P bit
863 let Inst{27-25} = 0b000;
866 // addrmode4 instructions
867 class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
868 string asm, string cstr, list<dag> pattern>
869 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
870 asm, cstr, pattern> {
871 let Inst{20} = 1; // L bit
872 let Inst{22} = 0; // S bit
873 let Inst{27-25} = 0b100;
875 class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
876 string asm, string cstr, list<dag> pattern>
877 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
878 asm, cstr, pattern> {
879 let Inst{20} = 0; // L bit
880 let Inst{22} = 0; // S bit
881 let Inst{27-25} = 0b100;
884 // Unsigned multiply, multiply-accumulate instructions.
885 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
886 string opc, string asm, list<dag> pattern>
887 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
888 opc, asm, "", pattern> {
889 let Inst{7-4} = 0b1001;
890 let Inst{20} = 0; // S bit
891 let Inst{27-21} = opcod;
893 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
894 string opc, string asm, list<dag> pattern>
895 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
896 opc, asm, "", pattern> {
897 let Inst{7-4} = 0b1001;
898 let Inst{27-21} = opcod;
901 // Most significant word multiply
902 class AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
903 string opc, string asm, list<dag> pattern>
904 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
905 opc, asm, "", pattern> {
906 let Inst{7-4} = 0b1001;
908 let Inst{27-21} = opcod;
911 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
912 class AMulxyI<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
913 string opc, string asm, list<dag> pattern>
914 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
915 opc, asm, "", pattern> {
919 let Inst{27-21} = opcod;
922 // Extend instructions.
923 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
924 string opc, string asm, list<dag> pattern>
925 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
926 opc, asm, "", pattern> {
927 let Inst{7-4} = 0b0111;
928 let Inst{27-20} = opcod;
931 // Misc Arithmetic instructions.
932 class AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
933 string opc, string asm, list<dag> pattern>
934 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
935 opc, asm, "", pattern> {
936 let Inst{27-20} = opcod;
939 //===----------------------------------------------------------------------===//
941 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
942 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
943 list<Predicate> Predicates = [IsARM];
945 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
946 list<Predicate> Predicates = [IsARM, HasV5TE];
948 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
949 list<Predicate> Predicates = [IsARM, HasV6];
952 //===----------------------------------------------------------------------===//
954 // Thumb Instruction Format Definitions.
957 // TI - Thumb instruction.
959 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
960 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
961 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
962 let OutOperandList = oops;
963 let InOperandList = iops;
965 let Pattern = pattern;
966 list<Predicate> Predicates = [IsThumb];
969 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
970 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
972 // Two-address instructions
973 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
975 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
978 // tBL, tBX 32-bit instructions
979 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
980 dag oops, dag iops, InstrItinClass itin, string asm,
982 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
984 let Inst{31-27} = opcod1;
985 let Inst{15-14} = opcod2;
986 let Inst{12} = opcod3;
989 // BR_JT instructions
990 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
992 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
995 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
996 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
997 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
998 let OutOperandList = oops;
999 let InOperandList = iops;
1000 let AsmString = asm;
1001 let Pattern = pattern;
1002 list<Predicate> Predicates = [IsThumb1Only];
1005 class T1I<dag oops, dag iops, InstrItinClass itin,
1006 string asm, list<dag> pattern>
1007 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
1008 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
1009 string asm, list<dag> pattern>
1010 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1011 class T1JTI<dag oops, dag iops, InstrItinClass itin,
1012 string asm, list<dag> pattern>
1013 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1015 // Two-address instructions
1016 class T1It<dag oops, dag iops, InstrItinClass itin,
1017 string asm, string cstr, list<dag> pattern>
1018 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
1019 asm, cstr, pattern>;
1021 // Thumb1 instruction that can either be predicated or set CPSR.
1022 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1023 InstrItinClass itin,
1024 string opc, string asm, string cstr, list<dag> pattern>
1025 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1026 let OutOperandList = !con(oops, (outs s_cc_out:$s));
1027 let InOperandList = !con(iops, (ins pred:$p));
1028 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
1029 let Pattern = pattern;
1030 list<Predicate> Predicates = [IsThumb1Only];
1033 class T1sI<dag oops, dag iops, InstrItinClass itin,
1034 string opc, string asm, list<dag> pattern>
1035 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1037 // Two-address instructions
1038 class T1sIt<dag oops, dag iops, InstrItinClass itin,
1039 string opc, string asm, list<dag> pattern>
1040 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1041 "$lhs = $dst", pattern>;
1043 // Thumb1 instruction that can be predicated.
1044 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1045 InstrItinClass itin,
1046 string opc, string asm, string cstr, list<dag> pattern>
1047 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1048 let OutOperandList = oops;
1049 let InOperandList = !con(iops, (ins pred:$p));
1050 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1051 let Pattern = pattern;
1052 list<Predicate> Predicates = [IsThumb1Only];
1055 class T1pI<dag oops, dag iops, InstrItinClass itin,
1056 string opc, string asm, list<dag> pattern>
1057 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1059 // Two-address instructions
1060 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1061 string opc, string asm, list<dag> pattern>
1062 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1063 "$lhs = $dst", pattern>;
1065 class T1pI1<dag oops, dag iops, InstrItinClass itin,
1066 string opc, string asm, list<dag> pattern>
1067 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
1068 class T1pI2<dag oops, dag iops, InstrItinClass itin,
1069 string opc, string asm, list<dag> pattern>
1070 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
1071 class T1pI4<dag oops, dag iops, InstrItinClass itin,
1072 string opc, string asm, list<dag> pattern>
1073 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
1074 class T1pIs<dag oops, dag iops,
1075 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1076 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
1078 class Encoding16 : Encoding {
1079 let Inst{31-16} = 0x0000;
1082 // A6.2 16-bit Thumb instruction encoding
1083 class T1Encoding<bits<6> opcode> : Encoding16 {
1084 let Inst{15-10} = opcode;
1087 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1088 class T1General<bits<5> opcode> : Encoding16 {
1089 let Inst{15-14} = 0b00;
1090 let Inst{13-9} = opcode;
1093 // A6.2.2 Data-processing encoding.
1094 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1095 let Inst{15-10} = 0b010000;
1096 let Inst{9-6} = opcode;
1099 // A6.2.3 Special data instructions and branch and exchange encoding.
1100 class T1Special<bits<4> opcode> : Encoding16 {
1101 let Inst{15-10} = 0b010001;
1102 let Inst{9-6} = opcode;
1105 // A6.2.4 Load/store single data item encoding.
1106 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1107 let Inst{15-12} = opA;
1108 let Inst{11-9} = opB;
1110 class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
1111 class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
1112 class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
1113 class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
1114 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1116 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1117 class T1Misc<bits<7> opcode> : Encoding16 {
1118 let Inst{15-12} = 0b1011;
1119 let Inst{11-5} = opcode;
1122 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1123 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1124 InstrItinClass itin,
1125 string opc, string asm, string cstr, list<dag> pattern>
1126 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1127 let OutOperandList = oops;
1128 let InOperandList = !con(iops, (ins pred:$p));
1129 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1130 let Pattern = pattern;
1131 list<Predicate> Predicates = [IsThumb2];
1134 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1135 // input operand since by default it's a zero register. It will become an
1136 // implicit def once it's "flipped".
1138 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1140 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1141 InstrItinClass itin,
1142 string opc, string asm, string cstr, list<dag> pattern>
1143 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1144 let OutOperandList = oops;
1145 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1146 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
1147 let Pattern = pattern;
1148 list<Predicate> Predicates = [IsThumb2];
1152 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1153 InstrItinClass itin,
1154 string asm, string cstr, list<dag> pattern>
1155 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1156 let OutOperandList = oops;
1157 let InOperandList = iops;
1158 let AsmString = asm;
1159 let Pattern = pattern;
1160 list<Predicate> Predicates = [IsThumb2];
1163 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1164 InstrItinClass itin,
1165 string asm, string cstr, list<dag> pattern>
1166 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1167 let OutOperandList = oops;
1168 let InOperandList = iops;
1169 let AsmString = asm;
1170 let Pattern = pattern;
1171 list<Predicate> Predicates = [IsThumb1Only];
1174 class T2I<dag oops, dag iops, InstrItinClass itin,
1175 string opc, string asm, list<dag> pattern>
1176 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1177 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1178 string opc, string asm, list<dag> pattern>
1179 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
1180 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1181 string opc, string asm, list<dag> pattern>
1182 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1183 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1184 string opc, string asm, list<dag> pattern>
1185 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1186 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1187 string opc, string asm, list<dag> pattern>
1188 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1189 class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
1190 string opc, string asm, list<dag> pattern>
1191 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1193 let Inst{31-27} = 0b11101;
1194 let Inst{26-25} = 0b00;
1196 let Inst{23} = ?; // The U bit.
1199 let Inst{20} = load;
1202 class T2sI<dag oops, dag iops, InstrItinClass itin,
1203 string opc, string asm, list<dag> pattern>
1204 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1206 class T2XI<dag oops, dag iops, InstrItinClass itin,
1207 string asm, list<dag> pattern>
1208 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1209 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1210 string asm, list<dag> pattern>
1211 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1213 class T2Ix2<dag oops, dag iops, InstrItinClass itin,
1214 string opc, string asm, list<dag> pattern>
1215 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
1217 // Two-address instructions
1218 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1219 string asm, string cstr, list<dag> pattern>
1220 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1222 // T2Iidxldst - Thumb2 indexed load / store instructions.
1223 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1225 AddrMode am, IndexMode im, InstrItinClass itin,
1226 string opc, string asm, string cstr, list<dag> pattern>
1227 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1228 let OutOperandList = oops;
1229 let InOperandList = !con(iops, (ins pred:$p));
1230 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1231 let Pattern = pattern;
1232 list<Predicate> Predicates = [IsThumb2];
1233 let Inst{31-27} = 0b11111;
1234 let Inst{26-25} = 0b00;
1235 let Inst{24} = signed;
1237 let Inst{22-21} = opcod;
1238 let Inst{20} = load;
1240 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1241 let Inst{10} = pre; // The P bit.
1242 let Inst{8} = 1; // The W bit.
1245 // Helper class for disassembly only
1246 // A6.3.16 & A6.3.17
1247 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1248 class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
1249 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1250 : T2I<oops, iops, itin, opc, asm, pattern> {
1251 let Inst{31-27} = 0b11111;
1252 let Inst{26-24} = 0b011;
1253 let Inst{23} = long;
1254 let Inst{22-20} = op22_20;
1255 let Inst{7-4} = op7_4;
1258 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1259 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1260 list<Predicate> Predicates = [IsThumb1Only, HasV5T];
1263 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1264 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1265 list<Predicate> Predicates = [IsThumb1Only];
1268 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1269 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1270 list<Predicate> Predicates = [IsThumb2];
1273 //===----------------------------------------------------------------------===//
1275 //===----------------------------------------------------------------------===//
1276 // ARM VFP Instruction templates.
1279 // Almost all VFP instructions are predicable.
1280 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1281 IndexMode im, Format f, InstrItinClass itin,
1282 string opc, string asm, string cstr, list<dag> pattern>
1283 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1284 let OutOperandList = oops;
1285 let InOperandList = !con(iops, (ins pred:$p));
1286 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1287 let Pattern = pattern;
1288 list<Predicate> Predicates = [HasVFP2];
1292 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1293 IndexMode im, Format f, InstrItinClass itin,
1294 string asm, string cstr, list<dag> pattern>
1295 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1296 let OutOperandList = oops;
1297 let InOperandList = iops;
1298 let AsmString = asm;
1299 let Pattern = pattern;
1300 list<Predicate> Predicates = [HasVFP2];
1303 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1304 string opc, string asm, list<dag> pattern>
1305 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1306 opc, asm, "", pattern>;
1308 // ARM VFP addrmode5 loads and stores
1309 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1310 InstrItinClass itin,
1311 string opc, string asm, list<dag> pattern>
1312 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1313 VFPLdStFrm, itin, opc, asm, "", pattern> {
1314 // TODO: Mark the instructions with the appropriate subtarget info.
1315 let Inst{27-24} = opcod1;
1316 let Inst{21-20} = opcod2;
1317 let Inst{11-8} = 0b1011;
1319 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1320 let D = VFPNeonDomain;
1323 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1324 InstrItinClass itin,
1325 string opc, string asm, list<dag> pattern>
1326 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1327 VFPLdStFrm, itin, opc, asm, "", pattern> {
1328 // TODO: Mark the instructions with the appropriate subtarget info.
1329 let Inst{27-24} = opcod1;
1330 let Inst{21-20} = opcod2;
1331 let Inst{11-8} = 0b1010;
1334 // VFP Load / store multiple pseudo instructions.
1335 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1337 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain,
1339 let OutOperandList = oops;
1340 let InOperandList = !con(iops, (ins pred:$p));
1341 let Pattern = pattern;
1342 list<Predicate> Predicates = [HasVFP2];
1345 // Load / store multiple
1346 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1347 string asm, string cstr, list<dag> pattern>
1348 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1349 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1350 // TODO: Mark the instructions with the appropriate subtarget info.
1351 let Inst{27-25} = 0b110;
1352 let Inst{11-8} = 0b1011;
1354 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1355 let D = VFPNeonDomain;
1358 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1359 string asm, string cstr, list<dag> pattern>
1360 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1361 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1362 // TODO: Mark the instructions with the appropriate subtarget info.
1363 let Inst{27-25} = 0b110;
1364 let Inst{11-8} = 0b1010;
1367 // Double precision, unary
1368 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1369 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1370 string asm, list<dag> pattern>
1371 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1372 let Inst{27-23} = opcod1;
1373 let Inst{21-20} = opcod2;
1374 let Inst{19-16} = opcod3;
1375 let Inst{11-8} = 0b1011;
1376 let Inst{7-6} = opcod4;
1377 let Inst{4} = opcod5;
1380 // Double precision, binary
1381 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1382 dag iops, InstrItinClass itin, string opc, string asm,
1384 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1385 let Inst{27-23} = opcod1;
1386 let Inst{21-20} = opcod2;
1387 let Inst{11-8} = 0b1011;
1392 // Double precision, binary, VML[AS] (for additional predicate)
1393 class ADbI_vmlX<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1394 dag iops, InstrItinClass itin, string opc, string asm,
1396 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1397 let Inst{27-23} = opcod1;
1398 let Inst{21-20} = opcod2;
1399 let Inst{11-8} = 0b1011;
1402 list<Predicate> Predicates = [HasVFP2, UseVMLx];
1405 // Single precision, unary
1406 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1407 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1408 string asm, list<dag> pattern>
1409 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1410 let Inst{27-23} = opcod1;
1411 let Inst{21-20} = opcod2;
1412 let Inst{19-16} = opcod3;
1413 let Inst{11-8} = 0b1010;
1414 let Inst{7-6} = opcod4;
1415 let Inst{4} = opcod5;
1418 // Single precision unary, if no NEON
1419 // Same as ASuI except not available if NEON is enabled
1420 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1421 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1422 string asm, list<dag> pattern>
1423 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1425 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1428 // Single precision, binary
1429 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1430 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1431 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1432 let Inst{27-23} = opcod1;
1433 let Inst{21-20} = opcod2;
1434 let Inst{11-8} = 0b1010;
1439 // Single precision binary, if no NEON
1440 // Same as ASbI except not available if NEON is enabled
1441 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1442 dag iops, InstrItinClass itin, string opc, string asm,
1444 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1445 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1448 // VFP conversion instructions
1449 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1450 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1452 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1453 let Inst{27-23} = opcod1;
1454 let Inst{21-20} = opcod2;
1455 let Inst{19-16} = opcod3;
1456 let Inst{11-8} = opcod4;
1461 // VFP conversion between floating-point and fixed-point
1462 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1463 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1465 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1466 // size (fixed-point number): sx == 0 ? 16 : 32
1467 let Inst{7} = op5; // sx
1470 // VFP conversion instructions, if no NEON
1471 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1472 dag oops, dag iops, InstrItinClass itin,
1473 string opc, string asm, list<dag> pattern>
1474 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1476 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1479 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1480 InstrItinClass itin,
1481 string opc, string asm, list<dag> pattern>
1482 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1483 let Inst{27-20} = opcod1;
1484 let Inst{11-8} = opcod2;
1488 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1489 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1490 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1492 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1493 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1494 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1496 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1497 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1498 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1500 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1501 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1502 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1504 //===----------------------------------------------------------------------===//
1506 //===----------------------------------------------------------------------===//
1507 // ARM NEON Instruction templates.
1510 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1511 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1513 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1514 let OutOperandList = oops;
1515 let InOperandList = !con(iops, (ins pred:$p));
1516 let AsmString = !strconcat(
1517 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
1518 !strconcat("\t", asm));
1519 let Pattern = pattern;
1520 list<Predicate> Predicates = [HasNEON];
1523 // Same as NeonI except it does not have a "data type" specifier.
1524 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1525 InstrItinClass itin, string opc, string asm, string cstr,
1527 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1528 let OutOperandList = oops;
1529 let InOperandList = !con(iops, (ins pred:$p));
1530 let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm));
1531 let Pattern = pattern;
1532 list<Predicate> Predicates = [HasNEON];
1535 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1536 dag oops, dag iops, InstrItinClass itin,
1537 string opc, string dt, string asm, string cstr, list<dag> pattern>
1538 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1540 let Inst{31-24} = 0b11110100;
1541 let Inst{23} = op23;
1542 let Inst{21-20} = op21_20;
1543 let Inst{11-8} = op11_8;
1544 let Inst{7-4} = op7_4;
1547 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1548 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1550 let OutOperandList = oops;
1551 let InOperandList = !con(iops, (ins pred:$p));
1552 list<Predicate> Predicates = [HasNEON];
1555 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr>
1556 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1558 let OutOperandList = oops;
1559 let InOperandList = !con(iops, (ins pred:$p));
1560 list<Predicate> Predicates = [HasNEON];
1563 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1564 string opc, string dt, string asm, string cstr, list<dag> pattern>
1565 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1567 let Inst{31-25} = 0b1111001;
1570 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1571 string opc, string asm, string cstr, list<dag> pattern>
1572 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1574 let Inst{31-25} = 0b1111001;
1577 // NEON "one register and a modified immediate" format.
1578 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1580 dag oops, dag iops, InstrItinClass itin,
1581 string opc, string dt, string asm, string cstr,
1583 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1584 let Inst{23} = op23;
1585 let Inst{21-19} = op21_19;
1586 let Inst{11-8} = op11_8;
1593 // NEON 2 vector register format.
1594 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1595 bits<5> op11_7, bit op6, bit op4,
1596 dag oops, dag iops, InstrItinClass itin,
1597 string opc, string dt, string asm, string cstr, list<dag> pattern>
1598 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1599 let Inst{24-23} = op24_23;
1600 let Inst{21-20} = op21_20;
1601 let Inst{19-18} = op19_18;
1602 let Inst{17-16} = op17_16;
1603 let Inst{11-7} = op11_7;
1608 // Same as N2V except it doesn't have a datatype suffix.
1609 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1610 bits<5> op11_7, bit op6, bit op4,
1611 dag oops, dag iops, InstrItinClass itin,
1612 string opc, string asm, string cstr, list<dag> pattern>
1613 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1614 let Inst{24-23} = op24_23;
1615 let Inst{21-20} = op21_20;
1616 let Inst{19-18} = op19_18;
1617 let Inst{17-16} = op17_16;
1618 let Inst{11-7} = op11_7;
1623 // NEON 2 vector register with immediate.
1624 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1625 dag oops, dag iops, Format f, InstrItinClass itin,
1626 string opc, string dt, string asm, string cstr, list<dag> pattern>
1627 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1628 let Inst{24} = op24;
1629 let Inst{23} = op23;
1630 let Inst{11-8} = op11_8;
1636 // NEON 3 vector register format.
1637 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1638 dag oops, dag iops, Format f, InstrItinClass itin,
1639 string opc, string dt, string asm, string cstr, list<dag> pattern>
1640 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1641 let Inst{24} = op24;
1642 let Inst{23} = op23;
1643 let Inst{21-20} = op21_20;
1644 let Inst{11-8} = op11_8;
1649 // Same as N3V except it doesn't have a data type suffix.
1650 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1652 dag oops, dag iops, Format f, InstrItinClass itin,
1653 string opc, string asm, string cstr, list<dag> pattern>
1654 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1655 let Inst{24} = op24;
1656 let Inst{23} = op23;
1657 let Inst{21-20} = op21_20;
1658 let Inst{11-8} = op11_8;
1663 // NEON VMOVs between scalar and core registers.
1664 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1665 dag oops, dag iops, Format f, InstrItinClass itin,
1666 string opc, string dt, string asm, list<dag> pattern>
1667 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain,
1669 let Inst{27-20} = opcod1;
1670 let Inst{11-8} = opcod2;
1671 let Inst{6-5} = opcod3;
1674 let OutOperandList = oops;
1675 let InOperandList = !con(iops, (ins pred:$p));
1676 let AsmString = !strconcat(
1677 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
1678 !strconcat("\t", asm));
1679 let Pattern = pattern;
1680 list<Predicate> Predicates = [HasNEON];
1682 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1683 dag oops, dag iops, InstrItinClass itin,
1684 string opc, string dt, string asm, list<dag> pattern>
1685 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1686 opc, dt, asm, pattern>;
1687 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1688 dag oops, dag iops, InstrItinClass itin,
1689 string opc, string dt, string asm, list<dag> pattern>
1690 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1691 opc, dt, asm, pattern>;
1692 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1693 dag oops, dag iops, InstrItinClass itin,
1694 string opc, string dt, string asm, list<dag> pattern>
1695 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1696 opc, dt, asm, pattern>;
1698 // Vector Duplicate Lane (from scalar to all elements)
1699 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1700 InstrItinClass itin, string opc, string dt, string asm,
1702 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1703 let Inst{24-23} = 0b11;
1704 let Inst{21-20} = 0b11;
1705 let Inst{19-16} = op19_16;
1706 let Inst{11-7} = 0b11000;
1711 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1712 // for single-precision FP.
1713 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1714 list<Predicate> Predicates = [HasNEON,UseNEONForFP];