1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // the instruction has a Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 class AddrMode<bits<5> val> {
91 def AddrModeNone : AddrMode<0>;
92 def AddrMode1 : AddrMode<1>;
93 def AddrMode2 : AddrMode<2>;
94 def AddrMode3 : AddrMode<3>;
95 def AddrMode4 : AddrMode<4>;
96 def AddrMode5 : AddrMode<5>;
97 def AddrMode6 : AddrMode<6>;
98 def AddrModeT1_1 : AddrMode<7>;
99 def AddrModeT1_2 : AddrMode<8>;
100 def AddrModeT1_4 : AddrMode<9>;
101 def AddrModeT1_s : AddrMode<10>;
102 def AddrModeT2_i12 : AddrMode<11>;
103 def AddrModeT2_i8 : AddrMode<12>;
104 def AddrModeT2_so : AddrMode<13>;
105 def AddrModeT2_pc : AddrMode<14>;
106 def AddrModeT2_i8s4 : AddrMode<15>;
107 def AddrMode_i12 : AddrMode<16>;
110 class SizeFlagVal<bits<3> val> {
113 def SizeInvalid : SizeFlagVal<0>; // Unset.
114 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
115 def Size8Bytes : SizeFlagVal<2>;
116 def Size4Bytes : SizeFlagVal<3>;
117 def Size2Bytes : SizeFlagVal<4>;
119 // Load / store index mode.
120 class IndexMode<bits<2> val> {
123 def IndexModeNone : IndexMode<0>;
124 def IndexModePre : IndexMode<1>;
125 def IndexModePost : IndexMode<2>;
126 def IndexModeUpd : IndexMode<3>;
128 // Instruction execution domain.
129 class Domain<bits<2> val> {
132 def GenericDomain : Domain<0>;
133 def VFPDomain : Domain<1>; // Instructions in VFP domain only
134 def NeonDomain : Domain<2>; // Instructions in Neon domain only
135 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
137 //===----------------------------------------------------------------------===//
139 // ARM special operands.
142 def CondCodeOperand : AsmOperandClass {
143 let Name = "CondCode";
144 let SuperClasses = [];
147 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
148 // register whose default is 0 (no register).
149 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
150 (ops (i32 14), (i32 zero_reg))> {
151 let PrintMethod = "printPredicateOperand";
152 let ParserMatchClass = CondCodeOperand;
155 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
156 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
157 let EncoderMethod = "getCCOutOpValue";
158 let PrintMethod = "printSBitModifierOperand";
161 // Same as cc_out except it defaults to setting CPSR.
162 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
163 let EncoderMethod = "getCCOutOpValue";
164 let PrintMethod = "printSBitModifierOperand";
167 // ARM special operands for disassembly only.
169 def setend_op : Operand<i32> {
170 let PrintMethod = "printSetendOperand";
173 def cps_opt : Operand<i32> {
174 let PrintMethod = "printCPSOptionOperand";
177 def msr_mask : Operand<i32> {
178 let PrintMethod = "printMSRMaskOperand";
181 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
182 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
183 def neg_zero : Operand<i32> {
184 let PrintMethod = "printNegZeroOperand";
187 //===----------------------------------------------------------------------===//
189 // ARM Instruction templates.
192 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
193 Format f, Domain d, string cstr, InstrItinClass itin>
195 let Namespace = "ARM";
200 bits<2> IndexModeBits = IM.Value;
202 bits<6> Form = F.Value;
204 bit isUnaryDataProc = 0;
205 bit canXformTo16Bit = 0;
207 // If this is a pseudo instruction, mark it isCodeGenOnly.
208 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
210 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
211 let TSFlags{4-0} = AM.Value;
212 let TSFlags{7-5} = SZ.Value;
213 let TSFlags{9-8} = IndexModeBits;
214 let TSFlags{15-10} = Form;
215 let TSFlags{16} = isUnaryDataProc;
216 let TSFlags{17} = canXformTo16Bit;
217 let TSFlags{19-18} = D.Value;
219 let Constraints = cstr;
220 let Itinerary = itin;
227 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
228 Format f, Domain d, string cstr, InstrItinClass itin>
229 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
231 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
232 // on by adding flavors to specific instructions.
233 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
234 Format f, Domain d, string cstr, InstrItinClass itin>
235 : InstTemplate<am, sz, im, f, d, cstr, itin>;
237 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
238 // FIXME: This really should derive from InstTemplate instead, as pseudos
239 // don't need encoding information. TableGen doesn't like that
240 // currently. Need to figure out why and fix it.
241 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
243 let OutOperandList = oops;
244 let InOperandList = iops;
245 let Pattern = pattern;
248 // PseudoInst that's ARM-mode only.
249 class ARMPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
251 : PseudoInst<oops, iops, itin, pattern> {
253 list<Predicate> Predicates = [IsARM];
256 // PseudoInst that's Thumb-mode only.
257 class tPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
259 : PseudoInst<oops, iops, itin, pattern> {
261 list<Predicate> Predicates = [IsThumb];
264 // Almost all ARM instructions are predicable.
265 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
266 IndexMode im, Format f, InstrItinClass itin,
267 string opc, string asm, string cstr,
269 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
272 let OutOperandList = oops;
273 let InOperandList = !con(iops, (ins pred:$p));
274 let AsmString = !strconcat(opc, "${p}", asm);
275 let Pattern = pattern;
276 list<Predicate> Predicates = [IsARM];
279 // A few are not predicable
280 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
281 IndexMode im, Format f, InstrItinClass itin,
282 string opc, string asm, string cstr,
284 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
285 let OutOperandList = oops;
286 let InOperandList = iops;
287 let AsmString = !strconcat(opc, asm);
288 let Pattern = pattern;
289 let isPredicable = 0;
290 list<Predicate> Predicates = [IsARM];
293 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
294 // operand since by default it's a zero register. It will become an implicit def
295 // once it's "flipped".
296 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
297 IndexMode im, Format f, InstrItinClass itin,
298 string opc, string asm, string cstr,
300 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
301 bits<4> p; // Predicate operand
302 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
306 let OutOperandList = oops;
307 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
308 let AsmString = !strconcat(opc, "${s}${p}", asm);
309 let Pattern = pattern;
310 list<Predicate> Predicates = [IsARM];
314 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
315 IndexMode im, Format f, InstrItinClass itin,
316 string asm, string cstr, list<dag> pattern>
317 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
318 let OutOperandList = oops;
319 let InOperandList = iops;
321 let Pattern = pattern;
322 list<Predicate> Predicates = [IsARM];
325 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
326 string opc, string asm, list<dag> pattern>
327 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
328 opc, asm, "", pattern>;
329 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
330 string opc, string asm, list<dag> pattern>
331 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
332 opc, asm, "", pattern>;
333 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
334 string asm, list<dag> pattern>
335 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
337 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
338 string opc, string asm, list<dag> pattern>
339 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
340 opc, asm, "", pattern>;
342 // Ctrl flow instructions
343 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
344 string opc, string asm, list<dag> pattern>
345 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
346 opc, asm, "", pattern> {
347 let Inst{27-24} = opcod;
349 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
350 string asm, list<dag> pattern>
351 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
353 let Inst{27-24} = opcod;
356 // BR_JT instructions
357 class JTI<dag oops, dag iops, InstrItinClass itin,
358 string asm, list<dag> pattern>
359 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
362 // Atomic load/store instructions
363 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
364 string opc, string asm, list<dag> pattern>
365 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
366 opc, asm, "", pattern> {
369 let Inst{27-23} = 0b00011;
370 let Inst{22-21} = opcod;
372 let Inst{19-16} = Rn;
373 let Inst{15-12} = Rt;
374 let Inst{11-0} = 0b111110011111;
376 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
377 string opc, string asm, list<dag> pattern>
378 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
379 opc, asm, "", pattern> {
383 let Inst{27-23} = 0b00011;
384 let Inst{22-21} = opcod;
386 let Inst{19-16} = Rn;
387 let Inst{15-12} = Rd;
388 let Inst{11-4} = 0b11111001;
391 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
392 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
396 let Inst{27-23} = 0b00010;
398 let Inst{21-20} = 0b00;
399 let Inst{19-16} = Rn;
400 let Inst{15-12} = Rt;
401 let Inst{11-4} = 0b00001001;
405 // addrmode1 instructions
406 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
407 string opc, string asm, list<dag> pattern>
408 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
409 opc, asm, "", pattern> {
410 let Inst{24-21} = opcod;
411 let Inst{27-26} = 0b00;
413 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
414 string opc, string asm, list<dag> pattern>
415 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
416 opc, asm, "", pattern> {
417 let Inst{24-21} = opcod;
418 let Inst{27-26} = 0b00;
420 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
421 string asm, list<dag> pattern>
422 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
424 let Inst{24-21} = opcod;
425 let Inst{27-26} = 0b00;
430 // LDR/LDRB/STR/STRB/...
431 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
432 Format f, InstrItinClass itin, string opc, string asm,
434 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
436 let Inst{27-25} = op;
437 let Inst{24} = 1; // 24 == P
439 let Inst{22} = isByte;
440 let Inst{21} = 0; // 21 == W
443 // Indexed load/stores
444 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
445 IndexMode im, Format f, InstrItinClass itin, string opc,
446 string asm, string cstr, list<dag> pattern>
447 : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin,
448 opc, asm, cstr, pattern> {
450 let Inst{27-26} = 0b01;
451 let Inst{24} = isPre; // P bit
452 let Inst{22} = isByte; // B bit
453 let Inst{21} = isPre; // W bit
454 let Inst{20} = isLd; // L bit
455 let Inst{15-12} = Rt;
457 class AI2stridx<bit isByte, bit isPre, dag oops, dag iops,
458 IndexMode im, Format f, InstrItinClass itin, string opc,
459 string asm, string cstr, list<dag> pattern>
460 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
462 // AM2 store w/ two operands: (GPR, am2offset)
463 // {13} 1 == Rm, 0 == imm12
468 let Inst{25} = offset{13};
469 let Inst{23} = offset{12};
470 let Inst{19-16} = Rn;
471 let Inst{11-0} = offset{11-0};
474 // addrmode3 instructions
475 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
476 InstrItinClass itin, string opc, string asm, list<dag> pattern>
477 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
478 opc, asm, "", pattern> {
481 let Inst{27-25} = 0b000;
482 let Inst{24} = 1; // P bit
483 let Inst{23} = addr{8}; // U bit
484 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
485 let Inst{21} = 0; // W bit
486 let Inst{20} = op20; // L bit
487 let Inst{19-16} = addr{12-9}; // Rn
488 let Inst{15-12} = Rt; // Rt
489 let Inst{11-8} = addr{7-4}; // imm7_4/zero
491 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
494 class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
495 IndexMode im, Format f, InstrItinClass itin, string opc,
496 string asm, string cstr, list<dag> pattern>
497 : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin,
498 opc, asm, cstr, pattern> {
500 let Inst{27-25} = 0b000;
501 let Inst{24} = isPre; // P bit
502 let Inst{21} = isPre; // W bit
503 let Inst{20} = op20; // L bit
504 let Inst{15-12} = Rt; // Rt
507 class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
508 IndexMode im, Format f, InstrItinClass itin, string opc,
509 string asm, string cstr, list<dag> pattern>
510 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
512 // AM3 store w/ two operands: (GPR, am3offset)
516 let Inst{27-25} = 0b000;
517 let Inst{23} = offset{8};
518 let Inst{22} = offset{9};
519 let Inst{19-16} = Rn;
520 let Inst{15-12} = Rt; // Rt
521 let Inst{11-8} = offset{7-4}; // imm7_4/zero
523 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
527 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
528 string opc, string asm, list<dag> pattern>
529 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
530 opc, asm, "", pattern> {
533 let Inst{27-25} = 0b000;
534 let Inst{24} = 1; // P bit
535 let Inst{23} = addr{8}; // U bit
536 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
537 let Inst{21} = 0; // W bit
538 let Inst{20} = 0; // L bit
539 let Inst{19-16} = addr{12-9}; // Rn
540 let Inst{15-12} = Rt; // Rt
541 let Inst{11-8} = addr{7-4}; // imm7_4/zero
543 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
546 // Pre-indexed stores
547 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
548 string opc, string asm, string cstr, list<dag> pattern>
549 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
550 opc, asm, cstr, pattern> {
552 let Inst{5} = 1; // H bit
553 let Inst{6} = 0; // S bit
555 let Inst{20} = 0; // L bit
556 let Inst{21} = 1; // W bit
557 let Inst{24} = 1; // P bit
558 let Inst{27-25} = 0b000;
560 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
561 string opc, string asm, string cstr, list<dag> pattern>
562 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
563 opc, asm, cstr, pattern> {
565 let Inst{5} = 1; // H bit
566 let Inst{6} = 1; // S bit
568 let Inst{20} = 0; // L bit
569 let Inst{21} = 1; // W bit
570 let Inst{24} = 1; // P bit
571 let Inst{27-25} = 0b000;
574 // Post-indexed stores
575 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
576 string opc, string asm, string cstr, list<dag> pattern>
577 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
578 opc, asm, cstr,pattern> {
580 let Inst{5} = 1; // H bit
581 let Inst{6} = 0; // S bit
583 let Inst{20} = 0; // L bit
584 let Inst{21} = 0; // W bit
585 let Inst{24} = 0; // P bit
586 let Inst{27-25} = 0b000;
588 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
589 string opc, string asm, string cstr, list<dag> pattern>
590 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
591 opc, asm, cstr, pattern> {
593 let Inst{5} = 1; // H bit
594 let Inst{6} = 1; // S bit
596 let Inst{20} = 0; // L bit
597 let Inst{21} = 0; // W bit
598 let Inst{24} = 0; // P bit
599 let Inst{27-25} = 0b000;
602 // addrmode4 instructions
603 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
604 string asm, string cstr, list<dag> pattern>
605 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> {
610 let Inst{27-25} = 0b100;
611 let Inst{22} = 0; // S bit
612 let Inst{19-16} = Rn;
613 let Inst{15-0} = regs;
616 // Unsigned multiply, multiply-accumulate instructions.
617 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
618 string opc, string asm, list<dag> pattern>
619 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
620 opc, asm, "", pattern> {
621 let Inst{7-4} = 0b1001;
622 let Inst{20} = 0; // S bit
623 let Inst{27-21} = opcod;
625 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
626 string opc, string asm, list<dag> pattern>
627 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
628 opc, asm, "", pattern> {
629 let Inst{7-4} = 0b1001;
630 let Inst{27-21} = opcod;
633 // Most significant word multiply
634 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
635 InstrItinClass itin, string opc, string asm, list<dag> pattern>
636 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
637 opc, asm, "", pattern> {
641 let Inst{7-4} = opc7_4;
643 let Inst{27-21} = opcod;
644 let Inst{19-16} = Rd;
648 // MSW multiple w/ Ra operand
649 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
650 InstrItinClass itin, string opc, string asm, list<dag> pattern>
651 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
653 let Inst{15-12} = Ra;
656 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
657 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
658 InstrItinClass itin, string opc, string asm, list<dag> pattern>
659 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
660 opc, asm, "", pattern> {
666 let Inst{27-21} = opcod;
667 let Inst{6-5} = bit6_5;
671 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
672 InstrItinClass itin, string opc, string asm, list<dag> pattern>
673 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
675 let Inst{19-16} = Rd;
678 // AMulxyI with Ra operand
679 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
680 InstrItinClass itin, string opc, string asm, list<dag> pattern>
681 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
683 let Inst{15-12} = Ra;
686 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
687 InstrItinClass itin, string opc, string asm, list<dag> pattern>
688 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
691 let Inst{19-16} = RdHi;
692 let Inst{15-12} = RdLo;
695 // Extend instructions.
696 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
697 string opc, string asm, list<dag> pattern>
698 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
699 opc, asm, "", pattern> {
700 // All AExtI instructions have Rd and Rm register operands.
703 let Inst{15-12} = Rd;
705 let Inst{7-4} = 0b0111;
706 let Inst{9-8} = 0b00;
707 let Inst{27-20} = opcod;
710 // Misc Arithmetic instructions.
711 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
712 InstrItinClass itin, string opc, string asm, list<dag> pattern>
713 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
714 opc, asm, "", pattern> {
717 let Inst{27-20} = opcod;
718 let Inst{19-16} = 0b1111;
719 let Inst{15-12} = Rd;
720 let Inst{11-8} = 0b1111;
721 let Inst{7-4} = opc7_4;
726 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
727 string opc, string asm, list<dag> pattern>
728 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
729 opc, asm, "", pattern> {
734 let Inst{27-20} = opcod;
735 let Inst{19-16} = Rn;
736 let Inst{15-12} = Rd;
737 let Inst{11-7} = sh{7-3};
739 let Inst{5-4} = 0b01;
743 //===----------------------------------------------------------------------===//
745 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
746 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
747 list<Predicate> Predicates = [IsARM];
749 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
750 list<Predicate> Predicates = [IsARM, HasV5TE];
752 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
753 list<Predicate> Predicates = [IsARM, HasV6];
756 //===----------------------------------------------------------------------===//
758 // Thumb Instruction Format Definitions.
761 // TI - Thumb instruction.
763 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
764 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
765 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
766 let OutOperandList = oops;
767 let InOperandList = iops;
769 let Pattern = pattern;
770 list<Predicate> Predicates = [IsThumb];
773 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
774 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
776 // Two-address instructions
777 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
779 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
782 // tBL, tBX 32-bit instructions
783 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
784 dag oops, dag iops, InstrItinClass itin, string asm,
786 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
788 let Inst{31-27} = opcod1;
789 let Inst{15-14} = opcod2;
790 let Inst{12} = opcod3;
793 // BR_JT instructions
794 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
796 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
799 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
800 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
801 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
802 let OutOperandList = oops;
803 let InOperandList = iops;
805 let Pattern = pattern;
806 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
809 class T1I<dag oops, dag iops, InstrItinClass itin,
810 string asm, list<dag> pattern>
811 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
812 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
813 string asm, list<dag> pattern>
814 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
816 // Two-address instructions
817 class T1It<dag oops, dag iops, InstrItinClass itin,
818 string asm, string cstr, list<dag> pattern>
819 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
822 // Thumb1 instruction that can either be predicated or set CPSR.
823 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
825 string opc, string asm, string cstr, list<dag> pattern>
826 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
827 let OutOperandList = !con(oops, (outs s_cc_out:$s));
828 let InOperandList = !con(iops, (ins pred:$p));
829 let AsmString = !strconcat(opc, "${s}${p}", asm);
830 let Pattern = pattern;
831 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
834 class T1sI<dag oops, dag iops, InstrItinClass itin,
835 string opc, string asm, list<dag> pattern>
836 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
838 // Two-address instructions
839 class T1sIt<dag oops, dag iops, InstrItinClass itin,
840 string opc, string asm, list<dag> pattern>
841 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
842 "$lhs = $dst", pattern>;
844 // Thumb1 instruction that can be predicated.
845 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
847 string opc, string asm, string cstr, list<dag> pattern>
848 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
849 let OutOperandList = oops;
850 let InOperandList = !con(iops, (ins pred:$p));
851 let AsmString = !strconcat(opc, "${p}", asm);
852 let Pattern = pattern;
853 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
856 class T1pI<dag oops, dag iops, InstrItinClass itin,
857 string opc, string asm, list<dag> pattern>
858 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
860 // Two-address instructions
861 class T1pIt<dag oops, dag iops, InstrItinClass itin,
862 string opc, string asm, list<dag> pattern>
863 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
864 "$lhs = $dst", pattern>;
866 class T1pI1<dag oops, dag iops, InstrItinClass itin,
867 string opc, string asm, list<dag> pattern>
868 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
869 class T1pI2<dag oops, dag iops, InstrItinClass itin,
870 string opc, string asm, list<dag> pattern>
871 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
872 class T1pI4<dag oops, dag iops, InstrItinClass itin,
873 string opc, string asm, list<dag> pattern>
874 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
875 class T1pIs<dag oops, dag iops,
876 InstrItinClass itin, string opc, string asm, list<dag> pattern>
877 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
879 class Encoding16 : Encoding {
880 let Inst{31-16} = 0x0000;
883 // A6.2 16-bit Thumb instruction encoding
884 class T1Encoding<bits<6> opcode> : Encoding16 {
885 let Inst{15-10} = opcode;
888 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
889 class T1General<bits<5> opcode> : Encoding16 {
890 let Inst{15-14} = 0b00;
891 let Inst{13-9} = opcode;
894 // A6.2.2 Data-processing encoding.
895 class T1DataProcessing<bits<4> opcode> : Encoding16 {
896 let Inst{15-10} = 0b010000;
897 let Inst{9-6} = opcode;
900 // A6.2.3 Special data instructions and branch and exchange encoding.
901 class T1Special<bits<4> opcode> : Encoding16 {
902 let Inst{15-10} = 0b010001;
903 let Inst{9-6} = opcode;
906 // A6.2.4 Load/store single data item encoding.
907 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
908 let Inst{15-12} = opA;
909 let Inst{11-9} = opB;
911 class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
912 class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
913 class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
914 class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
915 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
917 // A6.2.5 Miscellaneous 16-bit instructions encoding.
918 class T1Misc<bits<7> opcode> : Encoding16 {
919 let Inst{15-12} = 0b1011;
920 let Inst{11-5} = opcode;
923 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
924 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
926 string opc, string asm, string cstr, list<dag> pattern>
927 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
928 let OutOperandList = oops;
929 let InOperandList = !con(iops, (ins pred:$p));
930 let AsmString = !strconcat(opc, "${p}", asm);
931 let Pattern = pattern;
932 list<Predicate> Predicates = [IsThumb2];
935 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
936 // input operand since by default it's a zero register. It will become an
937 // implicit def once it's "flipped".
939 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
941 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
943 string opc, string asm, string cstr, list<dag> pattern>
944 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
945 let OutOperandList = oops;
946 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
947 let AsmString = !strconcat(opc, "${s}${p}", asm);
948 let Pattern = pattern;
949 list<Predicate> Predicates = [IsThumb2];
953 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
955 string asm, string cstr, list<dag> pattern>
956 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
957 let OutOperandList = oops;
958 let InOperandList = iops;
960 let Pattern = pattern;
961 list<Predicate> Predicates = [IsThumb2];
964 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
966 string asm, string cstr, list<dag> pattern>
967 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
968 let OutOperandList = oops;
969 let InOperandList = iops;
971 let Pattern = pattern;
972 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
975 class T2I<dag oops, dag iops, InstrItinClass itin,
976 string opc, string asm, list<dag> pattern>
977 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
978 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
979 string opc, string asm, list<dag> pattern>
980 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
981 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
982 string opc, string asm, list<dag> pattern>
983 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
984 class T2Iso<dag oops, dag iops, InstrItinClass itin,
985 string opc, string asm, list<dag> pattern>
986 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
987 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
988 string opc, string asm, list<dag> pattern>
989 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
990 class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
991 string opc, string asm, list<dag> pattern>
992 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
994 let Inst{31-27} = 0b11101;
995 let Inst{26-25} = 0b00;
997 let Inst{23} = ?; // The U bit.
1000 let Inst{20} = load;
1003 class T2sI<dag oops, dag iops, InstrItinClass itin,
1004 string opc, string asm, list<dag> pattern>
1005 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1007 class T2XI<dag oops, dag iops, InstrItinClass itin,
1008 string asm, list<dag> pattern>
1009 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1010 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1011 string asm, list<dag> pattern>
1012 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1014 // Two-address instructions
1015 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1016 string asm, string cstr, list<dag> pattern>
1017 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1019 // T2Iidxldst - Thumb2 indexed load / store instructions.
1020 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1022 AddrMode am, IndexMode im, InstrItinClass itin,
1023 string opc, string asm, string cstr, list<dag> pattern>
1024 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1025 let OutOperandList = oops;
1026 let InOperandList = !con(iops, (ins pred:$p));
1027 let AsmString = !strconcat(opc, "${p}", asm);
1028 let Pattern = pattern;
1029 list<Predicate> Predicates = [IsThumb2];
1030 let Inst{31-27} = 0b11111;
1031 let Inst{26-25} = 0b00;
1032 let Inst{24} = signed;
1034 let Inst{22-21} = opcod;
1035 let Inst{20} = load;
1037 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1038 let Inst{10} = pre; // The P bit.
1039 let Inst{8} = 1; // The W bit.
1042 let Inst{7-0} = addr{7-0};
1043 let Inst{9} = addr{8}; // Sign bit
1047 let Inst{15-12} = Rt{3-0};
1048 let Inst{19-16} = Rn{3-0};
1051 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1052 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1053 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1056 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1057 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1058 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1061 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1062 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1063 list<Predicate> Predicates = [IsThumb2];
1066 //===----------------------------------------------------------------------===//
1068 //===----------------------------------------------------------------------===//
1069 // ARM VFP Instruction templates.
1072 // Almost all VFP instructions are predicable.
1073 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1074 IndexMode im, Format f, InstrItinClass itin,
1075 string opc, string asm, string cstr, list<dag> pattern>
1076 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1078 let Inst{31-28} = p;
1079 let OutOperandList = oops;
1080 let InOperandList = !con(iops, (ins pred:$p));
1081 let AsmString = !strconcat(opc, "${p}", asm);
1082 let Pattern = pattern;
1083 list<Predicate> Predicates = [HasVFP2];
1087 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1088 IndexMode im, Format f, InstrItinClass itin,
1089 string asm, string cstr, list<dag> pattern>
1090 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1092 let Inst{31-28} = p;
1093 let OutOperandList = oops;
1094 let InOperandList = iops;
1095 let AsmString = asm;
1096 let Pattern = pattern;
1097 list<Predicate> Predicates = [HasVFP2];
1100 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1101 string opc, string asm, list<dag> pattern>
1102 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1103 opc, asm, "", pattern>;
1105 // ARM VFP addrmode5 loads and stores
1106 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1107 InstrItinClass itin,
1108 string opc, string asm, list<dag> pattern>
1109 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1110 VFPLdStFrm, itin, opc, asm, "", pattern> {
1111 // Instruction operands.
1115 // Encode instruction operands.
1116 let Inst{23} = addr{8}; // U (add = (U == '1'))
1117 let Inst{22} = Dd{4};
1118 let Inst{19-16} = addr{12-9}; // Rn
1119 let Inst{15-12} = Dd{3-0};
1120 let Inst{7-0} = addr{7-0}; // imm8
1122 // TODO: Mark the instructions with the appropriate subtarget info.
1123 let Inst{27-24} = opcod1;
1124 let Inst{21-20} = opcod2;
1125 let Inst{11-9} = 0b101;
1126 let Inst{8} = 1; // Double precision
1128 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1129 let D = VFPNeonDomain;
1132 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1133 InstrItinClass itin,
1134 string opc, string asm, list<dag> pattern>
1135 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1136 VFPLdStFrm, itin, opc, asm, "", pattern> {
1137 // Instruction operands.
1141 // Encode instruction operands.
1142 let Inst{23} = addr{8}; // U (add = (U == '1'))
1143 let Inst{22} = Sd{0};
1144 let Inst{19-16} = addr{12-9}; // Rn
1145 let Inst{15-12} = Sd{4-1};
1146 let Inst{7-0} = addr{7-0}; // imm8
1148 // TODO: Mark the instructions with the appropriate subtarget info.
1149 let Inst{27-24} = opcod1;
1150 let Inst{21-20} = opcod2;
1151 let Inst{11-9} = 0b101;
1152 let Inst{8} = 0; // Single precision
1155 // VFP Load / store multiple pseudo instructions.
1156 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1158 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain,
1160 let OutOperandList = oops;
1161 let InOperandList = !con(iops, (ins pred:$p));
1162 let Pattern = pattern;
1163 list<Predicate> Predicates = [HasVFP2];
1166 // Load / store multiple
1167 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1168 string asm, string cstr, list<dag> pattern>
1169 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1170 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1171 // Instruction operands.
1175 // Encode instruction operands.
1176 let Inst{19-16} = Rn;
1177 let Inst{22} = regs{12};
1178 let Inst{15-12} = regs{11-8};
1179 let Inst{7-0} = regs{7-0};
1181 // TODO: Mark the instructions with the appropriate subtarget info.
1182 let Inst{27-25} = 0b110;
1183 let Inst{11-9} = 0b101;
1184 let Inst{8} = 1; // Double precision
1186 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1187 let D = VFPNeonDomain;
1190 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1191 string asm, string cstr, list<dag> pattern>
1192 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1193 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1194 // Instruction operands.
1198 // Encode instruction operands.
1199 let Inst{19-16} = Rn;
1200 let Inst{22} = regs{8};
1201 let Inst{15-12} = regs{12-9};
1202 let Inst{7-0} = regs{7-0};
1204 // TODO: Mark the instructions with the appropriate subtarget info.
1205 let Inst{27-25} = 0b110;
1206 let Inst{11-9} = 0b101;
1207 let Inst{8} = 0; // Single precision
1210 // Double precision, unary
1211 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1212 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1213 string asm, list<dag> pattern>
1214 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1215 // Instruction operands.
1219 // Encode instruction operands.
1220 let Inst{3-0} = Dm{3-0};
1221 let Inst{5} = Dm{4};
1222 let Inst{15-12} = Dd{3-0};
1223 let Inst{22} = Dd{4};
1225 let Inst{27-23} = opcod1;
1226 let Inst{21-20} = opcod2;
1227 let Inst{19-16} = opcod3;
1228 let Inst{11-9} = 0b101;
1229 let Inst{8} = 1; // Double precision
1230 let Inst{7-6} = opcod4;
1231 let Inst{4} = opcod5;
1234 // Double precision, binary
1235 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1236 dag iops, InstrItinClass itin, string opc, string asm,
1238 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1239 // Instruction operands.
1244 // Encode instruction operands.
1245 let Inst{3-0} = Dm{3-0};
1246 let Inst{5} = Dm{4};
1247 let Inst{19-16} = Dn{3-0};
1248 let Inst{7} = Dn{4};
1249 let Inst{15-12} = Dd{3-0};
1250 let Inst{22} = Dd{4};
1252 let Inst{27-23} = opcod1;
1253 let Inst{21-20} = opcod2;
1254 let Inst{11-9} = 0b101;
1255 let Inst{8} = 1; // Double precision
1260 // Single precision, unary
1261 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1262 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1263 string asm, list<dag> pattern>
1264 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1265 // Instruction operands.
1269 // Encode instruction operands.
1270 let Inst{3-0} = Sm{4-1};
1271 let Inst{5} = Sm{0};
1272 let Inst{15-12} = Sd{4-1};
1273 let Inst{22} = Sd{0};
1275 let Inst{27-23} = opcod1;
1276 let Inst{21-20} = opcod2;
1277 let Inst{19-16} = opcod3;
1278 let Inst{11-9} = 0b101;
1279 let Inst{8} = 0; // Single precision
1280 let Inst{7-6} = opcod4;
1281 let Inst{4} = opcod5;
1284 // Single precision unary, if no NEON
1285 // Same as ASuI except not available if NEON is enabled
1286 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1287 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1288 string asm, list<dag> pattern>
1289 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1291 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1294 // Single precision, binary
1295 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1296 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1297 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1298 // Instruction operands.
1303 // Encode instruction operands.
1304 let Inst{3-0} = Sm{4-1};
1305 let Inst{5} = Sm{0};
1306 let Inst{19-16} = Sn{4-1};
1307 let Inst{7} = Sn{0};
1308 let Inst{15-12} = Sd{4-1};
1309 let Inst{22} = Sd{0};
1311 let Inst{27-23} = opcod1;
1312 let Inst{21-20} = opcod2;
1313 let Inst{11-9} = 0b101;
1314 let Inst{8} = 0; // Single precision
1319 // Single precision binary, if no NEON
1320 // Same as ASbI except not available if NEON is enabled
1321 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1322 dag iops, InstrItinClass itin, string opc, string asm,
1324 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1325 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1327 // Instruction operands.
1332 // Encode instruction operands.
1333 let Inst{3-0} = Sm{4-1};
1334 let Inst{5} = Sm{0};
1335 let Inst{19-16} = Sn{4-1};
1336 let Inst{7} = Sn{0};
1337 let Inst{15-12} = Sd{4-1};
1338 let Inst{22} = Sd{0};
1341 // VFP conversion instructions
1342 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1343 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1345 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1346 let Inst{27-23} = opcod1;
1347 let Inst{21-20} = opcod2;
1348 let Inst{19-16} = opcod3;
1349 let Inst{11-8} = opcod4;
1354 // VFP conversion between floating-point and fixed-point
1355 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1356 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1358 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1359 // size (fixed-point number): sx == 0 ? 16 : 32
1360 let Inst{7} = op5; // sx
1363 // VFP conversion instructions, if no NEON
1364 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1365 dag oops, dag iops, InstrItinClass itin,
1366 string opc, string asm, list<dag> pattern>
1367 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1369 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1372 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1373 InstrItinClass itin,
1374 string opc, string asm, list<dag> pattern>
1375 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1376 let Inst{27-20} = opcod1;
1377 let Inst{11-8} = opcod2;
1381 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1382 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1383 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1385 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1386 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1387 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1389 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1390 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1391 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1393 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1394 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1395 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1397 //===----------------------------------------------------------------------===//
1399 //===----------------------------------------------------------------------===//
1400 // ARM NEON Instruction templates.
1403 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1404 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1406 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1407 let OutOperandList = oops;
1408 let InOperandList = !con(iops, (ins pred:$p));
1409 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1410 let Pattern = pattern;
1411 list<Predicate> Predicates = [HasNEON];
1414 // Same as NeonI except it does not have a "data type" specifier.
1415 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1416 InstrItinClass itin, string opc, string asm, string cstr,
1418 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1419 let OutOperandList = oops;
1420 let InOperandList = !con(iops, (ins pred:$p));
1421 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1422 let Pattern = pattern;
1423 list<Predicate> Predicates = [HasNEON];
1426 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1427 dag oops, dag iops, InstrItinClass itin,
1428 string opc, string dt, string asm, string cstr, list<dag> pattern>
1429 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1431 let Inst{31-24} = 0b11110100;
1432 let Inst{23} = op23;
1433 let Inst{21-20} = op21_20;
1434 let Inst{11-8} = op11_8;
1435 let Inst{7-4} = op7_4;
1437 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1443 let Inst{22} = Vd{4};
1444 let Inst{15-12} = Vd{3-0};
1445 let Inst{19-16} = Rn{3-0};
1446 let Inst{3-0} = Rm{3-0};
1449 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1450 dag oops, dag iops, InstrItinClass itin,
1451 string opc, string dt, string asm, string cstr, list<dag> pattern>
1452 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1453 dt, asm, cstr, pattern> {
1457 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1458 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1460 let OutOperandList = oops;
1461 let InOperandList = !con(iops, (ins pred:$p));
1462 list<Predicate> Predicates = [HasNEON];
1465 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1467 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1469 let OutOperandList = oops;
1470 let InOperandList = !con(iops, (ins pred:$p));
1471 let Pattern = pattern;
1472 list<Predicate> Predicates = [HasNEON];
1475 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1476 string opc, string dt, string asm, string cstr, list<dag> pattern>
1477 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1479 let Inst{31-25} = 0b1111001;
1480 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1483 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1484 string opc, string asm, string cstr, list<dag> pattern>
1485 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1487 let Inst{31-25} = 0b1111001;
1490 // NEON "one register and a modified immediate" format.
1491 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1493 dag oops, dag iops, InstrItinClass itin,
1494 string opc, string dt, string asm, string cstr,
1496 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1497 let Inst{23} = op23;
1498 let Inst{21-19} = op21_19;
1499 let Inst{11-8} = op11_8;
1505 // Instruction operands.
1509 let Inst{15-12} = Vd{3-0};
1510 let Inst{22} = Vd{4};
1511 let Inst{24} = SIMM{7};
1512 let Inst{18-16} = SIMM{6-4};
1513 let Inst{3-0} = SIMM{3-0};
1516 // NEON 2 vector register format.
1517 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1518 bits<5> op11_7, bit op6, bit op4,
1519 dag oops, dag iops, InstrItinClass itin,
1520 string opc, string dt, string asm, string cstr, list<dag> pattern>
1521 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1522 let Inst{24-23} = op24_23;
1523 let Inst{21-20} = op21_20;
1524 let Inst{19-18} = op19_18;
1525 let Inst{17-16} = op17_16;
1526 let Inst{11-7} = op11_7;
1530 // Instruction operands.
1534 let Inst{15-12} = Vd{3-0};
1535 let Inst{22} = Vd{4};
1536 let Inst{3-0} = Vm{3-0};
1537 let Inst{5} = Vm{4};
1540 // Same as N2V except it doesn't have a datatype suffix.
1541 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1542 bits<5> op11_7, bit op6, bit op4,
1543 dag oops, dag iops, InstrItinClass itin,
1544 string opc, string asm, string cstr, list<dag> pattern>
1545 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1546 let Inst{24-23} = op24_23;
1547 let Inst{21-20} = op21_20;
1548 let Inst{19-18} = op19_18;
1549 let Inst{17-16} = op17_16;
1550 let Inst{11-7} = op11_7;
1554 // Instruction operands.
1558 let Inst{15-12} = Vd{3-0};
1559 let Inst{22} = Vd{4};
1560 let Inst{3-0} = Vm{3-0};
1561 let Inst{5} = Vm{4};
1564 // NEON 2 vector register with immediate.
1565 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1566 dag oops, dag iops, Format f, InstrItinClass itin,
1567 string opc, string dt, string asm, string cstr, list<dag> pattern>
1568 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1569 let Inst{24} = op24;
1570 let Inst{23} = op23;
1571 let Inst{11-8} = op11_8;
1576 // Instruction operands.
1581 let Inst{15-12} = Vd{3-0};
1582 let Inst{22} = Vd{4};
1583 let Inst{3-0} = Vm{3-0};
1584 let Inst{5} = Vm{4};
1585 let Inst{21-16} = SIMM{5-0};
1588 // NEON 3 vector register format.
1589 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1590 dag oops, dag iops, Format f, InstrItinClass itin,
1591 string opc, string dt, string asm, string cstr, list<dag> pattern>
1592 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1593 let Inst{24} = op24;
1594 let Inst{23} = op23;
1595 let Inst{21-20} = op21_20;
1596 let Inst{11-8} = op11_8;
1600 // Instruction operands.
1605 let Inst{15-12} = Vd{3-0};
1606 let Inst{22} = Vd{4};
1607 let Inst{19-16} = Vn{3-0};
1608 let Inst{7} = Vn{4};
1609 let Inst{3-0} = Vm{3-0};
1610 let Inst{5} = Vm{4};
1613 // Same as N3V except it doesn't have a data type suffix.
1614 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1616 dag oops, dag iops, Format f, InstrItinClass itin,
1617 string opc, string asm, string cstr, list<dag> pattern>
1618 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1619 let Inst{24} = op24;
1620 let Inst{23} = op23;
1621 let Inst{21-20} = op21_20;
1622 let Inst{11-8} = op11_8;
1626 // Instruction operands.
1631 let Inst{15-12} = Vd{3-0};
1632 let Inst{22} = Vd{4};
1633 let Inst{19-16} = Vn{3-0};
1634 let Inst{7} = Vn{4};
1635 let Inst{3-0} = Vm{3-0};
1636 let Inst{5} = Vm{4};
1639 // NEON VMOVs between scalar and core registers.
1640 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1641 dag oops, dag iops, Format f, InstrItinClass itin,
1642 string opc, string dt, string asm, list<dag> pattern>
1643 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain,
1645 let Inst{27-20} = opcod1;
1646 let Inst{11-8} = opcod2;
1647 let Inst{6-5} = opcod3;
1650 let OutOperandList = oops;
1651 let InOperandList = !con(iops, (ins pred:$p));
1652 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1653 let Pattern = pattern;
1654 list<Predicate> Predicates = [HasNEON];
1656 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1663 let Inst{31-28} = p{3-0};
1665 let Inst{19-16} = V{3-0};
1666 let Inst{15-12} = R{3-0};
1668 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1669 dag oops, dag iops, InstrItinClass itin,
1670 string opc, string dt, string asm, list<dag> pattern>
1671 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1672 opc, dt, asm, pattern>;
1673 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1674 dag oops, dag iops, InstrItinClass itin,
1675 string opc, string dt, string asm, list<dag> pattern>
1676 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1677 opc, dt, asm, pattern>;
1678 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1679 dag oops, dag iops, InstrItinClass itin,
1680 string opc, string dt, string asm, list<dag> pattern>
1681 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1682 opc, dt, asm, pattern>;
1684 // Vector Duplicate Lane (from scalar to all elements)
1685 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1686 InstrItinClass itin, string opc, string dt, string asm,
1688 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1689 let Inst{24-23} = 0b11;
1690 let Inst{21-20} = 0b11;
1691 let Inst{19-16} = op19_16;
1692 let Inst{11-7} = 0b11000;
1700 let Inst{22} = Vd{4};
1701 let Inst{15-12} = Vd{3-0};
1702 let Inst{5} = Vm{4};
1703 let Inst{3-0} = Vm{3-0};
1706 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1707 // for single-precision FP.
1708 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1709 list<Predicate> Predicates = [HasNEON,UseNEONForFP];