1 //===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
71 def DPSoRegImmFrm : Format<42>;
75 // The instruction has an Rn register operand.
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
77 // it doesn't have a Rn operand.
78 class UnaryDP { bit isUnaryDataProc = 1; }
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
82 class Xform16Bit { bit canXformTo16Bit = 1; }
84 //===----------------------------------------------------------------------===//
85 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 // FIXME: Once the JIT is MC-ized, these can go away.
90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>;
102 def AddrModeT1_4 : AddrMode<9>;
103 def AddrModeT1_s : AddrMode<10>;
104 def AddrModeT2_i12 : AddrMode<11>;
105 def AddrModeT2_i8 : AddrMode<12>;
106 def AddrModeT2_so : AddrMode<13>;
107 def AddrModeT2_pc : AddrMode<14>;
108 def AddrModeT2_i8s4 : AddrMode<15>;
109 def AddrMode_i12 : AddrMode<16>;
111 // Load / store index mode.
112 class IndexMode<bits<2> val> {
115 def IndexModeNone : IndexMode<0>;
116 def IndexModePre : IndexMode<1>;
117 def IndexModePost : IndexMode<2>;
118 def IndexModeUpd : IndexMode<3>;
120 // Instruction execution domain.
121 class Domain<bits<3> val> {
124 def GenericDomain : Domain<0>;
125 def VFPDomain : Domain<1>; // Instructions in VFP domain only
126 def NeonDomain : Domain<2>; // Instructions in Neon domain only
127 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
128 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
130 //===----------------------------------------------------------------------===//
131 // ARM special operands.
134 // ARM imod and iflag operands, used only by the CPS instruction.
135 def imod_op : Operand<i32> {
136 let PrintMethod = "printCPSIMod";
139 def ProcIFlagsOperand : AsmOperandClass {
140 let Name = "ProcIFlags";
141 let ParserMethod = "parseProcIFlagsOperand";
143 def iflags_op : Operand<i32> {
144 let PrintMethod = "printCPSIFlag";
145 let ParserMatchClass = ProcIFlagsOperand;
148 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
149 // register whose default is 0 (no register).
150 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
151 def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
152 (ops (i32 14), (i32 zero_reg))> {
153 let PrintMethod = "printPredicateOperand";
154 let ParserMatchClass = CondCodeOperand;
155 let DecoderMethod = "DecodePredicateOperand";
158 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
159 def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
160 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
161 let EncoderMethod = "getCCOutOpValue";
162 let PrintMethod = "printSBitModifierOperand";
163 let ParserMatchClass = CCOutOperand;
164 let DecoderMethod = "DecodeCCOutOperand";
167 // Same as cc_out except it defaults to setting CPSR.
168 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
169 let EncoderMethod = "getCCOutOpValue";
170 let PrintMethod = "printSBitModifierOperand";
171 let ParserMatchClass = CCOutOperand;
172 let DecoderMethod = "DecodeCCOutOperand";
175 // ARM special operands for disassembly only.
177 def SetEndAsmOperand : ImmAsmOperand {
178 let Name = "SetEndImm";
179 let ParserMethod = "parseSetEndImm";
181 def setend_op : Operand<i32> {
182 let PrintMethod = "printSetendOperand";
183 let ParserMatchClass = SetEndAsmOperand;
186 def MSRMaskOperand : AsmOperandClass {
187 let Name = "MSRMask";
188 let ParserMethod = "parseMSRMaskOperand";
190 def msr_mask : Operand<i32> {
191 let PrintMethod = "printMSRMaskOperand";
192 let DecoderMethod = "DecodeMSRMask";
193 let ParserMatchClass = MSRMaskOperand;
196 // Shift Right Immediate - A shift right immediate is encoded differently from
197 // other shift immediates. The imm6 field is encoded like so:
200 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
201 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
202 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
203 // 64 64 - <imm> is encoded in imm6<5:0>
204 def shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; }
205 def shr_imm8 : Operand<i32> {
206 let EncoderMethod = "getShiftRight8Imm";
207 let DecoderMethod = "DecodeShiftRight8Imm";
208 let ParserMatchClass = shr_imm8_asm_operand;
210 def shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; }
211 def shr_imm16 : Operand<i32> {
212 let EncoderMethod = "getShiftRight16Imm";
213 let DecoderMethod = "DecodeShiftRight16Imm";
214 let ParserMatchClass = shr_imm16_asm_operand;
216 def shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; }
217 def shr_imm32 : Operand<i32> {
218 let EncoderMethod = "getShiftRight32Imm";
219 let DecoderMethod = "DecodeShiftRight32Imm";
220 let ParserMatchClass = shr_imm32_asm_operand;
222 def shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; }
223 def shr_imm64 : Operand<i32> {
224 let EncoderMethod = "getShiftRight64Imm";
225 let DecoderMethod = "DecodeShiftRight64Imm";
226 let ParserMatchClass = shr_imm64_asm_operand;
229 //===----------------------------------------------------------------------===//
230 // ARM Assembler alias templates.
232 class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1>
233 : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>;
234 class tInstAlias<string Asm, dag Result, bit Emit = 0b1>
235 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>;
236 class t2InstAlias<string Asm, dag Result, bit Emit = 0b1>
237 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>;
238 class VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1>
239 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>;
240 class VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1>
241 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>;
242 class NEONInstAlias<string Asm, dag Result, bit Emit = 0b1>
243 : InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>;
246 class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
248 class NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
251 //===----------------------------------------------------------------------===//
252 // ARM Instruction templates.
256 class InstTemplate<AddrMode am, int sz, IndexMode im,
257 Format f, Domain d, string cstr, InstrItinClass itin>
259 let Namespace = "ARM";
264 bits<2> IndexModeBits = IM.Value;
266 bits<6> Form = F.Value;
268 bit isUnaryDataProc = 0;
269 bit canXformTo16Bit = 0;
270 // The instruction is a 16-bit flag setting Thumb instruction. Used
271 // by the parser to determine whether to require the 'S' suffix on the
272 // mnemonic (when not in an IT block) or preclude it (when in an IT block).
273 bit thumbArithFlagSetting = 0;
275 // If this is a pseudo instruction, mark it isCodeGenOnly.
276 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
278 // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
279 let TSFlags{4-0} = AM.Value;
280 let TSFlags{6-5} = IndexModeBits;
281 let TSFlags{12-7} = Form;
282 let TSFlags{13} = isUnaryDataProc;
283 let TSFlags{14} = canXformTo16Bit;
284 let TSFlags{17-15} = D.Value;
285 let TSFlags{18} = thumbArithFlagSetting;
287 let Constraints = cstr;
288 let Itinerary = itin;
295 class InstARM<AddrMode am, int sz, IndexMode im,
296 Format f, Domain d, string cstr, InstrItinClass itin>
297 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
298 let DecoderNamespace = "ARM";
301 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
302 // on by adding flavors to specific instructions.
303 class InstThumb<AddrMode am, int sz, IndexMode im,
304 Format f, Domain d, string cstr, InstrItinClass itin>
305 : InstTemplate<am, sz, im, f, d, cstr, itin> {
306 let DecoderNamespace = "Thumb";
309 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
310 // These are aliases that require C++ handling to convert to the target
311 // instruction, while InstAliases can be handled directly by tblgen.
312 class AsmPseudoInst<string asm, dag iops>
313 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
315 let OutOperandList = (outs);
316 let InOperandList = iops;
318 let isCodeGenOnly = 0; // So we get asm matcher for it.
323 class ARMAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
325 class tAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
327 class t2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
328 Requires<[IsThumb2]>;
329 class VFP2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
331 class NEONAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
334 // Pseudo instructions for the code generator.
335 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
336 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
337 GenericDomain, "", itin> {
338 let OutOperandList = oops;
339 let InOperandList = iops;
340 let Pattern = pattern;
341 let isCodeGenOnly = 1;
345 // PseudoInst that's ARM-mode only.
346 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
348 : PseudoInst<oops, iops, itin, pattern> {
350 list<Predicate> Predicates = [IsARM];
353 // PseudoInst that's Thumb-mode only.
354 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
356 : PseudoInst<oops, iops, itin, pattern> {
358 list<Predicate> Predicates = [IsThumb];
361 // PseudoInst that's Thumb2-mode only.
362 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
364 : PseudoInst<oops, iops, itin, pattern> {
366 list<Predicate> Predicates = [IsThumb2];
369 class ARMPseudoExpand<dag oops, dag iops, int sz,
370 InstrItinClass itin, list<dag> pattern,
372 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
373 PseudoInstExpansion<Result>;
375 class tPseudoExpand<dag oops, dag iops, int sz,
376 InstrItinClass itin, list<dag> pattern,
378 : tPseudoInst<oops, iops, sz, itin, pattern>,
379 PseudoInstExpansion<Result>;
381 class t2PseudoExpand<dag oops, dag iops, int sz,
382 InstrItinClass itin, list<dag> pattern,
384 : t2PseudoInst<oops, iops, sz, itin, pattern>,
385 PseudoInstExpansion<Result>;
387 // Almost all ARM instructions are predicable.
388 class I<dag oops, dag iops, AddrMode am, int sz,
389 IndexMode im, Format f, InstrItinClass itin,
390 string opc, string asm, string cstr,
392 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
395 let OutOperandList = oops;
396 let InOperandList = !con(iops, (ins pred:$p));
397 let AsmString = !strconcat(opc, "${p}", asm);
398 let Pattern = pattern;
399 list<Predicate> Predicates = [IsARM];
402 // A few are not predicable
403 class InoP<dag oops, dag iops, AddrMode am, int sz,
404 IndexMode im, Format f, InstrItinClass itin,
405 string opc, string asm, string cstr,
407 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
408 let OutOperandList = oops;
409 let InOperandList = iops;
410 let AsmString = !strconcat(opc, asm);
411 let Pattern = pattern;
412 let isPredicable = 0;
413 list<Predicate> Predicates = [IsARM];
416 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
417 // operand since by default it's a zero register. It will become an implicit def
418 // once it's "flipped".
419 class sI<dag oops, dag iops, AddrMode am, int sz,
420 IndexMode im, Format f, InstrItinClass itin,
421 string opc, string asm, string cstr,
423 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
424 bits<4> p; // Predicate operand
425 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
429 let OutOperandList = oops;
430 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
431 let AsmString = !strconcat(opc, "${s}${p}", asm);
432 let Pattern = pattern;
433 list<Predicate> Predicates = [IsARM];
437 class XI<dag oops, dag iops, AddrMode am, int sz,
438 IndexMode im, Format f, InstrItinClass itin,
439 string asm, string cstr, list<dag> pattern>
440 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
441 let OutOperandList = oops;
442 let InOperandList = iops;
444 let Pattern = pattern;
445 list<Predicate> Predicates = [IsARM];
448 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
449 string opc, string asm, list<dag> pattern>
450 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
451 opc, asm, "", pattern>;
452 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
453 string opc, string asm, list<dag> pattern>
454 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
455 opc, asm, "", pattern>;
456 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
457 string asm, list<dag> pattern>
458 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
460 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
461 string opc, string asm, list<dag> pattern>
462 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
463 opc, asm, "", pattern>;
465 // Ctrl flow instructions
466 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
467 string opc, string asm, list<dag> pattern>
468 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
469 opc, asm, "", pattern> {
470 let Inst{27-24} = opcod;
472 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
473 string asm, list<dag> pattern>
474 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
476 let Inst{27-24} = opcod;
479 // BR_JT instructions
480 class JTI<dag oops, dag iops, InstrItinClass itin,
481 string asm, list<dag> pattern>
482 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
485 // Atomic load/store instructions
486 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
487 string opc, string asm, list<dag> pattern>
488 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
489 opc, asm, "", pattern> {
492 let Inst{27-23} = 0b00011;
493 let Inst{22-21} = opcod;
495 let Inst{19-16} = addr;
496 let Inst{15-12} = Rt;
497 let Inst{11-0} = 0b111110011111;
499 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
500 string opc, string asm, list<dag> pattern>
501 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
502 opc, asm, "", pattern> {
506 let Inst{27-23} = 0b00011;
507 let Inst{22-21} = opcod;
509 let Inst{19-16} = addr;
510 let Inst{15-12} = Rd;
511 let Inst{11-4} = 0b11111001;
514 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
515 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
519 let Inst{27-23} = 0b00010;
521 let Inst{21-20} = 0b00;
522 let Inst{19-16} = addr;
523 let Inst{15-12} = Rt;
524 let Inst{11-4} = 0b00001001;
527 let DecoderMethod = "DecodeSwap";
530 // addrmode1 instructions
531 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
532 string opc, string asm, list<dag> pattern>
533 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
534 opc, asm, "", pattern> {
535 let Inst{24-21} = opcod;
536 let Inst{27-26} = 0b00;
538 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
539 string opc, string asm, list<dag> pattern>
540 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
541 opc, asm, "", pattern> {
542 let Inst{24-21} = opcod;
543 let Inst{27-26} = 0b00;
545 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
546 string asm, list<dag> pattern>
547 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
549 let Inst{24-21} = opcod;
550 let Inst{27-26} = 0b00;
555 // LDR/LDRB/STR/STRB/...
556 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
557 Format f, InstrItinClass itin, string opc, string asm,
559 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
561 let Inst{27-25} = op;
562 let Inst{24} = 1; // 24 == P
564 let Inst{22} = isByte;
565 let Inst{21} = 0; // 21 == W
568 // Indexed load/stores
569 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
570 IndexMode im, Format f, InstrItinClass itin, string opc,
571 string asm, string cstr, list<dag> pattern>
572 : I<oops, iops, AddrMode2, 4, im, f, itin,
573 opc, asm, cstr, pattern> {
575 let Inst{27-26} = 0b01;
576 let Inst{24} = isPre; // P bit
577 let Inst{22} = isByte; // B bit
578 let Inst{21} = isPre; // W bit
579 let Inst{20} = isLd; // L bit
580 let Inst{15-12} = Rt;
582 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
583 IndexMode im, Format f, InstrItinClass itin, string opc,
584 string asm, string cstr, list<dag> pattern>
585 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
587 // AM2 store w/ two operands: (GPR, am2offset)
593 let Inst{23} = offset{12};
594 let Inst{19-16} = Rn;
595 let Inst{11-5} = offset{11-5};
597 let Inst{3-0} = offset{3-0};
600 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
601 IndexMode im, Format f, InstrItinClass itin, string opc,
602 string asm, string cstr, list<dag> pattern>
603 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
605 // AM2 store w/ two operands: (GPR, am2offset)
611 let Inst{23} = offset{12};
612 let Inst{19-16} = Rn;
613 let Inst{11-0} = offset{11-0};
617 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
618 // but for now use this class for STRT and STRBT.
619 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
620 IndexMode im, Format f, InstrItinClass itin, string opc,
621 string asm, string cstr, list<dag> pattern>
622 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
624 // AM2 store w/ two operands: (GPR, am2offset)
626 // {13} 1 == Rm, 0 == imm12
630 let Inst{25} = addr{13};
631 let Inst{23} = addr{12};
632 let Inst{19-16} = addr{17-14};
633 let Inst{11-0} = addr{11-0};
636 // addrmode3 instructions
637 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
638 InstrItinClass itin, string opc, string asm, list<dag> pattern>
639 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
640 opc, asm, "", pattern> {
643 let Inst{27-25} = 0b000;
644 let Inst{24} = 1; // P bit
645 let Inst{23} = addr{8}; // U bit
646 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
647 let Inst{21} = 0; // W bit
648 let Inst{20} = op20; // L bit
649 let Inst{19-16} = addr{12-9}; // Rn
650 let Inst{15-12} = Rt; // Rt
651 let Inst{11-8} = addr{7-4}; // imm7_4/zero
653 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
655 let DecoderMethod = "DecodeAddrMode3Instruction";
658 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
659 IndexMode im, Format f, InstrItinClass itin, string opc,
660 string asm, string cstr, list<dag> pattern>
661 : I<oops, iops, AddrMode3, 4, im, f, itin,
662 opc, asm, cstr, pattern> {
664 let Inst{27-25} = 0b000;
665 let Inst{24} = isPre; // P bit
666 let Inst{21} = isPre; // W bit
667 let Inst{20} = op20; // L bit
668 let Inst{15-12} = Rt; // Rt
672 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
673 // but for now use this class for LDRSBT, LDRHT, LDSHT.
674 class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
675 IndexMode im, Format f, InstrItinClass itin, string opc,
676 string asm, string cstr, list<dag> pattern>
677 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> {
678 // {13} 1 == imm8, 0 == Rm
685 let Inst{27-25} = 0b000;
686 let Inst{24} = 0; // P bit
688 let Inst{20} = isLoad; // L bit
689 let Inst{19-16} = addr; // Rn
690 let Inst{15-12} = Rt; // Rt
695 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
696 string opc, string asm, list<dag> pattern>
697 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
698 opc, asm, "", pattern> {
701 let Inst{27-25} = 0b000;
702 let Inst{24} = 1; // P bit
703 let Inst{23} = addr{8}; // U bit
704 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
705 let Inst{21} = 0; // W bit
706 let Inst{20} = 0; // L bit
707 let Inst{19-16} = addr{12-9}; // Rn
708 let Inst{15-12} = Rt; // Rt
709 let Inst{11-8} = addr{7-4}; // imm7_4/zero
711 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
712 let DecoderMethod = "DecodeAddrMode3Instruction";
715 // addrmode4 instructions
716 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
717 string asm, string cstr, list<dag> pattern>
718 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
723 let Inst{27-25} = 0b100;
724 let Inst{22} = 0; // S bit
725 let Inst{19-16} = Rn;
726 let Inst{15-0} = regs;
729 // Unsigned multiply, multiply-accumulate instructions.
730 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
731 string opc, string asm, list<dag> pattern>
732 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
733 opc, asm, "", pattern> {
734 let Inst{7-4} = 0b1001;
735 let Inst{20} = 0; // S bit
736 let Inst{27-21} = opcod;
738 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
739 string opc, string asm, list<dag> pattern>
740 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
741 opc, asm, "", pattern> {
742 let Inst{7-4} = 0b1001;
743 let Inst{27-21} = opcod;
746 // Most significant word multiply
747 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
748 InstrItinClass itin, string opc, string asm, list<dag> pattern>
749 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
750 opc, asm, "", pattern> {
754 let Inst{7-4} = opc7_4;
756 let Inst{27-21} = opcod;
757 let Inst{19-16} = Rd;
761 // MSW multiple w/ Ra operand
762 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
763 InstrItinClass itin, string opc, string asm, list<dag> pattern>
764 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
766 let Inst{15-12} = Ra;
769 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
770 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
771 InstrItinClass itin, string opc, string asm, list<dag> pattern>
772 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
773 opc, asm, "", pattern> {
779 let Inst{27-21} = opcod;
780 let Inst{6-5} = bit6_5;
784 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
785 InstrItinClass itin, string opc, string asm, list<dag> pattern>
786 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
788 let Inst{19-16} = Rd;
791 // AMulxyI with Ra operand
792 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
793 InstrItinClass itin, string opc, string asm, list<dag> pattern>
794 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
796 let Inst{15-12} = Ra;
799 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
800 InstrItinClass itin, string opc, string asm, list<dag> pattern>
801 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
804 let Inst{19-16} = RdHi;
805 let Inst{15-12} = RdLo;
808 // Extend instructions.
809 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
810 string opc, string asm, list<dag> pattern>
811 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
812 opc, asm, "", pattern> {
813 // All AExtI instructions have Rd and Rm register operands.
816 let Inst{15-12} = Rd;
818 let Inst{7-4} = 0b0111;
819 let Inst{9-8} = 0b00;
820 let Inst{27-20} = opcod;
823 // Misc Arithmetic instructions.
824 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
825 InstrItinClass itin, string opc, string asm, list<dag> pattern>
826 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
827 opc, asm, "", pattern> {
830 let Inst{27-20} = opcod;
831 let Inst{19-16} = 0b1111;
832 let Inst{15-12} = Rd;
833 let Inst{11-8} = 0b1111;
834 let Inst{7-4} = opc7_4;
839 def PKHLSLAsmOperand : ImmAsmOperand {
840 let Name = "PKHLSLImm";
841 let ParserMethod = "parsePKHLSLImm";
843 def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
844 let PrintMethod = "printPKHLSLShiftImm";
845 let ParserMatchClass = PKHLSLAsmOperand;
847 def PKHASRAsmOperand : AsmOperandClass {
848 let Name = "PKHASRImm";
849 let ParserMethod = "parsePKHASRImm";
851 def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
852 let PrintMethod = "printPKHASRShiftImm";
853 let ParserMatchClass = PKHASRAsmOperand;
856 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
857 string opc, string asm, list<dag> pattern>
858 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
859 opc, asm, "", pattern> {
864 let Inst{27-20} = opcod;
865 let Inst{19-16} = Rn;
866 let Inst{15-12} = Rd;
869 let Inst{5-4} = 0b01;
873 //===----------------------------------------------------------------------===//
875 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
876 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
877 list<Predicate> Predicates = [IsARM];
879 class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
880 list<Predicate> Predicates = [IsARM, HasV5T];
882 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
883 list<Predicate> Predicates = [IsARM, HasV5TE];
885 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
886 list<Predicate> Predicates = [IsARM, HasV6];
889 //===----------------------------------------------------------------------===//
890 // Thumb Instruction Format Definitions.
893 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
894 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
895 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
896 let OutOperandList = oops;
897 let InOperandList = iops;
899 let Pattern = pattern;
900 list<Predicate> Predicates = [IsThumb];
903 // TI - Thumb instruction.
904 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
905 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
907 // Two-address instructions
908 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
910 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
913 // tBL, tBX 32-bit instructions
914 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
915 dag oops, dag iops, InstrItinClass itin, string asm,
917 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
919 let Inst{31-27} = opcod1;
920 let Inst{15-14} = opcod2;
921 let Inst{12} = opcod3;
924 // BR_JT instructions
925 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
927 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
930 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
931 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
932 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
933 let OutOperandList = oops;
934 let InOperandList = iops;
936 let Pattern = pattern;
937 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
940 class T1I<dag oops, dag iops, InstrItinClass itin,
941 string asm, list<dag> pattern>
942 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
943 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
944 string asm, list<dag> pattern>
945 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
947 // Two-address instructions
948 class T1It<dag oops, dag iops, InstrItinClass itin,
949 string asm, string cstr, list<dag> pattern>
950 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
953 // Thumb1 instruction that can either be predicated or set CPSR.
954 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
956 string opc, string asm, string cstr, list<dag> pattern>
957 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
958 let OutOperandList = !con(oops, (outs s_cc_out:$s));
959 let InOperandList = !con(iops, (ins pred:$p));
960 let AsmString = !strconcat(opc, "${s}${p}", asm);
961 let Pattern = pattern;
962 let thumbArithFlagSetting = 1;
963 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
964 let DecoderNamespace = "ThumbSBit";
967 class T1sI<dag oops, dag iops, InstrItinClass itin,
968 string opc, string asm, list<dag> pattern>
969 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
971 // Two-address instructions
972 class T1sIt<dag oops, dag iops, InstrItinClass itin,
973 string opc, string asm, list<dag> pattern>
974 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
975 "$Rn = $Rdn", pattern>;
977 // Thumb1 instruction that can be predicated.
978 class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
980 string opc, string asm, string cstr, list<dag> pattern>
981 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
982 let OutOperandList = oops;
983 let InOperandList = !con(iops, (ins pred:$p));
984 let AsmString = !strconcat(opc, "${p}", asm);
985 let Pattern = pattern;
986 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
989 class T1pI<dag oops, dag iops, InstrItinClass itin,
990 string opc, string asm, list<dag> pattern>
991 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
993 // Two-address instructions
994 class T1pIt<dag oops, dag iops, InstrItinClass itin,
995 string opc, string asm, list<dag> pattern>
996 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
997 "$Rn = $Rdn", pattern>;
999 class T1pIs<dag oops, dag iops,
1000 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1001 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
1003 class Encoding16 : Encoding {
1004 let Inst{31-16} = 0x0000;
1007 // A6.2 16-bit Thumb instruction encoding
1008 class T1Encoding<bits<6> opcode> : Encoding16 {
1009 let Inst{15-10} = opcode;
1012 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1013 class T1General<bits<5> opcode> : Encoding16 {
1014 let Inst{15-14} = 0b00;
1015 let Inst{13-9} = opcode;
1018 // A6.2.2 Data-processing encoding.
1019 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1020 let Inst{15-10} = 0b010000;
1021 let Inst{9-6} = opcode;
1024 // A6.2.3 Special data instructions and branch and exchange encoding.
1025 class T1Special<bits<4> opcode> : Encoding16 {
1026 let Inst{15-10} = 0b010001;
1027 let Inst{9-6} = opcode;
1030 // A6.2.4 Load/store single data item encoding.
1031 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1032 let Inst{15-12} = opA;
1033 let Inst{11-9} = opB;
1035 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1037 class T1BranchCond<bits<4> opcode> : Encoding16 {
1038 let Inst{15-12} = opcode;
1041 // Helper classes to encode Thumb1 loads and stores. For immediates, the
1042 // following bits are used for "opA" (see A6.2.4):
1044 // 0b0110 => Immediate, 4 bytes
1045 // 0b1000 => Immediate, 2 bytes
1046 // 0b0111 => Immediate, 1 byte
1047 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1048 InstrItinClass itin, string opc, string asm,
1050 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1051 T1LoadStore<0b0101, opcode> {
1054 let Inst{8-6} = addr{5-3}; // Rm
1055 let Inst{5-3} = addr{2-0}; // Rn
1058 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1059 InstrItinClass itin, string opc, string asm,
1061 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1062 T1LoadStore<opA, {opB,?,?}> {
1065 let Inst{10-6} = addr{7-3}; // imm5
1066 let Inst{5-3} = addr{2-0}; // Rn
1070 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1071 class T1Misc<bits<7> opcode> : Encoding16 {
1072 let Inst{15-12} = 0b1011;
1073 let Inst{11-5} = opcode;
1076 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1077 class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
1078 InstrItinClass itin,
1079 string opc, string asm, string cstr, list<dag> pattern>
1080 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1081 let OutOperandList = oops;
1082 let InOperandList = !con(iops, (ins pred:$p));
1083 let AsmString = !strconcat(opc, "${p}", asm);
1084 let Pattern = pattern;
1085 list<Predicate> Predicates = [IsThumb2];
1086 let DecoderNamespace = "Thumb2";
1089 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1090 // input operand since by default it's a zero register. It will become an
1091 // implicit def once it's "flipped".
1093 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1095 class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
1096 InstrItinClass itin,
1097 string opc, string asm, string cstr, list<dag> pattern>
1098 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1099 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1102 let OutOperandList = oops;
1103 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1104 let AsmString = !strconcat(opc, "${s}${p}", asm);
1105 let Pattern = pattern;
1106 list<Predicate> Predicates = [IsThumb2];
1107 let DecoderNamespace = "Thumb2";
1111 class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
1112 InstrItinClass itin,
1113 string asm, string cstr, list<dag> pattern>
1114 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1115 let OutOperandList = oops;
1116 let InOperandList = iops;
1117 let AsmString = asm;
1118 let Pattern = pattern;
1119 list<Predicate> Predicates = [IsThumb2];
1120 let DecoderNamespace = "Thumb2";
1123 class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
1124 InstrItinClass itin,
1125 string asm, string cstr, list<dag> pattern>
1126 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1127 let OutOperandList = oops;
1128 let InOperandList = iops;
1129 let AsmString = asm;
1130 let Pattern = pattern;
1131 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1132 let DecoderNamespace = "Thumb";
1135 class T2I<dag oops, dag iops, InstrItinClass itin,
1136 string opc, string asm, list<dag> pattern>
1137 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1138 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1139 string opc, string asm, list<dag> pattern>
1140 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
1141 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1142 string opc, string asm, list<dag> pattern>
1143 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
1144 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1145 string opc, string asm, list<dag> pattern>
1146 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
1147 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1148 string opc, string asm, list<dag> pattern>
1149 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
1150 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1151 string opc, string asm, string cstr, list<dag> pattern>
1152 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1157 let Inst{31-25} = 0b1110100;
1159 let Inst{23} = addr{8};
1162 let Inst{20} = isLoad;
1163 let Inst{19-16} = addr{12-9};
1164 let Inst{15-12} = Rt{3-0};
1165 let Inst{11-8} = Rt2{3-0};
1166 let Inst{7-0} = addr{7-0};
1168 class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops,
1169 InstrItinClass itin, string opc, string asm, string cstr,
1171 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1177 let Inst{31-25} = 0b1110100;
1179 let Inst{23} = imm{8};
1182 let Inst{20} = isLoad;
1183 let Inst{19-16} = addr;
1184 let Inst{15-12} = Rt{3-0};
1185 let Inst{11-8} = Rt2{3-0};
1186 let Inst{7-0} = imm{7-0};
1189 class T2sI<dag oops, dag iops, InstrItinClass itin,
1190 string opc, string asm, list<dag> pattern>
1191 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1193 class T2XI<dag oops, dag iops, InstrItinClass itin,
1194 string asm, list<dag> pattern>
1195 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1196 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1197 string asm, list<dag> pattern>
1198 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1200 // Move to/from coprocessor instructions
1201 class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern>
1202 : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> {
1203 let Inst{31-28} = opc;
1206 // Two-address instructions
1207 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1208 string asm, string cstr, list<dag> pattern>
1209 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
1211 // T2Ipreldst - Thumb2 pre-indexed load / store instructions.
1212 class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre,
1214 AddrMode am, IndexMode im, InstrItinClass itin,
1215 string opc, string asm, string cstr, list<dag> pattern>
1216 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1217 let OutOperandList = oops;
1218 let InOperandList = !con(iops, (ins pred:$p));
1219 let AsmString = !strconcat(opc, "${p}", asm);
1220 let Pattern = pattern;
1221 list<Predicate> Predicates = [IsThumb2];
1222 let DecoderNamespace = "Thumb2";
1226 let Inst{31-27} = 0b11111;
1227 let Inst{26-25} = 0b00;
1228 let Inst{24} = signed;
1230 let Inst{22-21} = opcod;
1231 let Inst{20} = load;
1232 let Inst{19-16} = addr{12-9};
1233 let Inst{15-12} = Rt{3-0};
1235 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1236 let Inst{10} = pre; // The P bit.
1237 let Inst{9} = addr{8}; // Sign bit
1238 let Inst{8} = 1; // The W bit.
1239 let Inst{7-0} = addr{7-0};
1241 let DecoderMethod = "DecodeT2LdStPre";
1244 // T2Ipostldst - Thumb2 post-indexed load / store instructions.
1245 class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre,
1247 AddrMode am, IndexMode im, InstrItinClass itin,
1248 string opc, string asm, string cstr, list<dag> pattern>
1249 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1250 let OutOperandList = oops;
1251 let InOperandList = !con(iops, (ins pred:$p));
1252 let AsmString = !strconcat(opc, "${p}", asm);
1253 let Pattern = pattern;
1254 list<Predicate> Predicates = [IsThumb2];
1255 let DecoderNamespace = "Thumb2";
1260 let Inst{31-27} = 0b11111;
1261 let Inst{26-25} = 0b00;
1262 let Inst{24} = signed;
1264 let Inst{22-21} = opcod;
1265 let Inst{20} = load;
1266 let Inst{19-16} = Rn;
1267 let Inst{15-12} = Rt{3-0};
1269 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1270 let Inst{10} = pre; // The P bit.
1271 let Inst{9} = offset{8}; // Sign bit
1272 let Inst{8} = 1; // The W bit.
1273 let Inst{7-0} = offset{7-0};
1275 let DecoderMethod = "DecodeT2LdStPre";
1278 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1279 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1280 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1283 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1284 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1285 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1288 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1289 class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1290 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1293 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1294 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1295 list<Predicate> Predicates = [IsThumb2];
1298 //===----------------------------------------------------------------------===//
1300 //===----------------------------------------------------------------------===//
1301 // ARM VFP Instruction templates.
1304 // Almost all VFP instructions are predicable.
1305 class VFPI<dag oops, dag iops, AddrMode am, int sz,
1306 IndexMode im, Format f, InstrItinClass itin,
1307 string opc, string asm, string cstr, list<dag> pattern>
1308 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1310 let Inst{31-28} = p;
1311 let OutOperandList = oops;
1312 let InOperandList = !con(iops, (ins pred:$p));
1313 let AsmString = !strconcat(opc, "${p}", asm);
1314 let Pattern = pattern;
1315 let PostEncoderMethod = "VFPThumb2PostEncoder";
1316 let DecoderNamespace = "VFP";
1317 list<Predicate> Predicates = [HasVFP2];
1321 class VFPXI<dag oops, dag iops, AddrMode am, int sz,
1322 IndexMode im, Format f, InstrItinClass itin,
1323 string asm, string cstr, list<dag> pattern>
1324 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1326 let Inst{31-28} = p;
1327 let OutOperandList = oops;
1328 let InOperandList = iops;
1329 let AsmString = asm;
1330 let Pattern = pattern;
1331 let PostEncoderMethod = "VFPThumb2PostEncoder";
1332 let DecoderNamespace = "VFP";
1333 list<Predicate> Predicates = [HasVFP2];
1336 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1337 string opc, string asm, list<dag> pattern>
1338 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
1339 opc, asm, "", pattern> {
1340 let PostEncoderMethod = "VFPThumb2PostEncoder";
1343 // ARM VFP addrmode5 loads and stores
1344 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1345 InstrItinClass itin,
1346 string opc, string asm, list<dag> pattern>
1347 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1348 VFPLdStFrm, itin, opc, asm, "", pattern> {
1349 // Instruction operands.
1353 // Encode instruction operands.
1354 let Inst{23} = addr{8}; // U (add = (U == '1'))
1355 let Inst{22} = Dd{4};
1356 let Inst{19-16} = addr{12-9}; // Rn
1357 let Inst{15-12} = Dd{3-0};
1358 let Inst{7-0} = addr{7-0}; // imm8
1360 // TODO: Mark the instructions with the appropriate subtarget info.
1361 let Inst{27-24} = opcod1;
1362 let Inst{21-20} = opcod2;
1363 let Inst{11-9} = 0b101;
1364 let Inst{8} = 1; // Double precision
1366 // Loads & stores operate on both NEON and VFP pipelines.
1367 let D = VFPNeonDomain;
1370 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1371 InstrItinClass itin,
1372 string opc, string asm, list<dag> pattern>
1373 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1374 VFPLdStFrm, itin, opc, asm, "", pattern> {
1375 // Instruction operands.
1379 // Encode instruction operands.
1380 let Inst{23} = addr{8}; // U (add = (U == '1'))
1381 let Inst{22} = Sd{0};
1382 let Inst{19-16} = addr{12-9}; // Rn
1383 let Inst{15-12} = Sd{4-1};
1384 let Inst{7-0} = addr{7-0}; // imm8
1386 // TODO: Mark the instructions with the appropriate subtarget info.
1387 let Inst{27-24} = opcod1;
1388 let Inst{21-20} = opcod2;
1389 let Inst{11-9} = 0b101;
1390 let Inst{8} = 0; // Single precision
1392 // Loads & stores operate on both NEON and VFP pipelines.
1393 let D = VFPNeonDomain;
1396 // VFP Load / store multiple pseudo instructions.
1397 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1399 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1401 let OutOperandList = oops;
1402 let InOperandList = !con(iops, (ins pred:$p));
1403 let Pattern = pattern;
1404 list<Predicate> Predicates = [HasVFP2];
1407 // Load / store multiple
1408 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1409 string asm, string cstr, list<dag> pattern>
1410 : VFPXI<oops, iops, AddrMode4, 4, im,
1411 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1412 // Instruction operands.
1416 // Encode instruction operands.
1417 let Inst{19-16} = Rn;
1418 let Inst{22} = regs{12};
1419 let Inst{15-12} = regs{11-8};
1420 let Inst{7-0} = regs{7-0};
1422 // TODO: Mark the instructions with the appropriate subtarget info.
1423 let Inst{27-25} = 0b110;
1424 let Inst{11-9} = 0b101;
1425 let Inst{8} = 1; // Double precision
1428 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1429 string asm, string cstr, list<dag> pattern>
1430 : VFPXI<oops, iops, AddrMode4, 4, im,
1431 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1432 // Instruction operands.
1436 // Encode instruction operands.
1437 let Inst{19-16} = Rn;
1438 let Inst{22} = regs{8};
1439 let Inst{15-12} = regs{12-9};
1440 let Inst{7-0} = regs{7-0};
1442 // TODO: Mark the instructions with the appropriate subtarget info.
1443 let Inst{27-25} = 0b110;
1444 let Inst{11-9} = 0b101;
1445 let Inst{8} = 0; // Single precision
1448 // Double precision, unary
1449 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1450 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1451 string asm, list<dag> pattern>
1452 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1453 // Instruction operands.
1457 // Encode instruction operands.
1458 let Inst{3-0} = Dm{3-0};
1459 let Inst{5} = Dm{4};
1460 let Inst{15-12} = Dd{3-0};
1461 let Inst{22} = Dd{4};
1463 let Inst{27-23} = opcod1;
1464 let Inst{21-20} = opcod2;
1465 let Inst{19-16} = opcod3;
1466 let Inst{11-9} = 0b101;
1467 let Inst{8} = 1; // Double precision
1468 let Inst{7-6} = opcod4;
1469 let Inst{4} = opcod5;
1472 // Double precision, binary
1473 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1474 dag iops, InstrItinClass itin, string opc, string asm,
1476 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1477 // Instruction operands.
1482 // Encode instruction operands.
1483 let Inst{3-0} = Dm{3-0};
1484 let Inst{5} = Dm{4};
1485 let Inst{19-16} = Dn{3-0};
1486 let Inst{7} = Dn{4};
1487 let Inst{15-12} = Dd{3-0};
1488 let Inst{22} = Dd{4};
1490 let Inst{27-23} = opcod1;
1491 let Inst{21-20} = opcod2;
1492 let Inst{11-9} = 0b101;
1493 let Inst{8} = 1; // Double precision
1498 // Single precision, unary
1499 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1500 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1501 string asm, list<dag> pattern>
1502 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1503 // Instruction operands.
1507 // Encode instruction operands.
1508 let Inst{3-0} = Sm{4-1};
1509 let Inst{5} = Sm{0};
1510 let Inst{15-12} = Sd{4-1};
1511 let Inst{22} = Sd{0};
1513 let Inst{27-23} = opcod1;
1514 let Inst{21-20} = opcod2;
1515 let Inst{19-16} = opcod3;
1516 let Inst{11-9} = 0b101;
1517 let Inst{8} = 0; // Single precision
1518 let Inst{7-6} = opcod4;
1519 let Inst{4} = opcod5;
1522 // Single precision unary, if no NEON. Same as ASuI except not available if
1524 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1525 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1526 string asm, list<dag> pattern>
1527 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1529 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1532 // Single precision, binary
1533 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1534 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1535 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1536 // Instruction operands.
1541 // Encode instruction operands.
1542 let Inst{3-0} = Sm{4-1};
1543 let Inst{5} = Sm{0};
1544 let Inst{19-16} = Sn{4-1};
1545 let Inst{7} = Sn{0};
1546 let Inst{15-12} = Sd{4-1};
1547 let Inst{22} = Sd{0};
1549 let Inst{27-23} = opcod1;
1550 let Inst{21-20} = opcod2;
1551 let Inst{11-9} = 0b101;
1552 let Inst{8} = 0; // Single precision
1557 // Single precision binary, if no NEON. Same as ASbI except not available if
1559 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1560 dag iops, InstrItinClass itin, string opc, string asm,
1562 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1563 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1565 // Instruction operands.
1570 // Encode instruction operands.
1571 let Inst{3-0} = Sm{4-1};
1572 let Inst{5} = Sm{0};
1573 let Inst{19-16} = Sn{4-1};
1574 let Inst{7} = Sn{0};
1575 let Inst{15-12} = Sd{4-1};
1576 let Inst{22} = Sd{0};
1579 // VFP conversion instructions
1580 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1581 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1583 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1584 let Inst{27-23} = opcod1;
1585 let Inst{21-20} = opcod2;
1586 let Inst{19-16} = opcod3;
1587 let Inst{11-8} = opcod4;
1592 // VFP conversion between floating-point and fixed-point
1593 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1594 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1596 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1597 // size (fixed-point number): sx == 0 ? 16 : 32
1598 let Inst{7} = op5; // sx
1601 // VFP conversion instructions, if no NEON
1602 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1603 dag oops, dag iops, InstrItinClass itin,
1604 string opc, string asm, list<dag> pattern>
1605 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1607 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1610 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1611 InstrItinClass itin,
1612 string opc, string asm, list<dag> pattern>
1613 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1614 let Inst{27-20} = opcod1;
1615 let Inst{11-8} = opcod2;
1619 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1620 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1621 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1623 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1624 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1625 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1627 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1628 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1629 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1631 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1632 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1633 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1635 //===----------------------------------------------------------------------===//
1637 //===----------------------------------------------------------------------===//
1638 // ARM NEON Instruction templates.
1641 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1642 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1644 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1645 let OutOperandList = oops;
1646 let InOperandList = !con(iops, (ins pred:$p));
1647 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1648 let Pattern = pattern;
1649 list<Predicate> Predicates = [HasNEON];
1650 let DecoderNamespace = "NEON";
1653 // Same as NeonI except it does not have a "data type" specifier.
1654 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1655 InstrItinClass itin, string opc, string asm, string cstr,
1657 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1658 let OutOperandList = oops;
1659 let InOperandList = !con(iops, (ins pred:$p));
1660 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1661 let Pattern = pattern;
1662 list<Predicate> Predicates = [HasNEON];
1663 let DecoderNamespace = "NEON";
1666 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1667 dag oops, dag iops, InstrItinClass itin,
1668 string opc, string dt, string asm, string cstr, list<dag> pattern>
1669 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1671 let Inst{31-24} = 0b11110100;
1672 let Inst{23} = op23;
1673 let Inst{21-20} = op21_20;
1674 let Inst{11-8} = op11_8;
1675 let Inst{7-4} = op7_4;
1677 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1678 let DecoderNamespace = "NEONLoadStore";
1684 let Inst{22} = Vd{4};
1685 let Inst{15-12} = Vd{3-0};
1686 let Inst{19-16} = Rn{3-0};
1687 let Inst{3-0} = Rm{3-0};
1690 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1691 dag oops, dag iops, InstrItinClass itin,
1692 string opc, string dt, string asm, string cstr, list<dag> pattern>
1693 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1694 dt, asm, cstr, pattern> {
1698 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1699 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1701 let OutOperandList = oops;
1702 let InOperandList = !con(iops, (ins pred:$p));
1703 list<Predicate> Predicates = [HasNEON];
1706 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1708 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1710 let OutOperandList = oops;
1711 let InOperandList = !con(iops, (ins pred:$p));
1712 let Pattern = pattern;
1713 list<Predicate> Predicates = [HasNEON];
1716 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1717 string opc, string dt, string asm, string cstr, list<dag> pattern>
1718 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1720 let Inst{31-25} = 0b1111001;
1721 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1722 let DecoderNamespace = "NEONData";
1725 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1726 string opc, string asm, string cstr, list<dag> pattern>
1727 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1729 let Inst{31-25} = 0b1111001;
1730 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1731 let DecoderNamespace = "NEONData";
1734 // NEON "one register and a modified immediate" format.
1735 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1737 dag oops, dag iops, InstrItinClass itin,
1738 string opc, string dt, string asm, string cstr,
1740 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1741 let Inst{23} = op23;
1742 let Inst{21-19} = op21_19;
1743 let Inst{11-8} = op11_8;
1749 // Instruction operands.
1753 let Inst{15-12} = Vd{3-0};
1754 let Inst{22} = Vd{4};
1755 let Inst{24} = SIMM{7};
1756 let Inst{18-16} = SIMM{6-4};
1757 let Inst{3-0} = SIMM{3-0};
1758 let DecoderMethod = "DecodeNEONModImmInstruction";
1761 // NEON 2 vector register format.
1762 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1763 bits<5> op11_7, bit op6, bit op4,
1764 dag oops, dag iops, InstrItinClass itin,
1765 string opc, string dt, string asm, string cstr, list<dag> pattern>
1766 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1767 let Inst{24-23} = op24_23;
1768 let Inst{21-20} = op21_20;
1769 let Inst{19-18} = op19_18;
1770 let Inst{17-16} = op17_16;
1771 let Inst{11-7} = op11_7;
1775 // Instruction operands.
1779 let Inst{15-12} = Vd{3-0};
1780 let Inst{22} = Vd{4};
1781 let Inst{3-0} = Vm{3-0};
1782 let Inst{5} = Vm{4};
1785 // Same as N2V except it doesn't have a datatype suffix.
1786 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1787 bits<5> op11_7, bit op6, bit op4,
1788 dag oops, dag iops, InstrItinClass itin,
1789 string opc, string asm, string cstr, list<dag> pattern>
1790 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1791 let Inst{24-23} = op24_23;
1792 let Inst{21-20} = op21_20;
1793 let Inst{19-18} = op19_18;
1794 let Inst{17-16} = op17_16;
1795 let Inst{11-7} = op11_7;
1799 // Instruction operands.
1803 let Inst{15-12} = Vd{3-0};
1804 let Inst{22} = Vd{4};
1805 let Inst{3-0} = Vm{3-0};
1806 let Inst{5} = Vm{4};
1809 // NEON 2 vector register with immediate.
1810 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1811 dag oops, dag iops, Format f, InstrItinClass itin,
1812 string opc, string dt, string asm, string cstr, list<dag> pattern>
1813 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1814 let Inst{24} = op24;
1815 let Inst{23} = op23;
1816 let Inst{11-8} = op11_8;
1821 // Instruction operands.
1826 let Inst{15-12} = Vd{3-0};
1827 let Inst{22} = Vd{4};
1828 let Inst{3-0} = Vm{3-0};
1829 let Inst{5} = Vm{4};
1830 let Inst{21-16} = SIMM{5-0};
1833 // NEON 3 vector register format.
1835 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1836 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1837 string opc, string dt, string asm, string cstr,
1839 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1840 let Inst{24} = op24;
1841 let Inst{23} = op23;
1842 let Inst{21-20} = op21_20;
1843 let Inst{11-8} = op11_8;
1848 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1849 dag oops, dag iops, Format f, InstrItinClass itin,
1850 string opc, string dt, string asm, string cstr, list<dag> pattern>
1851 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1852 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1854 // Instruction operands.
1859 let Inst{15-12} = Vd{3-0};
1860 let Inst{22} = Vd{4};
1861 let Inst{19-16} = Vn{3-0};
1862 let Inst{7} = Vn{4};
1863 let Inst{3-0} = Vm{3-0};
1864 let Inst{5} = Vm{4};
1867 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1868 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1869 string opc, string dt, string asm, string cstr,
1871 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1872 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1874 // Instruction operands.
1880 let Inst{15-12} = Vd{3-0};
1881 let Inst{22} = Vd{4};
1882 let Inst{19-16} = Vn{3-0};
1883 let Inst{7} = Vn{4};
1884 let Inst{3-0} = Vm{3-0};
1888 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1889 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1890 string opc, string dt, string asm, string cstr,
1892 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1893 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1895 // Instruction operands.
1901 let Inst{15-12} = Vd{3-0};
1902 let Inst{22} = Vd{4};
1903 let Inst{19-16} = Vn{3-0};
1904 let Inst{7} = Vn{4};
1905 let Inst{2-0} = Vm{2-0};
1906 let Inst{5} = lane{1};
1907 let Inst{3} = lane{0};
1910 // Same as N3V except it doesn't have a data type suffix.
1911 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1913 dag oops, dag iops, Format f, InstrItinClass itin,
1914 string opc, string asm, string cstr, list<dag> pattern>
1915 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1916 let Inst{24} = op24;
1917 let Inst{23} = op23;
1918 let Inst{21-20} = op21_20;
1919 let Inst{11-8} = op11_8;
1923 // Instruction operands.
1928 let Inst{15-12} = Vd{3-0};
1929 let Inst{22} = Vd{4};
1930 let Inst{19-16} = Vn{3-0};
1931 let Inst{7} = Vn{4};
1932 let Inst{3-0} = Vm{3-0};
1933 let Inst{5} = Vm{4};
1936 // NEON VMOVs between scalar and core registers.
1937 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1938 dag oops, dag iops, Format f, InstrItinClass itin,
1939 string opc, string dt, string asm, list<dag> pattern>
1940 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
1942 let Inst{27-20} = opcod1;
1943 let Inst{11-8} = opcod2;
1944 let Inst{6-5} = opcod3;
1946 // A8.6.303, A8.6.328, A8.6.329
1947 let Inst{3-0} = 0b0000;
1949 let OutOperandList = oops;
1950 let InOperandList = !con(iops, (ins pred:$p));
1951 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1952 let Pattern = pattern;
1953 list<Predicate> Predicates = [HasNEON];
1955 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1956 let DecoderNamespace = "NEONDup";
1963 let Inst{31-28} = p{3-0};
1965 let Inst{19-16} = V{3-0};
1966 let Inst{15-12} = R{3-0};
1968 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1969 dag oops, dag iops, InstrItinClass itin,
1970 string opc, string dt, string asm, list<dag> pattern>
1971 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1972 opc, dt, asm, pattern>;
1973 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1974 dag oops, dag iops, InstrItinClass itin,
1975 string opc, string dt, string asm, list<dag> pattern>
1976 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1977 opc, dt, asm, pattern>;
1978 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1979 dag oops, dag iops, InstrItinClass itin,
1980 string opc, string dt, string asm, list<dag> pattern>
1981 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1982 opc, dt, asm, pattern>;
1984 // Vector Duplicate Lane (from scalar to all elements)
1985 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1986 InstrItinClass itin, string opc, string dt, string asm,
1988 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1989 let Inst{24-23} = 0b11;
1990 let Inst{21-20} = 0b11;
1991 let Inst{19-16} = op19_16;
1992 let Inst{11-7} = 0b11000;
1999 let Inst{22} = Vd{4};
2000 let Inst{15-12} = Vd{3-0};
2001 let Inst{5} = Vm{4};
2002 let Inst{3-0} = Vm{3-0};
2005 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
2006 // for single-precision FP.
2007 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
2008 list<Predicate> Predicates = [HasNEON,UseNEONForFP];
2011 // VFP/NEON Instruction aliases for type suffices.
2012 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
2013 InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>;
2015 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
2016 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
2017 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
2018 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
2019 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
2022 // The same alias classes using AsmPseudo instead, for the more complex
2023 // stuff in NEON that InstAlias can't quite handle.
2024 // Note that we can't use anonymous defm references here like we can
2025 // above, as we care about the ultimate instruction enum names generated, unlike
2026 // for instalias defs.
2027 class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
2028 AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>;
2029 multiclass NEONDT8ReqAsmPseudoInst<string opc, string asm, dag iops> {
2030 def I8 : NEONDataTypeAsmPseudoInst<opc, ".i8", asm, iops>;
2031 def S8 : NEONDataTypeAsmPseudoInst<opc, ".s8", asm, iops>;
2032 def U8 : NEONDataTypeAsmPseudoInst<opc, ".u8", asm, iops>;
2033 def P8 : NEONDataTypeAsmPseudoInst<opc, ".p8", asm, iops>;
2035 // NEONDT8ReqAsmPseudoInst plus plain ".8"
2036 multiclass NEONDT8AsmPseudoInst<string opc, string asm, dag iops> {
2037 def _8 : NEONDataTypeAsmPseudoInst<opc, ".8", asm, iops>;
2038 defm _ : NEONDT8ReqAsmPseudoInst<opc, asm, iops>;
2040 multiclass NEONDT16ReqAsmPseudoInst<string opc, string asm, dag iops> {
2041 def I16 : NEONDataTypeAsmPseudoInst<opc, ".i16", asm, iops>;
2042 def S16 : NEONDataTypeAsmPseudoInst<opc, ".s16", asm, iops>;
2043 def U16 : NEONDataTypeAsmPseudoInst<opc, ".u16", asm, iops>;
2044 def P16 : NEONDataTypeAsmPseudoInst<opc, ".p16", asm, iops>;
2046 // NEONDT16ReqAsmPseudoInst plus plain ".16"
2047 multiclass NEONDT16AsmPseudoInst<string opc, string asm, dag iops> {
2048 def _16 : NEONDataTypeAsmPseudoInst<opc, ".16", asm, iops>;
2049 defm _ : NEONDT16ReqAsmPseudoInst<opc, asm, iops>;
2051 multiclass NEONDT32ReqAsmPseudoInst<string opc, string asm, dag iops> {
2052 def I32 : NEONDataTypeAsmPseudoInst<opc, ".i32", asm, iops>;
2053 def S32 : NEONDataTypeAsmPseudoInst<opc, ".s32", asm, iops>;
2054 def U32 : NEONDataTypeAsmPseudoInst<opc, ".u32", asm, iops>;
2055 def F32 : NEONDataTypeAsmPseudoInst<opc, ".f32", asm, iops>;
2056 def F : NEONDataTypeAsmPseudoInst<opc, ".f", asm, iops>;
2058 // NEONDT32ReqAsmPseudoInst plus plain ".32"
2059 multiclass NEONDT32AsmPseudoInst<string opc, string asm, dag iops> {
2060 def _32 : NEONDataTypeAsmPseudoInst<opc, ".32", asm, iops>;
2061 defm _ : NEONDT32ReqAsmPseudoInst<opc, asm, iops>;
2063 multiclass NEONDT64ReqAsmPseudoInst<string opc, string asm, dag iops> {
2064 def I64 : NEONDataTypeAsmPseudoInst<opc, ".i64", asm, iops>;
2065 def S64 : NEONDataTypeAsmPseudoInst<opc, ".s64", asm, iops>;
2066 def U64 : NEONDataTypeAsmPseudoInst<opc, ".u64", asm, iops>;
2067 def F64 : NEONDataTypeAsmPseudoInst<opc, ".f64", asm, iops>;
2068 def D : NEONDataTypeAsmPseudoInst<opc, ".d", asm, iops>;
2070 // NEONDT64ReqAsmPseudoInst plus plain ".64"
2071 multiclass NEONDT64AsmPseudoInst<string opc, string asm, dag iops> {
2072 def _64 : NEONDataTypeAsmPseudoInst<opc, ".64", asm, iops>;
2073 defm _ : NEONDT64ReqAsmPseudoInst<opc, asm, iops>;
2075 multiclass NEONDT64NoF64ReqAsmPseudoInst<string opc, string asm, dag iops> {
2076 def I64 : NEONDataTypeAsmPseudoInst<opc, ".i64", asm, iops>;
2077 def S64 : NEONDataTypeAsmPseudoInst<opc, ".s64", asm, iops>;
2078 def U64 : NEONDataTypeAsmPseudoInst<opc, ".u64", asm, iops>;
2079 def D : NEONDataTypeAsmPseudoInst<opc, ".d", asm, iops>;
2081 // NEONDT64ReqAsmPseudoInst plus plain ".64"
2082 multiclass NEONDT64NoF64AsmPseudoInst<string opc, string asm, dag iops> {
2083 def _64 : NEONDataTypeAsmPseudoInst<opc, ".64", asm, iops>;
2084 defm _ : NEONDT64ReqAsmPseudoInst<opc, asm, iops>;
2086 multiclass NEONDTAnyAsmPseudoInst<string opc, string asm, dag iops> {
2087 defm _ : NEONDT8AsmPseudoInst<opc, asm, iops>;
2088 defm _ : NEONDT16AsmPseudoInst<opc, asm, iops>;
2089 defm _ : NEONDT32AsmPseudoInst<opc, asm, iops>;
2090 defm _ : NEONDT64AsmPseudoInst<opc, asm, iops>;
2092 multiclass NEONDTAnyNoF64AsmPseudoInst<string opc, string asm, dag iops> {
2093 defm _ : NEONDT8AsmPseudoInst<opc, asm, iops>;
2094 defm _ : NEONDT16AsmPseudoInst<opc, asm, iops>;
2095 defm _ : NEONDT32AsmPseudoInst<opc, asm, iops>;
2096 defm _ : NEONDT64NoF64AsmPseudoInst<opc, asm, iops>;
2099 // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.
2100 def : TokenAlias<".s8", ".i8">;
2101 def : TokenAlias<".u8", ".i8">;
2102 def : TokenAlias<".s16", ".i16">;
2103 def : TokenAlias<".u16", ".i16">;
2104 def : TokenAlias<".s32", ".i32">;
2105 def : TokenAlias<".u32", ".i32">;
2106 def : TokenAlias<".s64", ".i64">;
2107 def : TokenAlias<".u64", ".i64">;
2109 def : TokenAlias<".i8", ".8">;
2110 def : TokenAlias<".i16", ".16">;
2111 def : TokenAlias<".i32", ".32">;
2112 def : TokenAlias<".i64", ".64">;
2114 def : TokenAlias<".p8", ".8">;
2115 def : TokenAlias<".p16", ".16">;
2117 def : TokenAlias<".f32", ".32">;
2118 def : TokenAlias<".f64", ".64">;
2119 def : TokenAlias<".f", ".f32">;
2120 def : TokenAlias<".d", ".f64">;