1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // the instruction has a Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 class AddrMode<bits<5> val> {
91 def AddrModeNone : AddrMode<0>;
92 def AddrMode1 : AddrMode<1>;
93 def AddrMode2 : AddrMode<2>;
94 def AddrMode3 : AddrMode<3>;
95 def AddrMode4 : AddrMode<4>;
96 def AddrMode5 : AddrMode<5>;
97 def AddrMode6 : AddrMode<6>;
98 def AddrModeT1_1 : AddrMode<7>;
99 def AddrModeT1_2 : AddrMode<8>;
100 def AddrModeT1_4 : AddrMode<9>;
101 def AddrModeT1_s : AddrMode<10>;
102 def AddrModeT2_i12 : AddrMode<11>;
103 def AddrModeT2_i8 : AddrMode<12>;
104 def AddrModeT2_so : AddrMode<13>;
105 def AddrModeT2_pc : AddrMode<14>;
106 def AddrModeT2_i8s4 : AddrMode<15>;
107 def AddrMode_i12 : AddrMode<16>;
110 class SizeFlagVal<bits<3> val> {
113 def SizeInvalid : SizeFlagVal<0>; // Unset.
114 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
115 def Size8Bytes : SizeFlagVal<2>;
116 def Size4Bytes : SizeFlagVal<3>;
117 def Size2Bytes : SizeFlagVal<4>;
119 // Load / store index mode.
120 class IndexMode<bits<2> val> {
123 def IndexModeNone : IndexMode<0>;
124 def IndexModePre : IndexMode<1>;
125 def IndexModePost : IndexMode<2>;
126 def IndexModeUpd : IndexMode<3>;
128 // Instruction execution domain.
129 class Domain<bits<2> val> {
132 def GenericDomain : Domain<0>;
133 def VFPDomain : Domain<1>; // Instructions in VFP domain only
134 def NeonDomain : Domain<2>; // Instructions in Neon domain only
135 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
137 //===----------------------------------------------------------------------===//
139 // ARM special operands.
142 def CondCodeOperand : AsmOperandClass {
143 let Name = "CondCode";
144 let SuperClasses = [];
147 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
148 // register whose default is 0 (no register).
149 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
150 (ops (i32 14), (i32 zero_reg))> {
151 let PrintMethod = "printPredicateOperand";
152 let ParserMatchClass = CondCodeOperand;
155 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
156 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
157 string EncoderMethod = "getCCOutOpValue";
158 let PrintMethod = "printSBitModifierOperand";
161 // Same as cc_out except it defaults to setting CPSR.
162 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
163 string EncoderMethod = "getCCOutOpValue";
164 let PrintMethod = "printSBitModifierOperand";
167 // ARM special operands for disassembly only.
169 def setend_op : Operand<i32> {
170 let PrintMethod = "printSetendOperand";
173 def cps_opt : Operand<i32> {
174 let PrintMethod = "printCPSOptionOperand";
177 def msr_mask : Operand<i32> {
178 let PrintMethod = "printMSRMaskOperand";
181 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
182 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
183 def neg_zero : Operand<i32> {
184 let PrintMethod = "printNegZeroOperand";
187 //===----------------------------------------------------------------------===//
189 // ARM Instruction templates.
192 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
193 Format f, Domain d, string cstr, InstrItinClass itin>
195 let Namespace = "ARM";
200 bits<2> IndexModeBits = IM.Value;
202 bits<6> Form = F.Value;
204 bit isUnaryDataProc = 0;
205 bit canXformTo16Bit = 0;
207 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
208 let TSFlags{4-0} = AM.Value;
209 let TSFlags{7-5} = SZ.Value;
210 let TSFlags{9-8} = IndexModeBits;
211 let TSFlags{15-10} = Form;
212 let TSFlags{16} = isUnaryDataProc;
213 let TSFlags{17} = canXformTo16Bit;
214 let TSFlags{19-18} = D.Value;
216 let Constraints = cstr;
217 let Itinerary = itin;
224 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
225 Format f, Domain d, string cstr, InstrItinClass itin>
226 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
228 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
229 // on by adding flavors to specific instructions.
230 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
231 Format f, Domain d, string cstr, InstrItinClass itin>
232 : InstTemplate<am, sz, im, f, d, cstr, itin>;
234 class PseudoInst<dag oops, dag iops, InstrItinClass itin,
235 string asm, list<dag> pattern>
236 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
238 let OutOperandList = oops;
239 let InOperandList = iops;
241 let Pattern = pattern;
244 // Almost all ARM instructions are predicable.
245 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
246 IndexMode im, Format f, InstrItinClass itin,
247 string opc, string asm, string cstr,
249 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
252 let OutOperandList = oops;
253 let InOperandList = !con(iops, (ins pred:$p));
254 let AsmString = !strconcat(opc, "${p}", asm);
255 let Pattern = pattern;
256 list<Predicate> Predicates = [IsARM];
259 // A few are not predicable
260 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
261 IndexMode im, Format f, InstrItinClass itin,
262 string opc, string asm, string cstr,
264 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
265 let OutOperandList = oops;
266 let InOperandList = iops;
267 let AsmString = !strconcat(opc, asm);
268 let Pattern = pattern;
269 let isPredicable = 0;
270 list<Predicate> Predicates = [IsARM];
273 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
274 // operand since by default it's a zero register. It will become an implicit def
275 // once it's "flipped".
276 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
277 IndexMode im, Format f, InstrItinClass itin,
278 string opc, string asm, string cstr,
280 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
281 bits<4> p; // Predicate operand
282 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
286 let OutOperandList = oops;
287 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
288 let AsmString = !strconcat(opc, "${s}${p}", asm);
289 let Pattern = pattern;
290 list<Predicate> Predicates = [IsARM];
294 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
295 IndexMode im, Format f, InstrItinClass itin,
296 string asm, string cstr, list<dag> pattern>
297 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
298 let OutOperandList = oops;
299 let InOperandList = iops;
301 let Pattern = pattern;
302 list<Predicate> Predicates = [IsARM];
305 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
306 string opc, string asm, list<dag> pattern>
307 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
308 opc, asm, "", pattern>;
309 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
310 string opc, string asm, list<dag> pattern>
311 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
312 opc, asm, "", pattern>;
313 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
314 string asm, list<dag> pattern>
315 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
317 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
318 string opc, string asm, list<dag> pattern>
319 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
320 opc, asm, "", pattern>;
322 // Ctrl flow instructions
323 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
324 string opc, string asm, list<dag> pattern>
325 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
326 opc, asm, "", pattern> {
327 let Inst{27-24} = opcod;
329 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
330 string asm, list<dag> pattern>
331 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
333 let Inst{27-24} = opcod;
335 class ABXIx2<dag oops, dag iops, InstrItinClass itin,
336 string asm, list<dag> pattern>
337 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, Pseudo, itin,
340 // BR_JT instructions
341 class JTI<dag oops, dag iops, InstrItinClass itin,
342 string asm, list<dag> pattern>
343 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
346 // Atomic load/store instructions
347 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
348 string opc, string asm, list<dag> pattern>
349 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
350 opc, asm, "", pattern> {
351 let Inst{27-23} = 0b00011;
352 let Inst{22-21} = opcod;
354 let Inst{11-0} = 0b111110011111;
356 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
357 string opc, string asm, list<dag> pattern>
358 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
359 opc, asm, "", pattern> {
360 let Inst{27-23} = 0b00011;
361 let Inst{22-21} = opcod;
363 let Inst{11-4} = 0b11111001;
366 // addrmode1 instructions
367 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
368 string opc, string asm, list<dag> pattern>
369 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
370 opc, asm, "", pattern> {
371 let Inst{24-21} = opcod;
372 let Inst{27-26} = 0b00;
374 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
375 string opc, string asm, list<dag> pattern>
376 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
377 opc, asm, "", pattern> {
378 let Inst{24-21} = opcod;
379 let Inst{27-26} = 0b00;
381 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
382 string asm, list<dag> pattern>
383 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
385 let Inst{24-21} = opcod;
386 let Inst{27-26} = 0b00;
388 class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
389 string opc, string asm, list<dag> pattern>
390 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
391 opc, asm, "", pattern>;
394 // addrmode2 loads and stores
395 class AI2<dag oops, dag iops, Format f, InstrItinClass itin,
396 string opc, string asm, list<dag> pattern>
397 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
398 opc, asm, "", pattern> {
399 let Inst{27-26} = 0b01;
405 class AIldr1<bits<3> op, bit opc22, dag oops, dag iops, AddrMode am, Format f,
406 InstrItinClass itin, string opc, string asm, list<dag> pattern>
407 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
409 let Inst{27-25} = op;
410 let Inst{24} = 1; // 24 == P
412 let Inst{22} = opc22;
413 let Inst{21} = 0; // 21 == W
416 // LDRH/LDRSB/LDRSH/LDRD
417 class AIldr2<bits<4> op, bit opc22, bit opc20, dag oops, dag iops, AddrMode am,
418 Format f, InstrItinClass itin, string opc, string asm,
420 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
422 let Inst{27-25} = 0b000;
423 let Inst{24} = 1; // 24 == P
425 let Inst{22} = opc22;
426 let Inst{21} = 0; // 21 == W
427 let Inst{20} = opc20;
435 class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
436 string opc, string asm, list<dag> pattern>
437 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
438 opc, asm, "", pattern> {
439 let Inst{20} = 1; // L bit
440 let Inst{21} = 0; // W bit
441 let Inst{22} = 0; // B bit
442 let Inst{24} = 1; // P bit
443 let Inst{27-26} = 0b01;
445 class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
446 string asm, list<dag> pattern>
447 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
449 let Inst{20} = 1; // L bit
450 let Inst{21} = 0; // W bit
451 let Inst{22} = 0; // B bit
452 let Inst{24} = 1; // P bit
453 let Inst{27-26} = 0b01;
455 class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
456 string opc, string asm, list<dag> pattern>
457 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
458 opc, asm, "", pattern> {
459 let Inst{20} = 1; // L bit
460 let Inst{21} = 0; // W bit
461 let Inst{22} = 1; // B bit
462 let Inst{24} = 1; // P bit
463 let Inst{27-26} = 0b01;
465 class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
466 string asm, list<dag> pattern>
467 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
469 let Inst{20} = 1; // L bit
470 let Inst{21} = 0; // W bit
471 let Inst{22} = 1; // B bit
472 let Inst{24} = 1; // P bit
473 let Inst{27-26} = 0b01;
477 class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
478 string opc, string asm, list<dag> pattern>
479 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
480 opc, asm, "", pattern> {
481 let Inst{20} = 0; // L bit
482 let Inst{21} = 0; // W bit
483 let Inst{22} = 0; // B bit
484 let Inst{24} = 1; // P bit
485 let Inst{27-26} = 0b01;
487 class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
488 string asm, list<dag> pattern>
489 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
491 let Inst{20} = 0; // L bit
492 let Inst{21} = 0; // W bit
493 let Inst{22} = 0; // B bit
494 let Inst{24} = 1; // P bit
495 let Inst{27-26} = 0b01;
497 class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
498 string opc, string asm, list<dag> pattern>
499 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
500 opc, asm, "", pattern> {
501 let Inst{20} = 0; // L bit
502 let Inst{21} = 0; // W bit
503 let Inst{22} = 1; // B bit
504 let Inst{24} = 1; // P bit
505 let Inst{27-26} = 0b01;
507 class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
508 string asm, list<dag> pattern>
509 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
511 let Inst{20} = 0; // L bit
512 let Inst{21} = 0; // W bit
513 let Inst{22} = 1; // B bit
514 let Inst{24} = 1; // P bit
515 let Inst{27-26} = 0b01;
519 class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
520 string opc, string asm, string cstr, list<dag> pattern>
521 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
522 opc, asm, cstr, pattern> {
523 let Inst{20} = 1; // L bit
524 let Inst{21} = 1; // W bit
525 let Inst{22} = 0; // B bit
526 let Inst{24} = 1; // P bit
527 let Inst{27-26} = 0b01;
529 class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
530 string opc, string asm, string cstr, list<dag> pattern>
531 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
532 opc, asm, cstr, pattern> {
533 let Inst{20} = 1; // L bit
534 let Inst{21} = 1; // W bit
535 let Inst{22} = 1; // B bit
536 let Inst{24} = 1; // P bit
537 let Inst{27-26} = 0b01;
540 // Pre-indexed stores
541 class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
542 string opc, string asm, string cstr, list<dag> pattern>
543 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
544 opc, asm, cstr, pattern> {
545 let Inst{20} = 0; // L bit
546 let Inst{21} = 1; // W bit
547 let Inst{22} = 0; // B bit
548 let Inst{24} = 1; // P bit
549 let Inst{27-26} = 0b01;
551 class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
552 string opc, string asm, string cstr, list<dag> pattern>
553 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
554 opc, asm, cstr, pattern> {
555 let Inst{20} = 0; // L bit
556 let Inst{21} = 1; // W bit
557 let Inst{22} = 1; // B bit
558 let Inst{24} = 1; // P bit
559 let Inst{27-26} = 0b01;
562 // Post-indexed loads
563 class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
564 string opc, string asm, string cstr, list<dag> pattern>
565 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
566 opc, asm, cstr,pattern> {
567 let Inst{20} = 1; // L bit
568 let Inst{21} = 0; // W bit
569 let Inst{22} = 0; // B bit
570 let Inst{24} = 0; // P bit
571 let Inst{27-26} = 0b01;
573 class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
574 string opc, string asm, string cstr, list<dag> pattern>
575 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
576 opc, asm, cstr,pattern> {
577 let Inst{20} = 1; // L bit
578 let Inst{21} = 0; // W bit
579 let Inst{22} = 1; // B bit
580 let Inst{24} = 0; // P bit
581 let Inst{27-26} = 0b01;
584 // Post-indexed stores
585 class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
586 string opc, string asm, string cstr, list<dag> pattern>
587 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
588 opc, asm, cstr,pattern> {
589 let Inst{20} = 0; // L bit
590 let Inst{21} = 0; // W bit
591 let Inst{22} = 0; // B bit
592 let Inst{24} = 0; // P bit
593 let Inst{27-26} = 0b01;
595 class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
596 string opc, string asm, string cstr, list<dag> pattern>
597 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
598 opc, asm, cstr,pattern> {
599 let Inst{20} = 0; // L bit
600 let Inst{21} = 0; // W bit
601 let Inst{22} = 1; // B bit
602 let Inst{24} = 0; // P bit
603 let Inst{27-26} = 0b01;
606 // addrmode3 instructions
607 class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
608 string opc, string asm, list<dag> pattern>
609 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
610 opc, asm, "", pattern>;
611 class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
612 string asm, list<dag> pattern>
613 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
617 class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
618 string opc, string asm, list<dag> pattern>
619 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
620 opc, asm, "", pattern> {
622 let Inst{5} = 1; // H bit
623 let Inst{6} = 0; // S bit
625 let Inst{20} = 1; // L bit
626 let Inst{21} = 0; // W bit
627 let Inst{24} = 1; // P bit
628 let Inst{27-25} = 0b000;
630 class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
631 string asm, list<dag> pattern>
632 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
635 let Inst{5} = 1; // H bit
636 let Inst{6} = 0; // S bit
638 let Inst{20} = 1; // L bit
639 let Inst{21} = 0; // W bit
640 let Inst{24} = 1; // P bit
642 class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
643 string opc, string asm, list<dag> pattern>
644 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
645 opc, asm, "", pattern> {
647 let Inst{5} = 1; // H bit
648 let Inst{6} = 1; // S bit
650 let Inst{20} = 1; // L bit
651 let Inst{21} = 0; // W bit
652 let Inst{24} = 1; // P bit
653 let Inst{27-25} = 0b000;
655 class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
656 string asm, list<dag> pattern>
657 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
660 let Inst{5} = 1; // H bit
661 let Inst{6} = 1; // S bit
663 let Inst{20} = 1; // L bit
664 let Inst{21} = 0; // W bit
665 let Inst{24} = 1; // P bit
667 class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
668 string opc, string asm, list<dag> pattern>
669 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
670 opc, asm, "", pattern> {
672 let Inst{5} = 0; // H bit
673 let Inst{6} = 1; // S bit
675 let Inst{20} = 1; // L bit
676 let Inst{21} = 0; // W bit
677 let Inst{24} = 1; // P bit
678 let Inst{27-25} = 0b000;
680 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
681 string asm, list<dag> pattern>
682 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
685 let Inst{5} = 0; // H bit
686 let Inst{6} = 1; // S bit
688 let Inst{20} = 1; // L bit
689 let Inst{21} = 0; // W bit
690 let Inst{24} = 1; // P bit
692 class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
693 string opc, string asm, list<dag> pattern>
694 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
695 opc, asm, "", pattern> {
697 let Inst{5} = 0; // H bit
698 let Inst{6} = 1; // S bit
700 let Inst{20} = 0; // L bit
701 let Inst{21} = 0; // W bit
702 let Inst{24} = 1; // P bit
703 let Inst{27-25} = 0b000;
707 class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
708 string opc, string asm, list<dag> pattern>
709 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
710 opc, asm, "", pattern> {
712 let Inst{5} = 1; // H bit
713 let Inst{6} = 0; // S bit
715 let Inst{20} = 0; // L bit
716 let Inst{21} = 0; // W bit
717 let Inst{24} = 1; // P bit
718 let Inst{27-25} = 0b000;
720 class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
721 string asm, list<dag> pattern>
722 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
725 let Inst{5} = 1; // H bit
726 let Inst{6} = 0; // S bit
728 let Inst{20} = 0; // L bit
729 let Inst{21} = 0; // W bit
730 let Inst{24} = 1; // P bit
732 class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
733 string opc, string asm, list<dag> pattern>
734 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
735 opc, asm, "", pattern> {
737 let Inst{5} = 1; // H bit
738 let Inst{6} = 1; // S bit
740 let Inst{20} = 0; // L bit
741 let Inst{21} = 0; // W bit
742 let Inst{24} = 1; // P bit
743 let Inst{27-25} = 0b000;
747 class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
748 string opc, string asm, string cstr, list<dag> pattern>
749 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
750 opc, asm, cstr, pattern> {
752 let Inst{5} = 1; // H bit
753 let Inst{6} = 0; // S bit
755 let Inst{20} = 1; // L bit
756 let Inst{21} = 1; // W bit
757 let Inst{24} = 1; // P bit
758 let Inst{27-25} = 0b000;
760 class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
761 string opc, string asm, string cstr, list<dag> pattern>
762 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
763 opc, asm, cstr, pattern> {
765 let Inst{5} = 1; // H bit
766 let Inst{6} = 1; // S bit
768 let Inst{20} = 1; // L bit
769 let Inst{21} = 1; // W bit
770 let Inst{24} = 1; // P bit
771 let Inst{27-25} = 0b000;
773 class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
774 string opc, string asm, string cstr, list<dag> pattern>
775 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
776 opc, asm, cstr, pattern> {
778 let Inst{5} = 0; // H bit
779 let Inst{6} = 1; // S bit
781 let Inst{20} = 1; // L bit
782 let Inst{21} = 1; // W bit
783 let Inst{24} = 1; // P bit
784 let Inst{27-25} = 0b000;
786 class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin,
787 string opc, string asm, string cstr, list<dag> pattern>
788 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
789 opc, asm, cstr, pattern> {
791 let Inst{5} = 0; // H bit
792 let Inst{6} = 1; // S bit
794 let Inst{20} = 0; // L bit
795 let Inst{21} = 1; // W bit
796 let Inst{24} = 1; // P bit
797 let Inst{27-25} = 0b000;
801 // Pre-indexed stores
802 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
803 string opc, string asm, string cstr, list<dag> pattern>
804 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
805 opc, asm, cstr, pattern> {
807 let Inst{5} = 1; // H bit
808 let Inst{6} = 0; // S bit
810 let Inst{20} = 0; // L bit
811 let Inst{21} = 1; // W bit
812 let Inst{24} = 1; // P bit
813 let Inst{27-25} = 0b000;
815 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
816 string opc, string asm, string cstr, list<dag> pattern>
817 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
818 opc, asm, cstr, pattern> {
820 let Inst{5} = 1; // H bit
821 let Inst{6} = 1; // S bit
823 let Inst{20} = 0; // L bit
824 let Inst{21} = 1; // W bit
825 let Inst{24} = 1; // P bit
826 let Inst{27-25} = 0b000;
829 // Post-indexed loads
830 class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
831 string opc, string asm, string cstr, list<dag> pattern>
832 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
833 opc, asm, cstr,pattern> {
835 let Inst{5} = 1; // H bit
836 let Inst{6} = 0; // S bit
838 let Inst{20} = 1; // L bit
839 let Inst{21} = 0; // W bit
840 let Inst{24} = 0; // P bit
841 let Inst{27-25} = 0b000;
843 class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
844 string opc, string asm, string cstr, list<dag> pattern>
845 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
846 opc, asm, cstr,pattern> {
848 let Inst{5} = 1; // H bit
849 let Inst{6} = 1; // S bit
851 let Inst{20} = 1; // L bit
852 let Inst{21} = 0; // W bit
853 let Inst{24} = 0; // P bit
854 let Inst{27-25} = 0b000;
856 class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
857 string opc, string asm, string cstr, list<dag> pattern>
858 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
859 opc, asm, cstr,pattern> {
861 let Inst{5} = 0; // H bit
862 let Inst{6} = 1; // S bit
864 let Inst{20} = 1; // L bit
865 let Inst{21} = 0; // W bit
866 let Inst{24} = 0; // P bit
867 let Inst{27-25} = 0b000;
869 class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin,
870 string opc, string asm, string cstr, list<dag> pattern>
871 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
872 opc, asm, cstr, pattern> {
874 let Inst{5} = 0; // H bit
875 let Inst{6} = 1; // S bit
877 let Inst{20} = 0; // L bit
878 let Inst{21} = 0; // W bit
879 let Inst{24} = 0; // P bit
880 let Inst{27-25} = 0b000;
883 // Post-indexed stores
884 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
885 string opc, string asm, string cstr, list<dag> pattern>
886 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
887 opc, asm, cstr,pattern> {
889 let Inst{5} = 1; // H bit
890 let Inst{6} = 0; // S bit
892 let Inst{20} = 0; // L bit
893 let Inst{21} = 0; // W bit
894 let Inst{24} = 0; // P bit
895 let Inst{27-25} = 0b000;
897 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
898 string opc, string asm, string cstr, list<dag> pattern>
899 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
900 opc, asm, cstr, pattern> {
902 let Inst{5} = 1; // H bit
903 let Inst{6} = 1; // S bit
905 let Inst{20} = 0; // L bit
906 let Inst{21} = 0; // W bit
907 let Inst{24} = 0; // P bit
908 let Inst{27-25} = 0b000;
911 // addrmode4 instructions
912 class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
913 string asm, string cstr, list<dag> pattern>
914 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
915 asm, cstr, pattern> {
916 let Inst{20} = 1; // L bit
917 let Inst{22} = 0; // S bit
918 let Inst{27-25} = 0b100;
920 class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
921 string asm, string cstr, list<dag> pattern>
922 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
923 asm, cstr, pattern> {
924 let Inst{20} = 0; // L bit
925 let Inst{22} = 0; // S bit
926 let Inst{27-25} = 0b100;
929 // Unsigned multiply, multiply-accumulate instructions.
930 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
931 string opc, string asm, list<dag> pattern>
932 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
933 opc, asm, "", pattern> {
934 let Inst{7-4} = 0b1001;
935 let Inst{20} = 0; // S bit
936 let Inst{27-21} = opcod;
938 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
939 string opc, string asm, list<dag> pattern>
940 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
941 opc, asm, "", pattern> {
942 let Inst{7-4} = 0b1001;
943 let Inst{27-21} = opcod;
946 // Most significant word multiply
947 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
948 InstrItinClass itin, string opc, string asm, list<dag> pattern>
949 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
950 opc, asm, "", pattern> {
954 let Inst{7-4} = opc7_4;
956 let Inst{27-21} = opcod;
957 let Inst{19-16} = Rd;
961 // MSW multiple w/ Ra operand
962 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
963 InstrItinClass itin, string opc, string asm, list<dag> pattern>
964 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
966 let Inst{15-12} = Ra;
969 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
970 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
971 InstrItinClass itin, string opc, string asm, list<dag> pattern>
972 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
973 opc, asm, "", pattern> {
979 let Inst{27-21} = opcod;
980 let Inst{6-5} = bit6_5;
984 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
985 InstrItinClass itin, string opc, string asm, list<dag> pattern>
986 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
988 let Inst{19-16} = Rd;
991 // AMulxyI with Ra operand
992 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
993 InstrItinClass itin, string opc, string asm, list<dag> pattern>
994 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
996 let Inst{15-12} = Ra;
999 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
1000 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1001 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
1004 let Inst{19-16} = RdHi;
1005 let Inst{15-12} = RdLo;
1008 // Extend instructions.
1009 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
1010 string opc, string asm, list<dag> pattern>
1011 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
1012 opc, asm, "", pattern> {
1013 // All AExtI instructions have Rd and Rm register operands.
1016 let Inst{15-12} = Rd;
1018 let Inst{7-4} = 0b0111;
1019 let Inst{9-8} = 0b00;
1020 let Inst{27-20} = opcod;
1023 // Misc Arithmetic instructions.
1024 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
1025 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1026 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
1027 opc, asm, "", pattern> {
1030 let Inst{27-20} = opcod;
1031 let Inst{19-16} = 0b1111;
1032 let Inst{15-12} = Rd;
1033 let Inst{11-8} = 0b1111;
1034 let Inst{7-4} = opc7_4;
1039 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
1040 string opc, string asm, list<dag> pattern>
1041 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
1042 opc, asm, "", pattern> {
1047 let Inst{27-20} = opcod;
1048 let Inst{19-16} = Rn;
1049 let Inst{15-12} = Rd;
1050 let Inst{11-7} = sh{7-3};
1052 let Inst{5-4} = 0b01;
1056 //===----------------------------------------------------------------------===//
1058 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
1059 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
1060 list<Predicate> Predicates = [IsARM];
1062 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
1063 list<Predicate> Predicates = [IsARM, HasV5TE];
1065 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
1066 list<Predicate> Predicates = [IsARM, HasV6];
1069 //===----------------------------------------------------------------------===//
1071 // Thumb Instruction Format Definitions.
1074 // TI - Thumb instruction.
1076 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1077 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1078 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1079 let OutOperandList = oops;
1080 let InOperandList = iops;
1081 let AsmString = asm;
1082 let Pattern = pattern;
1083 list<Predicate> Predicates = [IsThumb];
1086 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
1087 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
1089 // Two-address instructions
1090 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
1092 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
1095 // tBL, tBX 32-bit instructions
1096 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
1097 dag oops, dag iops, InstrItinClass itin, string asm,
1099 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
1101 let Inst{31-27} = opcod1;
1102 let Inst{15-14} = opcod2;
1103 let Inst{12} = opcod3;
1106 // BR_JT instructions
1107 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
1109 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1112 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1113 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1114 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1115 let OutOperandList = oops;
1116 let InOperandList = iops;
1117 let AsmString = asm;
1118 let Pattern = pattern;
1119 list<Predicate> Predicates = [IsThumb1Only];
1122 class T1I<dag oops, dag iops, InstrItinClass itin,
1123 string asm, list<dag> pattern>
1124 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
1125 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
1126 string asm, list<dag> pattern>
1127 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1128 class T1JTI<dag oops, dag iops, InstrItinClass itin,
1129 string asm, list<dag> pattern>
1130 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1132 // Two-address instructions
1133 class T1It<dag oops, dag iops, InstrItinClass itin,
1134 string asm, string cstr, list<dag> pattern>
1135 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
1136 asm, cstr, pattern>;
1138 // Thumb1 instruction that can either be predicated or set CPSR.
1139 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1140 InstrItinClass itin,
1141 string opc, string asm, string cstr, list<dag> pattern>
1142 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1143 let OutOperandList = !con(oops, (outs s_cc_out:$s));
1144 let InOperandList = !con(iops, (ins pred:$p));
1145 let AsmString = !strconcat(opc, "${s}${p}", asm);
1146 let Pattern = pattern;
1147 list<Predicate> Predicates = [IsThumb1Only];
1150 class T1sI<dag oops, dag iops, InstrItinClass itin,
1151 string opc, string asm, list<dag> pattern>
1152 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1154 // Two-address instructions
1155 class T1sIt<dag oops, dag iops, InstrItinClass itin,
1156 string opc, string asm, list<dag> pattern>
1157 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1158 "$lhs = $dst", pattern>;
1160 // Thumb1 instruction that can be predicated.
1161 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1162 InstrItinClass itin,
1163 string opc, string asm, string cstr, list<dag> pattern>
1164 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1165 let OutOperandList = oops;
1166 let InOperandList = !con(iops, (ins pred:$p));
1167 let AsmString = !strconcat(opc, "${p}", asm);
1168 let Pattern = pattern;
1169 list<Predicate> Predicates = [IsThumb1Only];
1172 class T1pI<dag oops, dag iops, InstrItinClass itin,
1173 string opc, string asm, list<dag> pattern>
1174 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1176 // Two-address instructions
1177 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1178 string opc, string asm, list<dag> pattern>
1179 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1180 "$lhs = $dst", pattern>;
1182 class T1pI1<dag oops, dag iops, InstrItinClass itin,
1183 string opc, string asm, list<dag> pattern>
1184 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
1185 class T1pI2<dag oops, dag iops, InstrItinClass itin,
1186 string opc, string asm, list<dag> pattern>
1187 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
1188 class T1pI4<dag oops, dag iops, InstrItinClass itin,
1189 string opc, string asm, list<dag> pattern>
1190 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
1191 class T1pIs<dag oops, dag iops,
1192 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1193 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
1195 class Encoding16 : Encoding {
1196 let Inst{31-16} = 0x0000;
1199 // A6.2 16-bit Thumb instruction encoding
1200 class T1Encoding<bits<6> opcode> : Encoding16 {
1201 let Inst{15-10} = opcode;
1204 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1205 class T1General<bits<5> opcode> : Encoding16 {
1206 let Inst{15-14} = 0b00;
1207 let Inst{13-9} = opcode;
1210 // A6.2.2 Data-processing encoding.
1211 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1212 let Inst{15-10} = 0b010000;
1213 let Inst{9-6} = opcode;
1216 // A6.2.3 Special data instructions and branch and exchange encoding.
1217 class T1Special<bits<4> opcode> : Encoding16 {
1218 let Inst{15-10} = 0b010001;
1219 let Inst{9-6} = opcode;
1222 // A6.2.4 Load/store single data item encoding.
1223 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1224 let Inst{15-12} = opA;
1225 let Inst{11-9} = opB;
1227 class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
1228 class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
1229 class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
1230 class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
1231 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1233 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1234 class T1Misc<bits<7> opcode> : Encoding16 {
1235 let Inst{15-12} = 0b1011;
1236 let Inst{11-5} = opcode;
1239 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1240 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1241 InstrItinClass itin,
1242 string opc, string asm, string cstr, list<dag> pattern>
1243 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1244 let OutOperandList = oops;
1245 let InOperandList = !con(iops, (ins pred:$p));
1246 let AsmString = !strconcat(opc, "${p}", asm);
1247 let Pattern = pattern;
1248 list<Predicate> Predicates = [IsThumb2];
1251 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1252 // input operand since by default it's a zero register. It will become an
1253 // implicit def once it's "flipped".
1255 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1257 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1258 InstrItinClass itin,
1259 string opc, string asm, string cstr, list<dag> pattern>
1260 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1261 let OutOperandList = oops;
1262 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1263 let AsmString = !strconcat(opc, "${s}${p}", asm);
1264 let Pattern = pattern;
1265 list<Predicate> Predicates = [IsThumb2];
1269 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1270 InstrItinClass itin,
1271 string asm, string cstr, list<dag> pattern>
1272 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1273 let OutOperandList = oops;
1274 let InOperandList = iops;
1275 let AsmString = asm;
1276 let Pattern = pattern;
1277 list<Predicate> Predicates = [IsThumb2];
1280 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1281 InstrItinClass itin,
1282 string asm, string cstr, list<dag> pattern>
1283 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1284 let OutOperandList = oops;
1285 let InOperandList = iops;
1286 let AsmString = asm;
1287 let Pattern = pattern;
1288 list<Predicate> Predicates = [IsThumb1Only];
1291 class T2I<dag oops, dag iops, InstrItinClass itin,
1292 string opc, string asm, list<dag> pattern>
1293 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1294 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1295 string opc, string asm, list<dag> pattern>
1296 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
1297 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1298 string opc, string asm, list<dag> pattern>
1299 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1300 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1301 string opc, string asm, list<dag> pattern>
1302 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1303 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1304 string opc, string asm, list<dag> pattern>
1305 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1306 class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
1307 string opc, string asm, list<dag> pattern>
1308 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1310 let Inst{31-27} = 0b11101;
1311 let Inst{26-25} = 0b00;
1313 let Inst{23} = ?; // The U bit.
1316 let Inst{20} = load;
1319 class T2sI<dag oops, dag iops, InstrItinClass itin,
1320 string opc, string asm, list<dag> pattern>
1321 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1323 class T2XI<dag oops, dag iops, InstrItinClass itin,
1324 string asm, list<dag> pattern>
1325 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1326 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1327 string asm, list<dag> pattern>
1328 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1330 class T2Ix2<dag oops, dag iops, InstrItinClass itin,
1331 string opc, string asm, list<dag> pattern>
1332 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
1334 // Two-address instructions
1335 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1336 string asm, string cstr, list<dag> pattern>
1337 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1339 // T2Iidxldst - Thumb2 indexed load / store instructions.
1340 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1342 AddrMode am, IndexMode im, InstrItinClass itin,
1343 string opc, string asm, string cstr, list<dag> pattern>
1344 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1345 let OutOperandList = oops;
1346 let InOperandList = !con(iops, (ins pred:$p));
1347 let AsmString = !strconcat(opc, "${p}", asm);
1348 let Pattern = pattern;
1349 list<Predicate> Predicates = [IsThumb2];
1350 let Inst{31-27} = 0b11111;
1351 let Inst{26-25} = 0b00;
1352 let Inst{24} = signed;
1354 let Inst{22-21} = opcod;
1355 let Inst{20} = load;
1357 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1358 let Inst{10} = pre; // The P bit.
1359 let Inst{8} = 1; // The W bit.
1362 // Helper class for disassembly only
1363 // A6.3.16 & A6.3.17
1364 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1365 class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
1366 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1367 : T2I<oops, iops, itin, opc, asm, pattern> {
1368 let Inst{31-27} = 0b11111;
1369 let Inst{26-24} = 0b011;
1370 let Inst{23} = long;
1371 let Inst{22-20} = op22_20;
1372 let Inst{7-4} = op7_4;
1375 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1376 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1377 list<Predicate> Predicates = [IsThumb1Only, HasV5T];
1380 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1381 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1382 list<Predicate> Predicates = [IsThumb1Only];
1385 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1386 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1387 list<Predicate> Predicates = [IsThumb2];
1390 //===----------------------------------------------------------------------===//
1392 //===----------------------------------------------------------------------===//
1393 // ARM VFP Instruction templates.
1396 // Almost all VFP instructions are predicable.
1397 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1398 IndexMode im, Format f, InstrItinClass itin,
1399 string opc, string asm, string cstr, list<dag> pattern>
1400 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1402 let Inst{31-28} = p;
1403 let OutOperandList = oops;
1404 let InOperandList = !con(iops, (ins pred:$p));
1405 let AsmString = !strconcat(opc, "${p}", asm);
1406 let Pattern = pattern;
1407 list<Predicate> Predicates = [HasVFP2];
1411 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1412 IndexMode im, Format f, InstrItinClass itin,
1413 string asm, string cstr, list<dag> pattern>
1414 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1415 let OutOperandList = oops;
1416 let InOperandList = iops;
1417 let AsmString = asm;
1418 let Pattern = pattern;
1419 list<Predicate> Predicates = [HasVFP2];
1422 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1423 string opc, string asm, list<dag> pattern>
1424 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1425 opc, asm, "", pattern>;
1427 // ARM VFP addrmode5 loads and stores
1428 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1429 InstrItinClass itin,
1430 string opc, string asm, list<dag> pattern>
1431 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1432 VFPLdStFrm, itin, opc, asm, "", pattern> {
1433 // TODO: Mark the instructions with the appropriate subtarget info.
1434 let Inst{27-24} = opcod1;
1435 let Inst{21-20} = opcod2;
1436 let Inst{11-9} = 0b101;
1437 let Inst{8} = 1; // Double precision
1439 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1440 let D = VFPNeonDomain;
1443 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1444 InstrItinClass itin,
1445 string opc, string asm, list<dag> pattern>
1446 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1447 VFPLdStFrm, itin, opc, asm, "", pattern> {
1448 // TODO: Mark the instructions with the appropriate subtarget info.
1449 let Inst{27-24} = opcod1;
1450 let Inst{21-20} = opcod2;
1451 let Inst{11-9} = 0b101;
1452 let Inst{8} = 0; // Single precision
1455 // VFP Load / store multiple pseudo instructions.
1456 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1458 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain,
1460 let OutOperandList = oops;
1461 let InOperandList = !con(iops, (ins pred:$p));
1462 let Pattern = pattern;
1463 list<Predicate> Predicates = [HasVFP2];
1466 // Load / store multiple
1467 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1468 string asm, string cstr, list<dag> pattern>
1469 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1470 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1471 // TODO: Mark the instructions with the appropriate subtarget info.
1472 let Inst{27-25} = 0b110;
1473 let Inst{11-9} = 0b101;
1474 let Inst{8} = 1; // Double precision
1476 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1477 let D = VFPNeonDomain;
1480 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1481 string asm, string cstr, list<dag> pattern>
1482 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1483 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1484 // TODO: Mark the instructions with the appropriate subtarget info.
1485 let Inst{27-25} = 0b110;
1486 let Inst{11-9} = 0b101;
1487 let Inst{8} = 0; // Single precision
1490 // Double precision, unary
1491 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1492 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1493 string asm, list<dag> pattern>
1494 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1495 let Inst{27-23} = opcod1;
1496 let Inst{21-20} = opcod2;
1497 let Inst{19-16} = opcod3;
1498 let Inst{11-9} = 0b101;
1499 let Inst{8} = 1; // Double precision
1500 let Inst{7-6} = opcod4;
1501 let Inst{4} = opcod5;
1504 // Double precision, binary
1505 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1506 dag iops, InstrItinClass itin, string opc, string asm,
1508 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1509 let Inst{27-23} = opcod1;
1510 let Inst{21-20} = opcod2;
1511 let Inst{11-9} = 0b101;
1512 let Inst{8} = 1; // Double precision
1517 // Double precision, binary, VML[AS] (for additional predicate)
1518 class ADbI_vmlX<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1519 dag iops, InstrItinClass itin, string opc, string asm,
1521 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1522 let Inst{27-23} = opcod1;
1523 let Inst{21-20} = opcod2;
1524 let Inst{11-9} = 0b101;
1525 let Inst{8} = 1; // Double precision
1528 list<Predicate> Predicates = [HasVFP2, UseVMLx];
1531 // Single precision, unary
1532 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1533 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1534 string asm, list<dag> pattern>
1535 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1536 let Inst{27-23} = opcod1;
1537 let Inst{21-20} = opcod2;
1538 let Inst{19-16} = opcod3;
1539 let Inst{11-9} = 0b101;
1540 let Inst{8} = 0; // Single precision
1541 let Inst{7-6} = opcod4;
1542 let Inst{4} = opcod5;
1545 // Single precision unary, if no NEON
1546 // Same as ASuI except not available if NEON is enabled
1547 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1548 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1549 string asm, list<dag> pattern>
1550 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1552 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1555 // Single precision, binary
1556 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1557 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1558 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1559 let Inst{27-23} = opcod1;
1560 let Inst{21-20} = opcod2;
1561 let Inst{11-9} = 0b101;
1562 let Inst{8} = 0; // Single precision
1567 // Single precision binary, if no NEON
1568 // Same as ASbI except not available if NEON is enabled
1569 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1570 dag iops, InstrItinClass itin, string opc, string asm,
1572 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1573 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1576 // VFP conversion instructions
1577 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1578 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1580 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1581 let Inst{27-23} = opcod1;
1582 let Inst{21-20} = opcod2;
1583 let Inst{19-16} = opcod3;
1584 let Inst{11-8} = opcod4;
1589 // VFP conversion between floating-point and fixed-point
1590 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1591 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1593 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1594 // size (fixed-point number): sx == 0 ? 16 : 32
1595 let Inst{7} = op5; // sx
1598 // VFP conversion instructions, if no NEON
1599 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1600 dag oops, dag iops, InstrItinClass itin,
1601 string opc, string asm, list<dag> pattern>
1602 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1604 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1607 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1608 InstrItinClass itin,
1609 string opc, string asm, list<dag> pattern>
1610 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1611 let Inst{27-20} = opcod1;
1612 let Inst{11-8} = opcod2;
1616 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1617 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1618 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1620 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1621 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1622 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1624 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1625 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1626 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1628 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1629 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1630 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1632 //===----------------------------------------------------------------------===//
1634 //===----------------------------------------------------------------------===//
1635 // ARM NEON Instruction templates.
1638 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1639 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1641 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1642 let OutOperandList = oops;
1643 let InOperandList = !con(iops, (ins pred:$p));
1644 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1645 let Pattern = pattern;
1646 list<Predicate> Predicates = [HasNEON];
1649 // Same as NeonI except it does not have a "data type" specifier.
1650 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1651 InstrItinClass itin, string opc, string asm, string cstr,
1653 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1654 let OutOperandList = oops;
1655 let InOperandList = !con(iops, (ins pred:$p));
1656 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1657 let Pattern = pattern;
1658 list<Predicate> Predicates = [HasNEON];
1661 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1662 dag oops, dag iops, InstrItinClass itin,
1663 string opc, string dt, string asm, string cstr, list<dag> pattern>
1664 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1666 let Inst{31-24} = 0b11110100;
1667 let Inst{23} = op23;
1668 let Inst{21-20} = op21_20;
1669 let Inst{11-8} = op11_8;
1670 let Inst{7-4} = op7_4;
1673 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1674 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1676 let OutOperandList = oops;
1677 let InOperandList = !con(iops, (ins pred:$p));
1678 list<Predicate> Predicates = [HasNEON];
1681 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1683 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1685 let OutOperandList = oops;
1686 let InOperandList = !con(iops, (ins pred:$p));
1687 let Pattern = pattern;
1688 list<Predicate> Predicates = [HasNEON];
1691 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1692 string opc, string dt, string asm, string cstr, list<dag> pattern>
1693 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1695 let Inst{31-25} = 0b1111001;
1698 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1699 string opc, string asm, string cstr, list<dag> pattern>
1700 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1702 let Inst{31-25} = 0b1111001;
1705 // NEON "one register and a modified immediate" format.
1706 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1708 dag oops, dag iops, InstrItinClass itin,
1709 string opc, string dt, string asm, string cstr,
1711 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1712 let Inst{23} = op23;
1713 let Inst{21-19} = op21_19;
1714 let Inst{11-8} = op11_8;
1720 // Instruction operands.
1724 let Inst{15-12} = Vd{3-0};
1725 let Inst{22} = Vd{4};
1726 let Inst{24} = SIMM{7};
1727 let Inst{18-16} = SIMM{6-4};
1728 let Inst{3-0} = SIMM{3-0};
1731 // NEON 2 vector register format.
1732 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1733 bits<5> op11_7, bit op6, bit op4,
1734 dag oops, dag iops, InstrItinClass itin,
1735 string opc, string dt, string asm, string cstr, list<dag> pattern>
1736 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1737 let Inst{24-23} = op24_23;
1738 let Inst{21-20} = op21_20;
1739 let Inst{19-18} = op19_18;
1740 let Inst{17-16} = op17_16;
1741 let Inst{11-7} = op11_7;
1745 // Instruction operands.
1749 let Inst{15-12} = Vd{3-0};
1750 let Inst{22} = Vd{4};
1751 let Inst{3-0} = Vm{3-0};
1752 let Inst{5} = Vm{4};
1755 // Same as N2V except it doesn't have a datatype suffix.
1756 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1757 bits<5> op11_7, bit op6, bit op4,
1758 dag oops, dag iops, InstrItinClass itin,
1759 string opc, string asm, string cstr, list<dag> pattern>
1760 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1761 let Inst{24-23} = op24_23;
1762 let Inst{21-20} = op21_20;
1763 let Inst{19-18} = op19_18;
1764 let Inst{17-16} = op17_16;
1765 let Inst{11-7} = op11_7;
1769 // Instruction operands.
1773 let Inst{15-12} = Vd{3-0};
1774 let Inst{22} = Vd{4};
1775 let Inst{3-0} = Vm{3-0};
1776 let Inst{5} = Vm{4};
1779 // NEON 2 vector register with immediate.
1780 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1781 dag oops, dag iops, Format f, InstrItinClass itin,
1782 string opc, string dt, string asm, string cstr, list<dag> pattern>
1783 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1784 let Inst{24} = op24;
1785 let Inst{23} = op23;
1786 let Inst{11-8} = op11_8;
1791 // Instruction operands.
1796 let Inst{15-12} = Vd{3-0};
1797 let Inst{22} = Vd{4};
1798 let Inst{3-0} = Vm{3-0};
1799 let Inst{5} = Vm{4};
1800 let Inst{21-16} = SIMM{5-0};
1803 // NEON 3 vector register format.
1804 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1805 dag oops, dag iops, Format f, InstrItinClass itin,
1806 string opc, string dt, string asm, string cstr, list<dag> pattern>
1807 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1808 let Inst{24} = op24;
1809 let Inst{23} = op23;
1810 let Inst{21-20} = op21_20;
1811 let Inst{11-8} = op11_8;
1815 // Instruction operands.
1820 let Inst{15-12} = Vd{3-0};
1821 let Inst{22} = Vd{4};
1822 let Inst{19-16} = Vn{3-0};
1823 let Inst{7} = Vn{4};
1824 let Inst{3-0} = Vm{3-0};
1825 let Inst{5} = Vm{4};
1828 // Same as N3V except it doesn't have a data type suffix.
1829 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1831 dag oops, dag iops, Format f, InstrItinClass itin,
1832 string opc, string asm, string cstr, list<dag> pattern>
1833 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1834 let Inst{24} = op24;
1835 let Inst{23} = op23;
1836 let Inst{21-20} = op21_20;
1837 let Inst{11-8} = op11_8;
1841 // Instruction operands.
1846 let Inst{15-12} = Vd{3-0};
1847 let Inst{22} = Vd{4};
1848 let Inst{19-16} = Vn{3-0};
1849 let Inst{7} = Vn{4};
1850 let Inst{3-0} = Vm{3-0};
1851 let Inst{5} = Vm{4};
1854 // NEON VMOVs between scalar and core registers.
1855 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1856 dag oops, dag iops, Format f, InstrItinClass itin,
1857 string opc, string dt, string asm, list<dag> pattern>
1858 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain,
1860 let Inst{27-20} = opcod1;
1861 let Inst{11-8} = opcod2;
1862 let Inst{6-5} = opcod3;
1865 let OutOperandList = oops;
1866 let InOperandList = !con(iops, (ins pred:$p));
1867 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1868 let Pattern = pattern;
1869 list<Predicate> Predicates = [HasNEON];
1876 let Inst{31-28} = p{3-0};
1878 let Inst{19-16} = V{3-0};
1879 let Inst{15-12} = R{3-0};
1881 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1882 dag oops, dag iops, InstrItinClass itin,
1883 string opc, string dt, string asm, list<dag> pattern>
1884 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1885 opc, dt, asm, pattern>;
1886 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1887 dag oops, dag iops, InstrItinClass itin,
1888 string opc, string dt, string asm, list<dag> pattern>
1889 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1890 opc, dt, asm, pattern>;
1891 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1892 dag oops, dag iops, InstrItinClass itin,
1893 string opc, string dt, string asm, list<dag> pattern>
1894 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1895 opc, dt, asm, pattern>;
1897 // Vector Duplicate Lane (from scalar to all elements)
1898 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1899 InstrItinClass itin, string opc, string dt, string asm,
1901 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1902 let Inst{24-23} = 0b11;
1903 let Inst{21-20} = 0b11;
1904 let Inst{19-16} = op19_16;
1905 let Inst{11-7} = 0b11000;
1913 let Inst{22} = Vd{4};
1914 let Inst{15-12} = Vd{3-0};
1915 let Inst{5} = Vm{4};
1916 let Inst{3-0} = Vm{3-0};
1919 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1920 // for single-precision FP.
1921 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1922 list<Predicate> Predicates = [HasNEON,UseNEONForFP];