1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<28>;
38 def ArithMiscFrm : Format<11>;
39 def ExtFrm : Format<12>;
41 def VFPUnaryFrm : Format<13>;
42 def VFPBinaryFrm : Format<14>;
43 def VFPConv1Frm : Format<15>;
44 def VFPConv2Frm : Format<16>;
45 def VFPConv3Frm : Format<17>;
46 def VFPConv4Frm : Format<18>;
47 def VFPConv5Frm : Format<19>;
48 def VFPLdStFrm : Format<20>;
49 def VFPLdStMulFrm : Format<21>;
50 def VFPMiscFrm : Format<22>;
52 def ThumbFrm : Format<23>;
54 def NEONFrm : Format<24>;
55 def NEONGetLnFrm : Format<25>;
56 def NEONSetLnFrm : Format<26>;
57 def NEONDupFrm : Format<27>;
61 // the instruction has a Rn register operand.
62 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
63 // it doesn't have a Rn operand.
64 class UnaryDP { bit isUnaryDataProc = 1; }
66 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
67 // a 16-bit Thumb instruction if certain conditions are met.
68 class Xform16Bit { bit canXformTo16Bit = 1; }
70 //===----------------------------------------------------------------------===//
71 // ARM Instruction flags. These need to match ARMInstrInfo.h.
75 class AddrMode<bits<4> val> {
78 def AddrModeNone : AddrMode<0>;
79 def AddrMode1 : AddrMode<1>;
80 def AddrMode2 : AddrMode<2>;
81 def AddrMode3 : AddrMode<3>;
82 def AddrMode4 : AddrMode<4>;
83 def AddrMode5 : AddrMode<5>;
84 def AddrMode6 : AddrMode<6>;
85 def AddrModeT1_1 : AddrMode<7>;
86 def AddrModeT1_2 : AddrMode<8>;
87 def AddrModeT1_4 : AddrMode<9>;
88 def AddrModeT1_s : AddrMode<10>;
89 def AddrModeT2_i12: AddrMode<11>;
90 def AddrModeT2_i8 : AddrMode<12>;
91 def AddrModeT2_so : AddrMode<13>;
92 def AddrModeT2_pc : AddrMode<14>;
93 def AddrModeT2_i8s4 : AddrMode<15>;
96 class SizeFlagVal<bits<3> val> {
99 def SizeInvalid : SizeFlagVal<0>; // Unset.
100 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
101 def Size8Bytes : SizeFlagVal<2>;
102 def Size4Bytes : SizeFlagVal<3>;
103 def Size2Bytes : SizeFlagVal<4>;
105 // Load / store index mode.
106 class IndexMode<bits<2> val> {
109 def IndexModeNone : IndexMode<0>;
110 def IndexModePre : IndexMode<1>;
111 def IndexModePost : IndexMode<2>;
113 // Instruction execution domain.
114 class Domain<bits<2> val> {
117 def GenericDomain : Domain<0>;
118 def VFPDomain : Domain<1>; // Instructions in VFP domain only
119 def NeonDomain : Domain<2>; // Instructions in Neon domain only
120 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
122 //===----------------------------------------------------------------------===//
124 // ARM special operands.
127 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
128 // register whose default is 0 (no register).
129 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
130 (ops (i32 14), (i32 zero_reg))> {
131 let PrintMethod = "printPredicateOperand";
134 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
135 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
136 let PrintMethod = "printSBitModifierOperand";
139 // Same as cc_out except it defaults to setting CPSR.
140 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
141 let PrintMethod = "printSBitModifierOperand";
144 //===----------------------------------------------------------------------===//
146 // ARM Instruction templates.
149 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
150 Format f, Domain d, string cstr, InstrItinClass itin>
152 let Namespace = "ARM";
156 bits<4> AddrModeBits = AM.Value;
159 bits<3> SizeFlag = SZ.Value;
162 bits<2> IndexModeBits = IM.Value;
165 bits<5> Form = F.Value;
168 bits<2> Dom = D.Value;
171 // Attributes specific to ARM instructions...
173 bit isUnaryDataProc = 0;
174 bit canXformTo16Bit = 0;
176 let Constraints = cstr;
177 let Itinerary = itin;
184 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
185 Format f, Domain d, string cstr, InstrItinClass itin>
186 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
188 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
189 // on by adding flavors to specific instructions.
190 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
191 Format f, Domain d, string cstr, InstrItinClass itin>
192 : InstTemplate<am, sz, im, f, d, cstr, itin>;
194 class PseudoInst<dag oops, dag iops, InstrItinClass itin,
195 string asm, list<dag> pattern>
196 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
198 let OutOperandList = oops;
199 let InOperandList = iops;
201 let Pattern = pattern;
204 // Almost all ARM instructions are predicable.
205 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
206 IndexMode im, Format f, InstrItinClass itin,
207 string opc, string asm, string cstr,
209 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
210 let OutOperandList = oops;
211 let InOperandList = !con(iops, (ops pred:$p));
212 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
213 let Pattern = pattern;
214 list<Predicate> Predicates = [IsARM];
216 // A few are not predicable
217 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
218 IndexMode im, Format f, InstrItinClass itin,
219 string opc, string asm, string cstr,
221 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
222 let OutOperandList = oops;
223 let InOperandList = iops;
224 let AsmString = !strconcat(opc, asm);
225 let Pattern = pattern;
226 let isPredicable = 0;
227 list<Predicate> Predicates = [IsARM];
230 // Same as I except it can optionally modify CPSR. Note it's modeled as
231 // an input operand since by default it's a zero register. It will
232 // become an implicit def once it's "flipped".
233 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
234 IndexMode im, Format f, InstrItinClass itin,
235 string opc, string asm, string cstr,
237 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
238 let OutOperandList = oops;
239 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
240 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
241 let Pattern = pattern;
242 list<Predicate> Predicates = [IsARM];
246 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
247 IndexMode im, Format f, InstrItinClass itin,
248 string asm, string cstr, list<dag> pattern>
249 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
250 let OutOperandList = oops;
251 let InOperandList = iops;
253 let Pattern = pattern;
254 list<Predicate> Predicates = [IsARM];
257 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
258 string opc, string asm, list<dag> pattern>
259 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
260 opc, asm, "", pattern>;
261 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
262 string opc, string asm, list<dag> pattern>
263 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
264 opc, asm, "", pattern>;
265 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
266 string asm, list<dag> pattern>
267 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
269 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
270 string opc, string asm, list<dag> pattern>
271 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
272 opc, asm, "", pattern>;
274 // Ctrl flow instructions
275 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
276 string opc, string asm, list<dag> pattern>
277 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
278 opc, asm, "", pattern> {
279 let Inst{27-24} = opcod;
281 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
282 string asm, list<dag> pattern>
283 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
285 let Inst{27-24} = opcod;
287 class ABXIx2<dag oops, dag iops, InstrItinClass itin,
288 string asm, list<dag> pattern>
289 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin,
292 // BR_JT instructions
293 class JTI<dag oops, dag iops, InstrItinClass itin,
294 string asm, list<dag> pattern>
295 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
299 // Atomic load/store instructions
301 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
302 string opc, string asm, list<dag> pattern>
303 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
304 opc, asm, "", pattern> {
305 let Inst{27-23} = 0b00011;
306 let Inst{22-21} = opcod;
308 let Inst{11-0} = 0b111110011111;
310 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
311 string opc, string asm, list<dag> pattern>
312 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
313 opc, asm, "", pattern> {
314 let Inst{27-23} = 0b00011;
315 let Inst{22-21} = opcod;
317 let Inst{11-4} = 0b11111001;
320 // addrmode1 instructions
321 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
322 string opc, string asm, list<dag> pattern>
323 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
324 opc, asm, "", pattern> {
325 let Inst{24-21} = opcod;
326 let Inst{27-26} = {0,0};
328 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
329 string opc, string asm, list<dag> pattern>
330 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
331 opc, asm, "", pattern> {
332 let Inst{24-21} = opcod;
333 let Inst{27-26} = {0,0};
335 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
336 string asm, list<dag> pattern>
337 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
339 let Inst{24-21} = opcod;
340 let Inst{27-26} = {0,0};
342 class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
343 string opc, string asm, list<dag> pattern>
344 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
345 opc, asm, "", pattern>;
348 // addrmode2 loads and stores
349 class AI2<dag oops, dag iops, Format f, InstrItinClass itin,
350 string opc, string asm, list<dag> pattern>
351 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
352 opc, asm, "", pattern> {
353 let Inst{27-26} = {0,1};
357 class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
358 string opc, string asm, list<dag> pattern>
359 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
360 opc, asm, "", pattern> {
361 let Inst{20} = 1; // L bit
362 let Inst{21} = 0; // W bit
363 let Inst{22} = 0; // B bit
364 let Inst{24} = 1; // P bit
365 let Inst{27-26} = {0,1};
367 class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
368 string asm, list<dag> pattern>
369 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
371 let Inst{20} = 1; // L bit
372 let Inst{21} = 0; // W bit
373 let Inst{22} = 0; // B bit
374 let Inst{24} = 1; // P bit
375 let Inst{27-26} = {0,1};
377 class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
378 string opc, string asm, list<dag> pattern>
379 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
380 opc, asm, "", pattern> {
381 let Inst{20} = 1; // L bit
382 let Inst{21} = 0; // W bit
383 let Inst{22} = 1; // B bit
384 let Inst{24} = 1; // P bit
385 let Inst{27-26} = {0,1};
387 class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
388 string asm, list<dag> pattern>
389 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
391 let Inst{20} = 1; // L bit
392 let Inst{21} = 0; // W bit
393 let Inst{22} = 1; // B bit
394 let Inst{24} = 1; // P bit
395 let Inst{27-26} = {0,1};
399 class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
400 string opc, string asm, list<dag> pattern>
401 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
402 opc, asm, "", pattern> {
403 let Inst{20} = 0; // L bit
404 let Inst{21} = 0; // W bit
405 let Inst{22} = 0; // B bit
406 let Inst{24} = 1; // P bit
407 let Inst{27-26} = {0,1};
409 class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
410 string asm, list<dag> pattern>
411 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
413 let Inst{20} = 0; // L bit
414 let Inst{21} = 0; // W bit
415 let Inst{22} = 0; // B bit
416 let Inst{24} = 1; // P bit
417 let Inst{27-26} = {0,1};
419 class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
420 string opc, string asm, list<dag> pattern>
421 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
422 opc, asm, "", pattern> {
423 let Inst{20} = 0; // L bit
424 let Inst{21} = 0; // W bit
425 let Inst{22} = 1; // B bit
426 let Inst{24} = 1; // P bit
427 let Inst{27-26} = {0,1};
429 class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
430 string asm, list<dag> pattern>
431 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
433 let Inst{20} = 0; // L bit
434 let Inst{21} = 0; // W bit
435 let Inst{22} = 1; // B bit
436 let Inst{24} = 1; // P bit
437 let Inst{27-26} = {0,1};
441 class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
442 string opc, string asm, string cstr, list<dag> pattern>
443 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
444 opc, asm, cstr, pattern> {
445 let Inst{20} = 1; // L bit
446 let Inst{21} = 1; // W bit
447 let Inst{22} = 0; // B bit
448 let Inst{24} = 1; // P bit
449 let Inst{27-26} = {0,1};
451 class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
452 string opc, string asm, string cstr, list<dag> pattern>
453 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
454 opc, asm, cstr, pattern> {
455 let Inst{20} = 1; // L bit
456 let Inst{21} = 1; // W bit
457 let Inst{22} = 1; // B bit
458 let Inst{24} = 1; // P bit
459 let Inst{27-26} = {0,1};
462 // Pre-indexed stores
463 class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
464 string opc, string asm, string cstr, list<dag> pattern>
465 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
466 opc, asm, cstr, pattern> {
467 let Inst{20} = 0; // L bit
468 let Inst{21} = 1; // W bit
469 let Inst{22} = 0; // B bit
470 let Inst{24} = 1; // P bit
471 let Inst{27-26} = {0,1};
473 class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
474 string opc, string asm, string cstr, list<dag> pattern>
475 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
476 opc, asm, cstr, pattern> {
477 let Inst{20} = 0; // L bit
478 let Inst{21} = 1; // W bit
479 let Inst{22} = 1; // B bit
480 let Inst{24} = 1; // P bit
481 let Inst{27-26} = {0,1};
484 // Post-indexed loads
485 class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
486 string opc, string asm, string cstr, list<dag> pattern>
487 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
488 opc, asm, cstr,pattern> {
489 let Inst{20} = 1; // L bit
490 let Inst{21} = 0; // W bit
491 let Inst{22} = 0; // B bit
492 let Inst{24} = 0; // P bit
493 let Inst{27-26} = {0,1};
495 class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
496 string opc, string asm, string cstr, list<dag> pattern>
497 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
498 opc, asm, cstr,pattern> {
499 let Inst{20} = 1; // L bit
500 let Inst{21} = 0; // W bit
501 let Inst{22} = 1; // B bit
502 let Inst{24} = 0; // P bit
503 let Inst{27-26} = {0,1};
506 // Post-indexed stores
507 class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
508 string opc, string asm, string cstr, list<dag> pattern>
509 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
510 opc, asm, cstr,pattern> {
511 let Inst{20} = 0; // L bit
512 let Inst{21} = 0; // W bit
513 let Inst{22} = 0; // B bit
514 let Inst{24} = 0; // P bit
515 let Inst{27-26} = {0,1};
517 class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
518 string opc, string asm, string cstr, list<dag> pattern>
519 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
520 opc, asm, cstr,pattern> {
521 let Inst{20} = 0; // L bit
522 let Inst{21} = 0; // W bit
523 let Inst{22} = 1; // B bit
524 let Inst{24} = 0; // P bit
525 let Inst{27-26} = {0,1};
528 // addrmode3 instructions
529 class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
530 string opc, string asm, list<dag> pattern>
531 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
532 opc, asm, "", pattern>;
533 class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
534 string asm, list<dag> pattern>
535 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
539 class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
540 string opc, string asm, list<dag> pattern>
541 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
542 opc, asm, "", pattern> {
544 let Inst{5} = 1; // H bit
545 let Inst{6} = 0; // S bit
547 let Inst{20} = 1; // L bit
548 let Inst{21} = 0; // W bit
549 let Inst{24} = 1; // P bit
550 let Inst{27-25} = 0b000;
552 class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
553 string asm, list<dag> pattern>
554 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
557 let Inst{5} = 1; // H bit
558 let Inst{6} = 0; // S bit
560 let Inst{20} = 1; // L bit
561 let Inst{21} = 0; // W bit
562 let Inst{24} = 1; // P bit
564 class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
565 string opc, string asm, list<dag> pattern>
566 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
567 opc, asm, "", pattern> {
569 let Inst{5} = 1; // H bit
570 let Inst{6} = 1; // S bit
572 let Inst{20} = 1; // L bit
573 let Inst{21} = 0; // W bit
574 let Inst{24} = 1; // P bit
575 let Inst{27-25} = 0b000;
577 class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
578 string asm, list<dag> pattern>
579 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
582 let Inst{5} = 1; // H bit
583 let Inst{6} = 1; // S bit
585 let Inst{20} = 1; // L bit
586 let Inst{21} = 0; // W bit
587 let Inst{24} = 1; // P bit
589 class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
590 string opc, string asm, list<dag> pattern>
591 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
592 opc, asm, "", pattern> {
594 let Inst{5} = 0; // H bit
595 let Inst{6} = 1; // S bit
597 let Inst{20} = 1; // L bit
598 let Inst{21} = 0; // W bit
599 let Inst{24} = 1; // P bit
600 let Inst{27-25} = 0b000;
602 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
603 string asm, list<dag> pattern>
604 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
607 let Inst{5} = 0; // H bit
608 let Inst{6} = 1; // S bit
610 let Inst{20} = 1; // L bit
611 let Inst{21} = 0; // W bit
612 let Inst{24} = 1; // P bit
614 class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
615 string opc, string asm, list<dag> pattern>
616 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
617 opc, asm, "", pattern> {
619 let Inst{5} = 0; // H bit
620 let Inst{6} = 1; // S bit
622 let Inst{20} = 0; // L bit
623 let Inst{21} = 0; // W bit
624 let Inst{24} = 1; // P bit
625 let Inst{27-25} = 0b000;
629 class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
630 string opc, string asm, list<dag> pattern>
631 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
632 opc, asm, "", pattern> {
634 let Inst{5} = 1; // H bit
635 let Inst{6} = 0; // S bit
637 let Inst{20} = 0; // L bit
638 let Inst{21} = 0; // W bit
639 let Inst{24} = 1; // P bit
640 let Inst{27-25} = 0b000;
642 class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
643 string asm, list<dag> pattern>
644 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
647 let Inst{5} = 1; // H bit
648 let Inst{6} = 0; // S bit
650 let Inst{20} = 0; // L bit
651 let Inst{21} = 0; // W bit
652 let Inst{24} = 1; // P bit
654 class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
655 string opc, string asm, list<dag> pattern>
656 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
657 opc, asm, "", pattern> {
659 let Inst{5} = 1; // H bit
660 let Inst{6} = 1; // S bit
662 let Inst{20} = 0; // L bit
663 let Inst{21} = 0; // W bit
664 let Inst{24} = 1; // P bit
665 let Inst{27-25} = 0b000;
669 class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
670 string opc, string asm, string cstr, list<dag> pattern>
671 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
672 opc, asm, cstr, pattern> {
674 let Inst{5} = 1; // H bit
675 let Inst{6} = 0; // S bit
677 let Inst{20} = 1; // L bit
678 let Inst{21} = 1; // W bit
679 let Inst{24} = 1; // P bit
680 let Inst{27-25} = 0b000;
682 class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
683 string opc, string asm, string cstr, list<dag> pattern>
684 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
685 opc, asm, cstr, pattern> {
687 let Inst{5} = 1; // H bit
688 let Inst{6} = 1; // S bit
690 let Inst{20} = 1; // L bit
691 let Inst{21} = 1; // W bit
692 let Inst{24} = 1; // P bit
693 let Inst{27-25} = 0b000;
695 class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
696 string opc, string asm, string cstr, list<dag> pattern>
697 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
698 opc, asm, cstr, pattern> {
700 let Inst{5} = 0; // H bit
701 let Inst{6} = 1; // S bit
703 let Inst{20} = 1; // L bit
704 let Inst{21} = 1; // W bit
705 let Inst{24} = 1; // P bit
706 let Inst{27-25} = 0b000;
709 // Pre-indexed stores
710 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
711 string opc, string asm, string cstr, list<dag> pattern>
712 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
713 opc, asm, cstr, pattern> {
715 let Inst{5} = 1; // H bit
716 let Inst{6} = 0; // S bit
718 let Inst{20} = 0; // L bit
719 let Inst{21} = 1; // W bit
720 let Inst{24} = 1; // P bit
721 let Inst{27-25} = 0b000;
724 // Post-indexed loads
725 class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
726 string opc, string asm, string cstr, list<dag> pattern>
727 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
728 opc, asm, cstr,pattern> {
730 let Inst{5} = 1; // H bit
731 let Inst{6} = 0; // S bit
733 let Inst{20} = 1; // L bit
734 let Inst{21} = 1; // W bit
735 let Inst{24} = 0; // P bit
736 let Inst{27-25} = 0b000;
738 class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
739 string opc, string asm, string cstr, list<dag> pattern>
740 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
741 opc, asm, cstr,pattern> {
743 let Inst{5} = 1; // H bit
744 let Inst{6} = 1; // S bit
746 let Inst{20} = 1; // L bit
747 let Inst{21} = 1; // W bit
748 let Inst{24} = 0; // P bit
749 let Inst{27-25} = 0b000;
751 class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
752 string opc, string asm, string cstr, list<dag> pattern>
753 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
754 opc, asm, cstr,pattern> {
756 let Inst{5} = 0; // H bit
757 let Inst{6} = 1; // S bit
759 let Inst{20} = 1; // L bit
760 let Inst{21} = 1; // W bit
761 let Inst{24} = 0; // P bit
762 let Inst{27-25} = 0b000;
765 // Post-indexed stores
766 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
767 string opc, string asm, string cstr, list<dag> pattern>
768 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
769 opc, asm, cstr,pattern> {
771 let Inst{5} = 1; // H bit
772 let Inst{6} = 0; // S bit
774 let Inst{20} = 0; // L bit
775 let Inst{21} = 1; // W bit
776 let Inst{24} = 0; // P bit
777 let Inst{27-25} = 0b000;
781 // addrmode4 instructions
782 class AXI4ld<dag oops, dag iops, Format f, InstrItinClass itin,
783 string asm, list<dag> pattern>
784 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin,
786 let Inst{20} = 1; // L bit
787 let Inst{22} = 0; // S bit
788 let Inst{27-25} = 0b100;
790 class AXI4st<dag oops, dag iops, Format f, InstrItinClass itin,
791 string asm, list<dag> pattern>
792 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin,
794 let Inst{20} = 0; // L bit
795 let Inst{22} = 0; // S bit
796 let Inst{27-25} = 0b100;
799 // Unsigned multiply, multiply-accumulate instructions.
800 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
801 string opc, string asm, list<dag> pattern>
802 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
803 opc, asm, "", pattern> {
804 let Inst{7-4} = 0b1001;
805 let Inst{20} = 0; // S bit
806 let Inst{27-21} = opcod;
808 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
809 string opc, string asm, list<dag> pattern>
810 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
811 opc, asm, "", pattern> {
812 let Inst{7-4} = 0b1001;
813 let Inst{27-21} = opcod;
816 // Most significant word multiply
817 class AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
818 string opc, string asm, list<dag> pattern>
819 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
820 opc, asm, "", pattern> {
821 let Inst{7-4} = 0b1001;
823 let Inst{27-21} = opcod;
826 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
827 class AMulxyI<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
828 string opc, string asm, list<dag> pattern>
829 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
830 opc, asm, "", pattern> {
834 let Inst{27-21} = opcod;
837 // Extend instructions.
838 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
839 string opc, string asm, list<dag> pattern>
840 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
841 opc, asm, "", pattern> {
842 let Inst{7-4} = 0b0111;
843 let Inst{27-20} = opcod;
846 // Misc Arithmetic instructions.
847 class AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
848 string opc, string asm, list<dag> pattern>
849 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
850 opc, asm, "", pattern> {
851 let Inst{27-20} = opcod;
854 //===----------------------------------------------------------------------===//
856 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
857 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
858 list<Predicate> Predicates = [IsARM];
860 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
861 list<Predicate> Predicates = [IsARM, HasV5TE];
863 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
864 list<Predicate> Predicates = [IsARM, HasV6];
867 //===----------------------------------------------------------------------===//
869 // Thumb Instruction Format Definitions.
872 // TI - Thumb instruction.
874 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
875 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
876 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
877 let OutOperandList = oops;
878 let InOperandList = iops;
880 let Pattern = pattern;
881 list<Predicate> Predicates = [IsThumb];
884 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
885 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
887 // Two-address instructions
888 class TIt<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
889 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", pattern>;
891 // tBL, tBX 32-bit instructions
892 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
893 dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
894 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, Encoding {
895 let Inst{31-27} = opcod1;
896 let Inst{15-14} = opcod2;
897 let Inst{12} = opcod3;
900 // BR_JT instructions
901 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
902 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
905 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
906 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
907 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
908 let OutOperandList = oops;
909 let InOperandList = iops;
911 let Pattern = pattern;
912 list<Predicate> Predicates = [IsThumb1Only];
915 class T1I<dag oops, dag iops, InstrItinClass itin,
916 string asm, list<dag> pattern>
917 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
918 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
919 string asm, list<dag> pattern>
920 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
921 class T1JTI<dag oops, dag iops, InstrItinClass itin,
922 string asm, list<dag> pattern>
923 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
925 // Two-address instructions
926 class T1It<dag oops, dag iops, InstrItinClass itin,
927 string asm, list<dag> pattern>
928 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
929 asm, "$lhs = $dst", pattern>;
931 // Thumb1 instruction that can either be predicated or set CPSR.
932 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
934 string opc, string asm, string cstr, list<dag> pattern>
935 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
936 let OutOperandList = !con(oops, (ops s_cc_out:$s));
937 let InOperandList = !con(iops, (ops pred:$p));
938 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
939 let Pattern = pattern;
940 list<Predicate> Predicates = [IsThumb1Only];
943 class T1sI<dag oops, dag iops, InstrItinClass itin,
944 string opc, string asm, list<dag> pattern>
945 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
947 // Two-address instructions
948 class T1sIt<dag oops, dag iops, InstrItinClass itin,
949 string opc, string asm, list<dag> pattern>
950 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
951 "$lhs = $dst", pattern>;
953 // Thumb1 instruction that can be predicated.
954 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
956 string opc, string asm, string cstr, list<dag> pattern>
957 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
958 let OutOperandList = oops;
959 let InOperandList = !con(iops, (ops pred:$p));
960 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
961 let Pattern = pattern;
962 list<Predicate> Predicates = [IsThumb1Only];
965 class T1pI<dag oops, dag iops, InstrItinClass itin,
966 string opc, string asm, list<dag> pattern>
967 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
969 // Two-address instructions
970 class T1pIt<dag oops, dag iops, InstrItinClass itin,
971 string opc, string asm, list<dag> pattern>
972 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
973 "$lhs = $dst", pattern>;
975 class T1pI1<dag oops, dag iops, InstrItinClass itin,
976 string opc, string asm, list<dag> pattern>
977 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
978 class T1pI2<dag oops, dag iops, InstrItinClass itin,
979 string opc, string asm, list<dag> pattern>
980 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
981 class T1pI4<dag oops, dag iops, InstrItinClass itin,
982 string opc, string asm, list<dag> pattern>
983 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
984 class T1pIs<dag oops, dag iops,
985 InstrItinClass itin, string opc, string asm, list<dag> pattern>
986 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
988 class Encoding16 : Encoding {
989 let Inst{31-16} = 0x0000;
992 // A6.2 16-bit Thumb instruction encoding
993 class T1Encoding<bits<6> opcode> : Encoding16 {
994 let Inst{15-10} = opcode;
997 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
998 class T1General<bits<5> opcode> : Encoding16 {
999 let Inst{15-14} = 0b00;
1000 let Inst{13-9} = opcode;
1003 // A6.2.2 Data-processing encoding.
1004 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1005 let Inst{15-10} = 0b010000;
1006 let Inst{9-6} = opcode;
1009 // A6.2.3 Special data instructions and branch and exchange encoding.
1010 class T1Special<bits<4> opcode> : Encoding16 {
1011 let Inst{15-10} = 0b010001;
1012 let Inst{9-6} = opcode;
1015 // A6.2.4 Load/store single data item encoding.
1016 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1017 let Inst{15-12} = opA;
1018 let Inst{11-9} = opB;
1020 class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
1021 class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
1022 class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
1023 class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
1024 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1026 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1027 class T1Misc<bits<7> opcode> : Encoding16 {
1028 let Inst{15-12} = 0b1011;
1029 let Inst{11-5} = opcode;
1032 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1033 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1034 InstrItinClass itin,
1035 string opc, string asm, string cstr, list<dag> pattern>
1036 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1037 let OutOperandList = oops;
1038 let InOperandList = !con(iops, (ops pred:$p));
1039 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1040 let Pattern = pattern;
1041 list<Predicate> Predicates = [IsThumb2];
1044 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as
1045 // an input operand since by default it's a zero register. It will
1046 // become an implicit def once it's "flipped".
1047 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1049 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1050 InstrItinClass itin,
1051 string opc, string asm, string cstr, list<dag> pattern>
1052 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1053 let OutOperandList = oops;
1054 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
1055 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
1056 let Pattern = pattern;
1057 list<Predicate> Predicates = [IsThumb2];
1061 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1062 InstrItinClass itin,
1063 string asm, string cstr, list<dag> pattern>
1064 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1065 let OutOperandList = oops;
1066 let InOperandList = iops;
1067 let AsmString = asm;
1068 let Pattern = pattern;
1069 list<Predicate> Predicates = [IsThumb2];
1072 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1073 InstrItinClass itin,
1074 string asm, string cstr, list<dag> pattern>
1075 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1076 let OutOperandList = oops;
1077 let InOperandList = iops;
1078 let AsmString = asm;
1079 let Pattern = pattern;
1080 list<Predicate> Predicates = [IsThumb1Only];
1083 class T2I<dag oops, dag iops, InstrItinClass itin,
1084 string opc, string asm, list<dag> pattern>
1085 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1086 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1087 string opc, string asm, list<dag> pattern>
1088 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "", pattern>;
1089 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1090 string opc, string asm, list<dag> pattern>
1091 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1092 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1093 string opc, string asm, list<dag> pattern>
1094 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1095 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1096 string opc, string asm, list<dag> pattern>
1097 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1098 class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
1099 string opc, string asm, list<dag> pattern>
1100 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1102 let Inst{31-27} = 0b11101;
1103 let Inst{26-25} = 0b00;
1105 let Inst{23} = ?; // The U bit.
1108 let Inst{20} = load;
1111 class T2sI<dag oops, dag iops, InstrItinClass itin,
1112 string opc, string asm, list<dag> pattern>
1113 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1115 class T2XI<dag oops, dag iops, InstrItinClass itin,
1116 string asm, list<dag> pattern>
1117 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1118 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1119 string asm, list<dag> pattern>
1120 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1122 class T2Ix2<dag oops, dag iops, InstrItinClass itin,
1123 string opc, string asm, list<dag> pattern>
1124 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
1127 // T2Iidxldst - Thumb2 indexed load / store instructions.
1128 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1130 AddrMode am, IndexMode im, InstrItinClass itin,
1131 string opc, string asm, string cstr, list<dag> pattern>
1132 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1133 let OutOperandList = oops;
1134 let InOperandList = !con(iops, (ops pred:$p));
1135 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1136 let Pattern = pattern;
1137 list<Predicate> Predicates = [IsThumb2];
1138 let Inst{31-27} = 0b11111;
1139 let Inst{26-25} = 0b00;
1140 let Inst{24} = signed;
1142 let Inst{22-21} = opcod;
1143 let Inst{20} = load;
1145 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1146 let Inst{10} = pre; // The P bit.
1147 let Inst{8} = 1; // The W bit.
1150 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1151 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1152 list<Predicate> Predicates = [IsThumb1Only, HasV5T];
1155 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1156 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1157 list<Predicate> Predicates = [IsThumb1Only];
1160 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1161 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1162 list<Predicate> Predicates = [IsThumb2];
1165 //===----------------------------------------------------------------------===//
1167 //===----------------------------------------------------------------------===//
1168 // ARM VFP Instruction templates.
1171 // Almost all VFP instructions are predicable.
1172 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1173 IndexMode im, Format f, InstrItinClass itin,
1174 string opc, string asm, string cstr, list<dag> pattern>
1175 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1176 let OutOperandList = oops;
1177 let InOperandList = !con(iops, (ops pred:$p));
1178 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1179 let Pattern = pattern;
1180 list<Predicate> Predicates = [HasVFP2];
1184 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1185 IndexMode im, Format f, InstrItinClass itin,
1186 string asm, string cstr, list<dag> pattern>
1187 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1188 let OutOperandList = oops;
1189 let InOperandList = iops;
1190 let AsmString = asm;
1191 let Pattern = pattern;
1192 list<Predicate> Predicates = [HasVFP2];
1195 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1196 string opc, string asm, list<dag> pattern>
1197 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1198 opc, asm, "", pattern>;
1200 // ARM VFP addrmode5 loads and stores
1201 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1202 InstrItinClass itin,
1203 string opc, string asm, list<dag> pattern>
1204 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1205 VFPLdStFrm, itin, opc, asm, "", pattern> {
1206 // TODO: Mark the instructions with the appropriate subtarget info.
1207 let Inst{27-24} = opcod1;
1208 let Inst{21-20} = opcod2;
1209 let Inst{11-8} = 0b1011;
1211 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1212 let Dom = VFPNeonDomain.Value;
1215 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1216 InstrItinClass itin,
1217 string opc, string asm, list<dag> pattern>
1218 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1219 VFPLdStFrm, itin, opc, asm, "", pattern> {
1220 // TODO: Mark the instructions with the appropriate subtarget info.
1221 let Inst{27-24} = opcod1;
1222 let Inst{21-20} = opcod2;
1223 let Inst{11-8} = 0b1010;
1226 // Load / store multiple
1227 class AXDI5<dag oops, dag iops, InstrItinClass itin,
1228 string asm, list<dag> pattern>
1229 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1230 VFPLdStMulFrm, itin, asm, "", pattern> {
1231 // TODO: Mark the instructions with the appropriate subtarget info.
1232 let Inst{27-25} = 0b110;
1233 let Inst{11-8} = 0b1011;
1235 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1236 let Dom = VFPNeonDomain.Value;
1239 class AXSI5<dag oops, dag iops, InstrItinClass itin,
1240 string asm, list<dag> pattern>
1241 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1242 VFPLdStMulFrm, itin, asm, "", pattern> {
1243 // TODO: Mark the instructions with the appropriate subtarget info.
1244 let Inst{27-25} = 0b110;
1245 let Inst{11-8} = 0b1010;
1248 // Double precision, unary
1249 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1250 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1251 string asm, list<dag> pattern>
1252 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1253 let Inst{27-23} = opcod1;
1254 let Inst{21-20} = opcod2;
1255 let Inst{19-16} = opcod3;
1256 let Inst{11-8} = 0b1011;
1257 let Inst{7-6} = opcod4;
1258 let Inst{4} = opcod5;
1261 // Double precision, binary
1262 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1263 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1264 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1265 let Inst{27-23} = opcod1;
1266 let Inst{21-20} = opcod2;
1267 let Inst{11-8} = 0b1011;
1272 // Single precision, unary
1273 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1274 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1275 string asm, list<dag> pattern>
1276 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1277 let Inst{27-23} = opcod1;
1278 let Inst{21-20} = opcod2;
1279 let Inst{19-16} = opcod3;
1280 let Inst{11-8} = 0b1010;
1281 let Inst{7-6} = opcod4;
1282 let Inst{4} = opcod5;
1285 // Single precision unary, if no NEON
1286 // Same as ASuI except not available if NEON is enabled
1287 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1288 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1289 string asm, list<dag> pattern>
1290 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1292 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1295 // Single precision, binary
1296 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1297 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1298 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1299 let Inst{27-23} = opcod1;
1300 let Inst{21-20} = opcod2;
1301 let Inst{11-8} = 0b1010;
1306 // Single precision binary, if no NEON
1307 // Same as ASbI except not available if NEON is enabled
1308 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1309 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1310 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1311 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1314 // VFP conversion instructions
1315 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1316 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1318 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1319 let Inst{27-23} = opcod1;
1320 let Inst{21-20} = opcod2;
1321 let Inst{19-16} = opcod3;
1322 let Inst{11-8} = opcod4;
1327 // VFP conversion between floating-point and fixed-point
1328 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1329 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1331 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1332 // size (fixed-point number): sx == 0 ? 16 : 32
1333 let Inst{7} = op5; // sx
1336 // VFP conversion instructions, if no NEON
1337 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1338 dag oops, dag iops, InstrItinClass itin,
1339 string opc, string asm, list<dag> pattern>
1340 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1342 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1345 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1346 InstrItinClass itin,
1347 string opc, string asm, list<dag> pattern>
1348 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1349 let Inst{27-20} = opcod1;
1350 let Inst{11-8} = opcod2;
1354 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1355 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1356 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1358 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1359 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1360 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1362 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1363 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1364 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1366 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1367 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1368 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1370 //===----------------------------------------------------------------------===//
1372 //===----------------------------------------------------------------------===//
1373 // ARM NEON Instruction templates.
1376 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
1377 string opc, string dt, string asm, string cstr, list<dag> pattern>
1378 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
1379 let OutOperandList = oops;
1380 let InOperandList = !con(iops, (ops pred:$p));
1381 let AsmString = !strconcat(
1382 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
1383 !strconcat("\t", asm));
1384 let Pattern = pattern;
1385 list<Predicate> Predicates = [HasNEON];
1388 // Same as NeonI except it does not have a "data type" specifier.
1389 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
1390 string opc, string asm, string cstr, list<dag> pattern>
1391 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
1392 let OutOperandList = oops;
1393 let InOperandList = !con(iops, (ops pred:$p));
1394 let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm));
1395 let Pattern = pattern;
1396 list<Predicate> Predicates = [HasNEON];
1399 class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1401 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "",
1405 class NI4<dag oops, dag iops, InstrItinClass itin, string opc,
1406 string asm, list<dag> pattern>
1407 : NeonXI<oops, iops, AddrMode4, IndexModeNone, itin, opc, asm, "",
1411 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1412 dag oops, dag iops, InstrItinClass itin,
1413 string opc, string dt, string asm, string cstr, list<dag> pattern>
1414 : NeonI<oops, iops, AddrMode6, IndexModeNone, itin, opc, dt, asm, cstr,
1416 let Inst{31-24} = 0b11110100;
1417 let Inst{23} = op23;
1418 let Inst{21-20} = op21_20;
1419 let Inst{11-8} = op11_8;
1420 let Inst{7-4} = op7_4;
1423 class NDataI<dag oops, dag iops, InstrItinClass itin,
1424 string opc, string dt, string asm, string cstr, list<dag> pattern>
1425 : NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, dt, asm,
1427 let Inst{31-25} = 0b1111001;
1430 class NDataXI<dag oops, dag iops, InstrItinClass itin,
1431 string opc, string asm, string cstr, list<dag> pattern>
1432 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm,
1434 let Inst{31-25} = 0b1111001;
1437 // NEON "one register and a modified immediate" format.
1438 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1440 dag oops, dag iops, InstrItinClass itin,
1441 string opc, string dt, string asm, string cstr, list<dag> pattern>
1442 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1443 let Inst{23} = op23;
1444 let Inst{21-19} = op21_19;
1445 let Inst{11-8} = op11_8;
1452 // NEON 2 vector register format.
1453 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1454 bits<5> op11_7, bit op6, bit op4,
1455 dag oops, dag iops, InstrItinClass itin,
1456 string opc, string dt, string asm, string cstr, list<dag> pattern>
1457 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1458 let Inst{24-23} = op24_23;
1459 let Inst{21-20} = op21_20;
1460 let Inst{19-18} = op19_18;
1461 let Inst{17-16} = op17_16;
1462 let Inst{11-7} = op11_7;
1467 // Same as N2V except it doesn't have a datatype suffix.
1468 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1469 bits<5> op11_7, bit op6, bit op4,
1470 dag oops, dag iops, InstrItinClass itin,
1471 string opc, string asm, string cstr, list<dag> pattern>
1472 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
1473 let Inst{24-23} = op24_23;
1474 let Inst{21-20} = op21_20;
1475 let Inst{19-18} = op19_18;
1476 let Inst{17-16} = op17_16;
1477 let Inst{11-7} = op11_7;
1482 // NEON 2 vector register with immediate.
1483 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1484 dag oops, dag iops, InstrItinClass itin,
1485 string opc, string dt, string asm, string cstr, list<dag> pattern>
1486 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1487 let Inst{24} = op24;
1488 let Inst{23} = op23;
1489 let Inst{11-8} = op11_8;
1495 // NEON 3 vector register format.
1496 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1497 dag oops, dag iops, InstrItinClass itin,
1498 string opc, string dt, string asm, string cstr, list<dag> pattern>
1499 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1500 let Inst{24} = op24;
1501 let Inst{23} = op23;
1502 let Inst{21-20} = op21_20;
1503 let Inst{11-8} = op11_8;
1508 // Same as N3VX except it doesn't have a data type suffix.
1509 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1510 dag oops, dag iops, InstrItinClass itin,
1511 string opc, string asm, string cstr, list<dag> pattern>
1512 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
1513 let Inst{24} = op24;
1514 let Inst{23} = op23;
1515 let Inst{21-20} = op21_20;
1516 let Inst{11-8} = op11_8;
1521 // NEON VMOVs between scalar and core registers.
1522 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1523 dag oops, dag iops, Format f, InstrItinClass itin,
1524 string opc, string dt, string asm, list<dag> pattern>
1525 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain,
1527 let Inst{27-20} = opcod1;
1528 let Inst{11-8} = opcod2;
1529 let Inst{6-5} = opcod3;
1532 let OutOperandList = oops;
1533 let InOperandList = !con(iops, (ops pred:$p));
1534 let AsmString = !strconcat(
1535 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
1536 !strconcat("\t", asm));
1537 let Pattern = pattern;
1538 list<Predicate> Predicates = [HasNEON];
1540 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1541 dag oops, dag iops, InstrItinClass itin,
1542 string opc, string dt, string asm, list<dag> pattern>
1543 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, itin,
1544 opc, dt, asm, pattern>;
1545 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1546 dag oops, dag iops, InstrItinClass itin,
1547 string opc, string dt, string asm, list<dag> pattern>
1548 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, itin,
1549 opc, dt, asm, pattern>;
1550 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1551 dag oops, dag iops, InstrItinClass itin,
1552 string opc, string dt, string asm, list<dag> pattern>
1553 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin,
1554 opc, dt, asm, pattern>;
1556 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1557 // for single-precision FP.
1558 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1559 list<Predicate> Predicates = [HasNEON,UseNEONForFP];