1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm1 : Format<2>;
24 def MulFrm2 : Format<3>;
25 def MulSMLAW : Format<4>;
26 def MulSMULW : Format<5>;
27 def MulSMLA : Format<6>;
28 def MulSMUL : Format<7>;
29 def Branch : Format<8>;
30 def BranchMisc : Format<9>;
32 def DPFrm : Format<10>;
33 def DPSoRegFrm : Format<11>;
35 def LdFrm : Format<12>;
36 def StFrm : Format<13>;
37 def LdMiscFrm : Format<14>;
38 def StMiscFrm : Format<15>;
39 def LdMulFrm : Format<16>;
40 def StMulFrm : Format<17>;
42 def ArithMisc : Format<18>;
43 def ThumbFrm : Format<19>;
44 def VFPFrm : Format<20>;
46 // Misc flag for data processing instructions that indicates whether
47 // the instruction has a Rn register operand.
48 class UnaryDP { bit isUnaryDataProc = 1; }
50 //===----------------------------------------------------------------------===//
52 // ARM Instruction templates.
55 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
56 Format f, string cstr>
60 let Namespace = "ARM";
62 bits<4> Opcode = opcod;
66 bits<4> AddrModeBits = AM.Value;
69 bits<3> SizeFlag = SZ.Value;
72 bits<2> IndexModeBits = IM.Value;
75 bits<5> Form = F.Value;
78 // Attributes specific to ARM instructions...
80 bit isUnaryDataProc = 0;
82 let Constraints = cstr;
85 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
86 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
87 let OutOperandList = oops;
88 let InOperandList = iops;
90 let Pattern = pattern;
93 // Almost all ARM instructions are predicable.
94 class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
95 IndexMode im, Format f, string opc, string asm, string cstr,
97 : InstARM<opcod, am, sz, im, f, cstr> {
98 let OutOperandList = oops;
99 let InOperandList = !con(iops, (ops pred:$p));
100 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
101 let Pattern = pattern;
102 list<Predicate> Predicates = [IsARM];
105 // Same as I except it can optionally modify CPSR. Note it's modeled as
106 // an input operand since by default it's a zero register. It will
107 // become an implicit def once it's "flipped".
108 class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
109 IndexMode im, Format f, string opc, string asm, string cstr,
111 : InstARM<opcod, am, sz, im, f, cstr> {
112 let OutOperandList = oops;
113 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
114 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
115 let Pattern = pattern;
116 list<Predicate> Predicates = [IsARM];
120 class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
121 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
122 : InstARM<opcod, am, sz, im, f, cstr> {
123 let OutOperandList = oops;
124 let InOperandList = iops;
126 let Pattern = pattern;
127 list<Predicate> Predicates = [IsARM];
130 class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
131 string asm, list<dag> pattern>
132 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
134 class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
135 string asm, list<dag> pattern>
136 : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
138 class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
140 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
143 // Ctrl flow instructions
144 class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
145 string asm, list<dag> pattern>
146 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
148 let Inst{27-24} = opcod;
150 class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
152 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
154 let Inst{27-24} = opcod;
157 class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
159 : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
161 class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
163 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
165 let Inst{27-24} = opcod;
167 class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
168 string asm, list<dag> pattern>
169 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
171 let Inst{27-24} = opcod;
174 // BR_JT instructions
176 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
177 : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
179 let Inst{20} = 0; // S Bit
180 let Inst{24-21} = opcod;
181 let Inst{27-26} = {0,0};
184 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
185 : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
187 let Inst{20} = 0; // S bit
188 let Inst{24-21} = opcod;
189 let Inst{27-26} = {0,0};
192 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
193 : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
195 let Inst{20} = 1; // L bit
196 let Inst{21} = 0; // W bit
197 let Inst{22} = 0; // B bit
198 let Inst{24} = 1; // P bit
199 let Inst{27-26} = {0,1};
203 // addrmode1 instructions
204 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
205 string asm, list<dag> pattern>
206 : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
208 let Inst{24-21} = opcod;
209 let Inst{27-26} = {0,0};
211 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
212 string asm, list<dag> pattern>
213 : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
215 let Inst{24-21} = opcod;
216 let Inst{27-26} = {0,0};
218 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
220 : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
222 let Inst{24-21} = opcod;
223 let Inst{27-26} = {0,0};
225 class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
226 string asm, list<dag> pattern>
227 : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
231 // addrmode2 loads and stores
232 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
233 string asm, list<dag> pattern>
234 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
236 let Inst{27-26} = {0,1};
240 class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
241 string asm, list<dag> pattern>
242 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
244 let Inst{20} = 1; // L bit
245 let Inst{21} = 0; // W bit
246 let Inst{22} = 0; // B bit
247 let Inst{24} = 1; // P bit
248 let Inst{27-26} = {0,1};
250 class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
252 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
254 let Inst{20} = 1; // L bit
255 let Inst{21} = 0; // W bit
256 let Inst{22} = 0; // B bit
257 let Inst{24} = 1; // P bit
258 let Inst{27-26} = {0,1};
260 class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
261 string asm, list<dag> pattern>
262 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
264 let Inst{20} = 1; // L bit
265 let Inst{21} = 0; // W bit
266 let Inst{22} = 1; // B bit
267 let Inst{24} = 1; // P bit
268 let Inst{27-26} = {0,1};
270 class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
272 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
274 let Inst{20} = 1; // L bit
275 let Inst{21} = 0; // W bit
276 let Inst{22} = 1; // B bit
277 let Inst{24} = 1; // P bit
278 let Inst{27-26} = {0,1};
282 class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
283 string asm, list<dag> pattern>
284 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
286 let Inst{20} = 0; // L bit
287 let Inst{21} = 0; // W bit
288 let Inst{22} = 0; // B bit
289 let Inst{24} = 1; // P bit
290 let Inst{27-26} = {0,1};
292 class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
294 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
296 let Inst{20} = 0; // L bit
297 let Inst{21} = 0; // W bit
298 let Inst{22} = 0; // B bit
299 let Inst{24} = 1; // P bit
300 let Inst{27-26} = {0,1};
302 class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
303 string asm, list<dag> pattern>
304 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
306 let Inst{20} = 0; // L bit
307 let Inst{21} = 0; // W bit
308 let Inst{22} = 1; // B bit
309 let Inst{24} = 1; // P bit
310 let Inst{27-26} = {0,1};
312 class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
314 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
316 let Inst{20} = 0; // L bit
317 let Inst{21} = 0; // W bit
318 let Inst{22} = 1; // B bit
319 let Inst{24} = 1; // P bit
320 let Inst{27-26} = {0,1};
324 class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
325 string asm, string cstr, list<dag> pattern>
326 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
327 asm, cstr, pattern> {
328 let Inst{20} = 1; // L bit
329 let Inst{21} = 1; // W bit
330 let Inst{22} = 0; // B bit
331 let Inst{24} = 1; // P bit
332 let Inst{27-26} = {0,1};
334 class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
335 string asm, string cstr, list<dag> pattern>
336 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
337 asm, cstr, pattern> {
338 let Inst{20} = 1; // L bit
339 let Inst{21} = 1; // W bit
340 let Inst{22} = 1; // B bit
341 let Inst{24} = 1; // P bit
342 let Inst{27-26} = {0,1};
345 // Pre-indexed stores
346 class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
347 string asm, string cstr, list<dag> pattern>
348 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
349 asm, cstr, pattern> {
350 let Inst{20} = 0; // L bit
351 let Inst{21} = 1; // W bit
352 let Inst{22} = 0; // B bit
353 let Inst{24} = 1; // P bit
354 let Inst{27-26} = {0,1};
356 class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
357 string asm, string cstr, list<dag> pattern>
358 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
359 asm, cstr, pattern> {
360 let Inst{20} = 0; // L bit
361 let Inst{21} = 1; // W bit
362 let Inst{22} = 1; // B bit
363 let Inst{24} = 1; // P bit
364 let Inst{27-26} = {0,1};
367 // Post-indexed loads
368 class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
369 string asm, string cstr, list<dag> pattern>
370 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
372 let Inst{20} = 1; // L bit
373 let Inst{21} = 0; // W bit
374 let Inst{22} = 0; // B bit
375 let Inst{24} = 0; // P bit
376 let Inst{27-26} = {0,1};
378 class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
379 string asm, string cstr, list<dag> pattern>
380 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
382 let Inst{20} = 1; // L bit
383 let Inst{21} = 0; // W bit
384 let Inst{22} = 1; // B bit
385 let Inst{24} = 0; // P bit
386 let Inst{27-26} = {0,1};
389 // Post-indexed stores
390 class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
391 string asm, string cstr, list<dag> pattern>
392 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
394 let Inst{20} = 0; // L bit
395 let Inst{21} = 0; // W bit
396 let Inst{22} = 0; // B bit
397 let Inst{24} = 0; // P bit
398 let Inst{27-26} = {0,1};
400 class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
401 string asm, string cstr, list<dag> pattern>
402 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
404 let Inst{20} = 0; // L bit
405 let Inst{21} = 0; // W bit
406 let Inst{22} = 1; // B bit
407 let Inst{24} = 0; // P bit
408 let Inst{27-26} = {0,1};
411 // addrmode3 instructions
412 class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
413 string asm, list<dag> pattern>
414 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
416 class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
418 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
422 class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
423 string asm, list<dag> pattern>
424 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
427 let Inst{5} = 1; // H bit
428 let Inst{6} = 0; // S bit
430 let Inst{20} = 1; // L bit
431 let Inst{21} = 0; // W bit
432 let Inst{24} = 1; // P bit
434 class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
436 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
439 let Inst{5} = 1; // H bit
440 let Inst{6} = 0; // S bit
442 let Inst{20} = 1; // L bit
443 let Inst{21} = 0; // W bit
444 let Inst{24} = 1; // P bit
446 class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
447 string asm, list<dag> pattern>
448 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
451 let Inst{5} = 1; // H bit
452 let Inst{6} = 1; // S bit
454 let Inst{20} = 1; // L bit
455 let Inst{21} = 0; // W bit
456 let Inst{24} = 1; // P bit
458 class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
460 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
463 let Inst{5} = 1; // H bit
464 let Inst{6} = 1; // S bit
466 let Inst{20} = 1; // L bit
467 let Inst{21} = 0; // W bit
468 let Inst{24} = 1; // P bit
470 class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
471 string asm, list<dag> pattern>
472 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
475 let Inst{5} = 0; // H bit
476 let Inst{6} = 1; // S bit
478 let Inst{20} = 1; // L bit
479 let Inst{21} = 0; // W bit
480 let Inst{24} = 1; // P bit
482 class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
484 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
487 let Inst{5} = 0; // H bit
488 let Inst{6} = 1; // S bit
490 let Inst{20} = 1; // L bit
491 let Inst{21} = 0; // W bit
492 let Inst{24} = 1; // P bit
494 class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
495 string asm, list<dag> pattern>
496 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
499 let Inst{5} = 0; // H bit
500 let Inst{6} = 1; // S bit
502 let Inst{20} = 0; // L bit
503 let Inst{21} = 0; // W bit
504 let Inst{24} = 1; // P bit
508 class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
509 string asm, list<dag> pattern>
510 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
513 let Inst{5} = 1; // H bit
514 let Inst{6} = 0; // S bit
516 let Inst{20} = 0; // L bit
517 let Inst{21} = 0; // W bit
518 let Inst{24} = 1; // P bit
520 class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm,
522 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
525 let Inst{5} = 1; // H bit
526 let Inst{6} = 0; // S bit
528 let Inst{20} = 0; // L bit
529 let Inst{21} = 0; // W bit
530 let Inst{24} = 1; // P bit
532 class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
533 string asm, list<dag> pattern>
534 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
537 let Inst{5} = 1; // H bit
538 let Inst{6} = 1; // S bit
540 let Inst{20} = 0; // L bit
541 let Inst{21} = 0; // W bit
542 let Inst{24} = 1; // P bit
546 class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
547 string asm, string cstr, list<dag> pattern>
548 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
549 asm, cstr, pattern> {
551 let Inst{5} = 1; // H bit
552 let Inst{6} = 0; // S bit
554 let Inst{20} = 1; // L bit
555 let Inst{21} = 1; // W bit
556 let Inst{24} = 1; // P bit
558 class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
559 string asm, string cstr, list<dag> pattern>
560 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
561 asm, cstr, pattern> {
563 let Inst{5} = 1; // H bit
564 let Inst{6} = 1; // S bit
566 let Inst{20} = 1; // L bit
567 let Inst{21} = 1; // W bit
568 let Inst{24} = 1; // P bit
570 class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
571 string asm, string cstr, list<dag> pattern>
572 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
573 asm, cstr, pattern> {
575 let Inst{5} = 0; // H bit
576 let Inst{6} = 1; // S bit
578 let Inst{20} = 1; // L bit
579 let Inst{21} = 1; // W bit
580 let Inst{24} = 1; // P bit
583 // Pre-indexed stores
584 class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
585 string asm, string cstr, list<dag> pattern>
586 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
587 asm, cstr, pattern> {
589 let Inst{5} = 1; // H bit
590 let Inst{6} = 0; // S bit
592 let Inst{20} = 0; // L bit
593 let Inst{21} = 1; // W bit
594 let Inst{24} = 1; // P bit
597 // Post-indexed loads
598 class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
599 string asm, string cstr, list<dag> pattern>
600 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
603 let Inst{5} = 1; // H bit
604 let Inst{6} = 0; // S bit
606 let Inst{20} = 1; // L bit
607 let Inst{21} = 1; // W bit
608 let Inst{24} = 0; // P bit
610 class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
611 string asm, string cstr, list<dag> pattern>
612 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
615 let Inst{5} = 1; // H bit
616 let Inst{6} = 1; // S bit
618 let Inst{20} = 1; // L bit
619 let Inst{21} = 1; // W bit
620 let Inst{24} = 0; // P bit
622 class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
623 string asm, string cstr, list<dag> pattern>
624 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
627 let Inst{5} = 0; // H bit
628 let Inst{6} = 1; // S bit
630 let Inst{20} = 1; // L bit
631 let Inst{21} = 1; // W bit
632 let Inst{24} = 0; // P bit
635 // Post-indexed stores
636 class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
637 string asm, string cstr, list<dag> pattern>
638 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
641 let Inst{5} = 1; // H bit
642 let Inst{6} = 0; // S bit
644 let Inst{20} = 0; // L bit
645 let Inst{21} = 1; // W bit
646 let Inst{24} = 0; // P bit
650 // addrmode4 instructions
651 class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
652 string asm, list<dag> pattern>
653 : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
655 let Inst{25-27} = {0,0,1};
657 class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm,
659 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
661 let Inst{20} = 1; // L bit
662 let Inst{22} = 0; // S bit
663 let Inst{27-25} = 0b100;
665 class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm,
667 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
669 let Inst{20} = 1; // L bit
670 let Inst{27-25} = 0b100;
672 class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
674 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
676 let Inst{20} = 0; // L bit
677 let Inst{22} = 0; // S bit
678 let Inst{27-25} = 0b100;
681 // Unsigned multiply, multiply-accumulate instructions.
682 class AMul1I<bits<4> opcod, dag oops, dag iops, string opc,
683 string asm, list<dag> pattern>
684 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm1, opc,
686 // FIXME: bits 7-4 should be a sub-mode (for SMLAxx, SMLAWy, ...)
687 let Inst{7-4} = 0b1001;
688 let Inst{27-24} = 0b0000;
689 let Inst{23-20} = opcod;
691 class AsMul1I<bits<4> opcod, dag oops, dag iops, string opc,
692 string asm, list<dag> pattern>
693 : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm1, opc,
695 // FIXME: bits 7-4 should be a sub-mode (for SMLAxx, SMLAWy, ...)
696 let Inst{7-4} = 0b1001;
697 let Inst{27-24} = 0b0000;
698 let Inst{23-20} = opcod;
701 //===----------------------------------------------------------------------===//
703 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
704 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
705 list<Predicate> Predicates = [IsARM];
707 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
708 list<Predicate> Predicates = [IsARM, HasV5TE];
710 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
711 list<Predicate> Predicates = [IsARM, HasV6];
714 //===----------------------------------------------------------------------===//
716 // Thumb Instruction Format Definitions.
720 // TI - Thumb instruction.
722 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
723 string asm, string cstr, list<dag> pattern>
724 // FIXME: Set all opcodes to 0 for now.
725 : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
726 let OutOperandList = outs;
727 let InOperandList = ins;
729 let Pattern = pattern;
730 list<Predicate> Predicates = [IsThumb];
733 class TI<dag outs, dag ins, string asm, list<dag> pattern>
734 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
735 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
736 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
737 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
738 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
739 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
740 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
741 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
742 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
744 // Two-address instructions
745 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
746 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
748 // BL, BLX(1) are translated by assembler into two instructions
749 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
750 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
752 // BR_JT instructions
753 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
754 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
757 //===----------------------------------------------------------------------===//
760 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
761 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
762 list<Predicate> Predicates = [IsThumb];
765 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
766 list<Predicate> Predicates = [IsThumb, HasV5T];