1 //===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
71 def DPSoRegImmFrm : Format<42>;
75 // The instruction has an Rn register operand.
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
77 // it doesn't have a Rn operand.
78 class UnaryDP { bit isUnaryDataProc = 1; }
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
82 class Xform16Bit { bit canXformTo16Bit = 1; }
84 //===----------------------------------------------------------------------===//
85 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 // FIXME: Once the JIT is MC-ized, these can go away.
90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>;
102 def AddrModeT1_4 : AddrMode<9>;
103 def AddrModeT1_s : AddrMode<10>;
104 def AddrModeT2_i12 : AddrMode<11>;
105 def AddrModeT2_i8 : AddrMode<12>;
106 def AddrModeT2_so : AddrMode<13>;
107 def AddrModeT2_pc : AddrMode<14>;
108 def AddrModeT2_i8s4 : AddrMode<15>;
109 def AddrMode_i12 : AddrMode<16>;
111 // Load / store index mode.
112 class IndexMode<bits<2> val> {
115 def IndexModeNone : IndexMode<0>;
116 def IndexModePre : IndexMode<1>;
117 def IndexModePost : IndexMode<2>;
118 def IndexModeUpd : IndexMode<3>;
120 // Instruction execution domain.
121 class Domain<bits<3> val> {
124 def GenericDomain : Domain<0>;
125 def VFPDomain : Domain<1>; // Instructions in VFP domain only
126 def NeonDomain : Domain<2>; // Instructions in Neon domain only
127 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
128 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
130 //===----------------------------------------------------------------------===//
131 // ARM special operands.
134 // ARM imod and iflag operands, used only by the CPS instruction.
135 def imod_op : Operand<i32> {
136 let PrintMethod = "printCPSIMod";
139 def ProcIFlagsOperand : AsmOperandClass {
140 let Name = "ProcIFlags";
141 let ParserMethod = "parseProcIFlagsOperand";
143 def iflags_op : Operand<i32> {
144 let PrintMethod = "printCPSIFlag";
145 let ParserMatchClass = ProcIFlagsOperand;
148 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
149 // register whose default is 0 (no register).
150 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
151 def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
152 (ops (i32 14), (i32 zero_reg))> {
153 let PrintMethod = "printPredicateOperand";
154 let ParserMatchClass = CondCodeOperand;
155 let DecoderMethod = "DecodePredicateOperand";
158 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
159 def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
160 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
161 let EncoderMethod = "getCCOutOpValue";
162 let PrintMethod = "printSBitModifierOperand";
163 let ParserMatchClass = CCOutOperand;
164 let DecoderMethod = "DecodeCCOutOperand";
167 // Same as cc_out except it defaults to setting CPSR.
168 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
169 let EncoderMethod = "getCCOutOpValue";
170 let PrintMethod = "printSBitModifierOperand";
171 let ParserMatchClass = CCOutOperand;
172 let DecoderMethod = "DecodeCCOutOperand";
175 // ARM special operands for disassembly only.
177 def SetEndAsmOperand : ImmAsmOperand {
178 let Name = "SetEndImm";
179 let ParserMethod = "parseSetEndImm";
181 def setend_op : Operand<i32> {
182 let PrintMethod = "printSetendOperand";
183 let ParserMatchClass = SetEndAsmOperand;
186 def MSRMaskOperand : AsmOperandClass {
187 let Name = "MSRMask";
188 let ParserMethod = "parseMSRMaskOperand";
190 def msr_mask : Operand<i32> {
191 let PrintMethod = "printMSRMaskOperand";
192 let DecoderMethod = "DecodeMSRMask";
193 let ParserMatchClass = MSRMaskOperand;
196 // Shift Right Immediate - A shift right immediate is encoded differently from
197 // other shift immediates. The imm6 field is encoded like so:
200 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
201 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
202 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
203 // 64 64 - <imm> is encoded in imm6<5:0>
204 def shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; }
205 def shr_imm8 : Operand<i32> {
206 let EncoderMethod = "getShiftRight8Imm";
207 let DecoderMethod = "DecodeShiftRight8Imm";
208 let ParserMatchClass = shr_imm8_asm_operand;
210 def shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; }
211 def shr_imm16 : Operand<i32> {
212 let EncoderMethod = "getShiftRight16Imm";
213 let DecoderMethod = "DecodeShiftRight16Imm";
214 let ParserMatchClass = shr_imm16_asm_operand;
216 def shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; }
217 def shr_imm32 : Operand<i32> {
218 let EncoderMethod = "getShiftRight32Imm";
219 let DecoderMethod = "DecodeShiftRight32Imm";
220 let ParserMatchClass = shr_imm32_asm_operand;
222 def shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; }
223 def shr_imm64 : Operand<i32> {
224 let EncoderMethod = "getShiftRight64Imm";
225 let DecoderMethod = "DecodeShiftRight64Imm";
226 let ParserMatchClass = shr_imm64_asm_operand;
229 //===----------------------------------------------------------------------===//
230 // ARM Assembler alias templates.
232 class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1>
233 : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>;
234 class tInstAlias<string Asm, dag Result, bit Emit = 0b1>
235 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>;
236 class t2InstAlias<string Asm, dag Result, bit Emit = 0b1>
237 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>;
238 class VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1>
239 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>;
240 class VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1>
241 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>;
242 class NEONInstAlias<string Asm, dag Result, bit Emit = 0b1>
243 : InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>;
246 class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
248 class NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
251 //===----------------------------------------------------------------------===//
252 // ARM Instruction templates.
256 class InstTemplate<AddrMode am, int sz, IndexMode im,
257 Format f, Domain d, string cstr, InstrItinClass itin>
259 let Namespace = "ARM";
264 bits<2> IndexModeBits = IM.Value;
266 bits<6> Form = F.Value;
268 bit isUnaryDataProc = 0;
269 bit canXformTo16Bit = 0;
270 // The instruction is a 16-bit flag setting Thumb instruction. Used
271 // by the parser to determine whether to require the 'S' suffix on the
272 // mnemonic (when not in an IT block) or preclude it (when in an IT block).
273 bit thumbArithFlagSetting = 0;
275 // If this is a pseudo instruction, mark it isCodeGenOnly.
276 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
278 // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
279 let TSFlags{4-0} = AM.Value;
280 let TSFlags{6-5} = IndexModeBits;
281 let TSFlags{12-7} = Form;
282 let TSFlags{13} = isUnaryDataProc;
283 let TSFlags{14} = canXformTo16Bit;
284 let TSFlags{17-15} = D.Value;
285 let TSFlags{18} = thumbArithFlagSetting;
287 let Constraints = cstr;
288 let Itinerary = itin;
293 // Mask of bits that cause an encoding to be UNPREDICTABLE.
294 // If a bit is set, then if the corresponding bit in the
295 // target encoding differs from its value in the "Inst" field,
296 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
297 field bits<32> Unpredictable = 0;
298 // SoftFail is the generic name for this field, but we alias it so
299 // as to make it more obvious what it means in ARM-land.
300 field bits<32> SoftFail = Unpredictable;
303 class InstARM<AddrMode am, int sz, IndexMode im,
304 Format f, Domain d, string cstr, InstrItinClass itin>
305 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
306 let DecoderNamespace = "ARM";
309 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
310 // on by adding flavors to specific instructions.
311 class InstThumb<AddrMode am, int sz, IndexMode im,
312 Format f, Domain d, string cstr, InstrItinClass itin>
313 : InstTemplate<am, sz, im, f, d, cstr, itin> {
314 let DecoderNamespace = "Thumb";
317 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
318 // These are aliases that require C++ handling to convert to the target
319 // instruction, while InstAliases can be handled directly by tblgen.
320 class AsmPseudoInst<string asm, dag iops>
321 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
323 let OutOperandList = (outs);
324 let InOperandList = iops;
326 let isCodeGenOnly = 0; // So we get asm matcher for it.
331 class ARMAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
333 class tAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
335 class t2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
336 Requires<[IsThumb2]>;
337 class VFP2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
339 class NEONAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
342 // Pseudo instructions for the code generator.
343 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
344 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
345 GenericDomain, "", itin> {
346 let OutOperandList = oops;
347 let InOperandList = iops;
348 let Pattern = pattern;
349 let isCodeGenOnly = 1;
353 // PseudoInst that's ARM-mode only.
354 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
356 : PseudoInst<oops, iops, itin, pattern> {
358 list<Predicate> Predicates = [IsARM];
361 // PseudoInst that's Thumb-mode only.
362 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
364 : PseudoInst<oops, iops, itin, pattern> {
366 list<Predicate> Predicates = [IsThumb];
369 // PseudoInst that's Thumb2-mode only.
370 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
372 : PseudoInst<oops, iops, itin, pattern> {
374 list<Predicate> Predicates = [IsThumb2];
377 class ARMPseudoExpand<dag oops, dag iops, int sz,
378 InstrItinClass itin, list<dag> pattern,
380 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
381 PseudoInstExpansion<Result>;
383 class tPseudoExpand<dag oops, dag iops, int sz,
384 InstrItinClass itin, list<dag> pattern,
386 : tPseudoInst<oops, iops, sz, itin, pattern>,
387 PseudoInstExpansion<Result>;
389 class t2PseudoExpand<dag oops, dag iops, int sz,
390 InstrItinClass itin, list<dag> pattern,
392 : t2PseudoInst<oops, iops, sz, itin, pattern>,
393 PseudoInstExpansion<Result>;
395 // Almost all ARM instructions are predicable.
396 class I<dag oops, dag iops, AddrMode am, int sz,
397 IndexMode im, Format f, InstrItinClass itin,
398 string opc, string asm, string cstr,
400 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
403 let OutOperandList = oops;
404 let InOperandList = !con(iops, (ins pred:$p));
405 let AsmString = !strconcat(opc, "${p}", asm);
406 let Pattern = pattern;
407 list<Predicate> Predicates = [IsARM];
410 // A few are not predicable
411 class InoP<dag oops, dag iops, AddrMode am, int sz,
412 IndexMode im, Format f, InstrItinClass itin,
413 string opc, string asm, string cstr,
415 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
416 let OutOperandList = oops;
417 let InOperandList = iops;
418 let AsmString = !strconcat(opc, asm);
419 let Pattern = pattern;
420 let isPredicable = 0;
421 list<Predicate> Predicates = [IsARM];
424 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
425 // operand since by default it's a zero register. It will become an implicit def
426 // once it's "flipped".
427 class sI<dag oops, dag iops, AddrMode am, int sz,
428 IndexMode im, Format f, InstrItinClass itin,
429 string opc, string asm, string cstr,
431 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
432 bits<4> p; // Predicate operand
433 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
437 let OutOperandList = oops;
438 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
439 let AsmString = !strconcat(opc, "${s}${p}", asm);
440 let Pattern = pattern;
441 list<Predicate> Predicates = [IsARM];
445 class XI<dag oops, dag iops, AddrMode am, int sz,
446 IndexMode im, Format f, InstrItinClass itin,
447 string asm, string cstr, list<dag> pattern>
448 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
449 let OutOperandList = oops;
450 let InOperandList = iops;
452 let Pattern = pattern;
453 list<Predicate> Predicates = [IsARM];
456 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
457 string opc, string asm, list<dag> pattern>
458 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
459 opc, asm, "", pattern>;
460 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
461 string opc, string asm, list<dag> pattern>
462 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
463 opc, asm, "", pattern>;
464 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
465 string asm, list<dag> pattern>
466 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
468 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
469 string opc, string asm, list<dag> pattern>
470 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
471 opc, asm, "", pattern>;
473 // Ctrl flow instructions
474 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
475 string opc, string asm, list<dag> pattern>
476 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
477 opc, asm, "", pattern> {
478 let Inst{27-24} = opcod;
480 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
481 string asm, list<dag> pattern>
482 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
484 let Inst{27-24} = opcod;
487 // BR_JT instructions
488 class JTI<dag oops, dag iops, InstrItinClass itin,
489 string asm, list<dag> pattern>
490 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
493 // Atomic load/store instructions
494 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
495 string opc, string asm, list<dag> pattern>
496 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
497 opc, asm, "", pattern> {
500 let Inst{27-23} = 0b00011;
501 let Inst{22-21} = opcod;
503 let Inst{19-16} = addr;
504 let Inst{15-12} = Rt;
505 let Inst{11-0} = 0b111110011111;
507 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
508 string opc, string asm, list<dag> pattern>
509 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
510 opc, asm, "", pattern> {
514 let Inst{27-23} = 0b00011;
515 let Inst{22-21} = opcod;
517 let Inst{19-16} = addr;
518 let Inst{15-12} = Rd;
519 let Inst{11-4} = 0b11111001;
522 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
523 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
527 let Inst{27-23} = 0b00010;
529 let Inst{21-20} = 0b00;
530 let Inst{19-16} = addr;
531 let Inst{15-12} = Rt;
532 let Inst{11-4} = 0b00001001;
535 let Unpredictable{11-8} = 0b1111;
536 let DecoderMethod = "DecodeSwap";
539 // addrmode1 instructions
540 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
541 string opc, string asm, list<dag> pattern>
542 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
543 opc, asm, "", pattern> {
544 let Inst{24-21} = opcod;
545 let Inst{27-26} = 0b00;
547 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
548 string opc, string asm, list<dag> pattern>
549 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
550 opc, asm, "", pattern> {
551 let Inst{24-21} = opcod;
552 let Inst{27-26} = 0b00;
554 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
555 string asm, list<dag> pattern>
556 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
558 let Inst{24-21} = opcod;
559 let Inst{27-26} = 0b00;
564 // LDR/LDRB/STR/STRB/...
565 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
566 Format f, InstrItinClass itin, string opc, string asm,
568 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
570 let Inst{27-25} = op;
571 let Inst{24} = 1; // 24 == P
573 let Inst{22} = isByte;
574 let Inst{21} = 0; // 21 == W
577 // Indexed load/stores
578 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
579 IndexMode im, Format f, InstrItinClass itin, string opc,
580 string asm, string cstr, list<dag> pattern>
581 : I<oops, iops, AddrMode2, 4, im, f, itin,
582 opc, asm, cstr, pattern> {
584 let Inst{27-26} = 0b01;
585 let Inst{24} = isPre; // P bit
586 let Inst{22} = isByte; // B bit
587 let Inst{21} = isPre; // W bit
588 let Inst{20} = isLd; // L bit
589 let Inst{15-12} = Rt;
591 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
592 IndexMode im, Format f, InstrItinClass itin, string opc,
593 string asm, string cstr, list<dag> pattern>
594 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
596 // AM2 store w/ two operands: (GPR, am2offset)
602 let Inst{23} = offset{12};
603 let Inst{19-16} = Rn;
604 let Inst{11-5} = offset{11-5};
606 let Inst{3-0} = offset{3-0};
609 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
610 IndexMode im, Format f, InstrItinClass itin, string opc,
611 string asm, string cstr, list<dag> pattern>
612 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
614 // AM2 store w/ two operands: (GPR, am2offset)
620 let Inst{23} = offset{12};
621 let Inst{19-16} = Rn;
622 let Inst{11-0} = offset{11-0};
626 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
627 // but for now use this class for STRT and STRBT.
628 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
629 IndexMode im, Format f, InstrItinClass itin, string opc,
630 string asm, string cstr, list<dag> pattern>
631 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
633 // AM2 store w/ two operands: (GPR, am2offset)
635 // {13} 1 == Rm, 0 == imm12
639 let Inst{25} = addr{13};
640 let Inst{23} = addr{12};
641 let Inst{19-16} = addr{17-14};
642 let Inst{11-0} = addr{11-0};
645 // addrmode3 instructions
646 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
647 InstrItinClass itin, string opc, string asm, list<dag> pattern>
648 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
649 opc, asm, "", pattern> {
652 let Inst{27-25} = 0b000;
653 let Inst{24} = 1; // P bit
654 let Inst{23} = addr{8}; // U bit
655 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
656 let Inst{21} = 0; // W bit
657 let Inst{20} = op20; // L bit
658 let Inst{19-16} = addr{12-9}; // Rn
659 let Inst{15-12} = Rt; // Rt
660 let Inst{11-8} = addr{7-4}; // imm7_4/zero
662 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
664 let DecoderMethod = "DecodeAddrMode3Instruction";
667 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
668 IndexMode im, Format f, InstrItinClass itin, string opc,
669 string asm, string cstr, list<dag> pattern>
670 : I<oops, iops, AddrMode3, 4, im, f, itin,
671 opc, asm, cstr, pattern> {
673 let Inst{27-25} = 0b000;
674 let Inst{24} = isPre; // P bit
675 let Inst{21} = isPre; // W bit
676 let Inst{20} = op20; // L bit
677 let Inst{15-12} = Rt; // Rt
681 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
682 // but for now use this class for LDRSBT, LDRHT, LDSHT.
683 class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
684 IndexMode im, Format f, InstrItinClass itin, string opc,
685 string asm, string cstr, list<dag> pattern>
686 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> {
687 // {13} 1 == imm8, 0 == Rm
694 let Inst{27-25} = 0b000;
695 let Inst{24} = 0; // P bit
697 let Inst{20} = isLoad; // L bit
698 let Inst{19-16} = addr; // Rn
699 let Inst{15-12} = Rt; // Rt
704 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
705 string opc, string asm, list<dag> pattern>
706 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
707 opc, asm, "", pattern> {
710 let Inst{27-25} = 0b000;
711 let Inst{24} = 1; // P bit
712 let Inst{23} = addr{8}; // U bit
713 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
714 let Inst{21} = 0; // W bit
715 let Inst{20} = 0; // L bit
716 let Inst{19-16} = addr{12-9}; // Rn
717 let Inst{15-12} = Rt; // Rt
718 let Inst{11-8} = addr{7-4}; // imm7_4/zero
720 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
721 let DecoderMethod = "DecodeAddrMode3Instruction";
724 // addrmode4 instructions
725 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
726 string asm, string cstr, list<dag> pattern>
727 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
732 let Inst{27-25} = 0b100;
733 let Inst{22} = 0; // S bit
734 let Inst{19-16} = Rn;
735 let Inst{15-0} = regs;
738 // Unsigned multiply, multiply-accumulate instructions.
739 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
740 string opc, string asm, list<dag> pattern>
741 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
742 opc, asm, "", pattern> {
743 let Inst{7-4} = 0b1001;
744 let Inst{20} = 0; // S bit
745 let Inst{27-21} = opcod;
747 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
748 string opc, string asm, list<dag> pattern>
749 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
750 opc, asm, "", pattern> {
751 let Inst{7-4} = 0b1001;
752 let Inst{27-21} = opcod;
755 // Most significant word multiply
756 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
757 InstrItinClass itin, string opc, string asm, list<dag> pattern>
758 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
759 opc, asm, "", pattern> {
763 let Inst{7-4} = opc7_4;
765 let Inst{27-21} = opcod;
766 let Inst{19-16} = Rd;
770 // MSW multiple w/ Ra operand
771 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
772 InstrItinClass itin, string opc, string asm, list<dag> pattern>
773 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
775 let Inst{15-12} = Ra;
778 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
779 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
780 InstrItinClass itin, string opc, string asm, list<dag> pattern>
781 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
782 opc, asm, "", pattern> {
788 let Inst{27-21} = opcod;
789 let Inst{6-5} = bit6_5;
793 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
794 InstrItinClass itin, string opc, string asm, list<dag> pattern>
795 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
797 let Inst{19-16} = Rd;
800 // AMulxyI with Ra operand
801 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
802 InstrItinClass itin, string opc, string asm, list<dag> pattern>
803 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
805 let Inst{15-12} = Ra;
808 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
809 InstrItinClass itin, string opc, string asm, list<dag> pattern>
810 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
813 let Inst{19-16} = RdHi;
814 let Inst{15-12} = RdLo;
817 // Extend instructions.
818 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
819 string opc, string asm, list<dag> pattern>
820 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
821 opc, asm, "", pattern> {
822 // All AExtI instructions have Rd and Rm register operands.
825 let Inst{15-12} = Rd;
827 let Inst{7-4} = 0b0111;
828 let Inst{9-8} = 0b00;
829 let Inst{27-20} = opcod;
831 let Unpredictable{9-8} = 0b11;
834 // Misc Arithmetic instructions.
835 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
836 InstrItinClass itin, string opc, string asm, list<dag> pattern>
837 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
838 opc, asm, "", pattern> {
841 let Inst{27-20} = opcod;
842 let Inst{19-16} = 0b1111;
843 let Inst{15-12} = Rd;
844 let Inst{11-8} = 0b1111;
845 let Inst{7-4} = opc7_4;
850 def PKHLSLAsmOperand : ImmAsmOperand {
851 let Name = "PKHLSLImm";
852 let ParserMethod = "parsePKHLSLImm";
854 def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
855 let PrintMethod = "printPKHLSLShiftImm";
856 let ParserMatchClass = PKHLSLAsmOperand;
858 def PKHASRAsmOperand : AsmOperandClass {
859 let Name = "PKHASRImm";
860 let ParserMethod = "parsePKHASRImm";
862 def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
863 let PrintMethod = "printPKHASRShiftImm";
864 let ParserMatchClass = PKHASRAsmOperand;
867 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
868 string opc, string asm, list<dag> pattern>
869 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
870 opc, asm, "", pattern> {
875 let Inst{27-20} = opcod;
876 let Inst{19-16} = Rn;
877 let Inst{15-12} = Rd;
880 let Inst{5-4} = 0b01;
884 //===----------------------------------------------------------------------===//
886 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
887 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
888 list<Predicate> Predicates = [IsARM];
890 class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
891 list<Predicate> Predicates = [IsARM, HasV5T];
893 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
894 list<Predicate> Predicates = [IsARM, HasV5TE];
896 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
897 list<Predicate> Predicates = [IsARM, HasV6];
900 //===----------------------------------------------------------------------===//
901 // Thumb Instruction Format Definitions.
904 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
905 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
906 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
907 let OutOperandList = oops;
908 let InOperandList = iops;
910 let Pattern = pattern;
911 list<Predicate> Predicates = [IsThumb];
914 // TI - Thumb instruction.
915 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
916 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
918 // Two-address instructions
919 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
921 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
924 // tBL, tBX 32-bit instructions
925 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
926 dag oops, dag iops, InstrItinClass itin, string asm,
928 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
930 let Inst{31-27} = opcod1;
931 let Inst{15-14} = opcod2;
932 let Inst{12} = opcod3;
935 // BR_JT instructions
936 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
938 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
941 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
942 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
943 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
944 let OutOperandList = oops;
945 let InOperandList = iops;
947 let Pattern = pattern;
948 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
951 class T1I<dag oops, dag iops, InstrItinClass itin,
952 string asm, list<dag> pattern>
953 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
954 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
955 string asm, list<dag> pattern>
956 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
958 // Two-address instructions
959 class T1It<dag oops, dag iops, InstrItinClass itin,
960 string asm, string cstr, list<dag> pattern>
961 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
964 // Thumb1 instruction that can either be predicated or set CPSR.
965 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
967 string opc, string asm, string cstr, list<dag> pattern>
968 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
969 let OutOperandList = !con(oops, (outs s_cc_out:$s));
970 let InOperandList = !con(iops, (ins pred:$p));
971 let AsmString = !strconcat(opc, "${s}${p}", asm);
972 let Pattern = pattern;
973 let thumbArithFlagSetting = 1;
974 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
975 let DecoderNamespace = "ThumbSBit";
978 class T1sI<dag oops, dag iops, InstrItinClass itin,
979 string opc, string asm, list<dag> pattern>
980 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
982 // Two-address instructions
983 class T1sIt<dag oops, dag iops, InstrItinClass itin,
984 string opc, string asm, list<dag> pattern>
985 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
986 "$Rn = $Rdn", pattern>;
988 // Thumb1 instruction that can be predicated.
989 class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
991 string opc, string asm, string cstr, list<dag> pattern>
992 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
993 let OutOperandList = oops;
994 let InOperandList = !con(iops, (ins pred:$p));
995 let AsmString = !strconcat(opc, "${p}", asm);
996 let Pattern = pattern;
997 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1000 class T1pI<dag oops, dag iops, InstrItinClass itin,
1001 string opc, string asm, list<dag> pattern>
1002 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
1004 // Two-address instructions
1005 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1006 string opc, string asm, list<dag> pattern>
1007 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
1008 "$Rn = $Rdn", pattern>;
1010 class T1pIs<dag oops, dag iops,
1011 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1012 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
1014 class Encoding16 : Encoding {
1015 let Inst{31-16} = 0x0000;
1018 // A6.2 16-bit Thumb instruction encoding
1019 class T1Encoding<bits<6> opcode> : Encoding16 {
1020 let Inst{15-10} = opcode;
1023 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1024 class T1General<bits<5> opcode> : Encoding16 {
1025 let Inst{15-14} = 0b00;
1026 let Inst{13-9} = opcode;
1029 // A6.2.2 Data-processing encoding.
1030 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1031 let Inst{15-10} = 0b010000;
1032 let Inst{9-6} = opcode;
1035 // A6.2.3 Special data instructions and branch and exchange encoding.
1036 class T1Special<bits<4> opcode> : Encoding16 {
1037 let Inst{15-10} = 0b010001;
1038 let Inst{9-6} = opcode;
1041 // A6.2.4 Load/store single data item encoding.
1042 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1043 let Inst{15-12} = opA;
1044 let Inst{11-9} = opB;
1046 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1048 class T1BranchCond<bits<4> opcode> : Encoding16 {
1049 let Inst{15-12} = opcode;
1052 // Helper classes to encode Thumb1 loads and stores. For immediates, the
1053 // following bits are used for "opA" (see A6.2.4):
1055 // 0b0110 => Immediate, 4 bytes
1056 // 0b1000 => Immediate, 2 bytes
1057 // 0b0111 => Immediate, 1 byte
1058 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1059 InstrItinClass itin, string opc, string asm,
1061 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1062 T1LoadStore<0b0101, opcode> {
1065 let Inst{8-6} = addr{5-3}; // Rm
1066 let Inst{5-3} = addr{2-0}; // Rn
1069 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1070 InstrItinClass itin, string opc, string asm,
1072 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1073 T1LoadStore<opA, {opB,?,?}> {
1076 let Inst{10-6} = addr{7-3}; // imm5
1077 let Inst{5-3} = addr{2-0}; // Rn
1081 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1082 class T1Misc<bits<7> opcode> : Encoding16 {
1083 let Inst{15-12} = 0b1011;
1084 let Inst{11-5} = opcode;
1087 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1088 class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
1089 InstrItinClass itin,
1090 string opc, string asm, string cstr, list<dag> pattern>
1091 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1092 let OutOperandList = oops;
1093 let InOperandList = !con(iops, (ins pred:$p));
1094 let AsmString = !strconcat(opc, "${p}", asm);
1095 let Pattern = pattern;
1096 list<Predicate> Predicates = [IsThumb2];
1097 let DecoderNamespace = "Thumb2";
1100 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1101 // input operand since by default it's a zero register. It will become an
1102 // implicit def once it's "flipped".
1104 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1106 class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
1107 InstrItinClass itin,
1108 string opc, string asm, string cstr, list<dag> pattern>
1109 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1110 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1113 let OutOperandList = oops;
1114 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1115 let AsmString = !strconcat(opc, "${s}${p}", asm);
1116 let Pattern = pattern;
1117 list<Predicate> Predicates = [IsThumb2];
1118 let DecoderNamespace = "Thumb2";
1122 class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
1123 InstrItinClass itin,
1124 string asm, string cstr, list<dag> pattern>
1125 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1126 let OutOperandList = oops;
1127 let InOperandList = iops;
1128 let AsmString = asm;
1129 let Pattern = pattern;
1130 list<Predicate> Predicates = [IsThumb2];
1131 let DecoderNamespace = "Thumb2";
1134 class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
1135 InstrItinClass itin,
1136 string asm, string cstr, list<dag> pattern>
1137 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1138 let OutOperandList = oops;
1139 let InOperandList = iops;
1140 let AsmString = asm;
1141 let Pattern = pattern;
1142 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1143 let DecoderNamespace = "Thumb";
1146 class T2I<dag oops, dag iops, InstrItinClass itin,
1147 string opc, string asm, list<dag> pattern>
1148 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1149 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1150 string opc, string asm, list<dag> pattern>
1151 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
1152 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1153 string opc, string asm, list<dag> pattern>
1154 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
1155 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1156 string opc, string asm, list<dag> pattern>
1157 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
1158 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1159 string opc, string asm, list<dag> pattern>
1160 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
1161 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1162 string opc, string asm, string cstr, list<dag> pattern>
1163 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1168 let Inst{31-25} = 0b1110100;
1170 let Inst{23} = addr{8};
1173 let Inst{20} = isLoad;
1174 let Inst{19-16} = addr{12-9};
1175 let Inst{15-12} = Rt{3-0};
1176 let Inst{11-8} = Rt2{3-0};
1177 let Inst{7-0} = addr{7-0};
1179 class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops,
1180 InstrItinClass itin, string opc, string asm, string cstr,
1182 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1188 let Inst{31-25} = 0b1110100;
1190 let Inst{23} = imm{8};
1193 let Inst{20} = isLoad;
1194 let Inst{19-16} = addr;
1195 let Inst{15-12} = Rt{3-0};
1196 let Inst{11-8} = Rt2{3-0};
1197 let Inst{7-0} = imm{7-0};
1200 class T2sI<dag oops, dag iops, InstrItinClass itin,
1201 string opc, string asm, list<dag> pattern>
1202 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1204 class T2XI<dag oops, dag iops, InstrItinClass itin,
1205 string asm, list<dag> pattern>
1206 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1207 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1208 string asm, list<dag> pattern>
1209 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1211 // Move to/from coprocessor instructions
1212 class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern>
1213 : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> {
1214 let Inst{31-28} = opc;
1217 // Two-address instructions
1218 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1219 string asm, string cstr, list<dag> pattern>
1220 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
1222 // T2Ipreldst - Thumb2 pre-indexed load / store instructions.
1223 class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre,
1225 AddrMode am, IndexMode im, InstrItinClass itin,
1226 string opc, string asm, string cstr, list<dag> pattern>
1227 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1228 let OutOperandList = oops;
1229 let InOperandList = !con(iops, (ins pred:$p));
1230 let AsmString = !strconcat(opc, "${p}", asm);
1231 let Pattern = pattern;
1232 list<Predicate> Predicates = [IsThumb2];
1233 let DecoderNamespace = "Thumb2";
1237 let Inst{31-27} = 0b11111;
1238 let Inst{26-25} = 0b00;
1239 let Inst{24} = signed;
1241 let Inst{22-21} = opcod;
1242 let Inst{20} = load;
1243 let Inst{19-16} = addr{12-9};
1244 let Inst{15-12} = Rt{3-0};
1246 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1247 let Inst{10} = pre; // The P bit.
1248 let Inst{9} = addr{8}; // Sign bit
1249 let Inst{8} = 1; // The W bit.
1250 let Inst{7-0} = addr{7-0};
1252 let DecoderMethod = "DecodeT2LdStPre";
1255 // T2Ipostldst - Thumb2 post-indexed load / store instructions.
1256 class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre,
1258 AddrMode am, IndexMode im, InstrItinClass itin,
1259 string opc, string asm, string cstr, list<dag> pattern>
1260 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1261 let OutOperandList = oops;
1262 let InOperandList = !con(iops, (ins pred:$p));
1263 let AsmString = !strconcat(opc, "${p}", asm);
1264 let Pattern = pattern;
1265 list<Predicate> Predicates = [IsThumb2];
1266 let DecoderNamespace = "Thumb2";
1271 let Inst{31-27} = 0b11111;
1272 let Inst{26-25} = 0b00;
1273 let Inst{24} = signed;
1275 let Inst{22-21} = opcod;
1276 let Inst{20} = load;
1277 let Inst{19-16} = Rn;
1278 let Inst{15-12} = Rt{3-0};
1280 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1281 let Inst{10} = pre; // The P bit.
1282 let Inst{9} = offset{8}; // Sign bit
1283 let Inst{8} = 1; // The W bit.
1284 let Inst{7-0} = offset{7-0};
1286 let DecoderMethod = "DecodeT2LdStPre";
1289 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1290 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1291 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1294 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1295 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1296 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1299 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1300 class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1301 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1304 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1305 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1306 list<Predicate> Predicates = [IsThumb2];
1309 //===----------------------------------------------------------------------===//
1311 //===----------------------------------------------------------------------===//
1312 // ARM VFP Instruction templates.
1315 // Almost all VFP instructions are predicable.
1316 class VFPI<dag oops, dag iops, AddrMode am, int sz,
1317 IndexMode im, Format f, InstrItinClass itin,
1318 string opc, string asm, string cstr, list<dag> pattern>
1319 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1321 let Inst{31-28} = p;
1322 let OutOperandList = oops;
1323 let InOperandList = !con(iops, (ins pred:$p));
1324 let AsmString = !strconcat(opc, "${p}", asm);
1325 let Pattern = pattern;
1326 let PostEncoderMethod = "VFPThumb2PostEncoder";
1327 let DecoderNamespace = "VFP";
1328 list<Predicate> Predicates = [HasVFP2];
1332 class VFPXI<dag oops, dag iops, AddrMode am, int sz,
1333 IndexMode im, Format f, InstrItinClass itin,
1334 string asm, string cstr, list<dag> pattern>
1335 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1337 let Inst{31-28} = p;
1338 let OutOperandList = oops;
1339 let InOperandList = iops;
1340 let AsmString = asm;
1341 let Pattern = pattern;
1342 let PostEncoderMethod = "VFPThumb2PostEncoder";
1343 let DecoderNamespace = "VFP";
1344 list<Predicate> Predicates = [HasVFP2];
1347 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1348 string opc, string asm, list<dag> pattern>
1349 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
1350 opc, asm, "", pattern> {
1351 let PostEncoderMethod = "VFPThumb2PostEncoder";
1354 // ARM VFP addrmode5 loads and stores
1355 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1356 InstrItinClass itin,
1357 string opc, string asm, list<dag> pattern>
1358 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1359 VFPLdStFrm, itin, opc, asm, "", pattern> {
1360 // Instruction operands.
1364 // Encode instruction operands.
1365 let Inst{23} = addr{8}; // U (add = (U == '1'))
1366 let Inst{22} = Dd{4};
1367 let Inst{19-16} = addr{12-9}; // Rn
1368 let Inst{15-12} = Dd{3-0};
1369 let Inst{7-0} = addr{7-0}; // imm8
1371 // TODO: Mark the instructions with the appropriate subtarget info.
1372 let Inst{27-24} = opcod1;
1373 let Inst{21-20} = opcod2;
1374 let Inst{11-9} = 0b101;
1375 let Inst{8} = 1; // Double precision
1377 // Loads & stores operate on both NEON and VFP pipelines.
1378 let D = VFPNeonDomain;
1381 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1382 InstrItinClass itin,
1383 string opc, string asm, list<dag> pattern>
1384 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1385 VFPLdStFrm, itin, opc, asm, "", pattern> {
1386 // Instruction operands.
1390 // Encode instruction operands.
1391 let Inst{23} = addr{8}; // U (add = (U == '1'))
1392 let Inst{22} = Sd{0};
1393 let Inst{19-16} = addr{12-9}; // Rn
1394 let Inst{15-12} = Sd{4-1};
1395 let Inst{7-0} = addr{7-0}; // imm8
1397 // TODO: Mark the instructions with the appropriate subtarget info.
1398 let Inst{27-24} = opcod1;
1399 let Inst{21-20} = opcod2;
1400 let Inst{11-9} = 0b101;
1401 let Inst{8} = 0; // Single precision
1403 // Loads & stores operate on both NEON and VFP pipelines.
1404 let D = VFPNeonDomain;
1407 // VFP Load / store multiple pseudo instructions.
1408 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1410 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1412 let OutOperandList = oops;
1413 let InOperandList = !con(iops, (ins pred:$p));
1414 let Pattern = pattern;
1415 list<Predicate> Predicates = [HasVFP2];
1418 // Load / store multiple
1419 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1420 string asm, string cstr, list<dag> pattern>
1421 : VFPXI<oops, iops, AddrMode4, 4, im,
1422 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1423 // Instruction operands.
1427 // Encode instruction operands.
1428 let Inst{19-16} = Rn;
1429 let Inst{22} = regs{12};
1430 let Inst{15-12} = regs{11-8};
1431 let Inst{7-0} = regs{7-0};
1433 // TODO: Mark the instructions with the appropriate subtarget info.
1434 let Inst{27-25} = 0b110;
1435 let Inst{11-9} = 0b101;
1436 let Inst{8} = 1; // Double precision
1439 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1440 string asm, string cstr, list<dag> pattern>
1441 : VFPXI<oops, iops, AddrMode4, 4, im,
1442 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1443 // Instruction operands.
1447 // Encode instruction operands.
1448 let Inst{19-16} = Rn;
1449 let Inst{22} = regs{8};
1450 let Inst{15-12} = regs{12-9};
1451 let Inst{7-0} = regs{7-0};
1453 // TODO: Mark the instructions with the appropriate subtarget info.
1454 let Inst{27-25} = 0b110;
1455 let Inst{11-9} = 0b101;
1456 let Inst{8} = 0; // Single precision
1459 // Double precision, unary
1460 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1461 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1462 string asm, list<dag> pattern>
1463 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1464 // Instruction operands.
1468 // Encode instruction operands.
1469 let Inst{3-0} = Dm{3-0};
1470 let Inst{5} = Dm{4};
1471 let Inst{15-12} = Dd{3-0};
1472 let Inst{22} = Dd{4};
1474 let Inst{27-23} = opcod1;
1475 let Inst{21-20} = opcod2;
1476 let Inst{19-16} = opcod3;
1477 let Inst{11-9} = 0b101;
1478 let Inst{8} = 1; // Double precision
1479 let Inst{7-6} = opcod4;
1480 let Inst{4} = opcod5;
1483 // Double precision, binary
1484 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1485 dag iops, InstrItinClass itin, string opc, string asm,
1487 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1488 // Instruction operands.
1493 // Encode instruction operands.
1494 let Inst{3-0} = Dm{3-0};
1495 let Inst{5} = Dm{4};
1496 let Inst{19-16} = Dn{3-0};
1497 let Inst{7} = Dn{4};
1498 let Inst{15-12} = Dd{3-0};
1499 let Inst{22} = Dd{4};
1501 let Inst{27-23} = opcod1;
1502 let Inst{21-20} = opcod2;
1503 let Inst{11-9} = 0b101;
1504 let Inst{8} = 1; // Double precision
1509 // Single precision, unary
1510 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1511 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1512 string asm, list<dag> pattern>
1513 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1514 // Instruction operands.
1518 // Encode instruction operands.
1519 let Inst{3-0} = Sm{4-1};
1520 let Inst{5} = Sm{0};
1521 let Inst{15-12} = Sd{4-1};
1522 let Inst{22} = Sd{0};
1524 let Inst{27-23} = opcod1;
1525 let Inst{21-20} = opcod2;
1526 let Inst{19-16} = opcod3;
1527 let Inst{11-9} = 0b101;
1528 let Inst{8} = 0; // Single precision
1529 let Inst{7-6} = opcod4;
1530 let Inst{4} = opcod5;
1533 // Single precision unary, if no NEON. Same as ASuI except not available if
1535 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1536 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1537 string asm, list<dag> pattern>
1538 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1540 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1543 // Single precision, binary
1544 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1545 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1546 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1547 // Instruction operands.
1552 // Encode instruction operands.
1553 let Inst{3-0} = Sm{4-1};
1554 let Inst{5} = Sm{0};
1555 let Inst{19-16} = Sn{4-1};
1556 let Inst{7} = Sn{0};
1557 let Inst{15-12} = Sd{4-1};
1558 let Inst{22} = Sd{0};
1560 let Inst{27-23} = opcod1;
1561 let Inst{21-20} = opcod2;
1562 let Inst{11-9} = 0b101;
1563 let Inst{8} = 0; // Single precision
1568 // Single precision binary, if no NEON. Same as ASbI except not available if
1570 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1571 dag iops, InstrItinClass itin, string opc, string asm,
1573 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1574 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1576 // Instruction operands.
1581 // Encode instruction operands.
1582 let Inst{3-0} = Sm{4-1};
1583 let Inst{5} = Sm{0};
1584 let Inst{19-16} = Sn{4-1};
1585 let Inst{7} = Sn{0};
1586 let Inst{15-12} = Sd{4-1};
1587 let Inst{22} = Sd{0};
1590 // VFP conversion instructions
1591 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1592 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1594 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1595 let Inst{27-23} = opcod1;
1596 let Inst{21-20} = opcod2;
1597 let Inst{19-16} = opcod3;
1598 let Inst{11-8} = opcod4;
1603 // VFP conversion between floating-point and fixed-point
1604 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1605 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1607 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1609 // size (fixed-point number): sx == 0 ? 16 : 32
1610 let Inst{7} = op5; // sx
1611 let Inst{5} = fbits{0};
1612 let Inst{3-0} = fbits{4-1};
1615 // VFP conversion instructions, if no NEON
1616 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1617 dag oops, dag iops, InstrItinClass itin,
1618 string opc, string asm, list<dag> pattern>
1619 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1621 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1624 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1625 InstrItinClass itin,
1626 string opc, string asm, list<dag> pattern>
1627 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1628 let Inst{27-20} = opcod1;
1629 let Inst{11-8} = opcod2;
1633 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1634 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1635 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1637 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1638 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1639 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1641 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1642 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1643 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1645 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1646 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1647 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1649 //===----------------------------------------------------------------------===//
1651 //===----------------------------------------------------------------------===//
1652 // ARM NEON Instruction templates.
1655 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1656 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1658 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1659 let OutOperandList = oops;
1660 let InOperandList = !con(iops, (ins pred:$p));
1661 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1662 let Pattern = pattern;
1663 list<Predicate> Predicates = [HasNEON];
1664 let DecoderNamespace = "NEON";
1667 // Same as NeonI except it does not have a "data type" specifier.
1668 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1669 InstrItinClass itin, string opc, string asm, string cstr,
1671 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1672 let OutOperandList = oops;
1673 let InOperandList = !con(iops, (ins pred:$p));
1674 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1675 let Pattern = pattern;
1676 list<Predicate> Predicates = [HasNEON];
1677 let DecoderNamespace = "NEON";
1680 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1681 dag oops, dag iops, InstrItinClass itin,
1682 string opc, string dt, string asm, string cstr, list<dag> pattern>
1683 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1685 let Inst{31-24} = 0b11110100;
1686 let Inst{23} = op23;
1687 let Inst{21-20} = op21_20;
1688 let Inst{11-8} = op11_8;
1689 let Inst{7-4} = op7_4;
1691 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1692 let DecoderNamespace = "NEONLoadStore";
1698 let Inst{22} = Vd{4};
1699 let Inst{15-12} = Vd{3-0};
1700 let Inst{19-16} = Rn{3-0};
1701 let Inst{3-0} = Rm{3-0};
1704 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1705 dag oops, dag iops, InstrItinClass itin,
1706 string opc, string dt, string asm, string cstr, list<dag> pattern>
1707 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1708 dt, asm, cstr, pattern> {
1712 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1713 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1715 let OutOperandList = oops;
1716 let InOperandList = !con(iops, (ins pred:$p));
1717 list<Predicate> Predicates = [HasNEON];
1720 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1722 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1724 let OutOperandList = oops;
1725 let InOperandList = !con(iops, (ins pred:$p));
1726 let Pattern = pattern;
1727 list<Predicate> Predicates = [HasNEON];
1730 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1731 string opc, string dt, string asm, string cstr, list<dag> pattern>
1732 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1734 let Inst{31-25} = 0b1111001;
1735 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1736 let DecoderNamespace = "NEONData";
1739 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1740 string opc, string asm, string cstr, list<dag> pattern>
1741 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1743 let Inst{31-25} = 0b1111001;
1744 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1745 let DecoderNamespace = "NEONData";
1748 // NEON "one register and a modified immediate" format.
1749 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1751 dag oops, dag iops, InstrItinClass itin,
1752 string opc, string dt, string asm, string cstr,
1754 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1755 let Inst{23} = op23;
1756 let Inst{21-19} = op21_19;
1757 let Inst{11-8} = op11_8;
1763 // Instruction operands.
1767 let Inst{15-12} = Vd{3-0};
1768 let Inst{22} = Vd{4};
1769 let Inst{24} = SIMM{7};
1770 let Inst{18-16} = SIMM{6-4};
1771 let Inst{3-0} = SIMM{3-0};
1772 let DecoderMethod = "DecodeNEONModImmInstruction";
1775 // NEON 2 vector register format.
1776 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1777 bits<5> op11_7, bit op6, bit op4,
1778 dag oops, dag iops, InstrItinClass itin,
1779 string opc, string dt, string asm, string cstr, list<dag> pattern>
1780 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1781 let Inst{24-23} = op24_23;
1782 let Inst{21-20} = op21_20;
1783 let Inst{19-18} = op19_18;
1784 let Inst{17-16} = op17_16;
1785 let Inst{11-7} = op11_7;
1789 // Instruction operands.
1793 let Inst{15-12} = Vd{3-0};
1794 let Inst{22} = Vd{4};
1795 let Inst{3-0} = Vm{3-0};
1796 let Inst{5} = Vm{4};
1799 // Same as N2V except it doesn't have a datatype suffix.
1800 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1801 bits<5> op11_7, bit op6, bit op4,
1802 dag oops, dag iops, InstrItinClass itin,
1803 string opc, string asm, string cstr, list<dag> pattern>
1804 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1805 let Inst{24-23} = op24_23;
1806 let Inst{21-20} = op21_20;
1807 let Inst{19-18} = op19_18;
1808 let Inst{17-16} = op17_16;
1809 let Inst{11-7} = op11_7;
1813 // Instruction operands.
1817 let Inst{15-12} = Vd{3-0};
1818 let Inst{22} = Vd{4};
1819 let Inst{3-0} = Vm{3-0};
1820 let Inst{5} = Vm{4};
1823 // NEON 2 vector register with immediate.
1824 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1825 dag oops, dag iops, Format f, InstrItinClass itin,
1826 string opc, string dt, string asm, string cstr, list<dag> pattern>
1827 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1828 let Inst{24} = op24;
1829 let Inst{23} = op23;
1830 let Inst{11-8} = op11_8;
1835 // Instruction operands.
1840 let Inst{15-12} = Vd{3-0};
1841 let Inst{22} = Vd{4};
1842 let Inst{3-0} = Vm{3-0};
1843 let Inst{5} = Vm{4};
1844 let Inst{21-16} = SIMM{5-0};
1847 // NEON 3 vector register format.
1849 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1850 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1851 string opc, string dt, string asm, string cstr,
1853 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1854 let Inst{24} = op24;
1855 let Inst{23} = op23;
1856 let Inst{21-20} = op21_20;
1857 let Inst{11-8} = op11_8;
1862 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1863 dag oops, dag iops, Format f, InstrItinClass itin,
1864 string opc, string dt, string asm, string cstr, list<dag> pattern>
1865 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1866 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1867 // Instruction operands.
1872 let Inst{15-12} = Vd{3-0};
1873 let Inst{22} = Vd{4};
1874 let Inst{19-16} = Vn{3-0};
1875 let Inst{7} = Vn{4};
1876 let Inst{3-0} = Vm{3-0};
1877 let Inst{5} = Vm{4};
1880 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1881 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1882 string opc, string dt, string asm, string cstr,
1884 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1885 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1887 // Instruction operands.
1893 let Inst{15-12} = Vd{3-0};
1894 let Inst{22} = Vd{4};
1895 let Inst{19-16} = Vn{3-0};
1896 let Inst{7} = Vn{4};
1897 let Inst{3-0} = Vm{3-0};
1901 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1902 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1903 string opc, string dt, string asm, string cstr,
1905 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1906 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1908 // Instruction operands.
1914 let Inst{15-12} = Vd{3-0};
1915 let Inst{22} = Vd{4};
1916 let Inst{19-16} = Vn{3-0};
1917 let Inst{7} = Vn{4};
1918 let Inst{2-0} = Vm{2-0};
1919 let Inst{5} = lane{1};
1920 let Inst{3} = lane{0};
1923 // Same as N3V except it doesn't have a data type suffix.
1924 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1926 dag oops, dag iops, Format f, InstrItinClass itin,
1927 string opc, string asm, string cstr, list<dag> pattern>
1928 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1929 let Inst{24} = op24;
1930 let Inst{23} = op23;
1931 let Inst{21-20} = op21_20;
1932 let Inst{11-8} = op11_8;
1936 // Instruction operands.
1941 let Inst{15-12} = Vd{3-0};
1942 let Inst{22} = Vd{4};
1943 let Inst{19-16} = Vn{3-0};
1944 let Inst{7} = Vn{4};
1945 let Inst{3-0} = Vm{3-0};
1946 let Inst{5} = Vm{4};
1949 // NEON VMOVs between scalar and core registers.
1950 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1951 dag oops, dag iops, Format f, InstrItinClass itin,
1952 string opc, string dt, string asm, list<dag> pattern>
1953 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
1955 let Inst{27-20} = opcod1;
1956 let Inst{11-8} = opcod2;
1957 let Inst{6-5} = opcod3;
1959 // A8.6.303, A8.6.328, A8.6.329
1960 let Inst{3-0} = 0b0000;
1962 let OutOperandList = oops;
1963 let InOperandList = !con(iops, (ins pred:$p));
1964 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1965 let Pattern = pattern;
1966 list<Predicate> Predicates = [HasNEON];
1968 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1969 let DecoderNamespace = "NEONDup";
1976 let Inst{31-28} = p{3-0};
1978 let Inst{19-16} = V{3-0};
1979 let Inst{15-12} = R{3-0};
1981 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1982 dag oops, dag iops, InstrItinClass itin,
1983 string opc, string dt, string asm, list<dag> pattern>
1984 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1985 opc, dt, asm, pattern>;
1986 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1987 dag oops, dag iops, InstrItinClass itin,
1988 string opc, string dt, string asm, list<dag> pattern>
1989 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1990 opc, dt, asm, pattern>;
1991 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1992 dag oops, dag iops, InstrItinClass itin,
1993 string opc, string dt, string asm, list<dag> pattern>
1994 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1995 opc, dt, asm, pattern>;
1997 // Vector Duplicate Lane (from scalar to all elements)
1998 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1999 InstrItinClass itin, string opc, string dt, string asm,
2001 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
2002 let Inst{24-23} = 0b11;
2003 let Inst{21-20} = 0b11;
2004 let Inst{19-16} = op19_16;
2005 let Inst{11-7} = 0b11000;
2012 let Inst{22} = Vd{4};
2013 let Inst{15-12} = Vd{3-0};
2014 let Inst{5} = Vm{4};
2015 let Inst{3-0} = Vm{3-0};
2018 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
2019 // for single-precision FP.
2020 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
2021 list<Predicate> Predicates = [HasNEON,UseNEONForFP];
2024 // VFP/NEON Instruction aliases for type suffices.
2025 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
2026 InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>;
2028 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
2029 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
2030 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
2031 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
2032 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
2035 multiclass NEONDTAnyInstAlias<string opc, string asm, dag Result> {
2036 let Predicates = [HasNEON] in {
2037 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
2038 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
2039 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
2040 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
2044 // The same alias classes using AsmPseudo instead, for the more complex
2045 // stuff in NEON that InstAlias can't quite handle.
2046 // Note that we can't use anonymous defm references here like we can
2047 // above, as we care about the ultimate instruction enum names generated, unlike
2048 // for instalias defs.
2049 class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
2050 AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>;
2052 // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.
2053 def : TokenAlias<".s8", ".i8">;
2054 def : TokenAlias<".u8", ".i8">;
2055 def : TokenAlias<".s16", ".i16">;
2056 def : TokenAlias<".u16", ".i16">;
2057 def : TokenAlias<".s32", ".i32">;
2058 def : TokenAlias<".u32", ".i32">;
2059 def : TokenAlias<".s64", ".i64">;
2060 def : TokenAlias<".u64", ".i64">;
2062 def : TokenAlias<".i8", ".8">;
2063 def : TokenAlias<".i16", ".16">;
2064 def : TokenAlias<".i32", ".32">;
2065 def : TokenAlias<".i64", ".64">;
2067 def : TokenAlias<".p8", ".8">;
2068 def : TokenAlias<".p16", ".16">;
2070 def : TokenAlias<".f32", ".32">;
2071 def : TokenAlias<".f64", ".64">;
2072 def : TokenAlias<".f", ".f32">;
2073 def : TokenAlias<".d", ".f64">;