1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm : Format<2>;
24 def MulSMLAW : Format<3>;
25 def MulSMULW : Format<4>;
26 def MulSMLA : Format<5>;
27 def MulSMUL : Format<6>;
28 def Branch : Format<7>;
29 def BranchMisc : Format<8>;
31 def DPRdIm : Format<9>;
32 def DPRdReg : Format<10>;
33 def DPRdSoReg : Format<11>;
34 def DPRdMisc : Format<12>;
35 def DPRnIm : Format<13>;
36 def DPRnReg : Format<14>;
37 def DPRnSoReg : Format<15>;
38 def DPRIm : Format<16>;
39 def DPRReg : Format<17>;
40 def DPRSoReg : Format<18>;
41 def DPRImS : Format<19>;
42 def DPRRegS : Format<20>;
43 def DPRSoRegS : Format<21>;
45 def LdFrm : Format<22>;
46 def StFrm : Format<23>;
48 def ArithMisc : Format<24>;
49 def ThumbFrm : Format<25>;
50 def VFPFrm : Format<26>;
53 //===----------------------------------------------------------------------===//
55 // ARM Instruction templates.
58 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
59 Format f, string cstr>
63 let Namespace = "ARM";
65 bits<4> Opcode = opcod;
67 bits<4> AddrModeBits = AM.Value;
70 bits<3> SizeFlag = SZ.Value;
73 bits<2> IndexModeBits = IM.Value;
76 bits<5> Form = F.Value;
78 let Constraints = cstr;
81 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
82 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
83 let OutOperandList = oops;
84 let InOperandList = iops;
86 let Pattern = pattern;
89 // Almost all ARM instructions are predicable.
90 class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
91 IndexMode im, Format f, string opc, string asm, string cstr,
93 : InstARM<opcod, am, sz, im, f, cstr> {
94 let OutOperandList = oops;
95 let InOperandList = !con(iops, (ops pred:$p));
96 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
97 let Pattern = pattern;
98 list<Predicate> Predicates = [IsARM];
101 // Same as I except it can optionally modify CPSR. Note it's modeled as
102 // an input operand since by default it's a zero register. It will
103 // become an implicit def once it's "flipped".
104 class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
105 IndexMode im, Format f, string opc, string asm, string cstr,
107 : InstARM<opcod, am, sz, im, f, cstr> {
108 let OutOperandList = oops;
109 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
110 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
111 let Pattern = pattern;
112 list<Predicate> Predicates = [IsARM];
116 class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
117 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
118 : InstARM<opcod, am, sz, im, f, cstr> {
119 let OutOperandList = oops;
120 let InOperandList = iops;
122 let Pattern = pattern;
123 list<Predicate> Predicates = [IsARM];
126 class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
127 string asm, list<dag> pattern>
128 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
130 class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
131 string asm, list<dag> pattern>
132 : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
134 class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
136 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
139 // Ctrl flow instructions
140 class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
141 string asm, list<dag> pattern>
142 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
144 let Inst{24} = 1; // L bit
147 class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
149 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
151 let Inst{24} = 1; // L bit
154 class ABLXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
156 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
159 let Inst{20-27} = 0x12;
162 class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
164 : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
166 class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
168 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
170 let Inst{24} = 0; // L bit
173 class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
174 string asm, list<dag> pattern>
175 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
177 let Inst{24} = 0; // L bit
181 // BR_JT instructions
183 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
184 : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
186 let Inst{20} = 0; // S Bit
187 let Inst{21-24} = 0xd;
191 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
192 : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
194 let Inst{20} = 1; // L bit
195 let Inst{21} = 0; // W bit
196 let Inst{22} = 0; // B bit
197 let Inst{24} = 1; // P bit
200 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
201 : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
203 let Inst{20} = 0; // S bit
209 // addrmode1 instructions
210 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
211 string asm, list<dag> pattern>
212 : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
214 let Inst{21-24} = opcod;
217 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
218 string asm, list<dag> pattern>
219 : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
222 let Inst{21-24} = opcod;
225 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
227 : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
230 let Inst{21-24} = opcod;
233 class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
234 string asm, list<dag> pattern>
235 : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
239 // addrmode2 loads and stores
240 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
241 string asm, list<dag> pattern>
242 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
246 class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
248 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
252 class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
253 string asm, list<dag> pattern>
254 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
255 let Inst{20} = 1; // L bit
256 let Inst{21} = 0; // W bit
257 let Inst{22} = 0; // B bit
258 let Inst{24} = 1; // P bit
260 class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
262 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
264 let Inst{20} = 1; // L bit
265 let Inst{21} = 0; // W bit
266 let Inst{22} = 0; // B bit
267 let Inst{24} = 1; // P bit
269 class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
270 string asm, list<dag> pattern>
271 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
272 let Inst{20} = 1; // L bit
273 let Inst{21} = 0; // W bit
274 let Inst{22} = 1; // B bit
275 let Inst{24} = 1; // P bit
277 class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
279 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
281 let Inst{20} = 1; // L bit
282 let Inst{21} = 0; // W bit
283 let Inst{22} = 1; // B bit
284 let Inst{24} = 1; // P bit
288 class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
289 string asm, list<dag> pattern>
290 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
291 let Inst{20} = 0; // L bit
292 let Inst{21} = 0; // W bit
293 let Inst{22} = 0; // B bit
294 let Inst{24} = 1; // P bit
296 class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
298 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
300 let Inst{20} = 0; // L bit
301 let Inst{21} = 0; // W bit
302 let Inst{22} = 0; // B bit
303 let Inst{24} = 1; // P bit
305 class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
306 string asm, list<dag> pattern>
307 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
308 let Inst{20} = 0; // L bit
309 let Inst{21} = 0; // W bit
310 let Inst{22} = 1; // B bit
311 let Inst{24} = 1; // P bit
313 class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
315 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
317 let Inst{20} = 0; // L bit
318 let Inst{21} = 0; // W bit
319 let Inst{22} = 1; // B bit
320 let Inst{24} = 1; // P bit
324 class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
325 string asm, string cstr, list<dag> pattern>
326 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
327 asm, cstr, pattern> {
328 let Inst{20} = 1; // L bit
329 let Inst{21} = 1; // W bit
330 let Inst{22} = 0; // B bit
331 let Inst{24} = 1; // P bit
333 class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
334 string asm, string cstr, list<dag> pattern>
335 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
336 asm, cstr, pattern> {
337 let Inst{20} = 1; // L bit
338 let Inst{21} = 1; // W bit
339 let Inst{22} = 1; // B bit
340 let Inst{24} = 1; // P bit
343 // Pre-indexed stores
344 class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
345 string asm, string cstr, list<dag> pattern>
346 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
347 asm, cstr, pattern> {
348 let Inst{20} = 0; // L bit
349 let Inst{21} = 1; // W bit
350 let Inst{22} = 0; // B bit
351 let Inst{24} = 1; // P bit
353 class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
354 string asm, string cstr, list<dag> pattern>
355 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
356 asm, cstr, pattern> {
357 let Inst{20} = 0; // L bit
358 let Inst{21} = 1; // W bit
359 let Inst{22} = 1; // B bit
360 let Inst{24} = 1; // P bit
363 // Post-indexed loads
364 class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
365 string asm, string cstr, list<dag> pattern>
366 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
368 let Inst{20} = 1; // L bit
369 let Inst{21} = 0; // W bit
370 let Inst{22} = 0; // B bit
371 let Inst{24} = 0; // P bit
373 class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
374 string asm, string cstr, list<dag> pattern>
375 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
377 let Inst{20} = 1; // L bit
378 let Inst{21} = 0; // W bit
379 let Inst{22} = 1; // B bit
380 let Inst{24} = 0; // P bit
383 // Post-indexed stores
384 class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
385 string asm, string cstr, list<dag> pattern>
386 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
388 let Inst{20} = 0; // L bit
389 let Inst{21} = 0; // W bit
390 let Inst{22} = 0; // B bit
391 let Inst{24} = 0; // P bit
393 class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
394 string asm, string cstr, list<dag> pattern>
395 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
397 let Inst{20} = 0; // L bit
398 let Inst{21} = 0; // W bit
399 let Inst{22} = 1; // B bit
400 let Inst{24} = 0; // P bit
403 // addrmode3 instructions
404 class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
405 string asm, list<dag> pattern>
406 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
408 class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
410 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
414 class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
415 string asm, list<dag> pattern>
416 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
419 let Inst{5} = 1; // H bit
420 let Inst{6} = 0; // S bit
422 let Inst{20} = 1; // L bit
423 let Inst{21} = 0; // W bit
424 let Inst{24} = 1; // P bit
426 class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
428 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
431 let Inst{5} = 1; // H bit
432 let Inst{6} = 0; // S bit
434 let Inst{20} = 1; // L bit
435 let Inst{21} = 0; // W bit
436 let Inst{24} = 1; // P bit
438 class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
439 string asm, list<dag> pattern>
440 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
443 let Inst{5} = 1; // H bit
444 let Inst{6} = 1; // S bit
446 let Inst{20} = 1; // L bit
447 let Inst{21} = 0; // W bit
448 let Inst{24} = 1; // P bit
450 class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
452 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
455 let Inst{5} = 1; // H bit
456 let Inst{6} = 1; // S bit
458 let Inst{20} = 1; // L bit
459 let Inst{21} = 0; // W bit
460 let Inst{24} = 1; // P bit
462 class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
463 string asm, list<dag> pattern>
464 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
467 let Inst{5} = 0; // H bit
468 let Inst{6} = 1; // S bit
470 let Inst{20} = 1; // L bit
471 let Inst{21} = 0; // W bit
472 let Inst{24} = 1; // P bit
474 class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
476 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
479 let Inst{5} = 0; // H bit
480 let Inst{6} = 1; // S bit
482 let Inst{20} = 1; // L bit
483 let Inst{21} = 0; // W bit
484 let Inst{24} = 1; // P bit
486 class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
487 string asm, list<dag> pattern>
488 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
491 let Inst{5} = 0; // H bit
492 let Inst{6} = 1; // S bit
494 let Inst{20} = 0; // L bit
495 let Inst{21} = 0; // W bit
496 let Inst{24} = 1; // P bit
500 class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
501 string asm, list<dag> pattern>
502 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
505 let Inst{5} = 1; // H bit
506 let Inst{6} = 0; // S bit
508 let Inst{20} = 0; // L bit
509 let Inst{21} = 0; // W bit
510 let Inst{24} = 1; // P bit
512 class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm,
514 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
517 let Inst{5} = 1; // H bit
518 let Inst{6} = 0; // S bit
520 let Inst{20} = 0; // L bit
521 let Inst{21} = 0; // W bit
522 let Inst{24} = 1; // P bit
524 class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
525 string asm, list<dag> pattern>
526 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
529 let Inst{5} = 1; // H bit
530 let Inst{6} = 1; // S bit
532 let Inst{20} = 0; // L bit
533 let Inst{21} = 0; // W bit
534 let Inst{24} = 1; // P bit
538 class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
539 string asm, string cstr, list<dag> pattern>
540 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
541 asm, cstr, pattern> {
543 let Inst{5} = 1; // H bit
544 let Inst{6} = 0; // S bit
546 let Inst{20} = 1; // L bit
547 let Inst{21} = 1; // W bit
548 let Inst{24} = 1; // P bit
550 class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
551 string asm, string cstr, list<dag> pattern>
552 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
553 asm, cstr, pattern> {
555 let Inst{5} = 1; // H bit
556 let Inst{6} = 1; // S bit
558 let Inst{20} = 1; // L bit
559 let Inst{21} = 1; // W bit
560 let Inst{24} = 1; // P bit
562 class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
563 string asm, string cstr, list<dag> pattern>
564 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
565 asm, cstr, pattern> {
567 let Inst{5} = 0; // H bit
568 let Inst{6} = 1; // S bit
570 let Inst{20} = 1; // L bit
571 let Inst{21} = 1; // W bit
572 let Inst{24} = 1; // P bit
575 // Pre-indexed stores
576 class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
577 string asm, string cstr, list<dag> pattern>
578 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
579 asm, cstr, pattern> {
581 let Inst{5} = 1; // H bit
582 let Inst{6} = 0; // S bit
584 let Inst{20} = 0; // L bit
585 let Inst{21} = 1; // W bit
586 let Inst{24} = 1; // P bit
589 // Post-indexed loads
590 class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
591 string asm, string cstr, list<dag> pattern>
592 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
595 let Inst{5} = 1; // H bit
596 let Inst{6} = 0; // S bit
598 let Inst{20} = 1; // L bit
599 let Inst{21} = 1; // W bit
600 let Inst{24} = 0; // P bit
602 class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
603 string asm, string cstr, list<dag> pattern>
604 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
607 let Inst{5} = 1; // H bit
608 let Inst{6} = 1; // S bit
610 let Inst{20} = 1; // L bit
611 let Inst{21} = 1; // W bit
612 let Inst{24} = 0; // P bit
614 class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
615 string asm, string cstr, list<dag> pattern>
616 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
619 let Inst{5} = 0; // H bit
620 let Inst{6} = 1; // S bit
622 let Inst{20} = 1; // L bit
623 let Inst{21} = 1; // W bit
624 let Inst{24} = 0; // P bit
627 // Post-indexed stores
628 class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
629 string asm, string cstr, list<dag> pattern>
630 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
633 let Inst{5} = 1; // H bit
634 let Inst{6} = 0; // S bit
636 let Inst{20} = 0; // L bit
637 let Inst{21} = 1; // W bit
638 let Inst{24} = 0; // P bit
642 // addrmode4 instructions
643 class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
644 string asm, list<dag> pattern>
645 : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
647 let Inst{25-27} = 0x4;
649 class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm,
651 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
653 let Inst{20} = 1; // L bit
654 let Inst{22} = 0; // S bit
655 let Inst{25-27} = 0x4;
657 class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm,
659 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
661 let Inst{20} = 1; // L bit
662 let Inst{22} = 1; // S bit
663 let Inst{25-27} = 0x4;
665 class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
667 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
669 let Inst{20} = 0; // L bit
670 let Inst{22} = 0; // S bit
671 let Inst{25-27} = 0x4;
675 //===----------------------------------------------------------------------===//
677 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
678 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
679 list<Predicate> Predicates = [IsARM];
681 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
682 list<Predicate> Predicates = [IsARM, HasV5TE];
684 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
685 list<Predicate> Predicates = [IsARM, HasV6];
688 //===----------------------------------------------------------------------===//
690 // Thumb Instruction Format Definitions.
694 // TI - Thumb instruction.
696 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
697 string asm, string cstr, list<dag> pattern>
698 // FIXME: Set all opcodes to 0 for now.
699 : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
700 let OutOperandList = outs;
701 let InOperandList = ins;
703 let Pattern = pattern;
704 list<Predicate> Predicates = [IsThumb];
707 class TI<dag outs, dag ins, string asm, list<dag> pattern>
708 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
709 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
710 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
711 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
712 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
713 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
714 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
715 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
716 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
718 // Two-address instructions
719 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
720 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
722 // BL, BLX(1) are translated by assembler into two instructions
723 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
724 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
726 // BR_JT instructions
727 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
728 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
731 //===----------------------------------------------------------------------===//
734 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
735 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
736 list<Predicate> Predicates = [IsThumb];
739 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
740 list<Predicate> Predicates = [IsThumb, HasV5T];