1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<28>;
38 def ArithMiscFrm : Format<11>;
39 def ExtFrm : Format<12>;
41 def VFPUnaryFrm : Format<13>;
42 def VFPBinaryFrm : Format<14>;
43 def VFPConv1Frm : Format<15>;
44 def VFPConv2Frm : Format<16>;
45 def VFPConv3Frm : Format<17>;
46 def VFPConv4Frm : Format<18>;
47 def VFPConv5Frm : Format<19>;
48 def VFPLdStFrm : Format<20>;
49 def VFPLdStMulFrm : Format<21>;
50 def VFPMiscFrm : Format<22>;
52 def ThumbFrm : Format<23>;
54 def NEONFrm : Format<24>;
55 def NEONGetLnFrm : Format<25>;
56 def NEONSetLnFrm : Format<26>;
57 def NEONDupFrm : Format<27>;
59 def MiscFrm : Format<29>;
60 def ThumbMiscFrm : Format<30>;
64 // the instruction has a Rn register operand.
65 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
66 // it doesn't have a Rn operand.
67 class UnaryDP { bit isUnaryDataProc = 1; }
69 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
70 // a 16-bit Thumb instruction if certain conditions are met.
71 class Xform16Bit { bit canXformTo16Bit = 1; }
73 //===----------------------------------------------------------------------===//
74 // ARM Instruction flags. These need to match ARMInstrInfo.h.
78 class AddrMode<bits<4> val> {
81 def AddrModeNone : AddrMode<0>;
82 def AddrMode1 : AddrMode<1>;
83 def AddrMode2 : AddrMode<2>;
84 def AddrMode3 : AddrMode<3>;
85 def AddrMode4 : AddrMode<4>;
86 def AddrMode5 : AddrMode<5>;
87 def AddrMode6 : AddrMode<6>;
88 def AddrModeT1_1 : AddrMode<7>;
89 def AddrModeT1_2 : AddrMode<8>;
90 def AddrModeT1_4 : AddrMode<9>;
91 def AddrModeT1_s : AddrMode<10>;
92 def AddrModeT2_i12: AddrMode<11>;
93 def AddrModeT2_i8 : AddrMode<12>;
94 def AddrModeT2_so : AddrMode<13>;
95 def AddrModeT2_pc : AddrMode<14>;
96 def AddrModeT2_i8s4 : AddrMode<15>;
99 class SizeFlagVal<bits<3> val> {
102 def SizeInvalid : SizeFlagVal<0>; // Unset.
103 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
104 def Size8Bytes : SizeFlagVal<2>;
105 def Size4Bytes : SizeFlagVal<3>;
106 def Size2Bytes : SizeFlagVal<4>;
108 // Load / store index mode.
109 class IndexMode<bits<2> val> {
112 def IndexModeNone : IndexMode<0>;
113 def IndexModePre : IndexMode<1>;
114 def IndexModePost : IndexMode<2>;
116 // Instruction execution domain.
117 class Domain<bits<2> val> {
120 def GenericDomain : Domain<0>;
121 def VFPDomain : Domain<1>; // Instructions in VFP domain only
122 def NeonDomain : Domain<2>; // Instructions in Neon domain only
123 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
125 //===----------------------------------------------------------------------===//
127 // ARM special operands.
130 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
131 // register whose default is 0 (no register).
132 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
133 (ops (i32 14), (i32 zero_reg))> {
134 let PrintMethod = "printPredicateOperand";
137 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
138 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
139 let PrintMethod = "printSBitModifierOperand";
142 // Same as cc_out except it defaults to setting CPSR.
143 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
144 let PrintMethod = "printSBitModifierOperand";
147 //===----------------------------------------------------------------------===//
149 // ARM Instruction templates.
152 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
153 Format f, Domain d, string cstr, InstrItinClass itin>
155 let Namespace = "ARM";
159 bits<4> AddrModeBits = AM.Value;
162 bits<3> SizeFlag = SZ.Value;
165 bits<2> IndexModeBits = IM.Value;
168 bits<5> Form = F.Value;
171 bits<2> Dom = D.Value;
174 // Attributes specific to ARM instructions...
176 bit isUnaryDataProc = 0;
177 bit canXformTo16Bit = 0;
179 let Constraints = cstr;
180 let Itinerary = itin;
187 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
188 Format f, Domain d, string cstr, InstrItinClass itin>
189 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
191 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
192 // on by adding flavors to specific instructions.
193 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
194 Format f, Domain d, string cstr, InstrItinClass itin>
195 : InstTemplate<am, sz, im, f, d, cstr, itin>;
197 class PseudoInst<dag oops, dag iops, InstrItinClass itin,
198 string asm, list<dag> pattern>
199 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
201 let OutOperandList = oops;
202 let InOperandList = iops;
204 let Pattern = pattern;
207 // Almost all ARM instructions are predicable.
208 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
209 IndexMode im, Format f, InstrItinClass itin,
210 string opc, string asm, string cstr,
212 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
213 let OutOperandList = oops;
214 let InOperandList = !con(iops, (ops pred:$p));
215 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
216 let Pattern = pattern;
217 list<Predicate> Predicates = [IsARM];
219 // A few are not predicable
220 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
221 IndexMode im, Format f, InstrItinClass itin,
222 string opc, string asm, string cstr,
224 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
225 let OutOperandList = oops;
226 let InOperandList = iops;
227 let AsmString = !strconcat(opc, asm);
228 let Pattern = pattern;
229 let isPredicable = 0;
230 list<Predicate> Predicates = [IsARM];
233 // Same as I except it can optionally modify CPSR. Note it's modeled as
234 // an input operand since by default it's a zero register. It will
235 // become an implicit def once it's "flipped".
236 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
237 IndexMode im, Format f, InstrItinClass itin,
238 string opc, string asm, string cstr,
240 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
241 let OutOperandList = oops;
242 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
243 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
244 let Pattern = pattern;
245 list<Predicate> Predicates = [IsARM];
249 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
250 IndexMode im, Format f, InstrItinClass itin,
251 string asm, string cstr, list<dag> pattern>
252 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
253 let OutOperandList = oops;
254 let InOperandList = iops;
256 let Pattern = pattern;
257 list<Predicate> Predicates = [IsARM];
260 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
261 string opc, string asm, list<dag> pattern>
262 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
263 opc, asm, "", pattern>;
264 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
265 string opc, string asm, list<dag> pattern>
266 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
267 opc, asm, "", pattern>;
268 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
269 string asm, list<dag> pattern>
270 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
272 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
273 string opc, string asm, list<dag> pattern>
274 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
275 opc, asm, "", pattern>;
277 // Ctrl flow instructions
278 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
279 string opc, string asm, list<dag> pattern>
280 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
281 opc, asm, "", pattern> {
282 let Inst{27-24} = opcod;
284 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
285 string asm, list<dag> pattern>
286 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
288 let Inst{27-24} = opcod;
290 class ABXIx2<dag oops, dag iops, InstrItinClass itin,
291 string asm, list<dag> pattern>
292 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin,
295 // BR_JT instructions
296 class JTI<dag oops, dag iops, InstrItinClass itin,
297 string asm, list<dag> pattern>
298 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
302 // Atomic load/store instructions
304 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
305 string opc, string asm, list<dag> pattern>
306 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
307 opc, asm, "", pattern> {
308 let Inst{27-23} = 0b00011;
309 let Inst{22-21} = opcod;
311 let Inst{11-0} = 0b111110011111;
313 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
314 string opc, string asm, list<dag> pattern>
315 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
316 opc, asm, "", pattern> {
317 let Inst{27-23} = 0b00011;
318 let Inst{22-21} = opcod;
320 let Inst{11-4} = 0b11111001;
323 // addrmode1 instructions
324 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
325 string opc, string asm, list<dag> pattern>
326 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
327 opc, asm, "", pattern> {
328 let Inst{24-21} = opcod;
329 let Inst{27-26} = {0,0};
331 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
332 string opc, string asm, list<dag> pattern>
333 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
334 opc, asm, "", pattern> {
335 let Inst{24-21} = opcod;
336 let Inst{27-26} = {0,0};
338 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
339 string asm, list<dag> pattern>
340 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
342 let Inst{24-21} = opcod;
343 let Inst{27-26} = {0,0};
345 class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
346 string opc, string asm, list<dag> pattern>
347 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
348 opc, asm, "", pattern>;
351 // addrmode2 loads and stores
352 class AI2<dag oops, dag iops, Format f, InstrItinClass itin,
353 string opc, string asm, list<dag> pattern>
354 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
355 opc, asm, "", pattern> {
356 let Inst{27-26} = {0,1};
360 class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
361 string opc, string asm, list<dag> pattern>
362 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
363 opc, asm, "", pattern> {
364 let Inst{20} = 1; // L bit
365 let Inst{21} = 0; // W bit
366 let Inst{22} = 0; // B bit
367 let Inst{24} = 1; // P bit
368 let Inst{27-26} = {0,1};
370 class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
371 string asm, list<dag> pattern>
372 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
374 let Inst{20} = 1; // L bit
375 let Inst{21} = 0; // W bit
376 let Inst{22} = 0; // B bit
377 let Inst{24} = 1; // P bit
378 let Inst{27-26} = {0,1};
380 class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
381 string opc, string asm, list<dag> pattern>
382 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
383 opc, asm, "", pattern> {
384 let Inst{20} = 1; // L bit
385 let Inst{21} = 0; // W bit
386 let Inst{22} = 1; // B bit
387 let Inst{24} = 1; // P bit
388 let Inst{27-26} = {0,1};
390 class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
391 string asm, list<dag> pattern>
392 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
394 let Inst{20} = 1; // L bit
395 let Inst{21} = 0; // W bit
396 let Inst{22} = 1; // B bit
397 let Inst{24} = 1; // P bit
398 let Inst{27-26} = {0,1};
402 class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
403 string opc, string asm, list<dag> pattern>
404 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
405 opc, asm, "", pattern> {
406 let Inst{20} = 0; // L bit
407 let Inst{21} = 0; // W bit
408 let Inst{22} = 0; // B bit
409 let Inst{24} = 1; // P bit
410 let Inst{27-26} = {0,1};
412 class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
413 string asm, list<dag> pattern>
414 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
416 let Inst{20} = 0; // L bit
417 let Inst{21} = 0; // W bit
418 let Inst{22} = 0; // B bit
419 let Inst{24} = 1; // P bit
420 let Inst{27-26} = {0,1};
422 class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
423 string opc, string asm, list<dag> pattern>
424 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
425 opc, asm, "", pattern> {
426 let Inst{20} = 0; // L bit
427 let Inst{21} = 0; // W bit
428 let Inst{22} = 1; // B bit
429 let Inst{24} = 1; // P bit
430 let Inst{27-26} = {0,1};
432 class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
433 string asm, list<dag> pattern>
434 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
436 let Inst{20} = 0; // L bit
437 let Inst{21} = 0; // W bit
438 let Inst{22} = 1; // B bit
439 let Inst{24} = 1; // P bit
440 let Inst{27-26} = {0,1};
444 class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
445 string opc, string asm, string cstr, list<dag> pattern>
446 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
447 opc, asm, cstr, pattern> {
448 let Inst{20} = 1; // L bit
449 let Inst{21} = 1; // W bit
450 let Inst{22} = 0; // B bit
451 let Inst{24} = 1; // P bit
452 let Inst{27-26} = {0,1};
454 class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
455 string opc, string asm, string cstr, list<dag> pattern>
456 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
457 opc, asm, cstr, pattern> {
458 let Inst{20} = 1; // L bit
459 let Inst{21} = 1; // W bit
460 let Inst{22} = 1; // B bit
461 let Inst{24} = 1; // P bit
462 let Inst{27-26} = {0,1};
465 // Pre-indexed stores
466 class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
467 string opc, string asm, string cstr, list<dag> pattern>
468 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
469 opc, asm, cstr, pattern> {
470 let Inst{20} = 0; // L bit
471 let Inst{21} = 1; // W bit
472 let Inst{22} = 0; // B bit
473 let Inst{24} = 1; // P bit
474 let Inst{27-26} = {0,1};
476 class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
477 string opc, string asm, string cstr, list<dag> pattern>
478 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
479 opc, asm, cstr, pattern> {
480 let Inst{20} = 0; // L bit
481 let Inst{21} = 1; // W bit
482 let Inst{22} = 1; // B bit
483 let Inst{24} = 1; // P bit
484 let Inst{27-26} = {0,1};
487 // Post-indexed loads
488 class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
489 string opc, string asm, string cstr, list<dag> pattern>
490 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
491 opc, asm, cstr,pattern> {
492 let Inst{20} = 1; // L bit
493 let Inst{21} = 0; // W bit
494 let Inst{22} = 0; // B bit
495 let Inst{24} = 0; // P bit
496 let Inst{27-26} = {0,1};
498 class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
499 string opc, string asm, string cstr, list<dag> pattern>
500 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
501 opc, asm, cstr,pattern> {
502 let Inst{20} = 1; // L bit
503 let Inst{21} = 0; // W bit
504 let Inst{22} = 1; // B bit
505 let Inst{24} = 0; // P bit
506 let Inst{27-26} = {0,1};
509 // Post-indexed stores
510 class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
511 string opc, string asm, string cstr, list<dag> pattern>
512 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
513 opc, asm, cstr,pattern> {
514 let Inst{20} = 0; // L bit
515 let Inst{21} = 0; // W bit
516 let Inst{22} = 0; // B bit
517 let Inst{24} = 0; // P bit
518 let Inst{27-26} = {0,1};
520 class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
521 string opc, string asm, string cstr, list<dag> pattern>
522 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
523 opc, asm, cstr,pattern> {
524 let Inst{20} = 0; // L bit
525 let Inst{21} = 0; // W bit
526 let Inst{22} = 1; // B bit
527 let Inst{24} = 0; // P bit
528 let Inst{27-26} = {0,1};
531 // addrmode3 instructions
532 class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
533 string opc, string asm, list<dag> pattern>
534 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
535 opc, asm, "", pattern>;
536 class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
537 string asm, list<dag> pattern>
538 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
542 class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
543 string opc, string asm, list<dag> pattern>
544 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
545 opc, asm, "", pattern> {
547 let Inst{5} = 1; // H bit
548 let Inst{6} = 0; // S bit
550 let Inst{20} = 1; // L bit
551 let Inst{21} = 0; // W bit
552 let Inst{24} = 1; // P bit
553 let Inst{27-25} = 0b000;
555 class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
556 string asm, list<dag> pattern>
557 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
560 let Inst{5} = 1; // H bit
561 let Inst{6} = 0; // S bit
563 let Inst{20} = 1; // L bit
564 let Inst{21} = 0; // W bit
565 let Inst{24} = 1; // P bit
567 class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
568 string opc, string asm, list<dag> pattern>
569 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
570 opc, asm, "", pattern> {
572 let Inst{5} = 1; // H bit
573 let Inst{6} = 1; // S bit
575 let Inst{20} = 1; // L bit
576 let Inst{21} = 0; // W bit
577 let Inst{24} = 1; // P bit
578 let Inst{27-25} = 0b000;
580 class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
581 string asm, list<dag> pattern>
582 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
585 let Inst{5} = 1; // H bit
586 let Inst{6} = 1; // S bit
588 let Inst{20} = 1; // L bit
589 let Inst{21} = 0; // W bit
590 let Inst{24} = 1; // P bit
592 class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
593 string opc, string asm, list<dag> pattern>
594 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
595 opc, asm, "", pattern> {
597 let Inst{5} = 0; // H bit
598 let Inst{6} = 1; // S bit
600 let Inst{20} = 1; // L bit
601 let Inst{21} = 0; // W bit
602 let Inst{24} = 1; // P bit
603 let Inst{27-25} = 0b000;
605 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
606 string asm, list<dag> pattern>
607 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
610 let Inst{5} = 0; // H bit
611 let Inst{6} = 1; // S bit
613 let Inst{20} = 1; // L bit
614 let Inst{21} = 0; // W bit
615 let Inst{24} = 1; // P bit
617 class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
618 string opc, string asm, list<dag> pattern>
619 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
620 opc, asm, "", pattern> {
622 let Inst{5} = 0; // H bit
623 let Inst{6} = 1; // S bit
625 let Inst{20} = 0; // L bit
626 let Inst{21} = 0; // W bit
627 let Inst{24} = 1; // P bit
628 let Inst{27-25} = 0b000;
632 class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
633 string opc, string asm, list<dag> pattern>
634 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
635 opc, asm, "", pattern> {
637 let Inst{5} = 1; // H bit
638 let Inst{6} = 0; // S bit
640 let Inst{20} = 0; // L bit
641 let Inst{21} = 0; // W bit
642 let Inst{24} = 1; // P bit
643 let Inst{27-25} = 0b000;
645 class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
646 string asm, list<dag> pattern>
647 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
650 let Inst{5} = 1; // H bit
651 let Inst{6} = 0; // S bit
653 let Inst{20} = 0; // L bit
654 let Inst{21} = 0; // W bit
655 let Inst{24} = 1; // P bit
657 class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
658 string opc, string asm, list<dag> pattern>
659 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
660 opc, asm, "", pattern> {
662 let Inst{5} = 1; // H bit
663 let Inst{6} = 1; // S bit
665 let Inst{20} = 0; // L bit
666 let Inst{21} = 0; // W bit
667 let Inst{24} = 1; // P bit
668 let Inst{27-25} = 0b000;
672 class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
673 string opc, string asm, string cstr, list<dag> pattern>
674 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
675 opc, asm, cstr, pattern> {
677 let Inst{5} = 1; // H bit
678 let Inst{6} = 0; // S bit
680 let Inst{20} = 1; // L bit
681 let Inst{21} = 1; // W bit
682 let Inst{24} = 1; // P bit
683 let Inst{27-25} = 0b000;
685 class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
686 string opc, string asm, string cstr, list<dag> pattern>
687 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
688 opc, asm, cstr, pattern> {
690 let Inst{5} = 1; // H bit
691 let Inst{6} = 1; // S bit
693 let Inst{20} = 1; // L bit
694 let Inst{21} = 1; // W bit
695 let Inst{24} = 1; // P bit
696 let Inst{27-25} = 0b000;
698 class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
699 string opc, string asm, string cstr, list<dag> pattern>
700 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
701 opc, asm, cstr, pattern> {
703 let Inst{5} = 0; // H bit
704 let Inst{6} = 1; // S bit
706 let Inst{20} = 1; // L bit
707 let Inst{21} = 1; // W bit
708 let Inst{24} = 1; // P bit
709 let Inst{27-25} = 0b000;
712 // Pre-indexed stores
713 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
714 string opc, string asm, string cstr, list<dag> pattern>
715 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
716 opc, asm, cstr, pattern> {
718 let Inst{5} = 1; // H bit
719 let Inst{6} = 0; // S bit
721 let Inst{20} = 0; // L bit
722 let Inst{21} = 1; // W bit
723 let Inst{24} = 1; // P bit
724 let Inst{27-25} = 0b000;
727 // Post-indexed loads
728 class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
729 string opc, string asm, string cstr, list<dag> pattern>
730 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
731 opc, asm, cstr,pattern> {
733 let Inst{5} = 1; // H bit
734 let Inst{6} = 0; // S bit
736 let Inst{20} = 1; // L bit
737 let Inst{21} = 1; // W bit
738 let Inst{24} = 0; // P bit
739 let Inst{27-25} = 0b000;
741 class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
742 string opc, string asm, string cstr, list<dag> pattern>
743 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
744 opc, asm, cstr,pattern> {
746 let Inst{5} = 1; // H bit
747 let Inst{6} = 1; // S bit
749 let Inst{20} = 1; // L bit
750 let Inst{21} = 1; // W bit
751 let Inst{24} = 0; // P bit
752 let Inst{27-25} = 0b000;
754 class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
755 string opc, string asm, string cstr, list<dag> pattern>
756 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
757 opc, asm, cstr,pattern> {
759 let Inst{5} = 0; // H bit
760 let Inst{6} = 1; // S bit
762 let Inst{20} = 1; // L bit
763 let Inst{21} = 1; // W bit
764 let Inst{24} = 0; // P bit
765 let Inst{27-25} = 0b000;
768 // Post-indexed stores
769 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
770 string opc, string asm, string cstr, list<dag> pattern>
771 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
772 opc, asm, cstr,pattern> {
774 let Inst{5} = 1; // H bit
775 let Inst{6} = 0; // S bit
777 let Inst{20} = 0; // L bit
778 let Inst{21} = 1; // W bit
779 let Inst{24} = 0; // P bit
780 let Inst{27-25} = 0b000;
784 // addrmode4 instructions
785 class AXI4ld<dag oops, dag iops, Format f, InstrItinClass itin,
786 string asm, list<dag> pattern>
787 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin,
789 let Inst{20} = 1; // L bit
790 let Inst{22} = 0; // S bit
791 let Inst{27-25} = 0b100;
793 class AXI4st<dag oops, dag iops, Format f, InstrItinClass itin,
794 string asm, list<dag> pattern>
795 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin,
797 let Inst{20} = 0; // L bit
798 let Inst{22} = 0; // S bit
799 let Inst{27-25} = 0b100;
802 // Unsigned multiply, multiply-accumulate instructions.
803 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
804 string opc, string asm, list<dag> pattern>
805 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
806 opc, asm, "", pattern> {
807 let Inst{7-4} = 0b1001;
808 let Inst{20} = 0; // S bit
809 let Inst{27-21} = opcod;
811 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
812 string opc, string asm, list<dag> pattern>
813 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
814 opc, asm, "", pattern> {
815 let Inst{7-4} = 0b1001;
816 let Inst{27-21} = opcod;
819 // Most significant word multiply
820 class AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
821 string opc, string asm, list<dag> pattern>
822 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
823 opc, asm, "", pattern> {
824 let Inst{7-4} = 0b1001;
826 let Inst{27-21} = opcod;
829 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
830 class AMulxyI<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
831 string opc, string asm, list<dag> pattern>
832 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
833 opc, asm, "", pattern> {
837 let Inst{27-21} = opcod;
840 // Extend instructions.
841 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
842 string opc, string asm, list<dag> pattern>
843 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
844 opc, asm, "", pattern> {
845 let Inst{7-4} = 0b0111;
846 let Inst{27-20} = opcod;
849 // Misc Arithmetic instructions.
850 class AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
851 string opc, string asm, list<dag> pattern>
852 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
853 opc, asm, "", pattern> {
854 let Inst{27-20} = opcod;
857 //===----------------------------------------------------------------------===//
859 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
860 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
861 list<Predicate> Predicates = [IsARM];
863 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
864 list<Predicate> Predicates = [IsARM, HasV5TE];
866 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
867 list<Predicate> Predicates = [IsARM, HasV6];
870 //===----------------------------------------------------------------------===//
872 // Thumb Instruction Format Definitions.
875 // TI - Thumb instruction.
877 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
878 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
879 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
880 let OutOperandList = oops;
881 let InOperandList = iops;
883 let Pattern = pattern;
884 list<Predicate> Predicates = [IsThumb];
887 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
888 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
890 // Two-address instructions
891 class TIt<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
892 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", pattern>;
894 // tBL, tBX 32-bit instructions
895 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
896 dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
897 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, Encoding {
898 let Inst{31-27} = opcod1;
899 let Inst{15-14} = opcod2;
900 let Inst{12} = opcod3;
903 // BR_JT instructions
904 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
905 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
908 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
909 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
910 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
911 let OutOperandList = oops;
912 let InOperandList = iops;
914 let Pattern = pattern;
915 list<Predicate> Predicates = [IsThumb1Only];
918 class T1I<dag oops, dag iops, InstrItinClass itin,
919 string asm, list<dag> pattern>
920 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
921 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
922 string asm, list<dag> pattern>
923 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
924 class T1JTI<dag oops, dag iops, InstrItinClass itin,
925 string asm, list<dag> pattern>
926 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
928 // Two-address instructions
929 class T1It<dag oops, dag iops, InstrItinClass itin,
930 string asm, list<dag> pattern>
931 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
932 asm, "$lhs = $dst", pattern>;
934 // Thumb1 instruction that can either be predicated or set CPSR.
935 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
937 string opc, string asm, string cstr, list<dag> pattern>
938 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
939 let OutOperandList = !con(oops, (ops s_cc_out:$s));
940 let InOperandList = !con(iops, (ops pred:$p));
941 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
942 let Pattern = pattern;
943 list<Predicate> Predicates = [IsThumb1Only];
946 class T1sI<dag oops, dag iops, InstrItinClass itin,
947 string opc, string asm, list<dag> pattern>
948 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
950 // Two-address instructions
951 class T1sIt<dag oops, dag iops, InstrItinClass itin,
952 string opc, string asm, list<dag> pattern>
953 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
954 "$lhs = $dst", pattern>;
956 // Thumb1 instruction that can be predicated.
957 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
959 string opc, string asm, string cstr, list<dag> pattern>
960 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
961 let OutOperandList = oops;
962 let InOperandList = !con(iops, (ops pred:$p));
963 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
964 let Pattern = pattern;
965 list<Predicate> Predicates = [IsThumb1Only];
968 class T1pI<dag oops, dag iops, InstrItinClass itin,
969 string opc, string asm, list<dag> pattern>
970 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
972 // Two-address instructions
973 class T1pIt<dag oops, dag iops, InstrItinClass itin,
974 string opc, string asm, list<dag> pattern>
975 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
976 "$lhs = $dst", pattern>;
978 class T1pI1<dag oops, dag iops, InstrItinClass itin,
979 string opc, string asm, list<dag> pattern>
980 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
981 class T1pI2<dag oops, dag iops, InstrItinClass itin,
982 string opc, string asm, list<dag> pattern>
983 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
984 class T1pI4<dag oops, dag iops, InstrItinClass itin,
985 string opc, string asm, list<dag> pattern>
986 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
987 class T1pIs<dag oops, dag iops,
988 InstrItinClass itin, string opc, string asm, list<dag> pattern>
989 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
991 class Encoding16 : Encoding {
992 let Inst{31-16} = 0x0000;
995 // A6.2 16-bit Thumb instruction encoding
996 class T1Encoding<bits<6> opcode> : Encoding16 {
997 let Inst{15-10} = opcode;
1000 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1001 class T1General<bits<5> opcode> : Encoding16 {
1002 let Inst{15-14} = 0b00;
1003 let Inst{13-9} = opcode;
1006 // A6.2.2 Data-processing encoding.
1007 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1008 let Inst{15-10} = 0b010000;
1009 let Inst{9-6} = opcode;
1012 // A6.2.3 Special data instructions and branch and exchange encoding.
1013 class T1Special<bits<4> opcode> : Encoding16 {
1014 let Inst{15-10} = 0b010001;
1015 let Inst{9-6} = opcode;
1018 // A6.2.4 Load/store single data item encoding.
1019 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1020 let Inst{15-12} = opA;
1021 let Inst{11-9} = opB;
1023 class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
1024 class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
1025 class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
1026 class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
1027 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1029 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1030 class T1Misc<bits<7> opcode> : Encoding16 {
1031 let Inst{15-12} = 0b1011;
1032 let Inst{11-5} = opcode;
1035 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1036 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1037 InstrItinClass itin,
1038 string opc, string asm, string cstr, list<dag> pattern>
1039 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1040 let OutOperandList = oops;
1041 let InOperandList = !con(iops, (ops pred:$p));
1042 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1043 let Pattern = pattern;
1044 list<Predicate> Predicates = [IsThumb2];
1047 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as
1048 // an input operand since by default it's a zero register. It will
1049 // become an implicit def once it's "flipped".
1050 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1052 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1053 InstrItinClass itin,
1054 string opc, string asm, string cstr, list<dag> pattern>
1055 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1056 let OutOperandList = oops;
1057 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
1058 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
1059 let Pattern = pattern;
1060 list<Predicate> Predicates = [IsThumb2];
1064 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1065 InstrItinClass itin,
1066 string asm, string cstr, list<dag> pattern>
1067 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1068 let OutOperandList = oops;
1069 let InOperandList = iops;
1070 let AsmString = asm;
1071 let Pattern = pattern;
1072 list<Predicate> Predicates = [IsThumb2];
1075 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1076 InstrItinClass itin,
1077 string asm, string cstr, list<dag> pattern>
1078 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1079 let OutOperandList = oops;
1080 let InOperandList = iops;
1081 let AsmString = asm;
1082 let Pattern = pattern;
1083 list<Predicate> Predicates = [IsThumb1Only];
1086 class T2I<dag oops, dag iops, InstrItinClass itin,
1087 string opc, string asm, list<dag> pattern>
1088 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1089 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1090 string opc, string asm, list<dag> pattern>
1091 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "", pattern>;
1092 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1093 string opc, string asm, list<dag> pattern>
1094 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1095 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1096 string opc, string asm, list<dag> pattern>
1097 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1098 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1099 string opc, string asm, list<dag> pattern>
1100 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1101 class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
1102 string opc, string asm, list<dag> pattern>
1103 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1105 let Inst{31-27} = 0b11101;
1106 let Inst{26-25} = 0b00;
1108 let Inst{23} = ?; // The U bit.
1111 let Inst{20} = load;
1114 class T2sI<dag oops, dag iops, InstrItinClass itin,
1115 string opc, string asm, list<dag> pattern>
1116 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1118 class T2XI<dag oops, dag iops, InstrItinClass itin,
1119 string asm, list<dag> pattern>
1120 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1121 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1122 string asm, list<dag> pattern>
1123 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1125 class T2Ix2<dag oops, dag iops, InstrItinClass itin,
1126 string opc, string asm, list<dag> pattern>
1127 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
1130 // T2Iidxldst - Thumb2 indexed load / store instructions.
1131 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1133 AddrMode am, IndexMode im, InstrItinClass itin,
1134 string opc, string asm, string cstr, list<dag> pattern>
1135 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1136 let OutOperandList = oops;
1137 let InOperandList = !con(iops, (ops pred:$p));
1138 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1139 let Pattern = pattern;
1140 list<Predicate> Predicates = [IsThumb2];
1141 let Inst{31-27} = 0b11111;
1142 let Inst{26-25} = 0b00;
1143 let Inst{24} = signed;
1145 let Inst{22-21} = opcod;
1146 let Inst{20} = load;
1148 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1149 let Inst{10} = pre; // The P bit.
1150 let Inst{8} = 1; // The W bit.
1153 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1154 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1155 list<Predicate> Predicates = [IsThumb1Only, HasV5T];
1158 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1159 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1160 list<Predicate> Predicates = [IsThumb1Only];
1163 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1164 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1165 list<Predicate> Predicates = [IsThumb2];
1168 //===----------------------------------------------------------------------===//
1170 //===----------------------------------------------------------------------===//
1171 // ARM VFP Instruction templates.
1174 // Almost all VFP instructions are predicable.
1175 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1176 IndexMode im, Format f, InstrItinClass itin,
1177 string opc, string asm, string cstr, list<dag> pattern>
1178 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1179 let OutOperandList = oops;
1180 let InOperandList = !con(iops, (ops pred:$p));
1181 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1182 let Pattern = pattern;
1183 list<Predicate> Predicates = [HasVFP2];
1187 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1188 IndexMode im, Format f, InstrItinClass itin,
1189 string asm, string cstr, list<dag> pattern>
1190 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1191 let OutOperandList = oops;
1192 let InOperandList = iops;
1193 let AsmString = asm;
1194 let Pattern = pattern;
1195 list<Predicate> Predicates = [HasVFP2];
1198 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1199 string opc, string asm, list<dag> pattern>
1200 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1201 opc, asm, "", pattern>;
1203 // ARM VFP addrmode5 loads and stores
1204 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1205 InstrItinClass itin,
1206 string opc, string asm, list<dag> pattern>
1207 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1208 VFPLdStFrm, itin, opc, asm, "", pattern> {
1209 // TODO: Mark the instructions with the appropriate subtarget info.
1210 let Inst{27-24} = opcod1;
1211 let Inst{21-20} = opcod2;
1212 let Inst{11-8} = 0b1011;
1214 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1215 let Dom = VFPNeonDomain.Value;
1218 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1219 InstrItinClass itin,
1220 string opc, string asm, list<dag> pattern>
1221 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1222 VFPLdStFrm, itin, opc, asm, "", pattern> {
1223 // TODO: Mark the instructions with the appropriate subtarget info.
1224 let Inst{27-24} = opcod1;
1225 let Inst{21-20} = opcod2;
1226 let Inst{11-8} = 0b1010;
1229 // Load / store multiple
1230 class AXDI5<dag oops, dag iops, InstrItinClass itin,
1231 string asm, list<dag> pattern>
1232 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1233 VFPLdStMulFrm, itin, asm, "", pattern> {
1234 // TODO: Mark the instructions with the appropriate subtarget info.
1235 let Inst{27-25} = 0b110;
1236 let Inst{11-8} = 0b1011;
1238 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1239 let Dom = VFPNeonDomain.Value;
1242 class AXSI5<dag oops, dag iops, InstrItinClass itin,
1243 string asm, list<dag> pattern>
1244 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1245 VFPLdStMulFrm, itin, asm, "", pattern> {
1246 // TODO: Mark the instructions with the appropriate subtarget info.
1247 let Inst{27-25} = 0b110;
1248 let Inst{11-8} = 0b1010;
1251 // Double precision, unary
1252 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1253 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1254 string asm, list<dag> pattern>
1255 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1256 let Inst{27-23} = opcod1;
1257 let Inst{21-20} = opcod2;
1258 let Inst{19-16} = opcod3;
1259 let Inst{11-8} = 0b1011;
1260 let Inst{7-6} = opcod4;
1261 let Inst{4} = opcod5;
1264 // Double precision, binary
1265 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1266 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1267 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1268 let Inst{27-23} = opcod1;
1269 let Inst{21-20} = opcod2;
1270 let Inst{11-8} = 0b1011;
1275 // Single precision, unary
1276 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1277 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1278 string asm, list<dag> pattern>
1279 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1280 let Inst{27-23} = opcod1;
1281 let Inst{21-20} = opcod2;
1282 let Inst{19-16} = opcod3;
1283 let Inst{11-8} = 0b1010;
1284 let Inst{7-6} = opcod4;
1285 let Inst{4} = opcod5;
1288 // Single precision unary, if no NEON
1289 // Same as ASuI except not available if NEON is enabled
1290 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1291 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1292 string asm, list<dag> pattern>
1293 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1295 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1298 // Single precision, binary
1299 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1300 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1301 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1302 let Inst{27-23} = opcod1;
1303 let Inst{21-20} = opcod2;
1304 let Inst{11-8} = 0b1010;
1309 // Single precision binary, if no NEON
1310 // Same as ASbI except not available if NEON is enabled
1311 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1312 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1313 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1314 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1317 // VFP conversion instructions
1318 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1319 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1321 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1322 let Inst{27-23} = opcod1;
1323 let Inst{21-20} = opcod2;
1324 let Inst{19-16} = opcod3;
1325 let Inst{11-8} = opcod4;
1330 // VFP conversion between floating-point and fixed-point
1331 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1332 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1334 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1335 // size (fixed-point number): sx == 0 ? 16 : 32
1336 let Inst{7} = op5; // sx
1339 // VFP conversion instructions, if no NEON
1340 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1341 dag oops, dag iops, InstrItinClass itin,
1342 string opc, string asm, list<dag> pattern>
1343 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1345 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1348 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1349 InstrItinClass itin,
1350 string opc, string asm, list<dag> pattern>
1351 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1352 let Inst{27-20} = opcod1;
1353 let Inst{11-8} = opcod2;
1357 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1358 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1359 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1361 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1362 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1363 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1365 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1366 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1367 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1369 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1370 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1371 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1373 //===----------------------------------------------------------------------===//
1375 //===----------------------------------------------------------------------===//
1376 // ARM NEON Instruction templates.
1379 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
1380 string opc, string dt, string asm, string cstr, list<dag> pattern>
1381 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
1382 let OutOperandList = oops;
1383 let InOperandList = !con(iops, (ops pred:$p));
1384 let AsmString = !strconcat(
1385 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
1386 !strconcat("\t", asm));
1387 let Pattern = pattern;
1388 list<Predicate> Predicates = [HasNEON];
1391 // Same as NeonI except it does not have a "data type" specifier.
1392 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
1393 string opc, string asm, string cstr, list<dag> pattern>
1394 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
1395 let OutOperandList = oops;
1396 let InOperandList = !con(iops, (ops pred:$p));
1397 let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm));
1398 let Pattern = pattern;
1399 list<Predicate> Predicates = [HasNEON];
1402 class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1404 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "",
1408 class NI4<dag oops, dag iops, InstrItinClass itin, string opc,
1409 string asm, list<dag> pattern>
1410 : NeonXI<oops, iops, AddrMode4, IndexModeNone, itin, opc, asm, "",
1414 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1415 dag oops, dag iops, InstrItinClass itin,
1416 string opc, string dt, string asm, string cstr, list<dag> pattern>
1417 : NeonI<oops, iops, AddrMode6, IndexModeNone, itin, opc, dt, asm, cstr,
1419 let Inst{31-24} = 0b11110100;
1420 let Inst{23} = op23;
1421 let Inst{21-20} = op21_20;
1422 let Inst{11-8} = op11_8;
1423 let Inst{7-4} = op7_4;
1426 class NDataI<dag oops, dag iops, InstrItinClass itin,
1427 string opc, string dt, string asm, string cstr, list<dag> pattern>
1428 : NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, dt, asm,
1430 let Inst{31-25} = 0b1111001;
1433 class NDataXI<dag oops, dag iops, InstrItinClass itin,
1434 string opc, string asm, string cstr, list<dag> pattern>
1435 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm,
1437 let Inst{31-25} = 0b1111001;
1440 // NEON "one register and a modified immediate" format.
1441 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1443 dag oops, dag iops, InstrItinClass itin,
1444 string opc, string dt, string asm, string cstr, list<dag> pattern>
1445 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1446 let Inst{23} = op23;
1447 let Inst{21-19} = op21_19;
1448 let Inst{11-8} = op11_8;
1455 // NEON 2 vector register format.
1456 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1457 bits<5> op11_7, bit op6, bit op4,
1458 dag oops, dag iops, InstrItinClass itin,
1459 string opc, string dt, string asm, string cstr, list<dag> pattern>
1460 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1461 let Inst{24-23} = op24_23;
1462 let Inst{21-20} = op21_20;
1463 let Inst{19-18} = op19_18;
1464 let Inst{17-16} = op17_16;
1465 let Inst{11-7} = op11_7;
1470 // Same as N2V except it doesn't have a datatype suffix.
1471 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1472 bits<5> op11_7, bit op6, bit op4,
1473 dag oops, dag iops, InstrItinClass itin,
1474 string opc, string asm, string cstr, list<dag> pattern>
1475 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
1476 let Inst{24-23} = op24_23;
1477 let Inst{21-20} = op21_20;
1478 let Inst{19-18} = op19_18;
1479 let Inst{17-16} = op17_16;
1480 let Inst{11-7} = op11_7;
1485 // NEON 2 vector register with immediate.
1486 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1487 dag oops, dag iops, InstrItinClass itin,
1488 string opc, string dt, string asm, string cstr, list<dag> pattern>
1489 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1490 let Inst{24} = op24;
1491 let Inst{23} = op23;
1492 let Inst{11-8} = op11_8;
1498 // NEON 3 vector register format.
1499 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1500 dag oops, dag iops, InstrItinClass itin,
1501 string opc, string dt, string asm, string cstr, list<dag> pattern>
1502 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1503 let Inst{24} = op24;
1504 let Inst{23} = op23;
1505 let Inst{21-20} = op21_20;
1506 let Inst{11-8} = op11_8;
1511 // Same as N3VX except it doesn't have a data type suffix.
1512 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1513 dag oops, dag iops, InstrItinClass itin,
1514 string opc, string asm, string cstr, list<dag> pattern>
1515 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
1516 let Inst{24} = op24;
1517 let Inst{23} = op23;
1518 let Inst{21-20} = op21_20;
1519 let Inst{11-8} = op11_8;
1524 // NEON VMOVs between scalar and core registers.
1525 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1526 dag oops, dag iops, Format f, InstrItinClass itin,
1527 string opc, string dt, string asm, list<dag> pattern>
1528 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain,
1530 let Inst{27-20} = opcod1;
1531 let Inst{11-8} = opcod2;
1532 let Inst{6-5} = opcod3;
1535 let OutOperandList = oops;
1536 let InOperandList = !con(iops, (ops pred:$p));
1537 let AsmString = !strconcat(
1538 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
1539 !strconcat("\t", asm));
1540 let Pattern = pattern;
1541 list<Predicate> Predicates = [HasNEON];
1543 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1544 dag oops, dag iops, InstrItinClass itin,
1545 string opc, string dt, string asm, list<dag> pattern>
1546 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, itin,
1547 opc, dt, asm, pattern>;
1548 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1549 dag oops, dag iops, InstrItinClass itin,
1550 string opc, string dt, string asm, list<dag> pattern>
1551 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, itin,
1552 opc, dt, asm, pattern>;
1553 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1554 dag oops, dag iops, InstrItinClass itin,
1555 string opc, string dt, string asm, list<dag> pattern>
1556 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin,
1557 opc, dt, asm, pattern>;
1559 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1560 // for single-precision FP.
1561 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1562 list<Predicate> Predicates = [HasNEON,UseNEONForFP];